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9274f4a9 BS |
1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
24 | ||
25 | #include <core/object.h> | |
26 | #include <core/device.h> | |
27 | #include <core/client.h> | |
9274f4a9 BS |
28 | #include <core/option.h> |
29 | ||
30 | #include <core/class.h> | |
31 | ||
dded35de | 32 | #include <engine/device.h> |
9274f4a9 BS |
33 | |
34 | static DEFINE_MUTEX(nv_devices_mutex); | |
35 | static LIST_HEAD(nv_devices); | |
36 | ||
37 | struct nouveau_device * | |
38 | nouveau_device_find(u64 name) | |
39 | { | |
40 | struct nouveau_device *device, *match = NULL; | |
41 | mutex_lock(&nv_devices_mutex); | |
42 | list_for_each_entry(device, &nv_devices, head) { | |
43 | if (device->handle == name) { | |
44 | match = device; | |
45 | break; | |
46 | } | |
47 | } | |
48 | mutex_unlock(&nv_devices_mutex); | |
49 | return match; | |
50 | } | |
51 | ||
52 | /****************************************************************************** | |
53 | * nouveau_devobj (0x0080): class implementation | |
54 | *****************************************************************************/ | |
55 | struct nouveau_devobj { | |
56 | struct nouveau_parent base; | |
57 | struct nouveau_object *subdev[NVDEV_SUBDEV_NR]; | |
9274f4a9 BS |
58 | }; |
59 | ||
60 | static const u64 disable_map[] = { | |
61 | [NVDEV_SUBDEV_VBIOS] = NV_DEVICE_DISABLE_VBIOS, | |
206c38a9 | 62 | [NVDEV_SUBDEV_DEVINIT] = NV_DEVICE_DISABLE_CORE, |
9274f4a9 BS |
63 | [NVDEV_SUBDEV_GPIO] = NV_DEVICE_DISABLE_CORE, |
64 | [NVDEV_SUBDEV_I2C] = NV_DEVICE_DISABLE_CORE, | |
206c38a9 BS |
65 | [NVDEV_SUBDEV_CLOCK] = NV_DEVICE_DISABLE_CORE, |
66 | [NVDEV_SUBDEV_MXM] = NV_DEVICE_DISABLE_CORE, | |
9274f4a9 | 67 | [NVDEV_SUBDEV_MC] = NV_DEVICE_DISABLE_CORE, |
a10220bb | 68 | [NVDEV_SUBDEV_BUS] = NV_DEVICE_DISABLE_CORE, |
9274f4a9 BS |
69 | [NVDEV_SUBDEV_TIMER] = NV_DEVICE_DISABLE_CORE, |
70 | [NVDEV_SUBDEV_FB] = NV_DEVICE_DISABLE_CORE, | |
206c38a9 BS |
71 | [NVDEV_SUBDEV_LTCG] = NV_DEVICE_DISABLE_CORE, |
72 | [NVDEV_SUBDEV_IBUS] = NV_DEVICE_DISABLE_CORE, | |
9274f4a9 | 73 | [NVDEV_SUBDEV_INSTMEM] = NV_DEVICE_DISABLE_CORE, |
206c38a9 | 74 | [NVDEV_SUBDEV_VM] = NV_DEVICE_DISABLE_CORE, |
9274f4a9 BS |
75 | [NVDEV_SUBDEV_BAR] = NV_DEVICE_DISABLE_CORE, |
76 | [NVDEV_SUBDEV_VOLT] = NV_DEVICE_DISABLE_CORE, | |
9274f4a9 BS |
77 | [NVDEV_SUBDEV_THERM] = NV_DEVICE_DISABLE_CORE, |
78 | [NVDEV_ENGINE_DMAOBJ] = NV_DEVICE_DISABLE_CORE, | |
206c38a9 BS |
79 | [NVDEV_ENGINE_FIFO] = NV_DEVICE_DISABLE_FIFO, |
80 | [NVDEV_ENGINE_SW] = NV_DEVICE_DISABLE_FIFO, | |
9274f4a9 BS |
81 | [NVDEV_ENGINE_GR] = NV_DEVICE_DISABLE_GRAPH, |
82 | [NVDEV_ENGINE_MPEG] = NV_DEVICE_DISABLE_MPEG, | |
83 | [NVDEV_ENGINE_ME] = NV_DEVICE_DISABLE_ME, | |
84 | [NVDEV_ENGINE_VP] = NV_DEVICE_DISABLE_VP, | |
85 | [NVDEV_ENGINE_CRYPT] = NV_DEVICE_DISABLE_CRYPT, | |
86 | [NVDEV_ENGINE_BSP] = NV_DEVICE_DISABLE_BSP, | |
87 | [NVDEV_ENGINE_PPP] = NV_DEVICE_DISABLE_PPP, | |
88 | [NVDEV_ENGINE_COPY0] = NV_DEVICE_DISABLE_COPY0, | |
89 | [NVDEV_ENGINE_COPY1] = NV_DEVICE_DISABLE_COPY1, | |
c42a7aec | 90 | [NVDEV_ENGINE_VIC] = NV_DEVICE_DISABLE_VIC, |
206c38a9 | 91 | [NVDEV_ENGINE_VENC] = NV_DEVICE_DISABLE_VENC, |
9274f4a9 BS |
92 | [NVDEV_ENGINE_DISP] = NV_DEVICE_DISABLE_DISP, |
93 | [NVDEV_SUBDEV_NR] = 0, | |
94 | }; | |
95 | ||
96 | static int | |
97 | nouveau_devobj_ctor(struct nouveau_object *parent, | |
98 | struct nouveau_object *engine, | |
99 | struct nouveau_oclass *oclass, void *data, u32 size, | |
100 | struct nouveau_object **pobject) | |
101 | { | |
102 | struct nouveau_client *client = nv_client(parent); | |
9274f4a9 BS |
103 | struct nouveau_device *device; |
104 | struct nouveau_devobj *devobj; | |
105 | struct nv_device_class *args = data; | |
950fbfab MS |
106 | u32 boot0, strap; |
107 | u64 disable, mmio_base, mmio_size; | |
9274f4a9 | 108 | void __iomem *map; |
7234d023 | 109 | int ret, i, c; |
9274f4a9 BS |
110 | |
111 | if (size < sizeof(struct nv_device_class)) | |
112 | return -EINVAL; | |
113 | ||
114 | /* find the device subdev that matches what the client requested */ | |
115 | device = nv_device(client->device); | |
116 | if (args->device != ~0) { | |
117 | device = nouveau_device_find(args->device); | |
118 | if (!device) | |
119 | return -ENODEV; | |
120 | } | |
121 | ||
122 | ret = nouveau_parent_create(parent, nv_object(device), oclass, 0, NULL, | |
123 | (1ULL << NVDEV_ENGINE_DMAOBJ) | | |
124 | (1ULL << NVDEV_ENGINE_FIFO) | | |
125 | (1ULL << NVDEV_ENGINE_DISP), &devobj); | |
126 | *pobject = nv_object(devobj); | |
127 | if (ret) | |
128 | return ret; | |
129 | ||
130 | mmio_base = pci_resource_start(device->pdev, 0); | |
131 | mmio_size = pci_resource_len(device->pdev, 0); | |
132 | ||
133 | /* translate api disable mask into internal mapping */ | |
134 | disable = args->debug0; | |
135 | for (i = 0; i < NVDEV_SUBDEV_NR; i++) { | |
136 | if (args->disable & disable_map[i]) | |
137 | disable |= (1ULL << i); | |
138 | } | |
139 | ||
140 | /* identify the chipset, and determine classes of subdev/engines */ | |
141 | if (!(args->disable & NV_DEVICE_DISABLE_IDENTIFY) && | |
142 | !device->card_type) { | |
143 | map = ioremap(mmio_base, 0x102000); | |
43b1e9c9 BS |
144 | if (map == NULL) |
145 | return -ENOMEM; | |
9274f4a9 BS |
146 | |
147 | /* switch mmio to cpu's native endianness */ | |
148 | #ifndef __BIG_ENDIAN | |
149 | if (ioread32_native(map + 0x000004) != 0x00000000) | |
150 | #else | |
151 | if (ioread32_native(map + 0x000004) == 0x00000000) | |
152 | #endif | |
153 | iowrite32_native(0x01000001, map + 0x000004); | |
154 | ||
155 | /* read boot0 and strapping information */ | |
156 | boot0 = ioread32_native(map + 0x000000); | |
157 | strap = ioread32_native(map + 0x101000); | |
158 | iounmap(map); | |
159 | ||
160 | /* determine chipset and derive architecture from it */ | |
dd5b84ac BS |
161 | if ((boot0 & 0x1f000000) > 0) { |
162 | device->chipset = (boot0 & 0x1ff00000) >> 20; | |
163 | switch (device->chipset & 0x1f0) { | |
4a0ff754 IM |
164 | case 0x10: { |
165 | if (0x461 & (1 << (device->chipset & 0xf))) | |
166 | device->card_type = NV_10; | |
167 | else | |
168 | device->card_type = NV_11; | |
169 | break; | |
170 | } | |
9274f4a9 BS |
171 | case 0x20: device->card_type = NV_20; break; |
172 | case 0x30: device->card_type = NV_30; break; | |
173 | case 0x40: | |
174 | case 0x60: device->card_type = NV_40; break; | |
175 | case 0x50: | |
176 | case 0x80: | |
177 | case 0x90: | |
178 | case 0xa0: device->card_type = NV_50; break; | |
179 | case 0xc0: device->card_type = NV_C0; break; | |
180 | case 0xd0: device->card_type = NV_D0; break; | |
7b4f638b BS |
181 | case 0xe0: |
182 | case 0xf0: device->card_type = NV_E0; break; | |
9274f4a9 BS |
183 | default: |
184 | break; | |
185 | } | |
186 | } else | |
187 | if ((boot0 & 0xff00fff0) == 0x20004000) { | |
188 | if (boot0 & 0x00f00000) | |
189 | device->chipset = 0x05; | |
190 | else | |
191 | device->chipset = 0x04; | |
192 | device->card_type = NV_04; | |
193 | } | |
194 | ||
195 | switch (device->card_type) { | |
196 | case NV_04: ret = nv04_identify(device); break; | |
4a0ff754 IM |
197 | case NV_10: |
198 | case NV_11: ret = nv10_identify(device); break; | |
9274f4a9 BS |
199 | case NV_20: ret = nv20_identify(device); break; |
200 | case NV_30: ret = nv30_identify(device); break; | |
201 | case NV_40: ret = nv40_identify(device); break; | |
202 | case NV_50: ret = nv50_identify(device); break; | |
203 | case NV_C0: | |
204 | case NV_D0: ret = nvc0_identify(device); break; | |
205 | case NV_E0: ret = nve0_identify(device); break; | |
206 | default: | |
207 | ret = -EINVAL; | |
208 | break; | |
209 | } | |
210 | ||
211 | if (ret) { | |
212 | nv_error(device, "unknown chipset, 0x%08x\n", boot0); | |
213 | return ret; | |
214 | } | |
215 | ||
216 | nv_info(device, "BOOT0 : 0x%08x\n", boot0); | |
2094dd82 BS |
217 | nv_info(device, "Chipset: %s (NV%02X)\n", |
218 | device->cname, device->chipset); | |
9274f4a9 BS |
219 | nv_info(device, "Family : NV%02X\n", device->card_type); |
220 | ||
221 | /* determine frequency of timing crystal */ | |
8aa816b0 | 222 | if ( device->card_type <= NV_10 || device->chipset < 0x17 || |
1f2285d4 | 223 | (device->chipset >= 0x20 && device->chipset < 0x25)) |
9274f4a9 BS |
224 | strap &= 0x00000040; |
225 | else | |
226 | strap &= 0x00400040; | |
227 | ||
228 | switch (strap) { | |
229 | case 0x00000000: device->crystal = 13500; break; | |
230 | case 0x00000040: device->crystal = 14318; break; | |
231 | case 0x00400000: device->crystal = 27000; break; | |
232 | case 0x00400040: device->crystal = 25000; break; | |
233 | } | |
234 | ||
235 | nv_debug(device, "crystal freq: %dKHz\n", device->crystal); | |
236 | } | |
237 | ||
238 | if (!(args->disable & NV_DEVICE_DISABLE_MMIO) && | |
239 | !nv_subdev(device)->mmio) { | |
240 | nv_subdev(device)->mmio = ioremap(mmio_base, mmio_size); | |
241 | if (!nv_subdev(device)->mmio) { | |
242 | nv_error(device, "unable to map device registers\n"); | |
43b1e9c9 | 243 | return -ENOMEM; |
9274f4a9 BS |
244 | } |
245 | } | |
246 | ||
247 | /* ensure requested subsystems are available for use */ | |
10caad33 | 248 | for (i = 1, c = 1; i < NVDEV_SUBDEV_NR; i++) { |
9274f4a9 BS |
249 | if (!(oclass = device->oclass[i]) || (disable & (1ULL << i))) |
250 | continue; | |
251 | ||
10caad33 | 252 | if (device->subdev[i]) { |
7234d023 BS |
253 | nouveau_object_ref(device->subdev[i], |
254 | &devobj->subdev[i]); | |
10caad33 | 255 | continue; |
9274f4a9 BS |
256 | } |
257 | ||
10caad33 BS |
258 | ret = nouveau_object_ctor(nv_object(device), NULL, |
259 | oclass, NULL, i, | |
260 | &devobj->subdev[i]); | |
261 | if (ret == -ENODEV) | |
262 | continue; | |
263 | if (ret) | |
264 | return ret; | |
265 | ||
7234d023 BS |
266 | /* note: can't init *any* subdevs until devinit has been run |
267 | * due to not knowing exactly what the vbios init tables will | |
268 | * mess with. devinit also can't be run until all of its | |
269 | * dependencies have been created. | |
270 | * | |
271 | * this code delays init of any subdev until all of devinit's | |
272 | * dependencies have been created, and then initialises each | |
273 | * subdev in turn as they're created. | |
274 | */ | |
275 | while (i >= NVDEV_SUBDEV_DEVINIT_LAST && c <= i) { | |
276 | struct nouveau_object *subdev = devobj->subdev[c++]; | |
277 | if (subdev && !nv_iclass(subdev, NV_ENGINE_CLASS)) { | |
278 | ret = nouveau_object_inc(subdev); | |
279 | if (ret) | |
280 | return ret; | |
10caad33 BS |
281 | atomic_dec(&nv_object(device)->usecount); |
282 | } else | |
283 | if (subdev) { | |
284 | nouveau_subdev_reset(subdev); | |
9274f4a9 BS |
285 | } |
286 | } | |
9274f4a9 BS |
287 | } |
288 | ||
289 | return 0; | |
290 | } | |
291 | ||
292 | static void | |
293 | nouveau_devobj_dtor(struct nouveau_object *object) | |
294 | { | |
295 | struct nouveau_devobj *devobj = (void *)object; | |
296 | int i; | |
297 | ||
298 | for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--) | |
299 | nouveau_object_ref(NULL, &devobj->subdev[i]); | |
300 | ||
301 | nouveau_parent_destroy(&devobj->base); | |
302 | } | |
303 | ||
9274f4a9 | 304 | static u8 |
0a32241d | 305 | nouveau_devobj_rd08(struct nouveau_object *object, u64 addr) |
9274f4a9 BS |
306 | { |
307 | return nv_rd08(object->engine, addr); | |
308 | } | |
309 | ||
310 | static u16 | |
0a32241d | 311 | nouveau_devobj_rd16(struct nouveau_object *object, u64 addr) |
9274f4a9 BS |
312 | { |
313 | return nv_rd16(object->engine, addr); | |
314 | } | |
315 | ||
316 | static u32 | |
0a32241d | 317 | nouveau_devobj_rd32(struct nouveau_object *object, u64 addr) |
9274f4a9 BS |
318 | { |
319 | return nv_rd32(object->engine, addr); | |
320 | } | |
321 | ||
322 | static void | |
0a32241d | 323 | nouveau_devobj_wr08(struct nouveau_object *object, u64 addr, u8 data) |
9274f4a9 BS |
324 | { |
325 | nv_wr08(object->engine, addr, data); | |
326 | } | |
327 | ||
328 | static void | |
0a32241d | 329 | nouveau_devobj_wr16(struct nouveau_object *object, u64 addr, u16 data) |
9274f4a9 BS |
330 | { |
331 | nv_wr16(object->engine, addr, data); | |
332 | } | |
333 | ||
334 | static void | |
0a32241d | 335 | nouveau_devobj_wr32(struct nouveau_object *object, u64 addr, u32 data) |
9274f4a9 BS |
336 | { |
337 | nv_wr32(object->engine, addr, data); | |
338 | } | |
339 | ||
340 | static struct nouveau_ofuncs | |
341 | nouveau_devobj_ofuncs = { | |
342 | .ctor = nouveau_devobj_ctor, | |
343 | .dtor = nouveau_devobj_dtor, | |
10caad33 BS |
344 | .init = _nouveau_parent_init, |
345 | .fini = _nouveau_parent_fini, | |
9274f4a9 BS |
346 | .rd08 = nouveau_devobj_rd08, |
347 | .rd16 = nouveau_devobj_rd16, | |
348 | .rd32 = nouveau_devobj_rd32, | |
349 | .wr08 = nouveau_devobj_wr08, | |
350 | .wr16 = nouveau_devobj_wr16, | |
351 | .wr32 = nouveau_devobj_wr32, | |
352 | }; | |
353 | ||
354 | /****************************************************************************** | |
355 | * nouveau_device: engine functions | |
356 | *****************************************************************************/ | |
9aecbada | 357 | static struct nouveau_oclass |
9274f4a9 BS |
358 | nouveau_device_sclass[] = { |
359 | { 0x0080, &nouveau_devobj_ofuncs }, | |
360 | {} | |
361 | }; | |
362 | ||
066a5d09 BS |
363 | static int |
364 | nouveau_device_fini(struct nouveau_object *object, bool suspend) | |
365 | { | |
366 | struct nouveau_device *device = (void *)object; | |
10caad33 BS |
367 | struct nouveau_object *subdev; |
368 | int ret, i; | |
369 | ||
370 | for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--) { | |
371 | if ((subdev = device->subdev[i])) { | |
372 | if (!nv_iclass(subdev, NV_ENGINE_CLASS)) { | |
373 | ret = nouveau_object_dec(subdev, suspend); | |
374 | if (ret && suspend) | |
375 | goto fail; | |
376 | } | |
377 | } | |
378 | } | |
379 | ||
380 | ret = 0; | |
381 | fail: | |
382 | for (; ret && i < NVDEV_SUBDEV_NR; i++) { | |
383 | if ((subdev = device->subdev[i])) { | |
384 | if (!nv_iclass(subdev, NV_ENGINE_CLASS)) { | |
385 | ret = nouveau_object_inc(subdev); | |
386 | if (ret) { | |
387 | /* XXX */ | |
388 | } | |
389 | } | |
390 | } | |
391 | } | |
392 | ||
393 | return ret; | |
066a5d09 BS |
394 | } |
395 | ||
396 | static int | |
397 | nouveau_device_init(struct nouveau_object *object) | |
398 | { | |
399 | struct nouveau_device *device = (void *)object; | |
10caad33 BS |
400 | struct nouveau_object *subdev; |
401 | int ret, i; | |
402 | ||
403 | for (i = 0; i < NVDEV_SUBDEV_NR; i++) { | |
404 | if ((subdev = device->subdev[i])) { | |
405 | if (!nv_iclass(subdev, NV_ENGINE_CLASS)) { | |
406 | ret = nouveau_object_inc(subdev); | |
407 | if (ret) | |
408 | goto fail; | |
409 | } else { | |
410 | nouveau_subdev_reset(subdev); | |
411 | } | |
412 | } | |
413 | } | |
414 | ||
415 | ret = 0; | |
416 | fail: | |
417 | for (--i; ret && i >= 0; i--) { | |
418 | if ((subdev = device->subdev[i])) { | |
419 | if (!nv_iclass(subdev, NV_ENGINE_CLASS)) | |
420 | nouveau_object_dec(subdev, false); | |
421 | } | |
422 | } | |
423 | ||
424 | return ret; | |
066a5d09 BS |
425 | } |
426 | ||
ebb945a9 BS |
427 | static void |
428 | nouveau_device_dtor(struct nouveau_object *object) | |
429 | { | |
430 | struct nouveau_device *device = (void *)object; | |
431 | ||
432 | mutex_lock(&nv_devices_mutex); | |
433 | list_del(&device->head); | |
434 | mutex_unlock(&nv_devices_mutex); | |
435 | ||
dded35de BS |
436 | if (nv_subdev(device)->mmio) |
437 | iounmap(nv_subdev(device)->mmio); | |
ebb945a9 | 438 | |
dded35de | 439 | nouveau_engine_destroy(&device->base); |
ebb945a9 BS |
440 | } |
441 | ||
9274f4a9 BS |
442 | static struct nouveau_oclass |
443 | nouveau_device_oclass = { | |
dded35de | 444 | .handle = NV_ENGINE(DEVICE, 0x00), |
9274f4a9 | 445 | .ofuncs = &(struct nouveau_ofuncs) { |
ebb945a9 | 446 | .dtor = nouveau_device_dtor, |
066a5d09 BS |
447 | .init = nouveau_device_init, |
448 | .fini = nouveau_device_fini, | |
9274f4a9 BS |
449 | }, |
450 | }; | |
451 | ||
452 | int | |
453 | nouveau_device_create_(struct pci_dev *pdev, u64 name, const char *sname, | |
454 | const char *cfg, const char *dbg, | |
455 | int length, void **pobject) | |
456 | { | |
457 | struct nouveau_device *device; | |
458 | int ret = -EEXIST; | |
459 | ||
460 | mutex_lock(&nv_devices_mutex); | |
461 | list_for_each_entry(device, &nv_devices, head) { | |
462 | if (device->handle == name) | |
463 | goto done; | |
464 | } | |
465 | ||
dded35de | 466 | ret = nouveau_engine_create_(NULL, NULL, &nouveau_device_oclass, true, |
9274f4a9 BS |
467 | "DEVICE", "device", length, pobject); |
468 | device = *pobject; | |
469 | if (ret) | |
470 | goto done; | |
471 | ||
9274f4a9 BS |
472 | device->pdev = pdev; |
473 | device->handle = name; | |
474 | device->cfgopt = cfg; | |
475 | device->dbgopt = dbg; | |
476 | device->name = sname; | |
477 | ||
478 | nv_subdev(device)->debug = nouveau_dbgopt(device->dbgopt, "DEVICE"); | |
9aecbada | 479 | nv_engine(device)->sclass = nouveau_device_sclass; |
9274f4a9 BS |
480 | list_add(&device->head, &nv_devices); |
481 | done: | |
482 | mutex_unlock(&nv_devices_mutex); | |
483 | return ret; | |
484 | } |