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1 | /* |
2 | * Copyright (C) 2013 Red Hat | |
3 | * Author: Rob Clark <robdclark@gmail.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | #ifndef __MSM_GPU_H__ | |
19 | #define __MSM_GPU_H__ | |
20 | ||
21 | #include <linux/clk.h> | |
22 | #include <linux/regulator/consumer.h> | |
23 | ||
24 | #include "msm_drv.h" | |
ca762a8a | 25 | #include "msm_fence.h" |
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26 | #include "msm_ringbuffer.h" |
27 | ||
28 | struct msm_gem_submit; | |
70c70f09 | 29 | struct msm_gpu_perfcntr; |
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30 | |
31 | /* So far, with hardware that I've seen to date, we can have: | |
32 | * + zero, one, or two z180 2d cores | |
33 | * + a3xx or a2xx 3d core, which share a common CP (the firmware | |
34 | * for the CP seems to implement some different PM4 packet types | |
35 | * but the basics of cmdstream submission are the same) | |
36 | * | |
37 | * Which means that the eventual complete "class" hierarchy, once | |
38 | * support for all past and present hw is in place, becomes: | |
39 | * + msm_gpu | |
40 | * + adreno_gpu | |
41 | * + a3xx_gpu | |
42 | * + a2xx_gpu | |
43 | * + z180_gpu | |
44 | */ | |
45 | struct msm_gpu_funcs { | |
46 | int (*get_param)(struct msm_gpu *gpu, uint32_t param, uint64_t *value); | |
47 | int (*hw_init)(struct msm_gpu *gpu); | |
48 | int (*pm_suspend)(struct msm_gpu *gpu); | |
49 | int (*pm_resume)(struct msm_gpu *gpu); | |
50 | int (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit, | |
51 | struct msm_file_private *ctx); | |
52 | void (*flush)(struct msm_gpu *gpu); | |
53 | void (*idle)(struct msm_gpu *gpu); | |
54 | irqreturn_t (*irq)(struct msm_gpu *irq); | |
55 | uint32_t (*last_fence)(struct msm_gpu *gpu); | |
bd6f82d8 | 56 | void (*recover)(struct msm_gpu *gpu); |
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57 | void (*destroy)(struct msm_gpu *gpu); |
58 | #ifdef CONFIG_DEBUG_FS | |
59 | /* show GPU status in debugfs: */ | |
60 | void (*show)(struct msm_gpu *gpu, struct seq_file *m); | |
61 | #endif | |
62 | }; | |
63 | ||
64 | struct msm_gpu { | |
65 | const char *name; | |
66 | struct drm_device *dev; | |
67 | const struct msm_gpu_funcs *funcs; | |
68 | ||
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69 | /* performance counters (hw & sw): */ |
70 | spinlock_t perf_lock; | |
71 | bool perfcntr_active; | |
72 | struct { | |
73 | bool active; | |
74 | ktime_t time; | |
75 | } last_sample; | |
76 | uint32_t totaltime, activetime; /* sw counters */ | |
77 | uint32_t last_cntrs[5]; /* hw counters */ | |
78 | const struct msm_gpu_perfcntr *perfcntrs; | |
79 | uint32_t num_perfcntrs; | |
80 | ||
ca762a8a | 81 | /* ringbuffer: */ |
7198e6b0 RC |
82 | struct msm_ringbuffer *rb; |
83 | uint32_t rb_iova; | |
84 | ||
85 | /* list of GEM active objects: */ | |
86 | struct list_head active_list; | |
87 | ||
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88 | /* fencing: */ |
89 | struct msm_fence_context *fctx; | |
bd6f82d8 | 90 | |
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91 | /* is gpu powered/active? */ |
92 | int active_cnt; | |
93 | bool inactive; | |
94 | ||
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95 | /* worker for handling active-list retiring: */ |
96 | struct work_struct retire_work; | |
97 | ||
98 | void __iomem *mmio; | |
99 | int irq; | |
100 | ||
871d812a | 101 | struct msm_mmu *mmu; |
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102 | int id; |
103 | ||
104 | /* Power Control: */ | |
105 | struct regulator *gpu_reg, *gpu_cx; | |
de558cd2 | 106 | struct clk *ebi1_clk, *grp_clks[6]; |
7198e6b0 | 107 | uint32_t fast_rate, slow_rate, bus_freq; |
bf2b33af | 108 | |
6490ad47 | 109 | #ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING |
bf2b33af | 110 | struct msm_bus_scale_pdata *bus_scale_table; |
7198e6b0 | 111 | uint32_t bsc; |
bf2b33af | 112 | #endif |
bd6f82d8 | 113 | |
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114 | /* Hang and Inactivity Detection: |
115 | */ | |
116 | #define DRM_MSM_INACTIVE_PERIOD 66 /* in ms (roughly four frames) */ | |
117 | #define DRM_MSM_INACTIVE_JIFFIES msecs_to_jiffies(DRM_MSM_INACTIVE_PERIOD) | |
118 | struct timer_list inactive_timer; | |
119 | struct work_struct inactive_work; | |
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120 | #define DRM_MSM_HANGCHECK_PERIOD 500 /* in ms */ |
121 | #define DRM_MSM_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_MSM_HANGCHECK_PERIOD) | |
122 | struct timer_list hangcheck_timer; | |
123 | uint32_t hangcheck_fence; | |
124 | struct work_struct recover_work; | |
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125 | |
126 | struct list_head submit_list; | |
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127 | }; |
128 | ||
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129 | static inline bool msm_gpu_active(struct msm_gpu *gpu) |
130 | { | |
ca762a8a | 131 | return gpu->fctx->last_fence > gpu->funcs->last_fence(gpu); |
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132 | } |
133 | ||
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134 | /* Perf-Counters: |
135 | * The select_reg and select_val are just there for the benefit of the child | |
136 | * class that actually enables the perf counter.. but msm_gpu base class | |
137 | * will handle sampling/displaying the counters. | |
138 | */ | |
139 | ||
140 | struct msm_gpu_perfcntr { | |
141 | uint32_t select_reg; | |
142 | uint32_t sample_reg; | |
143 | uint32_t select_val; | |
144 | const char *name; | |
145 | }; | |
146 | ||
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147 | static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data) |
148 | { | |
149 | msm_writel(data, gpu->mmio + (reg << 2)); | |
150 | } | |
151 | ||
152 | static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg) | |
153 | { | |
154 | return msm_readl(gpu->mmio + (reg << 2)); | |
155 | } | |
156 | ||
157 | int msm_gpu_pm_suspend(struct msm_gpu *gpu); | |
158 | int msm_gpu_pm_resume(struct msm_gpu *gpu); | |
159 | ||
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160 | void msm_gpu_perfcntr_start(struct msm_gpu *gpu); |
161 | void msm_gpu_perfcntr_stop(struct msm_gpu *gpu); | |
162 | int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime, | |
163 | uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs); | |
164 | ||
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165 | void msm_gpu_retire(struct msm_gpu *gpu); |
166 | int msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, | |
167 | struct msm_file_private *ctx); | |
168 | ||
169 | int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, | |
170 | struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs, | |
171 | const char *name, const char *ioname, const char *irqname, int ringsz); | |
172 | void msm_gpu_cleanup(struct msm_gpu *gpu); | |
173 | ||
e2550b7a | 174 | struct msm_gpu *adreno_load_gpu(struct drm_device *dev); |
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175 | void __init adreno_register(void); |
176 | void __exit adreno_unregister(void); | |
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177 | |
178 | #endif /* __MSM_GPU_H__ */ |