[linux-block.git] / drivers / gpu / drm / msm / mdp / mdp5 / mdp5_kms.c

/*
 * Copyright (C) 2013 Red Hat
 * Author: Rob Clark <robdclark@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */


#include "msm_drv.h"
#include "msm_mmu.h"
#include "mdp5_kms.h"

static const char *iommu_ports[] = {
		"mdp_0",
};

static struct mdp5_platform_config *mdp5_get_config(struct platform_device *dev);

const struct mdp5_config *mdp5_cfg;

static const struct mdp5_config msm8x74_config = {
	.name = "msm8x74",
	.smp = {
		.mmb_count = 22,
		.mmb_size = 4096,
	},
	.ctl = {
		.count = 5,
		.base = { 0x00600, 0x00700, 0x00800, 0x00900, 0x00a00 },
	},
	.pipe_vig = {
		.count = 3,
		.base = { 0x01200, 0x01600, 0x01a00 },
	},
	.pipe_rgb = {
		.count = 3,
		.base = { 0x01e00, 0x02200, 0x02600 },
	},
	.pipe_dma = {
		.count = 2,
		.base = { 0x02a00, 0x02e00 },
	},
	.lm = {
		.count = 5,
		.base = { 0x03200, 0x03600, 0x03a00, 0x03e00, 0x04200 },
	},
	.dspp = {
		.count = 3,
		.base = { 0x04600, 0x04a00, 0x04e00 },
	},
	.ad = {
		.count = 2,
		.base = { 0x13100, 0x13300 }, /* NOTE: no ad in v1.0 */
	},
	.intf = {
		.count = 4,
		.base = { 0x12500, 0x12700, 0x12900, 0x12b00 },
	},
	.max_clk = 200000000,
};

static const struct mdp5_config apq8084_config = {
	.name = "apq8084",
	.smp = {
		.mmb_count = 44,
		.mmb_size = 8192,
		.reserved_state[0] = GENMASK(7, 0),	/* first 8 MMBs */
		.reserved[CID_RGB0] = 2,
		.reserved[CID_RGB1] = 2,
		.reserved[CID_RGB2] = 2,
		.reserved[CID_RGB3] = 2,
	},
	.ctl = {
		.count = 5,
		.base = { 0x00600, 0x00700, 0x00800, 0x00900, 0x00a00 },
	},
	.pipe_vig = {
		.count = 4,
		.base = { 0x01200, 0x01600, 0x01a00, 0x01e00 },
	},
	.pipe_rgb = {
		.count = 4,
		.base = { 0x02200, 0x02600, 0x02a00, 0x02e00 },
	},
	.pipe_dma = {
		.count = 2,
		.base = { 0x03200, 0x03600 },
	},
	.lm = {
		.count = 6,
		.base = { 0x03a00, 0x03e00, 0x04200, 0x04600, 0x04a00, 0x04e00 },
	},
	.dspp = {
		.count = 4,
		.base = { 0x05200, 0x05600, 0x05a00, 0x05e00 },

	},
	.ad = {
		.count = 3,
		.base = { 0x13500, 0x13700, 0x13900 },
	},
	.intf = {
		.count = 5,
		.base = { 0x12500, 0x12700, 0x12900, 0x12b00, 0x12d00 },
	},
	.max_clk = 320000000,
};

struct mdp5_config_entry {
	int revision;
	const struct mdp5_config *config;
};

static const struct mdp5_config_entry mdp5_configs[] = {
	{ .revision = 0, .config = &msm8x74_config },
	{ .revision = 2, .config = &msm8x74_config },
	{ .revision = 3, .config = &apq8084_config },
};

static int mdp5_select_hw_cfg(struct msm_kms *kms)
{
	struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
	struct drm_device *dev = mdp5_kms->dev;
	uint32_t version, major, minor;
	int i, ret = 0;

	mdp5_enable(mdp5_kms);
	version = mdp5_read(mdp5_kms, REG_MDP5_MDP_VERSION);
	mdp5_disable(mdp5_kms);

	major = FIELD(version, MDP5_MDP_VERSION_MAJOR);
	minor = FIELD(version, MDP5_MDP_VERSION_MINOR);

	DBG("found MDP5 version v%d.%d", major, minor);

	if (major != 1) {
		dev_err(dev->dev, "unexpected MDP major version: v%d.%d\n",
				major, minor);
		ret = -ENXIO;
		goto out;
	}

	mdp5_kms->rev = minor;

	/* only after mdp5_cfg global pointer's init can we access the hw */
	for (i = 0; i < ARRAY_SIZE(mdp5_configs); i++) {
		if (mdp5_configs[i].revision != minor)
			continue;
		mdp5_kms->hw_cfg = mdp5_cfg = mdp5_configs[i].config;
		break;
	}
	if (unlikely(!mdp5_kms->hw_cfg)) {
		dev_err(dev->dev, "unexpected MDP minor revision: v%d.%d\n",
				major, minor);
		ret = -ENXIO;
		goto out;
	}

	DBG("MDP5: %s config selected", mdp5_kms->hw_cfg->name);

	return 0;
out:
	return ret;
}

static int mdp5_hw_init(struct msm_kms *kms)
{
	struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
	struct drm_device *dev = mdp5_kms->dev;
	int i;

	pm_runtime_get_sync(dev->dev);

	/* Magic unknown register writes:
	 *
	 *    W VBIF:0x004 00000001      (mdss_mdp.c:839)
	 *    W MDP5:0x2e0 0xe9          (mdss_mdp.c:839)
	 *    W MDP5:0x2e4 0x55          (mdss_mdp.c:839)
	 *    W MDP5:0x3ac 0xc0000ccc    (mdss_mdp.c:839)
	 *    W MDP5:0x3b4 0xc0000ccc    (mdss_mdp.c:839)
	 *    W MDP5:0x3bc 0xcccccc      (mdss_mdp.c:839)
	 *    W MDP5:0x4a8 0xcccc0c0     (mdss_mdp.c:839)
	 *    W MDP5:0x4b0 0xccccc0c0    (mdss_mdp.c:839)
	 *    W MDP5:0x4b8 0xccccc000    (mdss_mdp.c:839)
	 *
	 * Downstream fbdev driver gets these register offsets/values
	 * from DT.. not really sure what these registers are or if
	 * different values for different boards/SoC's, etc.  I guess
	 * they are the golden registers.
	 *
	 * Not setting these does not seem to cause any problem.  But
	 * we may be getting lucky with the bootloader initializing
	 * them for us.  OTOH, if we can always count on the bootloader
	 * setting the golden registers, then perhaps we don't need to
	 * care.
	 */

	mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, 0);

	for (i = 0; i < mdp5_kms->hw_cfg->ctl.count; i++)
		mdp5_write(mdp5_kms, REG_MDP5_CTL_OP(i), 0);

	pm_runtime_put_sync(dev->dev);

	return 0;
}

static long mdp5_round_pixclk(struct msm_kms *kms, unsigned long rate,
		struct drm_encoder *encoder)
{
	return rate;
}

static void mdp5_preclose(struct msm_kms *kms, struct drm_file *file)
{
	struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
	struct msm_drm_private *priv = mdp5_kms->dev->dev_private;
	unsigned i;

	for (i = 0; i < priv->num_crtcs; i++)
		mdp5_crtc_cancel_pending_flip(priv->crtcs[i], file);
}

static void mdp5_destroy(struct msm_kms *kms)
{
	struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
	struct msm_mmu *mmu = mdp5_kms->mmu;
	void *smp = mdp5_kms->smp_priv;

	mdp5_irq_domain_fini(mdp5_kms);

	if (mmu) {
		mmu->funcs->detach(mmu, iommu_ports, ARRAY_SIZE(iommu_ports));
		mmu->funcs->destroy(mmu);
	}

	if (smp)
		mdp5_smp_destroy(smp);

	kfree(mdp5_kms);
}

static const struct mdp_kms_funcs kms_funcs = {
	.base = {
		.hw_init         = mdp5_hw_init,
		.irq_preinstall  = mdp5_irq_preinstall,
		.irq_postinstall = mdp5_irq_postinstall,
		.irq_uninstall   = mdp5_irq_uninstall,
		.irq             = mdp5_irq,
		.enable_vblank   = mdp5_enable_vblank,
		.disable_vblank  = mdp5_disable_vblank,
		.get_format      = mdp_get_format,
		.round_pixclk    = mdp5_round_pixclk,
		.preclose        = mdp5_preclose,
		.destroy         = mdp5_destroy,
	},
	.set_irqmask         = mdp5_set_irqmask,
};

int mdp5_disable(struct mdp5_kms *mdp5_kms)
{
	DBG("");

	clk_disable_unprepare(mdp5_kms->ahb_clk);
	clk_disable_unprepare(mdp5_kms->axi_clk);
	clk_disable_unprepare(mdp5_kms->core_clk);
	clk_disable_unprepare(mdp5_kms->lut_clk);

	return 0;
}

int mdp5_enable(struct mdp5_kms *mdp5_kms)
{
	DBG("");

	clk_prepare_enable(mdp5_kms->ahb_clk);
	clk_prepare_enable(mdp5_kms->axi_clk);
	clk_prepare_enable(mdp5_kms->core_clk);
	clk_prepare_enable(mdp5_kms->lut_clk);

	return 0;
}

static int modeset_init(struct mdp5_kms *mdp5_kms)
{
	static const enum mdp5_pipe crtcs[] = {
			SSPP_RGB0, SSPP_RGB1, SSPP_RGB2, SSPP_RGB3,
	};
	struct drm_device *dev = mdp5_kms->dev;
	struct msm_drm_private *priv = dev->dev_private;
	struct drm_encoder *encoder;
	int i, ret;

	/* register our interrupt-controller for hdmi/eDP/dsi/etc
	 * to use for irqs routed through mdp:
	 */
	ret = mdp5_irq_domain_init(mdp5_kms);
	if (ret)
		goto fail;

	/* construct CRTCs: */
	for (i = 0; i < mdp5_kms->hw_cfg->pipe_rgb.count; i++) {
		struct drm_plane *plane;
		struct drm_crtc *crtc;

		plane = mdp5_plane_init(dev, crtcs[i], true);
		if (IS_ERR(plane)) {
			ret = PTR_ERR(plane);
			dev_err(dev->dev, "failed to construct plane for %s (%d)\n",
					pipe2name(crtcs[i]), ret);
			goto fail;
		}

		crtc  = mdp5_crtc_init(dev, plane, i);
		if (IS_ERR(crtc)) {
			ret = PTR_ERR(crtc);
			dev_err(dev->dev, "failed to construct crtc for %s (%d)\n",
					pipe2name(crtcs[i]), ret);
			goto fail;
		}
		priv->crtcs[priv->num_crtcs++] = crtc;
	}

	/* Construct encoder for HDMI: */
	encoder = mdp5_encoder_init(dev, 3, INTF_HDMI);
	if (IS_ERR(encoder)) {
		dev_err(dev->dev, "failed to construct encoder\n");
		ret = PTR_ERR(encoder);
		goto fail;
	}

	/* NOTE: the vsync and error irq's are actually associated with
	 * the INTF/encoder.. the easiest way to deal with this (ie. what
	 * we do now) is assume a fixed relationship between crtc's and
	 * encoders.  I'm not sure if there is ever a need to more freely
	 * assign crtcs to encoders, but if there is then we need to take
	 * care of error and vblank irq's that the crtc has registered,
	 * and also update user-requested vblank_mask.
	 */
	encoder->possible_crtcs = BIT(0);
	mdp5_crtc_set_intf(priv->crtcs[0], 3, INTF_HDMI);

	priv->encoders[priv->num_encoders++] = encoder;

	/* Construct bridge/connector for HDMI: */
	if (priv->hdmi) {
		ret = hdmi_modeset_init(priv->hdmi, dev, encoder);
		if (ret) {
			dev_err(dev->dev, "failed to initialize HDMI: %d\n", ret);
			goto fail;
		}
	}

	return 0;

fail:
	return ret;
}

static int get_clk(struct platform_device *pdev, struct clk **clkp,
		const char *name)
{
	struct device *dev = &pdev->dev;
	struct clk *clk = devm_clk_get(dev, name);
	if (IS_ERR(clk)) {
		dev_err(dev, "failed to get %s (%ld)\n", name, PTR_ERR(clk));
		return PTR_ERR(clk);
	}
	*clkp = clk;
	return 0;
}

struct msm_kms *mdp5_kms_init(struct drm_device *dev)
{
	struct platform_device *pdev = dev->platformdev;
	struct mdp5_platform_config *config = mdp5_get_config(pdev);
	struct mdp5_kms *mdp5_kms;
	struct msm_kms *kms = NULL;
	struct msm_mmu *mmu;
	void *priv;
	int i, ret;

	mdp5_kms = kzalloc(sizeof(*mdp5_kms), GFP_KERNEL);
	if (!mdp5_kms) {
		dev_err(dev->dev, "failed to allocate kms\n");
		ret = -ENOMEM;
		goto fail;
	}

	mdp_kms_init(&mdp5_kms->base, &kms_funcs);

	kms = &mdp5_kms->base.base;

	mdp5_kms->dev = dev;

	mdp5_kms->mmio = msm_ioremap(pdev, "mdp_phys", "MDP5");
	if (IS_ERR(mdp5_kms->mmio)) {
		ret = PTR_ERR(mdp5_kms->mmio);
		goto fail;
	}

	mdp5_kms->vbif = msm_ioremap(pdev, "vbif_phys", "VBIF");
	if (IS_ERR(mdp5_kms->vbif)) {
		ret = PTR_ERR(mdp5_kms->vbif);
		goto fail;
	}

	mdp5_kms->vdd = devm_regulator_get(&pdev->dev, "vdd");
	if (IS_ERR(mdp5_kms->vdd)) {
		ret = PTR_ERR(mdp5_kms->vdd);
		goto fail;
	}

	ret = regulator_enable(mdp5_kms->vdd);
	if (ret) {
		dev_err(dev->dev, "failed to enable regulator vdd: %d\n", ret);
		goto fail;
	}

	ret = get_clk(pdev, &mdp5_kms->axi_clk, "bus_clk");
	if (ret)
		goto fail;
	ret = get_clk(pdev, &mdp5_kms->ahb_clk, "iface_clk");
	if (ret)
		goto fail;
	ret = get_clk(pdev, &mdp5_kms->src_clk, "core_clk_src");
	if (ret)
		goto fail;
	ret = get_clk(pdev, &mdp5_kms->core_clk, "core_clk");
	if (ret)
		goto fail;
	ret = get_clk(pdev, &mdp5_kms->lut_clk, "lut_clk");
	if (ret)
		goto fail;
	ret = get_clk(pdev, &mdp5_kms->vsync_clk, "vsync_clk");
	if (ret)
		goto fail;

	ret = mdp5_select_hw_cfg(kms);
	if (ret)
		goto fail;

	/* TODO: compute core clock rate at runtime */
	clk_set_rate(mdp5_kms->src_clk, mdp5_kms->hw_cfg->max_clk);

	priv = mdp5_smp_init(mdp5_kms->dev, &mdp5_kms->hw_cfg->smp);
	if (IS_ERR(priv)) {
		ret = PTR_ERR(priv);
		goto fail;
	}
	mdp5_kms->smp_priv = priv;

	/* make sure things are off before attaching iommu (bootloader could
	 * have left things on, in which case we'll start getting faults if
	 * we don't disable):
	 */
	mdp5_enable(mdp5_kms);
	for (i = 0; i < mdp5_kms->hw_cfg->intf.count; i++)
		mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(i), 0);
	mdp5_disable(mdp5_kms);
	mdelay(16);

	if (config->iommu) {
		mmu = msm_iommu_new(&pdev->dev, config->iommu);
		if (IS_ERR(mmu)) {
			ret = PTR_ERR(mmu);
			dev_err(dev->dev, "failed to init iommu: %d\n", ret);
			goto fail;
		}

		ret = mmu->funcs->attach(mmu, iommu_ports,
				ARRAY_SIZE(iommu_ports));
		if (ret) {
			dev_err(dev->dev, "failed to attach iommu: %d\n", ret);
			mmu->funcs->destroy(mmu);
			goto fail;
		}
	} else {
		dev_info(dev->dev, "no iommu, fallback to phys "
				"contig buffers for scanout\n");
		mmu = NULL;
	}
	mdp5_kms->mmu = mmu;

	mdp5_kms->id = msm_register_mmu(dev, mmu);
	if (mdp5_kms->id < 0) {
		ret = mdp5_kms->id;
		dev_err(dev->dev, "failed to register mdp5 iommu: %d\n", ret);
		goto fail;
	}

	ret = modeset_init(mdp5_kms);
	if (ret) {
		dev_err(dev->dev, "modeset_init failed: %d\n", ret);
		goto fail;
	}

	return kms;

fail:
	if (kms)
		mdp5_destroy(kms);
	return ERR_PTR(ret);
}

static struct mdp5_platform_config *mdp5_get_config(struct platform_device *dev)
{
	static struct mdp5_platform_config config = {};
#ifdef CONFIG_OF
	/* TODO */
#endif
	config.iommu = iommu_domain_alloc(&platform_bus_type);

	return &config;
}
Commit	Line	Data
06c0dd96 RC	1	/*
	2	* Copyright (C) 2013 Red Hat
	3	* Author: Rob Clark <robdclark@gmail.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of the GNU General Public License version 2 as published by
	7	* the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along with
	15	* this program. If not, see <http://www.gnu.org/licenses/>.
	16	*/
	17
	18
	19	#include "msm_drv.h"
	20	#include "msm_mmu.h"
	21	#include "mdp5_kms.h"
	22
87e956e9 SV	23	static const char *iommu_ports[] = {
	24	"mdp_0",
	25	};
	26
06c0dd96 RC	27	static struct mdp5_platform_config mdp5_get_config(struct platform_device dev);
06c0dd96 RC	28
3d47fd47 SV	29	const struct mdp5_config *mdp5_cfg;
	30
	31	static const struct mdp5_config msm8x74_config = {
	32	.name = "msm8x74",
bfcdfb0e SV	33	.smp = {
	34	.mmb_count = 22,
	35	.mmb_size = 4096,
	36	},
3d47fd47 SV	37	.ctl = {
	38	.count = 5,
	39	.base = { 0x00600, 0x00700, 0x00800, 0x00900, 0x00a00 },
	40	},
	41	.pipe_vig = {
	42	.count = 3,
	43	.base = { 0x01200, 0x01600, 0x01a00 },
	44	},
	45	.pipe_rgb = {
	46	.count = 3,
	47	.base = { 0x01e00, 0x02200, 0x02600 },
	48	},
	49	.pipe_dma = {
	50	.count = 2,
	51	.base = { 0x02a00, 0x02e00 },
	52	},
	53	.lm = {
	54	.count = 5,
	55	.base = { 0x03200, 0x03600, 0x03a00, 0x03e00, 0x04200 },
	56	},
	57	.dspp = {
	58	.count = 3,
	59	.base = { 0x04600, 0x04a00, 0x04e00 },
	60	},
	61	.ad = {
	62	.count = 2,
	63	.base = { 0x13100, 0x13300 }, /* NOTE: no ad in v1.0 */
	64	},
	65	.intf = {
	66	.count = 4,
	67	.base = { 0x12500, 0x12700, 0x12900, 0x12b00 },
	68	},
3f307963	69	.max_clk = 200000000,
3d47fd47 SV	70	};
	71
	72	static const struct mdp5_config apq8084_config = {
	73	.name = "apq8084",
bfcdfb0e SV	74	.smp = {
	75	.mmb_count = 44,
	76	.mmb_size = 8192,
	77	.reserved_state[0] = GENMASK(7, 0), /* first 8 MMBs */
	78	.reserved[CID_RGB0] = 2,
	79	.reserved[CID_RGB1] = 2,
	80	.reserved[CID_RGB2] = 2,
	81	.reserved[CID_RGB3] = 2,
	82	},
3d47fd47 SV	83	.ctl = {
	84	.count = 5,
	85	.base = { 0x00600, 0x00700, 0x00800, 0x00900, 0x00a00 },
	86	},
	87	.pipe_vig = {
	88	.count = 4,
	89	.base = { 0x01200, 0x01600, 0x01a00, 0x01e00 },
	90	},
	91	.pipe_rgb = {
	92	.count = 4,
	93	.base = { 0x02200, 0x02600, 0x02a00, 0x02e00 },
	94	},
	95	.pipe_dma = {
	96	.count = 2,
	97	.base = { 0x03200, 0x03600 },
	98	},
	99	.lm = {
	100	.count = 6,
	101	.base = { 0x03a00, 0x03e00, 0x04200, 0x04600, 0x04a00, 0x04e00 },
	102	},
	103	.dspp = {
	104	.count = 4,
	105	.base = { 0x05200, 0x05600, 0x05a00, 0x05e00 },
	106
	107	},
	108	.ad = {
	109	.count = 3,
	110	.base = { 0x13500, 0x13700, 0x13900 },
	111	},
	112	.intf = {
	113	.count = 5,
	114	.base = { 0x12500, 0x12700, 0x12900, 0x12b00, 0x12d00 },
	115	},
3f307963	116	.max_clk = 320000000,
3d47fd47 SV	117	};
	118
	119	struct mdp5_config_entry {
	120	int revision;
	121	const struct mdp5_config *config;
	122	};
	123
	124	static const struct mdp5_config_entry mdp5_configs[] = {
	125	{ .revision = 0, .config = &msm8x74_config },
	126	{ .revision = 2, .config = &msm8x74_config },
	127	{ .revision = 3, .config = &apq8084_config },
	128	};
	129
	130	static int mdp5_select_hw_cfg(struct msm_kms *kms)
06c0dd96 RC	131	{
	132	struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
	133	struct drm_device *dev = mdp5_kms->dev;
	134	uint32_t version, major, minor;
3d47fd47	135	int i, ret = 0;
06c0dd96 RC	136
	137	mdp5_enable(mdp5_kms);
	138	version = mdp5_read(mdp5_kms, REG_MDP5_MDP_VERSION);
	139	mdp5_disable(mdp5_kms);
	140
	141	major = FIELD(version, MDP5_MDP_VERSION_MAJOR);
	142	minor = FIELD(version, MDP5_MDP_VERSION_MINOR);
	143
	144	DBG("found MDP5 version v%d.%d", major, minor);
	145
3d47fd47 SV	146	if (major != 1) {
3d47fd47 SV	147	dev_err(dev->dev, "unexpected MDP major version: v%d.%d\n",
06c0dd96 RC	148	major, minor);
	149	ret = -ENXIO;
	150	goto out;
	151	}
	152
	153	mdp5_kms->rev = minor;
	154
3d47fd47 SV	155	/* only after mdp5_cfg global pointer's init can we access the hw */
	156	for (i = 0; i < ARRAY_SIZE(mdp5_configs); i++) {
	157	if (mdp5_configs[i].revision != minor)
	158	continue;
	159	mdp5_kms->hw_cfg = mdp5_cfg = mdp5_configs[i].config;
	160	break;
	161	}
	162	if (unlikely(!mdp5_kms->hw_cfg)) {
	163	dev_err(dev->dev, "unexpected MDP minor revision: v%d.%d\n",
	164	major, minor);
	165	ret = -ENXIO;
	166	goto out;
	167	}
	168
	169	DBG("MDP5: %s config selected", mdp5_kms->hw_cfg->name);
	170
	171	return 0;
	172	out:
	173	return ret;
	174	}
	175
	176	static int mdp5_hw_init(struct msm_kms *kms)
	177	{
	178	struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
	179	struct drm_device *dev = mdp5_kms->dev;
	180	int i;
	181
	182	pm_runtime_get_sync(dev->dev);
	183
06c0dd96 RC	184	/* Magic unknown register writes:
	185	*
	186	* W VBIF:0x004 00000001 (mdss_mdp.c:839)
	187	* W MDP5:0x2e0 0xe9 (mdss_mdp.c:839)
	188	* W MDP5:0x2e4 0x55 (mdss_mdp.c:839)
	189	* W MDP5:0x3ac 0xc0000ccc (mdss_mdp.c:839)
	190	* W MDP5:0x3b4 0xc0000ccc (mdss_mdp.c:839)
	191	* W MDP5:0x3bc 0xcccccc (mdss_mdp.c:839)
	192	* W MDP5:0x4a8 0xcccc0c0 (mdss_mdp.c:839)
	193	* W MDP5:0x4b0 0xccccc0c0 (mdss_mdp.c:839)
	194	* W MDP5:0x4b8 0xccccc000 (mdss_mdp.c:839)
	195	*
	196	* Downstream fbdev driver gets these register offsets/values
	197	* from DT.. not really sure what these registers are or if
	198	* different values for different boards/SoC's, etc. I guess
	199	* they are the golden registers.
	200	*
	201	* Not setting these does not seem to cause any problem. But
	202	* we may be getting lucky with the bootloader initializing
	203	* them for us. OTOH, if we can always count on the bootloader
	204	* setting the golden registers, then perhaps we don't need to
	205	* care.
	206	*/
	207
	208	mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, 0);
06c0dd96	209
3d47fd47 SV	210	for (i = 0; i < mdp5_kms->hw_cfg->ctl.count; i++)
	211	mdp5_write(mdp5_kms, REG_MDP5_CTL_OP(i), 0);
	212
06c0dd96 RC	213	pm_runtime_put_sync(dev->dev);
06c0dd96 RC	214
3d47fd47	215	return 0;
06c0dd96 RC	216	}
	217
	218	static long mdp5_round_pixclk(struct msm_kms *kms, unsigned long rate,
	219	struct drm_encoder *encoder)
	220	{
	221	return rate;
	222	}
	223
	224	static void mdp5_preclose(struct msm_kms kms, struct drm_file file)
	225	{
	226	struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
	227	struct msm_drm_private *priv = mdp5_kms->dev->dev_private;
	228	unsigned i;
	229
	230	for (i = 0; i < priv->num_crtcs; i++)
	231	mdp5_crtc_cancel_pending_flip(priv->crtcs[i], file);
	232	}
	233
	234	static void mdp5_destroy(struct msm_kms *kms)
	235	{
	236	struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
87e956e9	237	struct msm_mmu *mmu = mdp5_kms->mmu;
bfcdfb0e	238	void *smp = mdp5_kms->smp_priv;
87e956e9	239
f6a8eaca RC	240	mdp5_irq_domain_fini(mdp5_kms);
f6a8eaca RC	241
87e956e9 SV	242	if (mmu) {
	243	mmu->funcs->detach(mmu, iommu_ports, ARRAY_SIZE(iommu_ports));
	244	mmu->funcs->destroy(mmu);
	245	}
f6a8eaca	246
bfcdfb0e SV	247	if (smp)
	248	mdp5_smp_destroy(smp);
	249
06c0dd96 RC	250	kfree(mdp5_kms);
	251	}
	252
	253	static const struct mdp_kms_funcs kms_funcs = {
	254	.base = {
	255	.hw_init = mdp5_hw_init,
	256	.irq_preinstall = mdp5_irq_preinstall,
	257	.irq_postinstall = mdp5_irq_postinstall,
	258	.irq_uninstall = mdp5_irq_uninstall,
	259	.irq = mdp5_irq,
	260	.enable_vblank = mdp5_enable_vblank,
	261	.disable_vblank = mdp5_disable_vblank,
	262	.get_format = mdp_get_format,
	263	.round_pixclk = mdp5_round_pixclk,
	264	.preclose = mdp5_preclose,
	265	.destroy = mdp5_destroy,
	266	},
	267	.set_irqmask = mdp5_set_irqmask,
	268	};
	269
	270	int mdp5_disable(struct mdp5_kms *mdp5_kms)
	271	{
	272	DBG("");
	273
	274	clk_disable_unprepare(mdp5_kms->ahb_clk);
	275	clk_disable_unprepare(mdp5_kms->axi_clk);
	276	clk_disable_unprepare(mdp5_kms->core_clk);
	277	clk_disable_unprepare(mdp5_kms->lut_clk);
	278
	279	return 0;
	280	}
	281
	282	int mdp5_enable(struct mdp5_kms *mdp5_kms)
	283	{
	284	DBG("");
	285
	286	clk_prepare_enable(mdp5_kms->ahb_clk);
	287	clk_prepare_enable(mdp5_kms->axi_clk);
	288	clk_prepare_enable(mdp5_kms->core_clk);
	289	clk_prepare_enable(mdp5_kms->lut_clk);
	290
	291	return 0;
	292	}
	293
	294	static int modeset_init(struct mdp5_kms *mdp5_kms)
	295	{
	296	static const enum mdp5_pipe crtcs[] = {
3d47fd47	297	SSPP_RGB0, SSPP_RGB1, SSPP_RGB2, SSPP_RGB3,
06c0dd96 RC	298	};
	299	struct drm_device *dev = mdp5_kms->dev;
	300	struct msm_drm_private *priv = dev->dev_private;
	301	struct drm_encoder *encoder;
	302	int i, ret;
	303
f6a8eaca RC	304	/* register our interrupt-controller for hdmi/eDP/dsi/etc
	305	* to use for irqs routed through mdp:
	306	*/
	307	ret = mdp5_irq_domain_init(mdp5_kms);
	308	if (ret)
	309	goto fail;
	310
06c0dd96	311	/* construct CRTCs: */
3d47fd47	312	for (i = 0; i < mdp5_kms->hw_cfg->pipe_rgb.count; i++) {
06c0dd96 RC	313	struct drm_plane *plane;
	314	struct drm_crtc *crtc;
	315
	316	plane = mdp5_plane_init(dev, crtcs[i], true);
	317	if (IS_ERR(plane)) {
	318	ret = PTR_ERR(plane);
	319	dev_err(dev->dev, "failed to construct plane for %s (%d)\n",
	320	pipe2name(crtcs[i]), ret);
	321	goto fail;
	322	}
	323
	324	crtc = mdp5_crtc_init(dev, plane, i);
	325	if (IS_ERR(crtc)) {
	326	ret = PTR_ERR(crtc);
	327	dev_err(dev->dev, "failed to construct crtc for %s (%d)\n",
	328	pipe2name(crtcs[i]), ret);
	329	goto fail;
	330	}
	331	priv->crtcs[priv->num_crtcs++] = crtc;
	332	}
	333
	334	/* Construct encoder for HDMI: */
	335	encoder = mdp5_encoder_init(dev, 3, INTF_HDMI);
	336	if (IS_ERR(encoder)) {
	337	dev_err(dev->dev, "failed to construct encoder\n");
	338	ret = PTR_ERR(encoder);
	339	goto fail;
	340	}
	341
	342	/* NOTE: the vsync and error irq's are actually associated with
	343	* the INTF/encoder.. the easiest way to deal with this (ie. what
	344	* we do now) is assume a fixed relationship between crtc's and
	345	* encoders. I'm not sure if there is ever a need to more freely
	346	* assign crtcs to encoders, but if there is then we need to take
	347	* care of error and vblank irq's that the crtc has registered,
	348	* and also update user-requested vblank_mask.
	349	*/
	350	encoder->possible_crtcs = BIT(0);
	351	mdp5_crtc_set_intf(priv->crtcs[0], 3, INTF_HDMI);
	352
	353	priv->encoders[priv->num_encoders++] = encoder;
	354
	355	/* Construct bridge/connector for HDMI: */
067fef37 RC	356	if (priv->hdmi) {
	357	ret = hdmi_modeset_init(priv->hdmi, dev, encoder);
	358	if (ret) {
	359	dev_err(dev->dev, "failed to initialize HDMI: %d\n", ret);
	360	goto fail;
	361	}
06c0dd96 RC	362	}
	363
	364	return 0;
	365
	366	fail:
	367	return ret;
	368	}
	369
06c0dd96 RC	370	static int get_clk(struct platform_device pdev, struct clk *clkp,
	371	const char *name)
	372	{
	373	struct device *dev = &pdev->dev;
	374	struct clk *clk = devm_clk_get(dev, name);
	375	if (IS_ERR(clk)) {
	376	dev_err(dev, "failed to get %s (%ld)\n", name, PTR_ERR(clk));
	377	return PTR_ERR(clk);
	378	}
	379	*clkp = clk;
	380	return 0;
	381	}
	382
	383	struct msm_kms mdp5_kms_init(struct drm_device dev)
	384	{
	385	struct platform_device *pdev = dev->platformdev;
	386	struct mdp5_platform_config *config = mdp5_get_config(pdev);
	387	struct mdp5_kms *mdp5_kms;
	388	struct msm_kms *kms = NULL;
	389	struct msm_mmu *mmu;
bfcdfb0e	390	void *priv;
3d47fd47	391	int i, ret;
06c0dd96 RC	392
	393	mdp5_kms = kzalloc(sizeof(*mdp5_kms), GFP_KERNEL);
	394	if (!mdp5_kms) {
	395	dev_err(dev->dev, "failed to allocate kms\n");
	396	ret = -ENOMEM;
	397	goto fail;
	398	}
	399
	400	mdp_kms_init(&mdp5_kms->base, &kms_funcs);
	401
	402	kms = &mdp5_kms->base.base;
	403
	404	mdp5_kms->dev = dev;
06c0dd96 RC	405
	406	mdp5_kms->mmio = msm_ioremap(pdev, "mdp_phys", "MDP5");
	407	if (IS_ERR(mdp5_kms->mmio)) {
	408	ret = PTR_ERR(mdp5_kms->mmio);
	409	goto fail;
	410	}
	411
	412	mdp5_kms->vbif = msm_ioremap(pdev, "vbif_phys", "VBIF");
	413	if (IS_ERR(mdp5_kms->vbif)) {
	414	ret = PTR_ERR(mdp5_kms->vbif);
	415	goto fail;
	416	}
	417
	418	mdp5_kms->vdd = devm_regulator_get(&pdev->dev, "vdd");
	419	if (IS_ERR(mdp5_kms->vdd)) {
	420	ret = PTR_ERR(mdp5_kms->vdd);
	421	goto fail;
	422	}
	423
	424	ret = regulator_enable(mdp5_kms->vdd);
	425	if (ret) {
	426	dev_err(dev->dev, "failed to enable regulator vdd: %d\n", ret);
	427	goto fail;
	428	}
	429
a0906a02 RC	430	ret = get_clk(pdev, &mdp5_kms->axi_clk, "bus_clk");
	431	if (ret)
	432	goto fail;
	433	ret = get_clk(pdev, &mdp5_kms->ahb_clk, "iface_clk");
	434	if (ret)
	435	goto fail;
	436	ret = get_clk(pdev, &mdp5_kms->src_clk, "core_clk_src");
	437	if (ret)
	438	goto fail;
	439	ret = get_clk(pdev, &mdp5_kms->core_clk, "core_clk");
	440	if (ret)
	441	goto fail;
	442	ret = get_clk(pdev, &mdp5_kms->lut_clk, "lut_clk");
	443	if (ret)
	444	goto fail;
	445	ret = get_clk(pdev, &mdp5_kms->vsync_clk, "vsync_clk");
06c0dd96 RC	446	if (ret)
	447	goto fail;
	448
3d47fd47 SV	449	ret = mdp5_select_hw_cfg(kms);
	450	if (ret)
	451	goto fail;
	452
3f307963 SV	453	/* TODO: compute core clock rate at runtime */
	454	clk_set_rate(mdp5_kms->src_clk, mdp5_kms->hw_cfg->max_clk);
	455
bfcdfb0e SV	456	priv = mdp5_smp_init(mdp5_kms->dev, &mdp5_kms->hw_cfg->smp);
	457	if (IS_ERR(priv)) {
	458	ret = PTR_ERR(priv);
	459	goto fail;
	460	}
	461	mdp5_kms->smp_priv = priv;
	462
06c0dd96 RC	463	/* make sure things are off before attaching iommu (bootloader could
	464	* have left things on, in which case we'll start getting faults if
	465	* we don't disable):
	466	*/
	467	mdp5_enable(mdp5_kms);
3d47fd47 SV	468	for (i = 0; i < mdp5_kms->hw_cfg->intf.count; i++)
3d47fd47 SV	469	mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(i), 0);
06c0dd96 RC	470	mdp5_disable(mdp5_kms);
	471	mdelay(16);
	472
	473	if (config->iommu) {
944fc36c	474	mmu = msm_iommu_new(&pdev->dev, config->iommu);
06c0dd96 RC	475	if (IS_ERR(mmu)) {
06c0dd96 RC	476	ret = PTR_ERR(mmu);
87e956e9	477	dev_err(dev->dev, "failed to init iommu: %d\n", ret);
06c0dd96 RC	478	goto fail;
06c0dd96 RC	479	}
87e956e9	480
06c0dd96 RC	481	ret = mmu->funcs->attach(mmu, iommu_ports,
06c0dd96 RC	482	ARRAY_SIZE(iommu_ports));
87e956e9 SV	483	if (ret) {
	484	dev_err(dev->dev, "failed to attach iommu: %d\n", ret);
	485	mmu->funcs->destroy(mmu);
06c0dd96	486	goto fail;
87e956e9	487	}
06c0dd96 RC	488	} else {
	489	dev_info(dev->dev, "no iommu, fallback to phys "
	490	"contig buffers for scanout\n");
	491	mmu = NULL;
	492	}
87e956e9	493	mdp5_kms->mmu = mmu;
06c0dd96 RC	494
	495	mdp5_kms->id = msm_register_mmu(dev, mmu);
	496	if (mdp5_kms->id < 0) {
	497	ret = mdp5_kms->id;
	498	dev_err(dev->dev, "failed to register mdp5 iommu: %d\n", ret);
	499	goto fail;
	500	}
	501
	502	ret = modeset_init(mdp5_kms);
	503	if (ret) {
	504	dev_err(dev->dev, "modeset_init failed: %d\n", ret);
	505	goto fail;
	506	}
	507
	508	return kms;
	509
	510	fail:
	511	if (kms)
	512	mdp5_destroy(kms);
	513	return ERR_PTR(ret);
	514	}
	515
	516	static struct mdp5_platform_config mdp5_get_config(struct platform_device dev)
	517	{
	518	static struct mdp5_platform_config config = {};
	519	#ifdef CONFIG_OF
	520	/* TODO */
	521	#endif
3bf6c1ec	522	config.iommu = iommu_domain_alloc(&platform_bus_type);
3bf6c1ec	523
06c0dd96 RC	524	return &config;
06c0dd96 RC	525	}