Commit | Line | Data |
---|---|---|
06c0dd96 | 1 | /* |
2e362e17 | 2 | * Copyright (c) 2014, The Linux Foundation. All rights reserved. |
06c0dd96 RC |
3 | * Copyright (C) 2013 Red Hat |
4 | * Author: Rob Clark <robdclark@gmail.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published by | |
8 | * the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along with | |
16 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | ||
aec095ec | 19 | #include <linux/of_irq.h> |
06c0dd96 RC |
20 | |
21 | #include "msm_drv.h" | |
667ce33e | 22 | #include "msm_gem.h" |
06c0dd96 RC |
23 | #include "msm_mmu.h" |
24 | #include "mdp5_kms.h" | |
25 | ||
87e956e9 SV |
26 | static const char *iommu_ports[] = { |
27 | "mdp_0", | |
28 | }; | |
29 | ||
3d47fd47 SV |
30 | static int mdp5_hw_init(struct msm_kms *kms) |
31 | { | |
32 | struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); | |
0a6030d2 | 33 | struct platform_device *pdev = mdp5_kms->pdev; |
0deed25b | 34 | unsigned long flags; |
3d47fd47 | 35 | |
0a6030d2 | 36 | pm_runtime_get_sync(&pdev->dev); |
7c8f0235 | 37 | mdp5_enable(mdp5_kms); |
3d47fd47 | 38 | |
06c0dd96 RC |
39 | /* Magic unknown register writes: |
40 | * | |
41 | * W VBIF:0x004 00000001 (mdss_mdp.c:839) | |
42 | * W MDP5:0x2e0 0xe9 (mdss_mdp.c:839) | |
43 | * W MDP5:0x2e4 0x55 (mdss_mdp.c:839) | |
44 | * W MDP5:0x3ac 0xc0000ccc (mdss_mdp.c:839) | |
45 | * W MDP5:0x3b4 0xc0000ccc (mdss_mdp.c:839) | |
46 | * W MDP5:0x3bc 0xcccccc (mdss_mdp.c:839) | |
47 | * W MDP5:0x4a8 0xcccc0c0 (mdss_mdp.c:839) | |
48 | * W MDP5:0x4b0 0xccccc0c0 (mdss_mdp.c:839) | |
49 | * W MDP5:0x4b8 0xccccc000 (mdss_mdp.c:839) | |
50 | * | |
51 | * Downstream fbdev driver gets these register offsets/values | |
52 | * from DT.. not really sure what these registers are or if | |
53 | * different values for different boards/SoC's, etc. I guess | |
54 | * they are the golden registers. | |
55 | * | |
56 | * Not setting these does not seem to cause any problem. But | |
57 | * we may be getting lucky with the bootloader initializing | |
58 | * them for us. OTOH, if we can always count on the bootloader | |
59 | * setting the golden registers, then perhaps we don't need to | |
60 | * care. | |
61 | */ | |
62 | ||
0deed25b | 63 | spin_lock_irqsave(&mdp5_kms->resource_lock, flags); |
7b59c7e4 | 64 | mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, 0); |
0deed25b | 65 | spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags); |
06c0dd96 | 66 | |
42238da8 | 67 | mdp5_ctlm_hw_reset(mdp5_kms->ctlm); |
3d47fd47 | 68 | |
7c8f0235 | 69 | mdp5_disable(mdp5_kms); |
0a6030d2 | 70 | pm_runtime_put_sync(&pdev->dev); |
06c0dd96 | 71 | |
3d47fd47 | 72 | return 0; |
06c0dd96 RC |
73 | } |
74 | ||
ac2a3fd3 RC |
75 | struct mdp5_state *mdp5_get_state(struct drm_atomic_state *s) |
76 | { | |
77 | struct msm_drm_private *priv = s->dev->dev_private; | |
78 | struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); | |
79 | struct msm_kms_state *state = to_kms_state(s); | |
80 | struct mdp5_state *new_state; | |
81 | int ret; | |
82 | ||
83 | if (state->state) | |
84 | return state->state; | |
85 | ||
86 | ret = drm_modeset_lock(&mdp5_kms->state_lock, s->acquire_ctx); | |
87 | if (ret) | |
88 | return ERR_PTR(ret); | |
89 | ||
90 | new_state = kmalloc(sizeof(*mdp5_kms->state), GFP_KERNEL); | |
91 | if (!new_state) | |
92 | return ERR_PTR(-ENOMEM); | |
93 | ||
94 | /* Copy state: */ | |
4a0f012d | 95 | new_state->hwpipe = mdp5_kms->state->hwpipe; |
49ec5b2e RC |
96 | if (mdp5_kms->smp) |
97 | new_state->smp = mdp5_kms->state->smp; | |
ac2a3fd3 RC |
98 | |
99 | state->state = new_state; | |
100 | ||
101 | return new_state; | |
102 | } | |
103 | ||
104 | static void mdp5_swap_state(struct msm_kms *kms, struct drm_atomic_state *state) | |
105 | { | |
106 | struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); | |
107 | swap(to_kms_state(state)->state, mdp5_kms->state); | |
108 | } | |
109 | ||
0b776d45 RC |
110 | static void mdp5_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state) |
111 | { | |
112 | struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); | |
49ec5b2e | 113 | |
0b776d45 | 114 | mdp5_enable(mdp5_kms); |
49ec5b2e RC |
115 | |
116 | if (mdp5_kms->smp) | |
117 | mdp5_smp_prepare_commit(mdp5_kms->smp, &mdp5_kms->state->smp); | |
0b776d45 RC |
118 | } |
119 | ||
120 | static void mdp5_complete_commit(struct msm_kms *kms, struct drm_atomic_state *state) | |
121 | { | |
122 | struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); | |
657c63f0 | 123 | |
49ec5b2e RC |
124 | if (mdp5_kms->smp) |
125 | mdp5_smp_complete_commit(mdp5_kms->smp, &mdp5_kms->state->smp); | |
126 | ||
0b776d45 RC |
127 | mdp5_disable(mdp5_kms); |
128 | } | |
129 | ||
0a5c9aad HL |
130 | static void mdp5_wait_for_crtc_commit_done(struct msm_kms *kms, |
131 | struct drm_crtc *crtc) | |
132 | { | |
133 | mdp5_crtc_wait_for_commit_done(crtc); | |
134 | } | |
135 | ||
06c0dd96 RC |
136 | static long mdp5_round_pixclk(struct msm_kms *kms, unsigned long rate, |
137 | struct drm_encoder *encoder) | |
138 | { | |
139 | return rate; | |
140 | } | |
141 | ||
d5af49c9 HL |
142 | static int mdp5_set_split_display(struct msm_kms *kms, |
143 | struct drm_encoder *encoder, | |
144 | struct drm_encoder *slave_encoder, | |
145 | bool is_cmd_mode) | |
146 | { | |
147 | if (is_cmd_mode) | |
148 | return mdp5_cmd_encoder_set_split_display(encoder, | |
149 | slave_encoder); | |
150 | else | |
151 | return mdp5_encoder_set_split_display(encoder, slave_encoder); | |
152 | } | |
153 | ||
9c9f6f8d AT |
154 | static void mdp5_set_encoder_mode(struct msm_kms *kms, |
155 | struct drm_encoder *encoder, | |
156 | bool cmd_mode) | |
157 | { | |
158 | mdp5_encoder_set_intf_mode(encoder, cmd_mode); | |
159 | } | |
160 | ||
1dd0a0b1 | 161 | static void mdp5_kms_destroy(struct msm_kms *kms) |
06c0dd96 RC |
162 | { |
163 | struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); | |
667ce33e | 164 | struct msm_gem_address_space *aspace = mdp5_kms->aspace; |
c056b55d RC |
165 | int i; |
166 | ||
167 | for (i = 0; i < mdp5_kms->num_hwpipes; i++) | |
168 | mdp5_pipe_destroy(mdp5_kms->hwpipes[i]); | |
87e956e9 | 169 | |
667ce33e RC |
170 | if (aspace) { |
171 | aspace->mmu->funcs->detach(aspace->mmu, | |
172 | iommu_ports, ARRAY_SIZE(iommu_ports)); | |
173 | msm_gem_address_space_destroy(aspace); | |
87e956e9 | 174 | } |
aec095ec AT |
175 | } |
176 | ||
bc5289ee RC |
177 | #ifdef CONFIG_DEBUG_FS |
178 | static int smp_show(struct seq_file *m, void *arg) | |
179 | { | |
180 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
181 | struct drm_device *dev = node->minor->dev; | |
182 | struct msm_drm_private *priv = dev->dev_private; | |
183 | struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); | |
184 | struct drm_printer p = drm_seq_file_printer(m); | |
185 | ||
186 | if (!mdp5_kms->smp) { | |
187 | drm_printf(&p, "no SMP pool\n"); | |
188 | return 0; | |
189 | } | |
190 | ||
191 | mdp5_smp_dump(mdp5_kms->smp, &p); | |
192 | ||
193 | return 0; | |
194 | } | |
195 | ||
196 | static struct drm_info_list mdp5_debugfs_list[] = { | |
197 | {"smp", smp_show }, | |
198 | }; | |
199 | ||
200 | static int mdp5_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor) | |
201 | { | |
202 | struct drm_device *dev = minor->dev; | |
203 | int ret; | |
204 | ||
205 | ret = drm_debugfs_create_files(mdp5_debugfs_list, | |
206 | ARRAY_SIZE(mdp5_debugfs_list), | |
207 | minor->debugfs_root, minor); | |
208 | ||
209 | if (ret) { | |
210 | dev_err(dev->dev, "could not install mdp5_debugfs_list\n"); | |
211 | return ret; | |
212 | } | |
213 | ||
214 | return 0; | |
215 | } | |
216 | ||
217 | static void mdp5_kms_debugfs_cleanup(struct msm_kms *kms, struct drm_minor *minor) | |
218 | { | |
219 | drm_debugfs_remove_files(mdp5_debugfs_list, | |
220 | ARRAY_SIZE(mdp5_debugfs_list), minor); | |
221 | } | |
222 | #endif | |
223 | ||
06c0dd96 RC |
224 | static const struct mdp_kms_funcs kms_funcs = { |
225 | .base = { | |
226 | .hw_init = mdp5_hw_init, | |
227 | .irq_preinstall = mdp5_irq_preinstall, | |
228 | .irq_postinstall = mdp5_irq_postinstall, | |
229 | .irq_uninstall = mdp5_irq_uninstall, | |
230 | .irq = mdp5_irq, | |
231 | .enable_vblank = mdp5_enable_vblank, | |
232 | .disable_vblank = mdp5_disable_vblank, | |
ac2a3fd3 | 233 | .swap_state = mdp5_swap_state, |
0b776d45 RC |
234 | .prepare_commit = mdp5_prepare_commit, |
235 | .complete_commit = mdp5_complete_commit, | |
0a5c9aad | 236 | .wait_for_crtc_commit_done = mdp5_wait_for_crtc_commit_done, |
06c0dd96 RC |
237 | .get_format = mdp_get_format, |
238 | .round_pixclk = mdp5_round_pixclk, | |
d5af49c9 | 239 | .set_split_display = mdp5_set_split_display, |
9c9f6f8d | 240 | .set_encoder_mode = mdp5_set_encoder_mode, |
392ae6e0 | 241 | .destroy = mdp5_kms_destroy, |
bc5289ee RC |
242 | #ifdef CONFIG_DEBUG_FS |
243 | .debugfs_init = mdp5_kms_debugfs_init, | |
244 | .debugfs_cleanup = mdp5_kms_debugfs_cleanup, | |
245 | #endif | |
06c0dd96 RC |
246 | }, |
247 | .set_irqmask = mdp5_set_irqmask, | |
248 | }; | |
249 | ||
250 | int mdp5_disable(struct mdp5_kms *mdp5_kms) | |
251 | { | |
252 | DBG(""); | |
253 | ||
254 | clk_disable_unprepare(mdp5_kms->ahb_clk); | |
255 | clk_disable_unprepare(mdp5_kms->axi_clk); | |
256 | clk_disable_unprepare(mdp5_kms->core_clk); | |
3a84f846 SV |
257 | if (mdp5_kms->lut_clk) |
258 | clk_disable_unprepare(mdp5_kms->lut_clk); | |
06c0dd96 RC |
259 | |
260 | return 0; | |
261 | } | |
262 | ||
263 | int mdp5_enable(struct mdp5_kms *mdp5_kms) | |
264 | { | |
265 | DBG(""); | |
266 | ||
267 | clk_prepare_enable(mdp5_kms->ahb_clk); | |
268 | clk_prepare_enable(mdp5_kms->axi_clk); | |
269 | clk_prepare_enable(mdp5_kms->core_clk); | |
3a84f846 SV |
270 | if (mdp5_kms->lut_clk) |
271 | clk_prepare_enable(mdp5_kms->lut_clk); | |
06c0dd96 RC |
272 | |
273 | return 0; | |
274 | } | |
275 | ||
5722a9e3 HL |
276 | static struct drm_encoder *construct_encoder(struct mdp5_kms *mdp5_kms, |
277 | enum mdp5_intf_type intf_type, int intf_num, | |
c71716b1 | 278 | enum mdp5_intf_mode intf_mode, struct mdp5_ctl *ctl) |
67ac0a2d SV |
279 | { |
280 | struct drm_device *dev = mdp5_kms->dev; | |
281 | struct msm_drm_private *priv = dev->dev_private; | |
282 | struct drm_encoder *encoder; | |
283 | struct mdp5_interface intf = { | |
284 | .num = intf_num, | |
285 | .type = intf_type, | |
5722a9e3 | 286 | .mode = intf_mode, |
67ac0a2d | 287 | }; |
67ac0a2d | 288 | |
d5af49c9 HL |
289 | if ((intf_type == INTF_DSI) && |
290 | (intf_mode == MDP5_INTF_DSI_MODE_COMMAND)) | |
c71716b1 | 291 | encoder = mdp5_cmd_encoder_init(dev, &intf, ctl); |
d5af49c9 | 292 | else |
c71716b1 | 293 | encoder = mdp5_encoder_init(dev, &intf, ctl); |
d5af49c9 | 294 | |
67ac0a2d | 295 | if (IS_ERR(encoder)) { |
5722a9e3 HL |
296 | dev_err(dev->dev, "failed to construct encoder\n"); |
297 | return encoder; | |
67ac0a2d SV |
298 | } |
299 | ||
300 | encoder->possible_crtcs = (1 << priv->num_crtcs) - 1; | |
301 | priv->encoders[priv->num_encoders++] = encoder; | |
302 | ||
5722a9e3 HL |
303 | return encoder; |
304 | } | |
305 | ||
d5af49c9 HL |
306 | static int get_dsi_id_from_intf(const struct mdp5_cfg_hw *hw_cfg, int intf_num) |
307 | { | |
fe34464d SV |
308 | const enum mdp5_intf_type *intfs = hw_cfg->intf.connect; |
309 | const int intf_cnt = ARRAY_SIZE(hw_cfg->intf.connect); | |
d5af49c9 HL |
310 | int id = 0, i; |
311 | ||
312 | for (i = 0; i < intf_cnt; i++) { | |
313 | if (intfs[i] == INTF_DSI) { | |
314 | if (intf_num == i) | |
315 | return id; | |
316 | ||
317 | id++; | |
318 | } | |
319 | } | |
320 | ||
321 | return -EINVAL; | |
322 | } | |
323 | ||
5722a9e3 HL |
324 | static int modeset_init_intf(struct mdp5_kms *mdp5_kms, int intf_num) |
325 | { | |
326 | struct drm_device *dev = mdp5_kms->dev; | |
327 | struct msm_drm_private *priv = dev->dev_private; | |
328 | const struct mdp5_cfg_hw *hw_cfg = | |
329 | mdp5_cfg_get_hw_config(mdp5_kms->cfg); | |
fe34464d | 330 | enum mdp5_intf_type intf_type = hw_cfg->intf.connect[intf_num]; |
c71716b1 HL |
331 | struct mdp5_ctl_manager *ctlm = mdp5_kms->ctlm; |
332 | struct mdp5_ctl *ctl; | |
5722a9e3 HL |
333 | struct drm_encoder *encoder; |
334 | int ret = 0; | |
335 | ||
336 | switch (intf_type) { | |
337 | case INTF_DISABLED: | |
338 | break; | |
339 | case INTF_eDP: | |
340 | if (!priv->edp) | |
341 | break; | |
342 | ||
c71716b1 HL |
343 | ctl = mdp5_ctlm_request(ctlm, intf_num); |
344 | if (!ctl) { | |
345 | ret = -EINVAL; | |
346 | break; | |
347 | } | |
348 | ||
5722a9e3 | 349 | encoder = construct_encoder(mdp5_kms, INTF_eDP, intf_num, |
c71716b1 | 350 | MDP5_INTF_MODE_NONE, ctl); |
5722a9e3 HL |
351 | if (IS_ERR(encoder)) { |
352 | ret = PTR_ERR(encoder); | |
353 | break; | |
354 | } | |
67ac0a2d | 355 | |
67ac0a2d | 356 | ret = msm_edp_modeset_init(priv->edp, dev, encoder); |
5722a9e3 HL |
357 | break; |
358 | case INTF_HDMI: | |
359 | if (!priv->hdmi) | |
360 | break; | |
361 | ||
c71716b1 HL |
362 | ctl = mdp5_ctlm_request(ctlm, intf_num); |
363 | if (!ctl) { | |
364 | ret = -EINVAL; | |
365 | break; | |
366 | } | |
367 | ||
5722a9e3 | 368 | encoder = construct_encoder(mdp5_kms, INTF_HDMI, intf_num, |
c71716b1 | 369 | MDP5_INTF_MODE_NONE, ctl); |
5722a9e3 HL |
370 | if (IS_ERR(encoder)) { |
371 | ret = PTR_ERR(encoder); | |
372 | break; | |
373 | } | |
374 | ||
fcda50c8 | 375 | ret = msm_hdmi_modeset_init(priv->hdmi, dev, encoder); |
5722a9e3 | 376 | break; |
d5af49c9 HL |
377 | case INTF_DSI: |
378 | { | |
379 | int dsi_id = get_dsi_id_from_intf(hw_cfg, intf_num); | |
d5af49c9 HL |
380 | |
381 | if ((dsi_id >= ARRAY_SIZE(priv->dsi)) || (dsi_id < 0)) { | |
382 | dev_err(dev->dev, "failed to find dsi from intf %d\n", | |
383 | intf_num); | |
384 | ret = -EINVAL; | |
385 | break; | |
386 | } | |
387 | ||
388 | if (!priv->dsi[dsi_id]) | |
389 | break; | |
390 | ||
c71716b1 HL |
391 | ctl = mdp5_ctlm_request(ctlm, intf_num); |
392 | if (!ctl) { | |
393 | ret = -EINVAL; | |
394 | break; | |
395 | } | |
396 | ||
97e00119 AT |
397 | encoder = construct_encoder(mdp5_kms, INTF_DSI, intf_num, |
398 | MDP5_INTF_DSI_MODE_VIDEO, ctl); | |
399 | if (IS_ERR(encoder)) { | |
400 | ret = PTR_ERR(encoder); | |
401 | break; | |
d5af49c9 HL |
402 | } |
403 | ||
97e00119 | 404 | ret = msm_dsi_modeset_init(priv->dsi[dsi_id], dev, encoder); |
d5af49c9 HL |
405 | break; |
406 | } | |
5722a9e3 HL |
407 | default: |
408 | dev_err(dev->dev, "unknown intf: %d\n", intf_type); | |
409 | ret = -EINVAL; | |
410 | break; | |
67ac0a2d SV |
411 | } |
412 | ||
413 | return ret; | |
414 | } | |
415 | ||
06c0dd96 RC |
416 | static int modeset_init(struct mdp5_kms *mdp5_kms) |
417 | { | |
06c0dd96 RC |
418 | struct drm_device *dev = mdp5_kms->dev; |
419 | struct msm_drm_private *priv = dev->dev_private; | |
2e362e17 | 420 | const struct mdp5_cfg_hw *hw_cfg; |
06c0dd96 RC |
421 | int i, ret; |
422 | ||
42238da8 | 423 | hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); |
2e362e17 | 424 | |
c056b55d RC |
425 | /* Construct planes equaling the number of hw pipes, and CRTCs |
426 | * for the N layer-mixers (LM). The first N planes become primary | |
427 | * planes for the CRTCs, with the remainder as overlay planes: | |
428 | */ | |
429 | for (i = 0; i < mdp5_kms->num_hwpipes; i++) { | |
430 | bool primary = i < mdp5_cfg->lm.count; | |
06c0dd96 RC |
431 | struct drm_plane *plane; |
432 | struct drm_crtc *crtc; | |
433 | ||
4a0f012d | 434 | plane = mdp5_plane_init(dev, primary); |
06c0dd96 RC |
435 | if (IS_ERR(plane)) { |
436 | ret = PTR_ERR(plane); | |
c056b55d | 437 | dev_err(dev->dev, "failed to construct plane %d (%d)\n", i, ret); |
06c0dd96 RC |
438 | goto fail; |
439 | } | |
bc5289ee | 440 | priv->planes[priv->num_planes++] = plane; |
06c0dd96 | 441 | |
c056b55d RC |
442 | if (!primary) |
443 | continue; | |
444 | ||
06c0dd96 RC |
445 | crtc = mdp5_crtc_init(dev, plane, i); |
446 | if (IS_ERR(crtc)) { | |
447 | ret = PTR_ERR(crtc); | |
c056b55d | 448 | dev_err(dev->dev, "failed to construct crtc %d (%d)\n", i, ret); |
06c0dd96 RC |
449 | goto fail; |
450 | } | |
451 | priv->crtcs[priv->num_crtcs++] = crtc; | |
452 | } | |
453 | ||
5722a9e3 HL |
454 | /* Construct encoders and modeset initialize connector devices |
455 | * for each external display interface. | |
456 | */ | |
fe34464d | 457 | for (i = 0; i < ARRAY_SIZE(hw_cfg->intf.connect); i++) { |
5722a9e3 | 458 | ret = modeset_init_intf(mdp5_kms, i); |
67ac0a2d | 459 | if (ret) |
00453981 | 460 | goto fail; |
00453981 HL |
461 | } |
462 | ||
06c0dd96 RC |
463 | return 0; |
464 | ||
465 | fail: | |
466 | return ret; | |
467 | } | |
468 | ||
1dd0a0b1 AT |
469 | static void read_mdp_hw_revision(struct mdp5_kms *mdp5_kms, |
470 | u32 *major, u32 *minor) | |
471 | { | |
472 | u32 version; | |
473 | ||
474 | mdp5_enable(mdp5_kms); | |
7b59c7e4 | 475 | version = mdp5_read(mdp5_kms, REG_MDP5_HW_VERSION); |
1dd0a0b1 AT |
476 | mdp5_disable(mdp5_kms); |
477 | ||
7b59c7e4 AT |
478 | *major = FIELD(version, MDP5_HW_VERSION_MAJOR); |
479 | *minor = FIELD(version, MDP5_HW_VERSION_MINOR); | |
1dd0a0b1 AT |
480 | |
481 | DBG("MDP5 version v%d.%d", *major, *minor); | |
482 | } | |
483 | ||
06c0dd96 | 484 | static int get_clk(struct platform_device *pdev, struct clk **clkp, |
d40325b4 | 485 | const char *name, bool mandatory) |
06c0dd96 RC |
486 | { |
487 | struct device *dev = &pdev->dev; | |
488 | struct clk *clk = devm_clk_get(dev, name); | |
d40325b4 | 489 | if (IS_ERR(clk) && mandatory) { |
06c0dd96 RC |
490 | dev_err(dev, "failed to get %s (%ld)\n", name, PTR_ERR(clk)); |
491 | return PTR_ERR(clk); | |
492 | } | |
d40325b4 SV |
493 | if (IS_ERR(clk)) |
494 | DBG("skipping %s", name); | |
495 | else | |
496 | *clkp = clk; | |
497 | ||
06c0dd96 RC |
498 | return 0; |
499 | } | |
500 | ||
e2dd9f9f AT |
501 | static struct drm_encoder *get_encoder_from_crtc(struct drm_crtc *crtc) |
502 | { | |
503 | struct drm_device *dev = crtc->dev; | |
504 | struct drm_encoder *encoder; | |
505 | ||
506 | drm_for_each_encoder(encoder, dev) | |
507 | if (encoder->crtc == crtc) | |
508 | return encoder; | |
509 | ||
510 | return NULL; | |
511 | } | |
512 | ||
513 | static int mdp5_get_scanoutpos(struct drm_device *dev, unsigned int pipe, | |
514 | unsigned int flags, int *vpos, int *hpos, | |
515 | ktime_t *stime, ktime_t *etime, | |
516 | const struct drm_display_mode *mode) | |
517 | { | |
518 | struct msm_drm_private *priv = dev->dev_private; | |
519 | struct drm_crtc *crtc; | |
520 | struct drm_encoder *encoder; | |
521 | int line, vsw, vbp, vactive_start, vactive_end, vfp_end; | |
522 | int ret = 0; | |
523 | ||
524 | crtc = priv->crtcs[pipe]; | |
525 | if (!crtc) { | |
526 | DRM_ERROR("Invalid crtc %d\n", pipe); | |
527 | return 0; | |
528 | } | |
529 | ||
530 | encoder = get_encoder_from_crtc(crtc); | |
531 | if (!encoder) { | |
532 | DRM_ERROR("no encoder found for crtc %d\n", pipe); | |
533 | return 0; | |
534 | } | |
535 | ||
536 | ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; | |
537 | ||
538 | vsw = mode->crtc_vsync_end - mode->crtc_vsync_start; | |
539 | vbp = mode->crtc_vtotal - mode->crtc_vsync_end; | |
540 | ||
541 | /* | |
542 | * the line counter is 1 at the start of the VSYNC pulse and VTOTAL at | |
543 | * the end of VFP. Translate the porch values relative to the line | |
544 | * counter positions. | |
545 | */ | |
546 | ||
547 | vactive_start = vsw + vbp + 1; | |
548 | ||
549 | vactive_end = vactive_start + mode->crtc_vdisplay; | |
550 | ||
551 | /* last scan line before VSYNC */ | |
552 | vfp_end = mode->crtc_vtotal; | |
553 | ||
554 | if (stime) | |
555 | *stime = ktime_get(); | |
556 | ||
557 | line = mdp5_encoder_get_linecount(encoder); | |
558 | ||
559 | if (line < vactive_start) { | |
560 | line -= vactive_start; | |
561 | ret |= DRM_SCANOUTPOS_IN_VBLANK; | |
562 | } else if (line > vactive_end) { | |
563 | line = line - vfp_end - vactive_start; | |
564 | ret |= DRM_SCANOUTPOS_IN_VBLANK; | |
565 | } else { | |
566 | line -= vactive_start; | |
567 | } | |
568 | ||
569 | *vpos = line; | |
570 | *hpos = 0; | |
571 | ||
572 | if (etime) | |
573 | *etime = ktime_get(); | |
574 | ||
575 | return ret; | |
576 | } | |
577 | ||
578 | static int mdp5_get_vblank_timestamp(struct drm_device *dev, unsigned int pipe, | |
579 | int *max_error, | |
580 | struct timeval *vblank_time, | |
581 | unsigned flags) | |
582 | { | |
583 | struct msm_drm_private *priv = dev->dev_private; | |
584 | struct drm_crtc *crtc; | |
585 | ||
586 | if (pipe < 0 || pipe >= priv->num_crtcs) { | |
587 | DRM_ERROR("Invalid crtc %d\n", pipe); | |
588 | return -EINVAL; | |
589 | } | |
590 | ||
591 | crtc = priv->crtcs[pipe]; | |
592 | if (!crtc) { | |
593 | DRM_ERROR("Invalid crtc %d\n", pipe); | |
594 | return -EINVAL; | |
595 | } | |
596 | ||
597 | return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, | |
598 | vblank_time, flags, | |
599 | &crtc->mode); | |
600 | } | |
601 | ||
602 | static u32 mdp5_get_vblank_counter(struct drm_device *dev, unsigned int pipe) | |
603 | { | |
604 | struct msm_drm_private *priv = dev->dev_private; | |
605 | struct drm_crtc *crtc; | |
606 | struct drm_encoder *encoder; | |
607 | ||
608 | if (pipe < 0 || pipe >= priv->num_crtcs) | |
609 | return 0; | |
610 | ||
611 | crtc = priv->crtcs[pipe]; | |
612 | if (!crtc) | |
613 | return 0; | |
614 | ||
615 | encoder = get_encoder_from_crtc(crtc); | |
616 | if (!encoder) | |
617 | return 0; | |
618 | ||
619 | return mdp5_encoder_get_framecount(encoder); | |
620 | } | |
621 | ||
06c0dd96 | 622 | struct msm_kms *mdp5_kms_init(struct drm_device *dev) |
aec095ec AT |
623 | { |
624 | struct msm_drm_private *priv = dev->dev_private; | |
625 | struct platform_device *pdev; | |
626 | struct mdp5_kms *mdp5_kms; | |
627 | struct mdp5_cfg *config; | |
628 | struct msm_kms *kms; | |
667ce33e | 629 | struct msm_gem_address_space *aspace; |
aec095ec AT |
630 | int irq, i, ret; |
631 | ||
632 | /* priv->kms would have been populated by the MDP5 driver */ | |
633 | kms = priv->kms; | |
634 | if (!kms) | |
635 | return NULL; | |
636 | ||
637 | mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); | |
638 | ||
639 | mdp_kms_init(&mdp5_kms->base, &kms_funcs); | |
640 | ||
641 | pdev = mdp5_kms->pdev; | |
642 | ||
643 | irq = irq_of_parse_and_map(pdev->dev.of_node, 0); | |
644 | if (irq < 0) { | |
645 | ret = irq; | |
646 | dev_err(&pdev->dev, "failed to get irq: %d\n", ret); | |
647 | goto fail; | |
648 | } | |
649 | ||
650 | kms->irq = irq; | |
651 | ||
652 | config = mdp5_cfg_get_config(mdp5_kms->cfg); | |
653 | ||
654 | /* make sure things are off before attaching iommu (bootloader could | |
655 | * have left things on, in which case we'll start getting faults if | |
656 | * we don't disable): | |
657 | */ | |
658 | mdp5_enable(mdp5_kms); | |
659 | for (i = 0; i < MDP5_INTF_NUM_MAX; i++) { | |
660 | if (mdp5_cfg_intf_is_virtual(config->hw->intf.connect[i]) || | |
661 | !config->hw->intf.base[i]) | |
662 | continue; | |
663 | mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(i), 0); | |
664 | ||
665 | mdp5_write(mdp5_kms, REG_MDP5_INTF_FRAME_LINE_COUNT_EN(i), 0x3); | |
666 | } | |
667 | mdp5_disable(mdp5_kms); | |
668 | mdelay(16); | |
669 | ||
670 | if (config->platform.iommu) { | |
667ce33e RC |
671 | aspace = msm_gem_address_space_create(&pdev->dev, |
672 | config->platform.iommu, "mdp5"); | |
673 | if (IS_ERR(aspace)) { | |
674 | ret = PTR_ERR(aspace); | |
aec095ec AT |
675 | goto fail; |
676 | } | |
677 | ||
667ce33e RC |
678 | mdp5_kms->aspace = aspace; |
679 | ||
680 | ret = aspace->mmu->funcs->attach(aspace->mmu, iommu_ports, | |
aec095ec AT |
681 | ARRAY_SIZE(iommu_ports)); |
682 | if (ret) { | |
683 | dev_err(&pdev->dev, "failed to attach iommu: %d\n", | |
684 | ret); | |
aec095ec AT |
685 | goto fail; |
686 | } | |
687 | } else { | |
688 | dev_info(&pdev->dev, | |
689 | "no iommu, fallback to phys contig buffers for scanout\n"); | |
667ce33e | 690 | aspace = NULL;; |
aec095ec | 691 | } |
aec095ec | 692 | |
667ce33e | 693 | mdp5_kms->id = msm_register_address_space(dev, aspace); |
aec095ec AT |
694 | if (mdp5_kms->id < 0) { |
695 | ret = mdp5_kms->id; | |
696 | dev_err(&pdev->dev, "failed to register mdp5 iommu: %d\n", ret); | |
697 | goto fail; | |
698 | } | |
699 | ||
700 | ret = modeset_init(mdp5_kms); | |
701 | if (ret) { | |
702 | dev_err(&pdev->dev, "modeset_init failed: %d\n", ret); | |
703 | goto fail; | |
704 | } | |
705 | ||
706 | dev->mode_config.min_width = 0; | |
707 | dev->mode_config.min_height = 0; | |
9708ebbe RC |
708 | dev->mode_config.max_width = 0xffff; |
709 | dev->mode_config.max_height = 0xffff; | |
aec095ec AT |
710 | |
711 | dev->driver->get_vblank_timestamp = mdp5_get_vblank_timestamp; | |
712 | dev->driver->get_scanout_position = mdp5_get_scanoutpos; | |
713 | dev->driver->get_vblank_counter = mdp5_get_vblank_counter; | |
714 | dev->max_vblank_count = 0xffffffff; | |
715 | dev->vblank_disable_immediate = true; | |
716 | ||
717 | return kms; | |
718 | fail: | |
719 | if (kms) | |
392ae6e0 | 720 | mdp5_kms_destroy(kms); |
aec095ec AT |
721 | return ERR_PTR(ret); |
722 | } | |
723 | ||
1dd0a0b1 AT |
724 | static void mdp5_destroy(struct platform_device *pdev) |
725 | { | |
726 | struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev); | |
727 | ||
728 | if (mdp5_kms->ctlm) | |
729 | mdp5_ctlm_destroy(mdp5_kms->ctlm); | |
730 | if (mdp5_kms->smp) | |
731 | mdp5_smp_destroy(mdp5_kms->smp); | |
732 | if (mdp5_kms->cfg) | |
733 | mdp5_cfg_destroy(mdp5_kms->cfg); | |
cd792726 AT |
734 | |
735 | if (mdp5_kms->rpm_enabled) | |
736 | pm_runtime_disable(&pdev->dev); | |
ac2a3fd3 RC |
737 | |
738 | kfree(mdp5_kms->state); | |
1dd0a0b1 AT |
739 | } |
740 | ||
c056b55d RC |
741 | static int construct_pipes(struct mdp5_kms *mdp5_kms, int cnt, |
742 | const enum mdp5_pipe *pipes, const uint32_t *offsets, | |
743 | uint32_t caps) | |
744 | { | |
745 | struct drm_device *dev = mdp5_kms->dev; | |
746 | int i, ret; | |
747 | ||
748 | for (i = 0; i < cnt; i++) { | |
749 | struct mdp5_hw_pipe *hwpipe; | |
750 | ||
751 | hwpipe = mdp5_pipe_init(pipes[i], offsets[i], caps); | |
752 | if (IS_ERR(hwpipe)) { | |
753 | ret = PTR_ERR(hwpipe); | |
754 | dev_err(dev->dev, "failed to construct pipe for %s (%d)\n", | |
755 | pipe2name(pipes[i]), ret); | |
756 | return ret; | |
757 | } | |
758 | hwpipe->idx = mdp5_kms->num_hwpipes; | |
759 | mdp5_kms->hwpipes[mdp5_kms->num_hwpipes++] = hwpipe; | |
760 | } | |
761 | ||
762 | return 0; | |
763 | } | |
764 | ||
765 | static int hwpipe_init(struct mdp5_kms *mdp5_kms) | |
766 | { | |
767 | static const enum mdp5_pipe rgb_planes[] = { | |
768 | SSPP_RGB0, SSPP_RGB1, SSPP_RGB2, SSPP_RGB3, | |
769 | }; | |
770 | static const enum mdp5_pipe vig_planes[] = { | |
771 | SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3, | |
772 | }; | |
773 | static const enum mdp5_pipe dma_planes[] = { | |
774 | SSPP_DMA0, SSPP_DMA1, | |
775 | }; | |
776 | const struct mdp5_cfg_hw *hw_cfg; | |
777 | int ret; | |
778 | ||
779 | hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); | |
780 | ||
781 | /* Construct RGB pipes: */ | |
782 | ret = construct_pipes(mdp5_kms, hw_cfg->pipe_rgb.count, rgb_planes, | |
783 | hw_cfg->pipe_rgb.base, hw_cfg->pipe_rgb.caps); | |
784 | if (ret) | |
785 | return ret; | |
786 | ||
787 | /* Construct video (VIG) pipes: */ | |
788 | ret = construct_pipes(mdp5_kms, hw_cfg->pipe_vig.count, vig_planes, | |
789 | hw_cfg->pipe_vig.base, hw_cfg->pipe_vig.caps); | |
790 | if (ret) | |
791 | return ret; | |
792 | ||
793 | /* Construct DMA pipes: */ | |
794 | ret = construct_pipes(mdp5_kms, hw_cfg->pipe_dma.count, dma_planes, | |
795 | hw_cfg->pipe_dma.base, hw_cfg->pipe_dma.caps); | |
796 | if (ret) | |
797 | return ret; | |
798 | ||
799 | return 0; | |
800 | } | |
801 | ||
1dd0a0b1 AT |
802 | static int mdp5_init(struct platform_device *pdev, struct drm_device *dev) |
803 | { | |
804 | struct msm_drm_private *priv = dev->dev_private; | |
805 | struct mdp5_kms *mdp5_kms; | |
806 | struct mdp5_cfg *config; | |
807 | u32 major, minor; | |
808 | int ret; | |
809 | ||
810 | mdp5_kms = devm_kzalloc(&pdev->dev, sizeof(*mdp5_kms), GFP_KERNEL); | |
811 | if (!mdp5_kms) { | |
812 | ret = -ENOMEM; | |
813 | goto fail; | |
814 | } | |
815 | ||
816 | platform_set_drvdata(pdev, mdp5_kms); | |
817 | ||
818 | spin_lock_init(&mdp5_kms->resource_lock); | |
819 | ||
820 | mdp5_kms->dev = dev; | |
821 | mdp5_kms->pdev = pdev; | |
822 | ||
ac2a3fd3 RC |
823 | drm_modeset_lock_init(&mdp5_kms->state_lock); |
824 | mdp5_kms->state = kzalloc(sizeof(*mdp5_kms->state), GFP_KERNEL); | |
825 | if (!mdp5_kms->state) { | |
826 | ret = -ENOMEM; | |
827 | goto fail; | |
828 | } | |
829 | ||
1dd0a0b1 AT |
830 | mdp5_kms->mmio = msm_ioremap(pdev, "mdp_phys", "MDP5"); |
831 | if (IS_ERR(mdp5_kms->mmio)) { | |
832 | ret = PTR_ERR(mdp5_kms->mmio); | |
833 | goto fail; | |
834 | } | |
835 | ||
836 | /* mandatory clocks: */ | |
837 | ret = get_clk(pdev, &mdp5_kms->axi_clk, "bus_clk", true); | |
838 | if (ret) | |
839 | goto fail; | |
840 | ret = get_clk(pdev, &mdp5_kms->ahb_clk, "iface_clk", true); | |
841 | if (ret) | |
842 | goto fail; | |
843 | ret = get_clk(pdev, &mdp5_kms->core_clk, "core_clk", true); | |
844 | if (ret) | |
845 | goto fail; | |
846 | ret = get_clk(pdev, &mdp5_kms->vsync_clk, "vsync_clk", true); | |
847 | if (ret) | |
848 | goto fail; | |
849 | ||
850 | /* optional clocks: */ | |
851 | get_clk(pdev, &mdp5_kms->lut_clk, "lut_clk", false); | |
852 | ||
853 | /* we need to set a default rate before enabling. Set a safe | |
854 | * rate first, then figure out hw revision, and then set a | |
855 | * more optimal rate: | |
856 | */ | |
857 | clk_set_rate(mdp5_kms->core_clk, 200000000); | |
858 | ||
cd792726 AT |
859 | pm_runtime_enable(&pdev->dev); |
860 | mdp5_kms->rpm_enabled = true; | |
861 | ||
1dd0a0b1 AT |
862 | read_mdp_hw_revision(mdp5_kms, &major, &minor); |
863 | ||
864 | mdp5_kms->cfg = mdp5_cfg_init(mdp5_kms, major, minor); | |
865 | if (IS_ERR(mdp5_kms->cfg)) { | |
866 | ret = PTR_ERR(mdp5_kms->cfg); | |
867 | mdp5_kms->cfg = NULL; | |
868 | goto fail; | |
869 | } | |
870 | ||
871 | config = mdp5_cfg_get_config(mdp5_kms->cfg); | |
872 | mdp5_kms->caps = config->hw->mdp.caps; | |
873 | ||
874 | /* TODO: compute core clock rate at runtime */ | |
875 | clk_set_rate(mdp5_kms->core_clk, config->hw->max_clk); | |
876 | ||
877 | /* | |
878 | * Some chipsets have a Shared Memory Pool (SMP), while others | |
879 | * have dedicated latency buffering per source pipe instead; | |
880 | * this section initializes the SMP: | |
881 | */ | |
882 | if (mdp5_kms->caps & MDP_CAP_SMP) { | |
49ec5b2e | 883 | mdp5_kms->smp = mdp5_smp_init(mdp5_kms, &config->hw->smp); |
1dd0a0b1 AT |
884 | if (IS_ERR(mdp5_kms->smp)) { |
885 | ret = PTR_ERR(mdp5_kms->smp); | |
886 | mdp5_kms->smp = NULL; | |
887 | goto fail; | |
888 | } | |
889 | } | |
890 | ||
891 | mdp5_kms->ctlm = mdp5_ctlm_init(dev, mdp5_kms->mmio, mdp5_kms->cfg); | |
892 | if (IS_ERR(mdp5_kms->ctlm)) { | |
893 | ret = PTR_ERR(mdp5_kms->ctlm); | |
894 | mdp5_kms->ctlm = NULL; | |
895 | goto fail; | |
896 | } | |
897 | ||
c056b55d RC |
898 | ret = hwpipe_init(mdp5_kms); |
899 | if (ret) | |
900 | goto fail; | |
901 | ||
1dd0a0b1 AT |
902 | /* set uninit-ed kms */ |
903 | priv->kms = &mdp5_kms->base.base; | |
904 | ||
905 | return 0; | |
906 | fail: | |
907 | mdp5_destroy(pdev); | |
908 | return ret; | |
909 | } | |
910 | ||
911 | static int mdp5_bind(struct device *dev, struct device *master, void *data) | |
912 | { | |
913 | struct drm_device *ddev = dev_get_drvdata(master); | |
914 | struct platform_device *pdev = to_platform_device(dev); | |
915 | ||
916 | DBG(""); | |
917 | ||
918 | return mdp5_init(pdev, ddev); | |
919 | } | |
920 | ||
921 | static void mdp5_unbind(struct device *dev, struct device *master, | |
922 | void *data) | |
923 | { | |
924 | struct platform_device *pdev = to_platform_device(dev); | |
925 | ||
926 | mdp5_destroy(pdev); | |
927 | } | |
928 | ||
929 | static const struct component_ops mdp5_ops = { | |
930 | .bind = mdp5_bind, | |
931 | .unbind = mdp5_unbind, | |
932 | }; | |
933 | ||
934 | static int mdp5_dev_probe(struct platform_device *pdev) | |
935 | { | |
936 | DBG(""); | |
937 | return component_add(&pdev->dev, &mdp5_ops); | |
938 | } | |
939 | ||
940 | static int mdp5_dev_remove(struct platform_device *pdev) | |
941 | { | |
942 | DBG(""); | |
943 | component_del(&pdev->dev, &mdp5_ops); | |
944 | return 0; | |
945 | } | |
946 | ||
96a611b5 AT |
947 | static const struct of_device_id mdp5_dt_match[] = { |
948 | { .compatible = "qcom,mdp5", }, | |
949 | /* to support downstream DT files */ | |
950 | { .compatible = "qcom,mdss_mdp", }, | |
951 | {} | |
952 | }; | |
953 | MODULE_DEVICE_TABLE(of, mdp5_dt_match); | |
954 | ||
1dd0a0b1 AT |
955 | static struct platform_driver mdp5_driver = { |
956 | .probe = mdp5_dev_probe, | |
957 | .remove = mdp5_dev_remove, | |
958 | .driver = { | |
959 | .name = "msm_mdp", | |
96a611b5 | 960 | .of_match_table = mdp5_dt_match, |
1dd0a0b1 AT |
961 | }, |
962 | }; | |
963 | ||
964 | void __init msm_mdp_register(void) | |
965 | { | |
966 | DBG(""); | |
967 | platform_driver_register(&mdp5_driver); | |
968 | } | |
969 | ||
970 | void __exit msm_mdp_unregister(void) | |
971 | { | |
972 | DBG(""); | |
973 | platform_driver_unregister(&mdp5_driver); | |
974 | } |