Commit | Line | Data |
---|---|---|
06c0dd96 | 1 | /* |
2e362e17 | 2 | * Copyright (c) 2014, The Linux Foundation. All rights reserved. |
06c0dd96 RC |
3 | * Copyright (C) 2013 Red Hat |
4 | * Author: Rob Clark <robdclark@gmail.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published by | |
8 | * the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along with | |
16 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | ||
aec095ec | 19 | #include <linux/of_irq.h> |
06c0dd96 RC |
20 | |
21 | #include "msm_drv.h" | |
667ce33e | 22 | #include "msm_gem.h" |
06c0dd96 RC |
23 | #include "msm_mmu.h" |
24 | #include "mdp5_kms.h" | |
25 | ||
87e956e9 SV |
26 | static const char *iommu_ports[] = { |
27 | "mdp_0", | |
28 | }; | |
29 | ||
3d47fd47 SV |
30 | static int mdp5_hw_init(struct msm_kms *kms) |
31 | { | |
32 | struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); | |
0a6030d2 | 33 | struct platform_device *pdev = mdp5_kms->pdev; |
0deed25b | 34 | unsigned long flags; |
3d47fd47 | 35 | |
0a6030d2 | 36 | pm_runtime_get_sync(&pdev->dev); |
7c8f0235 | 37 | mdp5_enable(mdp5_kms); |
3d47fd47 | 38 | |
06c0dd96 RC |
39 | /* Magic unknown register writes: |
40 | * | |
41 | * W VBIF:0x004 00000001 (mdss_mdp.c:839) | |
42 | * W MDP5:0x2e0 0xe9 (mdss_mdp.c:839) | |
43 | * W MDP5:0x2e4 0x55 (mdss_mdp.c:839) | |
44 | * W MDP5:0x3ac 0xc0000ccc (mdss_mdp.c:839) | |
45 | * W MDP5:0x3b4 0xc0000ccc (mdss_mdp.c:839) | |
46 | * W MDP5:0x3bc 0xcccccc (mdss_mdp.c:839) | |
47 | * W MDP5:0x4a8 0xcccc0c0 (mdss_mdp.c:839) | |
48 | * W MDP5:0x4b0 0xccccc0c0 (mdss_mdp.c:839) | |
49 | * W MDP5:0x4b8 0xccccc000 (mdss_mdp.c:839) | |
50 | * | |
51 | * Downstream fbdev driver gets these register offsets/values | |
52 | * from DT.. not really sure what these registers are or if | |
53 | * different values for different boards/SoC's, etc. I guess | |
54 | * they are the golden registers. | |
55 | * | |
56 | * Not setting these does not seem to cause any problem. But | |
57 | * we may be getting lucky with the bootloader initializing | |
58 | * them for us. OTOH, if we can always count on the bootloader | |
59 | * setting the golden registers, then perhaps we don't need to | |
60 | * care. | |
61 | */ | |
62 | ||
0deed25b | 63 | spin_lock_irqsave(&mdp5_kms->resource_lock, flags); |
7b59c7e4 | 64 | mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, 0); |
0deed25b | 65 | spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags); |
06c0dd96 | 66 | |
42238da8 | 67 | mdp5_ctlm_hw_reset(mdp5_kms->ctlm); |
3d47fd47 | 68 | |
7c8f0235 | 69 | mdp5_disable(mdp5_kms); |
0a6030d2 | 70 | pm_runtime_put_sync(&pdev->dev); |
06c0dd96 | 71 | |
3d47fd47 | 72 | return 0; |
06c0dd96 RC |
73 | } |
74 | ||
ac2a3fd3 RC |
75 | struct mdp5_state *mdp5_get_state(struct drm_atomic_state *s) |
76 | { | |
77 | struct msm_drm_private *priv = s->dev->dev_private; | |
78 | struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); | |
79 | struct msm_kms_state *state = to_kms_state(s); | |
80 | struct mdp5_state *new_state; | |
81 | int ret; | |
82 | ||
83 | if (state->state) | |
84 | return state->state; | |
85 | ||
86 | ret = drm_modeset_lock(&mdp5_kms->state_lock, s->acquire_ctx); | |
87 | if (ret) | |
88 | return ERR_PTR(ret); | |
89 | ||
90 | new_state = kmalloc(sizeof(*mdp5_kms->state), GFP_KERNEL); | |
91 | if (!new_state) | |
92 | return ERR_PTR(-ENOMEM); | |
93 | ||
94 | /* Copy state: */ | |
4a0f012d | 95 | new_state->hwpipe = mdp5_kms->state->hwpipe; |
49ec5b2e RC |
96 | if (mdp5_kms->smp) |
97 | new_state->smp = mdp5_kms->state->smp; | |
ac2a3fd3 RC |
98 | |
99 | state->state = new_state; | |
100 | ||
101 | return new_state; | |
102 | } | |
103 | ||
104 | static void mdp5_swap_state(struct msm_kms *kms, struct drm_atomic_state *state) | |
105 | { | |
106 | struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); | |
107 | swap(to_kms_state(state)->state, mdp5_kms->state); | |
108 | } | |
109 | ||
0b776d45 RC |
110 | static void mdp5_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state) |
111 | { | |
112 | struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); | |
49ec5b2e | 113 | |
0b776d45 | 114 | mdp5_enable(mdp5_kms); |
49ec5b2e RC |
115 | |
116 | if (mdp5_kms->smp) | |
117 | mdp5_smp_prepare_commit(mdp5_kms->smp, &mdp5_kms->state->smp); | |
0b776d45 RC |
118 | } |
119 | ||
120 | static void mdp5_complete_commit(struct msm_kms *kms, struct drm_atomic_state *state) | |
121 | { | |
122 | struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); | |
657c63f0 | 123 | |
49ec5b2e RC |
124 | if (mdp5_kms->smp) |
125 | mdp5_smp_complete_commit(mdp5_kms->smp, &mdp5_kms->state->smp); | |
126 | ||
0b776d45 RC |
127 | mdp5_disable(mdp5_kms); |
128 | } | |
129 | ||
0a5c9aad HL |
130 | static void mdp5_wait_for_crtc_commit_done(struct msm_kms *kms, |
131 | struct drm_crtc *crtc) | |
132 | { | |
133 | mdp5_crtc_wait_for_commit_done(crtc); | |
134 | } | |
135 | ||
06c0dd96 RC |
136 | static long mdp5_round_pixclk(struct msm_kms *kms, unsigned long rate, |
137 | struct drm_encoder *encoder) | |
138 | { | |
139 | return rate; | |
140 | } | |
141 | ||
d5af49c9 HL |
142 | static int mdp5_set_split_display(struct msm_kms *kms, |
143 | struct drm_encoder *encoder, | |
144 | struct drm_encoder *slave_encoder, | |
145 | bool is_cmd_mode) | |
146 | { | |
147 | if (is_cmd_mode) | |
148 | return mdp5_cmd_encoder_set_split_display(encoder, | |
149 | slave_encoder); | |
150 | else | |
151 | return mdp5_encoder_set_split_display(encoder, slave_encoder); | |
152 | } | |
153 | ||
1dd0a0b1 | 154 | static void mdp5_kms_destroy(struct msm_kms *kms) |
06c0dd96 RC |
155 | { |
156 | struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); | |
667ce33e | 157 | struct msm_gem_address_space *aspace = mdp5_kms->aspace; |
c056b55d RC |
158 | int i; |
159 | ||
160 | for (i = 0; i < mdp5_kms->num_hwpipes; i++) | |
161 | mdp5_pipe_destroy(mdp5_kms->hwpipes[i]); | |
87e956e9 | 162 | |
667ce33e RC |
163 | if (aspace) { |
164 | aspace->mmu->funcs->detach(aspace->mmu, | |
165 | iommu_ports, ARRAY_SIZE(iommu_ports)); | |
166 | msm_gem_address_space_destroy(aspace); | |
87e956e9 | 167 | } |
aec095ec AT |
168 | } |
169 | ||
bc5289ee RC |
170 | #ifdef CONFIG_DEBUG_FS |
171 | static int smp_show(struct seq_file *m, void *arg) | |
172 | { | |
173 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
174 | struct drm_device *dev = node->minor->dev; | |
175 | struct msm_drm_private *priv = dev->dev_private; | |
176 | struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); | |
177 | struct drm_printer p = drm_seq_file_printer(m); | |
178 | ||
179 | if (!mdp5_kms->smp) { | |
180 | drm_printf(&p, "no SMP pool\n"); | |
181 | return 0; | |
182 | } | |
183 | ||
184 | mdp5_smp_dump(mdp5_kms->smp, &p); | |
185 | ||
186 | return 0; | |
187 | } | |
188 | ||
189 | static struct drm_info_list mdp5_debugfs_list[] = { | |
190 | {"smp", smp_show }, | |
191 | }; | |
192 | ||
193 | static int mdp5_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor) | |
194 | { | |
195 | struct drm_device *dev = minor->dev; | |
196 | int ret; | |
197 | ||
198 | ret = drm_debugfs_create_files(mdp5_debugfs_list, | |
199 | ARRAY_SIZE(mdp5_debugfs_list), | |
200 | minor->debugfs_root, minor); | |
201 | ||
202 | if (ret) { | |
203 | dev_err(dev->dev, "could not install mdp5_debugfs_list\n"); | |
204 | return ret; | |
205 | } | |
206 | ||
207 | return 0; | |
208 | } | |
209 | ||
210 | static void mdp5_kms_debugfs_cleanup(struct msm_kms *kms, struct drm_minor *minor) | |
211 | { | |
212 | drm_debugfs_remove_files(mdp5_debugfs_list, | |
213 | ARRAY_SIZE(mdp5_debugfs_list), minor); | |
214 | } | |
215 | #endif | |
216 | ||
06c0dd96 RC |
217 | static const struct mdp_kms_funcs kms_funcs = { |
218 | .base = { | |
219 | .hw_init = mdp5_hw_init, | |
220 | .irq_preinstall = mdp5_irq_preinstall, | |
221 | .irq_postinstall = mdp5_irq_postinstall, | |
222 | .irq_uninstall = mdp5_irq_uninstall, | |
223 | .irq = mdp5_irq, | |
224 | .enable_vblank = mdp5_enable_vblank, | |
225 | .disable_vblank = mdp5_disable_vblank, | |
ac2a3fd3 | 226 | .swap_state = mdp5_swap_state, |
0b776d45 RC |
227 | .prepare_commit = mdp5_prepare_commit, |
228 | .complete_commit = mdp5_complete_commit, | |
0a5c9aad | 229 | .wait_for_crtc_commit_done = mdp5_wait_for_crtc_commit_done, |
06c0dd96 RC |
230 | .get_format = mdp_get_format, |
231 | .round_pixclk = mdp5_round_pixclk, | |
d5af49c9 | 232 | .set_split_display = mdp5_set_split_display, |
392ae6e0 | 233 | .destroy = mdp5_kms_destroy, |
bc5289ee RC |
234 | #ifdef CONFIG_DEBUG_FS |
235 | .debugfs_init = mdp5_kms_debugfs_init, | |
236 | .debugfs_cleanup = mdp5_kms_debugfs_cleanup, | |
237 | #endif | |
06c0dd96 RC |
238 | }, |
239 | .set_irqmask = mdp5_set_irqmask, | |
240 | }; | |
241 | ||
242 | int mdp5_disable(struct mdp5_kms *mdp5_kms) | |
243 | { | |
244 | DBG(""); | |
245 | ||
246 | clk_disable_unprepare(mdp5_kms->ahb_clk); | |
247 | clk_disable_unprepare(mdp5_kms->axi_clk); | |
248 | clk_disable_unprepare(mdp5_kms->core_clk); | |
3a84f846 SV |
249 | if (mdp5_kms->lut_clk) |
250 | clk_disable_unprepare(mdp5_kms->lut_clk); | |
06c0dd96 RC |
251 | |
252 | return 0; | |
253 | } | |
254 | ||
255 | int mdp5_enable(struct mdp5_kms *mdp5_kms) | |
256 | { | |
257 | DBG(""); | |
258 | ||
259 | clk_prepare_enable(mdp5_kms->ahb_clk); | |
260 | clk_prepare_enable(mdp5_kms->axi_clk); | |
261 | clk_prepare_enable(mdp5_kms->core_clk); | |
3a84f846 SV |
262 | if (mdp5_kms->lut_clk) |
263 | clk_prepare_enable(mdp5_kms->lut_clk); | |
06c0dd96 RC |
264 | |
265 | return 0; | |
266 | } | |
267 | ||
5722a9e3 HL |
268 | static struct drm_encoder *construct_encoder(struct mdp5_kms *mdp5_kms, |
269 | enum mdp5_intf_type intf_type, int intf_num, | |
c71716b1 | 270 | enum mdp5_intf_mode intf_mode, struct mdp5_ctl *ctl) |
67ac0a2d SV |
271 | { |
272 | struct drm_device *dev = mdp5_kms->dev; | |
273 | struct msm_drm_private *priv = dev->dev_private; | |
274 | struct drm_encoder *encoder; | |
275 | struct mdp5_interface intf = { | |
276 | .num = intf_num, | |
277 | .type = intf_type, | |
5722a9e3 | 278 | .mode = intf_mode, |
67ac0a2d | 279 | }; |
67ac0a2d | 280 | |
d5af49c9 HL |
281 | if ((intf_type == INTF_DSI) && |
282 | (intf_mode == MDP5_INTF_DSI_MODE_COMMAND)) | |
c71716b1 | 283 | encoder = mdp5_cmd_encoder_init(dev, &intf, ctl); |
d5af49c9 | 284 | else |
c71716b1 | 285 | encoder = mdp5_encoder_init(dev, &intf, ctl); |
d5af49c9 | 286 | |
67ac0a2d | 287 | if (IS_ERR(encoder)) { |
5722a9e3 HL |
288 | dev_err(dev->dev, "failed to construct encoder\n"); |
289 | return encoder; | |
67ac0a2d SV |
290 | } |
291 | ||
292 | encoder->possible_crtcs = (1 << priv->num_crtcs) - 1; | |
293 | priv->encoders[priv->num_encoders++] = encoder; | |
294 | ||
5722a9e3 HL |
295 | return encoder; |
296 | } | |
297 | ||
d5af49c9 HL |
298 | static int get_dsi_id_from_intf(const struct mdp5_cfg_hw *hw_cfg, int intf_num) |
299 | { | |
fe34464d SV |
300 | const enum mdp5_intf_type *intfs = hw_cfg->intf.connect; |
301 | const int intf_cnt = ARRAY_SIZE(hw_cfg->intf.connect); | |
d5af49c9 HL |
302 | int id = 0, i; |
303 | ||
304 | for (i = 0; i < intf_cnt; i++) { | |
305 | if (intfs[i] == INTF_DSI) { | |
306 | if (intf_num == i) | |
307 | return id; | |
308 | ||
309 | id++; | |
310 | } | |
311 | } | |
312 | ||
313 | return -EINVAL; | |
314 | } | |
315 | ||
5722a9e3 HL |
316 | static int modeset_init_intf(struct mdp5_kms *mdp5_kms, int intf_num) |
317 | { | |
318 | struct drm_device *dev = mdp5_kms->dev; | |
319 | struct msm_drm_private *priv = dev->dev_private; | |
320 | const struct mdp5_cfg_hw *hw_cfg = | |
321 | mdp5_cfg_get_hw_config(mdp5_kms->cfg); | |
fe34464d | 322 | enum mdp5_intf_type intf_type = hw_cfg->intf.connect[intf_num]; |
c71716b1 HL |
323 | struct mdp5_ctl_manager *ctlm = mdp5_kms->ctlm; |
324 | struct mdp5_ctl *ctl; | |
5722a9e3 HL |
325 | struct drm_encoder *encoder; |
326 | int ret = 0; | |
327 | ||
328 | switch (intf_type) { | |
329 | case INTF_DISABLED: | |
330 | break; | |
331 | case INTF_eDP: | |
332 | if (!priv->edp) | |
333 | break; | |
334 | ||
c71716b1 HL |
335 | ctl = mdp5_ctlm_request(ctlm, intf_num); |
336 | if (!ctl) { | |
337 | ret = -EINVAL; | |
338 | break; | |
339 | } | |
340 | ||
5722a9e3 | 341 | encoder = construct_encoder(mdp5_kms, INTF_eDP, intf_num, |
c71716b1 | 342 | MDP5_INTF_MODE_NONE, ctl); |
5722a9e3 HL |
343 | if (IS_ERR(encoder)) { |
344 | ret = PTR_ERR(encoder); | |
345 | break; | |
346 | } | |
67ac0a2d | 347 | |
67ac0a2d | 348 | ret = msm_edp_modeset_init(priv->edp, dev, encoder); |
5722a9e3 HL |
349 | break; |
350 | case INTF_HDMI: | |
351 | if (!priv->hdmi) | |
352 | break; | |
353 | ||
c71716b1 HL |
354 | ctl = mdp5_ctlm_request(ctlm, intf_num); |
355 | if (!ctl) { | |
356 | ret = -EINVAL; | |
357 | break; | |
358 | } | |
359 | ||
5722a9e3 | 360 | encoder = construct_encoder(mdp5_kms, INTF_HDMI, intf_num, |
c71716b1 | 361 | MDP5_INTF_MODE_NONE, ctl); |
5722a9e3 HL |
362 | if (IS_ERR(encoder)) { |
363 | ret = PTR_ERR(encoder); | |
364 | break; | |
365 | } | |
366 | ||
fcda50c8 | 367 | ret = msm_hdmi_modeset_init(priv->hdmi, dev, encoder); |
5722a9e3 | 368 | break; |
d5af49c9 HL |
369 | case INTF_DSI: |
370 | { | |
371 | int dsi_id = get_dsi_id_from_intf(hw_cfg, intf_num); | |
d5af49c9 HL |
372 | |
373 | if ((dsi_id >= ARRAY_SIZE(priv->dsi)) || (dsi_id < 0)) { | |
374 | dev_err(dev->dev, "failed to find dsi from intf %d\n", | |
375 | intf_num); | |
376 | ret = -EINVAL; | |
377 | break; | |
378 | } | |
379 | ||
380 | if (!priv->dsi[dsi_id]) | |
381 | break; | |
382 | ||
c71716b1 HL |
383 | ctl = mdp5_ctlm_request(ctlm, intf_num); |
384 | if (!ctl) { | |
385 | ret = -EINVAL; | |
386 | break; | |
387 | } | |
388 | ||
97e00119 AT |
389 | encoder = construct_encoder(mdp5_kms, INTF_DSI, intf_num, |
390 | MDP5_INTF_DSI_MODE_VIDEO, ctl); | |
391 | if (IS_ERR(encoder)) { | |
392 | ret = PTR_ERR(encoder); | |
393 | break; | |
d5af49c9 HL |
394 | } |
395 | ||
97e00119 | 396 | ret = msm_dsi_modeset_init(priv->dsi[dsi_id], dev, encoder); |
d5af49c9 HL |
397 | break; |
398 | } | |
5722a9e3 HL |
399 | default: |
400 | dev_err(dev->dev, "unknown intf: %d\n", intf_type); | |
401 | ret = -EINVAL; | |
402 | break; | |
67ac0a2d SV |
403 | } |
404 | ||
405 | return ret; | |
406 | } | |
407 | ||
06c0dd96 RC |
408 | static int modeset_init(struct mdp5_kms *mdp5_kms) |
409 | { | |
06c0dd96 RC |
410 | struct drm_device *dev = mdp5_kms->dev; |
411 | struct msm_drm_private *priv = dev->dev_private; | |
2e362e17 | 412 | const struct mdp5_cfg_hw *hw_cfg; |
06c0dd96 RC |
413 | int i, ret; |
414 | ||
42238da8 | 415 | hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); |
2e362e17 | 416 | |
c056b55d RC |
417 | /* Construct planes equaling the number of hw pipes, and CRTCs |
418 | * for the N layer-mixers (LM). The first N planes become primary | |
419 | * planes for the CRTCs, with the remainder as overlay planes: | |
420 | */ | |
421 | for (i = 0; i < mdp5_kms->num_hwpipes; i++) { | |
422 | bool primary = i < mdp5_cfg->lm.count; | |
06c0dd96 RC |
423 | struct drm_plane *plane; |
424 | struct drm_crtc *crtc; | |
425 | ||
4a0f012d | 426 | plane = mdp5_plane_init(dev, primary); |
06c0dd96 RC |
427 | if (IS_ERR(plane)) { |
428 | ret = PTR_ERR(plane); | |
c056b55d | 429 | dev_err(dev->dev, "failed to construct plane %d (%d)\n", i, ret); |
06c0dd96 RC |
430 | goto fail; |
431 | } | |
bc5289ee | 432 | priv->planes[priv->num_planes++] = plane; |
06c0dd96 | 433 | |
c056b55d RC |
434 | if (!primary) |
435 | continue; | |
436 | ||
06c0dd96 RC |
437 | crtc = mdp5_crtc_init(dev, plane, i); |
438 | if (IS_ERR(crtc)) { | |
439 | ret = PTR_ERR(crtc); | |
c056b55d | 440 | dev_err(dev->dev, "failed to construct crtc %d (%d)\n", i, ret); |
06c0dd96 RC |
441 | goto fail; |
442 | } | |
443 | priv->crtcs[priv->num_crtcs++] = crtc; | |
444 | } | |
445 | ||
5722a9e3 HL |
446 | /* Construct encoders and modeset initialize connector devices |
447 | * for each external display interface. | |
448 | */ | |
fe34464d | 449 | for (i = 0; i < ARRAY_SIZE(hw_cfg->intf.connect); i++) { |
5722a9e3 | 450 | ret = modeset_init_intf(mdp5_kms, i); |
67ac0a2d | 451 | if (ret) |
00453981 | 452 | goto fail; |
00453981 HL |
453 | } |
454 | ||
06c0dd96 RC |
455 | return 0; |
456 | ||
457 | fail: | |
458 | return ret; | |
459 | } | |
460 | ||
1dd0a0b1 AT |
461 | static void read_mdp_hw_revision(struct mdp5_kms *mdp5_kms, |
462 | u32 *major, u32 *minor) | |
463 | { | |
464 | u32 version; | |
465 | ||
466 | mdp5_enable(mdp5_kms); | |
7b59c7e4 | 467 | version = mdp5_read(mdp5_kms, REG_MDP5_HW_VERSION); |
1dd0a0b1 AT |
468 | mdp5_disable(mdp5_kms); |
469 | ||
7b59c7e4 AT |
470 | *major = FIELD(version, MDP5_HW_VERSION_MAJOR); |
471 | *minor = FIELD(version, MDP5_HW_VERSION_MINOR); | |
1dd0a0b1 AT |
472 | |
473 | DBG("MDP5 version v%d.%d", *major, *minor); | |
474 | } | |
475 | ||
06c0dd96 | 476 | static int get_clk(struct platform_device *pdev, struct clk **clkp, |
d40325b4 | 477 | const char *name, bool mandatory) |
06c0dd96 RC |
478 | { |
479 | struct device *dev = &pdev->dev; | |
480 | struct clk *clk = devm_clk_get(dev, name); | |
d40325b4 | 481 | if (IS_ERR(clk) && mandatory) { |
06c0dd96 RC |
482 | dev_err(dev, "failed to get %s (%ld)\n", name, PTR_ERR(clk)); |
483 | return PTR_ERR(clk); | |
484 | } | |
d40325b4 SV |
485 | if (IS_ERR(clk)) |
486 | DBG("skipping %s", name); | |
487 | else | |
488 | *clkp = clk; | |
489 | ||
06c0dd96 RC |
490 | return 0; |
491 | } | |
492 | ||
e2dd9f9f AT |
493 | static struct drm_encoder *get_encoder_from_crtc(struct drm_crtc *crtc) |
494 | { | |
495 | struct drm_device *dev = crtc->dev; | |
496 | struct drm_encoder *encoder; | |
497 | ||
498 | drm_for_each_encoder(encoder, dev) | |
499 | if (encoder->crtc == crtc) | |
500 | return encoder; | |
501 | ||
502 | return NULL; | |
503 | } | |
504 | ||
505 | static int mdp5_get_scanoutpos(struct drm_device *dev, unsigned int pipe, | |
506 | unsigned int flags, int *vpos, int *hpos, | |
507 | ktime_t *stime, ktime_t *etime, | |
508 | const struct drm_display_mode *mode) | |
509 | { | |
510 | struct msm_drm_private *priv = dev->dev_private; | |
511 | struct drm_crtc *crtc; | |
512 | struct drm_encoder *encoder; | |
513 | int line, vsw, vbp, vactive_start, vactive_end, vfp_end; | |
514 | int ret = 0; | |
515 | ||
516 | crtc = priv->crtcs[pipe]; | |
517 | if (!crtc) { | |
518 | DRM_ERROR("Invalid crtc %d\n", pipe); | |
519 | return 0; | |
520 | } | |
521 | ||
522 | encoder = get_encoder_from_crtc(crtc); | |
523 | if (!encoder) { | |
524 | DRM_ERROR("no encoder found for crtc %d\n", pipe); | |
525 | return 0; | |
526 | } | |
527 | ||
528 | ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; | |
529 | ||
530 | vsw = mode->crtc_vsync_end - mode->crtc_vsync_start; | |
531 | vbp = mode->crtc_vtotal - mode->crtc_vsync_end; | |
532 | ||
533 | /* | |
534 | * the line counter is 1 at the start of the VSYNC pulse and VTOTAL at | |
535 | * the end of VFP. Translate the porch values relative to the line | |
536 | * counter positions. | |
537 | */ | |
538 | ||
539 | vactive_start = vsw + vbp + 1; | |
540 | ||
541 | vactive_end = vactive_start + mode->crtc_vdisplay; | |
542 | ||
543 | /* last scan line before VSYNC */ | |
544 | vfp_end = mode->crtc_vtotal; | |
545 | ||
546 | if (stime) | |
547 | *stime = ktime_get(); | |
548 | ||
549 | line = mdp5_encoder_get_linecount(encoder); | |
550 | ||
551 | if (line < vactive_start) { | |
552 | line -= vactive_start; | |
553 | ret |= DRM_SCANOUTPOS_IN_VBLANK; | |
554 | } else if (line > vactive_end) { | |
555 | line = line - vfp_end - vactive_start; | |
556 | ret |= DRM_SCANOUTPOS_IN_VBLANK; | |
557 | } else { | |
558 | line -= vactive_start; | |
559 | } | |
560 | ||
561 | *vpos = line; | |
562 | *hpos = 0; | |
563 | ||
564 | if (etime) | |
565 | *etime = ktime_get(); | |
566 | ||
567 | return ret; | |
568 | } | |
569 | ||
570 | static int mdp5_get_vblank_timestamp(struct drm_device *dev, unsigned int pipe, | |
571 | int *max_error, | |
572 | struct timeval *vblank_time, | |
573 | unsigned flags) | |
574 | { | |
575 | struct msm_drm_private *priv = dev->dev_private; | |
576 | struct drm_crtc *crtc; | |
577 | ||
578 | if (pipe < 0 || pipe >= priv->num_crtcs) { | |
579 | DRM_ERROR("Invalid crtc %d\n", pipe); | |
580 | return -EINVAL; | |
581 | } | |
582 | ||
583 | crtc = priv->crtcs[pipe]; | |
584 | if (!crtc) { | |
585 | DRM_ERROR("Invalid crtc %d\n", pipe); | |
586 | return -EINVAL; | |
587 | } | |
588 | ||
589 | return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, | |
590 | vblank_time, flags, | |
591 | &crtc->mode); | |
592 | } | |
593 | ||
594 | static u32 mdp5_get_vblank_counter(struct drm_device *dev, unsigned int pipe) | |
595 | { | |
596 | struct msm_drm_private *priv = dev->dev_private; | |
597 | struct drm_crtc *crtc; | |
598 | struct drm_encoder *encoder; | |
599 | ||
600 | if (pipe < 0 || pipe >= priv->num_crtcs) | |
601 | return 0; | |
602 | ||
603 | crtc = priv->crtcs[pipe]; | |
604 | if (!crtc) | |
605 | return 0; | |
606 | ||
607 | encoder = get_encoder_from_crtc(crtc); | |
608 | if (!encoder) | |
609 | return 0; | |
610 | ||
611 | return mdp5_encoder_get_framecount(encoder); | |
612 | } | |
613 | ||
06c0dd96 | 614 | struct msm_kms *mdp5_kms_init(struct drm_device *dev) |
aec095ec AT |
615 | { |
616 | struct msm_drm_private *priv = dev->dev_private; | |
617 | struct platform_device *pdev; | |
618 | struct mdp5_kms *mdp5_kms; | |
619 | struct mdp5_cfg *config; | |
620 | struct msm_kms *kms; | |
667ce33e | 621 | struct msm_gem_address_space *aspace; |
aec095ec AT |
622 | int irq, i, ret; |
623 | ||
624 | /* priv->kms would have been populated by the MDP5 driver */ | |
625 | kms = priv->kms; | |
626 | if (!kms) | |
627 | return NULL; | |
628 | ||
629 | mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); | |
630 | ||
631 | mdp_kms_init(&mdp5_kms->base, &kms_funcs); | |
632 | ||
633 | pdev = mdp5_kms->pdev; | |
634 | ||
635 | irq = irq_of_parse_and_map(pdev->dev.of_node, 0); | |
636 | if (irq < 0) { | |
637 | ret = irq; | |
638 | dev_err(&pdev->dev, "failed to get irq: %d\n", ret); | |
639 | goto fail; | |
640 | } | |
641 | ||
642 | kms->irq = irq; | |
643 | ||
644 | config = mdp5_cfg_get_config(mdp5_kms->cfg); | |
645 | ||
646 | /* make sure things are off before attaching iommu (bootloader could | |
647 | * have left things on, in which case we'll start getting faults if | |
648 | * we don't disable): | |
649 | */ | |
650 | mdp5_enable(mdp5_kms); | |
651 | for (i = 0; i < MDP5_INTF_NUM_MAX; i++) { | |
652 | if (mdp5_cfg_intf_is_virtual(config->hw->intf.connect[i]) || | |
653 | !config->hw->intf.base[i]) | |
654 | continue; | |
655 | mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(i), 0); | |
656 | ||
657 | mdp5_write(mdp5_kms, REG_MDP5_INTF_FRAME_LINE_COUNT_EN(i), 0x3); | |
658 | } | |
659 | mdp5_disable(mdp5_kms); | |
660 | mdelay(16); | |
661 | ||
662 | if (config->platform.iommu) { | |
667ce33e RC |
663 | aspace = msm_gem_address_space_create(&pdev->dev, |
664 | config->platform.iommu, "mdp5"); | |
665 | if (IS_ERR(aspace)) { | |
666 | ret = PTR_ERR(aspace); | |
aec095ec AT |
667 | goto fail; |
668 | } | |
669 | ||
667ce33e RC |
670 | mdp5_kms->aspace = aspace; |
671 | ||
672 | ret = aspace->mmu->funcs->attach(aspace->mmu, iommu_ports, | |
aec095ec AT |
673 | ARRAY_SIZE(iommu_ports)); |
674 | if (ret) { | |
675 | dev_err(&pdev->dev, "failed to attach iommu: %d\n", | |
676 | ret); | |
aec095ec AT |
677 | goto fail; |
678 | } | |
679 | } else { | |
680 | dev_info(&pdev->dev, | |
681 | "no iommu, fallback to phys contig buffers for scanout\n"); | |
667ce33e | 682 | aspace = NULL;; |
aec095ec | 683 | } |
aec095ec | 684 | |
667ce33e | 685 | mdp5_kms->id = msm_register_address_space(dev, aspace); |
aec095ec AT |
686 | if (mdp5_kms->id < 0) { |
687 | ret = mdp5_kms->id; | |
688 | dev_err(&pdev->dev, "failed to register mdp5 iommu: %d\n", ret); | |
689 | goto fail; | |
690 | } | |
691 | ||
692 | ret = modeset_init(mdp5_kms); | |
693 | if (ret) { | |
694 | dev_err(&pdev->dev, "modeset_init failed: %d\n", ret); | |
695 | goto fail; | |
696 | } | |
697 | ||
698 | dev->mode_config.min_width = 0; | |
699 | dev->mode_config.min_height = 0; | |
9708ebbe RC |
700 | dev->mode_config.max_width = 0xffff; |
701 | dev->mode_config.max_height = 0xffff; | |
aec095ec AT |
702 | |
703 | dev->driver->get_vblank_timestamp = mdp5_get_vblank_timestamp; | |
704 | dev->driver->get_scanout_position = mdp5_get_scanoutpos; | |
705 | dev->driver->get_vblank_counter = mdp5_get_vblank_counter; | |
706 | dev->max_vblank_count = 0xffffffff; | |
707 | dev->vblank_disable_immediate = true; | |
708 | ||
709 | return kms; | |
710 | fail: | |
711 | if (kms) | |
392ae6e0 | 712 | mdp5_kms_destroy(kms); |
aec095ec AT |
713 | return ERR_PTR(ret); |
714 | } | |
715 | ||
1dd0a0b1 AT |
716 | static void mdp5_destroy(struct platform_device *pdev) |
717 | { | |
718 | struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev); | |
719 | ||
720 | if (mdp5_kms->ctlm) | |
721 | mdp5_ctlm_destroy(mdp5_kms->ctlm); | |
722 | if (mdp5_kms->smp) | |
723 | mdp5_smp_destroy(mdp5_kms->smp); | |
724 | if (mdp5_kms->cfg) | |
725 | mdp5_cfg_destroy(mdp5_kms->cfg); | |
cd792726 AT |
726 | |
727 | if (mdp5_kms->rpm_enabled) | |
728 | pm_runtime_disable(&pdev->dev); | |
ac2a3fd3 RC |
729 | |
730 | kfree(mdp5_kms->state); | |
1dd0a0b1 AT |
731 | } |
732 | ||
c056b55d RC |
733 | static int construct_pipes(struct mdp5_kms *mdp5_kms, int cnt, |
734 | const enum mdp5_pipe *pipes, const uint32_t *offsets, | |
735 | uint32_t caps) | |
736 | { | |
737 | struct drm_device *dev = mdp5_kms->dev; | |
738 | int i, ret; | |
739 | ||
740 | for (i = 0; i < cnt; i++) { | |
741 | struct mdp5_hw_pipe *hwpipe; | |
742 | ||
743 | hwpipe = mdp5_pipe_init(pipes[i], offsets[i], caps); | |
744 | if (IS_ERR(hwpipe)) { | |
745 | ret = PTR_ERR(hwpipe); | |
746 | dev_err(dev->dev, "failed to construct pipe for %s (%d)\n", | |
747 | pipe2name(pipes[i]), ret); | |
748 | return ret; | |
749 | } | |
750 | hwpipe->idx = mdp5_kms->num_hwpipes; | |
751 | mdp5_kms->hwpipes[mdp5_kms->num_hwpipes++] = hwpipe; | |
752 | } | |
753 | ||
754 | return 0; | |
755 | } | |
756 | ||
757 | static int hwpipe_init(struct mdp5_kms *mdp5_kms) | |
758 | { | |
759 | static const enum mdp5_pipe rgb_planes[] = { | |
760 | SSPP_RGB0, SSPP_RGB1, SSPP_RGB2, SSPP_RGB3, | |
761 | }; | |
762 | static const enum mdp5_pipe vig_planes[] = { | |
763 | SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3, | |
764 | }; | |
765 | static const enum mdp5_pipe dma_planes[] = { | |
766 | SSPP_DMA0, SSPP_DMA1, | |
767 | }; | |
768 | const struct mdp5_cfg_hw *hw_cfg; | |
769 | int ret; | |
770 | ||
771 | hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); | |
772 | ||
773 | /* Construct RGB pipes: */ | |
774 | ret = construct_pipes(mdp5_kms, hw_cfg->pipe_rgb.count, rgb_planes, | |
775 | hw_cfg->pipe_rgb.base, hw_cfg->pipe_rgb.caps); | |
776 | if (ret) | |
777 | return ret; | |
778 | ||
779 | /* Construct video (VIG) pipes: */ | |
780 | ret = construct_pipes(mdp5_kms, hw_cfg->pipe_vig.count, vig_planes, | |
781 | hw_cfg->pipe_vig.base, hw_cfg->pipe_vig.caps); | |
782 | if (ret) | |
783 | return ret; | |
784 | ||
785 | /* Construct DMA pipes: */ | |
786 | ret = construct_pipes(mdp5_kms, hw_cfg->pipe_dma.count, dma_planes, | |
787 | hw_cfg->pipe_dma.base, hw_cfg->pipe_dma.caps); | |
788 | if (ret) | |
789 | return ret; | |
790 | ||
791 | return 0; | |
792 | } | |
793 | ||
1dd0a0b1 AT |
794 | static int mdp5_init(struct platform_device *pdev, struct drm_device *dev) |
795 | { | |
796 | struct msm_drm_private *priv = dev->dev_private; | |
797 | struct mdp5_kms *mdp5_kms; | |
798 | struct mdp5_cfg *config; | |
799 | u32 major, minor; | |
800 | int ret; | |
801 | ||
802 | mdp5_kms = devm_kzalloc(&pdev->dev, sizeof(*mdp5_kms), GFP_KERNEL); | |
803 | if (!mdp5_kms) { | |
804 | ret = -ENOMEM; | |
805 | goto fail; | |
806 | } | |
807 | ||
808 | platform_set_drvdata(pdev, mdp5_kms); | |
809 | ||
810 | spin_lock_init(&mdp5_kms->resource_lock); | |
811 | ||
812 | mdp5_kms->dev = dev; | |
813 | mdp5_kms->pdev = pdev; | |
814 | ||
ac2a3fd3 RC |
815 | drm_modeset_lock_init(&mdp5_kms->state_lock); |
816 | mdp5_kms->state = kzalloc(sizeof(*mdp5_kms->state), GFP_KERNEL); | |
817 | if (!mdp5_kms->state) { | |
818 | ret = -ENOMEM; | |
819 | goto fail; | |
820 | } | |
821 | ||
1dd0a0b1 AT |
822 | mdp5_kms->mmio = msm_ioremap(pdev, "mdp_phys", "MDP5"); |
823 | if (IS_ERR(mdp5_kms->mmio)) { | |
824 | ret = PTR_ERR(mdp5_kms->mmio); | |
825 | goto fail; | |
826 | } | |
827 | ||
828 | /* mandatory clocks: */ | |
829 | ret = get_clk(pdev, &mdp5_kms->axi_clk, "bus_clk", true); | |
830 | if (ret) | |
831 | goto fail; | |
832 | ret = get_clk(pdev, &mdp5_kms->ahb_clk, "iface_clk", true); | |
833 | if (ret) | |
834 | goto fail; | |
835 | ret = get_clk(pdev, &mdp5_kms->core_clk, "core_clk", true); | |
836 | if (ret) | |
837 | goto fail; | |
838 | ret = get_clk(pdev, &mdp5_kms->vsync_clk, "vsync_clk", true); | |
839 | if (ret) | |
840 | goto fail; | |
841 | ||
842 | /* optional clocks: */ | |
843 | get_clk(pdev, &mdp5_kms->lut_clk, "lut_clk", false); | |
844 | ||
845 | /* we need to set a default rate before enabling. Set a safe | |
846 | * rate first, then figure out hw revision, and then set a | |
847 | * more optimal rate: | |
848 | */ | |
849 | clk_set_rate(mdp5_kms->core_clk, 200000000); | |
850 | ||
cd792726 AT |
851 | pm_runtime_enable(&pdev->dev); |
852 | mdp5_kms->rpm_enabled = true; | |
853 | ||
1dd0a0b1 AT |
854 | read_mdp_hw_revision(mdp5_kms, &major, &minor); |
855 | ||
856 | mdp5_kms->cfg = mdp5_cfg_init(mdp5_kms, major, minor); | |
857 | if (IS_ERR(mdp5_kms->cfg)) { | |
858 | ret = PTR_ERR(mdp5_kms->cfg); | |
859 | mdp5_kms->cfg = NULL; | |
860 | goto fail; | |
861 | } | |
862 | ||
863 | config = mdp5_cfg_get_config(mdp5_kms->cfg); | |
864 | mdp5_kms->caps = config->hw->mdp.caps; | |
865 | ||
866 | /* TODO: compute core clock rate at runtime */ | |
867 | clk_set_rate(mdp5_kms->core_clk, config->hw->max_clk); | |
868 | ||
869 | /* | |
870 | * Some chipsets have a Shared Memory Pool (SMP), while others | |
871 | * have dedicated latency buffering per source pipe instead; | |
872 | * this section initializes the SMP: | |
873 | */ | |
874 | if (mdp5_kms->caps & MDP_CAP_SMP) { | |
49ec5b2e | 875 | mdp5_kms->smp = mdp5_smp_init(mdp5_kms, &config->hw->smp); |
1dd0a0b1 AT |
876 | if (IS_ERR(mdp5_kms->smp)) { |
877 | ret = PTR_ERR(mdp5_kms->smp); | |
878 | mdp5_kms->smp = NULL; | |
879 | goto fail; | |
880 | } | |
881 | } | |
882 | ||
883 | mdp5_kms->ctlm = mdp5_ctlm_init(dev, mdp5_kms->mmio, mdp5_kms->cfg); | |
884 | if (IS_ERR(mdp5_kms->ctlm)) { | |
885 | ret = PTR_ERR(mdp5_kms->ctlm); | |
886 | mdp5_kms->ctlm = NULL; | |
887 | goto fail; | |
888 | } | |
889 | ||
c056b55d RC |
890 | ret = hwpipe_init(mdp5_kms); |
891 | if (ret) | |
892 | goto fail; | |
893 | ||
1dd0a0b1 AT |
894 | /* set uninit-ed kms */ |
895 | priv->kms = &mdp5_kms->base.base; | |
896 | ||
897 | return 0; | |
898 | fail: | |
899 | mdp5_destroy(pdev); | |
900 | return ret; | |
901 | } | |
902 | ||
903 | static int mdp5_bind(struct device *dev, struct device *master, void *data) | |
904 | { | |
905 | struct drm_device *ddev = dev_get_drvdata(master); | |
906 | struct platform_device *pdev = to_platform_device(dev); | |
907 | ||
908 | DBG(""); | |
909 | ||
910 | return mdp5_init(pdev, ddev); | |
911 | } | |
912 | ||
913 | static void mdp5_unbind(struct device *dev, struct device *master, | |
914 | void *data) | |
915 | { | |
916 | struct platform_device *pdev = to_platform_device(dev); | |
917 | ||
918 | mdp5_destroy(pdev); | |
919 | } | |
920 | ||
921 | static const struct component_ops mdp5_ops = { | |
922 | .bind = mdp5_bind, | |
923 | .unbind = mdp5_unbind, | |
924 | }; | |
925 | ||
926 | static int mdp5_dev_probe(struct platform_device *pdev) | |
927 | { | |
928 | DBG(""); | |
929 | return component_add(&pdev->dev, &mdp5_ops); | |
930 | } | |
931 | ||
932 | static int mdp5_dev_remove(struct platform_device *pdev) | |
933 | { | |
934 | DBG(""); | |
935 | component_del(&pdev->dev, &mdp5_ops); | |
936 | return 0; | |
937 | } | |
938 | ||
96a611b5 AT |
939 | static const struct of_device_id mdp5_dt_match[] = { |
940 | { .compatible = "qcom,mdp5", }, | |
941 | /* to support downstream DT files */ | |
942 | { .compatible = "qcom,mdss_mdp", }, | |
943 | {} | |
944 | }; | |
945 | MODULE_DEVICE_TABLE(of, mdp5_dt_match); | |
946 | ||
1dd0a0b1 AT |
947 | static struct platform_driver mdp5_driver = { |
948 | .probe = mdp5_dev_probe, | |
949 | .remove = mdp5_dev_remove, | |
950 | .driver = { | |
951 | .name = "msm_mdp", | |
96a611b5 | 952 | .of_match_table = mdp5_dt_match, |
1dd0a0b1 AT |
953 | }, |
954 | }; | |
955 | ||
956 | void __init msm_mdp_register(void) | |
957 | { | |
958 | DBG(""); | |
959 | platform_driver_register(&mdp5_driver); | |
960 | } | |
961 | ||
962 | void __exit msm_mdp_unregister(void) | |
963 | { | |
964 | DBG(""); | |
965 | platform_driver_unregister(&mdp5_driver); | |
966 | } |