Commit | Line | Data |
---|---|---|
06c0dd96 | 1 | /* |
2e362e17 | 2 | * Copyright (c) 2014, The Linux Foundation. All rights reserved. |
06c0dd96 RC |
3 | * Copyright (C) 2013 Red Hat |
4 | * Author: Rob Clark <robdclark@gmail.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published by | |
8 | * the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along with | |
16 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | ||
aec095ec | 19 | #include <linux/of_irq.h> |
06c0dd96 RC |
20 | |
21 | #include "msm_drv.h" | |
667ce33e | 22 | #include "msm_gem.h" |
06c0dd96 RC |
23 | #include "msm_mmu.h" |
24 | #include "mdp5_kms.h" | |
25 | ||
87e956e9 SV |
26 | static const char *iommu_ports[] = { |
27 | "mdp_0", | |
28 | }; | |
29 | ||
3d47fd47 SV |
30 | static int mdp5_hw_init(struct msm_kms *kms) |
31 | { | |
32 | struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); | |
0a6030d2 | 33 | struct platform_device *pdev = mdp5_kms->pdev; |
0deed25b | 34 | unsigned long flags; |
3d47fd47 | 35 | |
0a6030d2 | 36 | pm_runtime_get_sync(&pdev->dev); |
7c8f0235 | 37 | mdp5_enable(mdp5_kms); |
3d47fd47 | 38 | |
06c0dd96 RC |
39 | /* Magic unknown register writes: |
40 | * | |
41 | * W VBIF:0x004 00000001 (mdss_mdp.c:839) | |
42 | * W MDP5:0x2e0 0xe9 (mdss_mdp.c:839) | |
43 | * W MDP5:0x2e4 0x55 (mdss_mdp.c:839) | |
44 | * W MDP5:0x3ac 0xc0000ccc (mdss_mdp.c:839) | |
45 | * W MDP5:0x3b4 0xc0000ccc (mdss_mdp.c:839) | |
46 | * W MDP5:0x3bc 0xcccccc (mdss_mdp.c:839) | |
47 | * W MDP5:0x4a8 0xcccc0c0 (mdss_mdp.c:839) | |
48 | * W MDP5:0x4b0 0xccccc0c0 (mdss_mdp.c:839) | |
49 | * W MDP5:0x4b8 0xccccc000 (mdss_mdp.c:839) | |
50 | * | |
51 | * Downstream fbdev driver gets these register offsets/values | |
52 | * from DT.. not really sure what these registers are or if | |
53 | * different values for different boards/SoC's, etc. I guess | |
54 | * they are the golden registers. | |
55 | * | |
56 | * Not setting these does not seem to cause any problem. But | |
57 | * we may be getting lucky with the bootloader initializing | |
58 | * them for us. OTOH, if we can always count on the bootloader | |
59 | * setting the golden registers, then perhaps we don't need to | |
60 | * care. | |
61 | */ | |
62 | ||
0deed25b | 63 | spin_lock_irqsave(&mdp5_kms->resource_lock, flags); |
7b59c7e4 | 64 | mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, 0); |
0deed25b | 65 | spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags); |
06c0dd96 | 66 | |
42238da8 | 67 | mdp5_ctlm_hw_reset(mdp5_kms->ctlm); |
3d47fd47 | 68 | |
7c8f0235 | 69 | mdp5_disable(mdp5_kms); |
0a6030d2 | 70 | pm_runtime_put_sync(&pdev->dev); |
06c0dd96 | 71 | |
3d47fd47 | 72 | return 0; |
06c0dd96 RC |
73 | } |
74 | ||
ac2a3fd3 RC |
75 | struct mdp5_state *mdp5_get_state(struct drm_atomic_state *s) |
76 | { | |
77 | struct msm_drm_private *priv = s->dev->dev_private; | |
78 | struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); | |
79 | struct msm_kms_state *state = to_kms_state(s); | |
80 | struct mdp5_state *new_state; | |
81 | int ret; | |
82 | ||
83 | if (state->state) | |
84 | return state->state; | |
85 | ||
86 | ret = drm_modeset_lock(&mdp5_kms->state_lock, s->acquire_ctx); | |
87 | if (ret) | |
88 | return ERR_PTR(ret); | |
89 | ||
90 | new_state = kmalloc(sizeof(*mdp5_kms->state), GFP_KERNEL); | |
91 | if (!new_state) | |
92 | return ERR_PTR(-ENOMEM); | |
93 | ||
94 | /* Copy state: */ | |
4a0f012d | 95 | new_state->hwpipe = mdp5_kms->state->hwpipe; |
894558ec | 96 | new_state->hwmixer = mdp5_kms->state->hwmixer; |
49ec5b2e RC |
97 | if (mdp5_kms->smp) |
98 | new_state->smp = mdp5_kms->state->smp; | |
ac2a3fd3 RC |
99 | |
100 | state->state = new_state; | |
101 | ||
102 | return new_state; | |
103 | } | |
104 | ||
105 | static void mdp5_swap_state(struct msm_kms *kms, struct drm_atomic_state *state) | |
106 | { | |
107 | struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); | |
108 | swap(to_kms_state(state)->state, mdp5_kms->state); | |
109 | } | |
110 | ||
0b776d45 RC |
111 | static void mdp5_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state) |
112 | { | |
113 | struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); | |
49ec5b2e | 114 | |
0b776d45 | 115 | mdp5_enable(mdp5_kms); |
49ec5b2e RC |
116 | |
117 | if (mdp5_kms->smp) | |
118 | mdp5_smp_prepare_commit(mdp5_kms->smp, &mdp5_kms->state->smp); | |
0b776d45 RC |
119 | } |
120 | ||
121 | static void mdp5_complete_commit(struct msm_kms *kms, struct drm_atomic_state *state) | |
122 | { | |
123 | struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); | |
657c63f0 | 124 | |
49ec5b2e RC |
125 | if (mdp5_kms->smp) |
126 | mdp5_smp_complete_commit(mdp5_kms->smp, &mdp5_kms->state->smp); | |
127 | ||
0b776d45 RC |
128 | mdp5_disable(mdp5_kms); |
129 | } | |
130 | ||
0a5c9aad HL |
131 | static void mdp5_wait_for_crtc_commit_done(struct msm_kms *kms, |
132 | struct drm_crtc *crtc) | |
133 | { | |
134 | mdp5_crtc_wait_for_commit_done(crtc); | |
135 | } | |
136 | ||
06c0dd96 RC |
137 | static long mdp5_round_pixclk(struct msm_kms *kms, unsigned long rate, |
138 | struct drm_encoder *encoder) | |
139 | { | |
140 | return rate; | |
141 | } | |
142 | ||
d5af49c9 HL |
143 | static int mdp5_set_split_display(struct msm_kms *kms, |
144 | struct drm_encoder *encoder, | |
145 | struct drm_encoder *slave_encoder, | |
146 | bool is_cmd_mode) | |
147 | { | |
148 | if (is_cmd_mode) | |
149 | return mdp5_cmd_encoder_set_split_display(encoder, | |
150 | slave_encoder); | |
151 | else | |
df8a71d2 AT |
152 | return mdp5_vid_encoder_set_split_display(encoder, |
153 | slave_encoder); | |
d5af49c9 HL |
154 | } |
155 | ||
9c9f6f8d AT |
156 | static void mdp5_set_encoder_mode(struct msm_kms *kms, |
157 | struct drm_encoder *encoder, | |
158 | bool cmd_mode) | |
159 | { | |
160 | mdp5_encoder_set_intf_mode(encoder, cmd_mode); | |
161 | } | |
162 | ||
1dd0a0b1 | 163 | static void mdp5_kms_destroy(struct msm_kms *kms) |
06c0dd96 RC |
164 | { |
165 | struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); | |
667ce33e | 166 | struct msm_gem_address_space *aspace = mdp5_kms->aspace; |
c056b55d RC |
167 | int i; |
168 | ||
6803c606 AT |
169 | for (i = 0; i < mdp5_kms->num_hwmixers; i++) |
170 | mdp5_mixer_destroy(mdp5_kms->hwmixers[i]); | |
171 | ||
c056b55d RC |
172 | for (i = 0; i < mdp5_kms->num_hwpipes; i++) |
173 | mdp5_pipe_destroy(mdp5_kms->hwpipes[i]); | |
87e956e9 | 174 | |
667ce33e RC |
175 | if (aspace) { |
176 | aspace->mmu->funcs->detach(aspace->mmu, | |
177 | iommu_ports, ARRAY_SIZE(iommu_ports)); | |
ee546cd3 | 178 | msm_gem_address_space_put(aspace); |
87e956e9 | 179 | } |
aec095ec AT |
180 | } |
181 | ||
bc5289ee RC |
182 | #ifdef CONFIG_DEBUG_FS |
183 | static int smp_show(struct seq_file *m, void *arg) | |
184 | { | |
185 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
186 | struct drm_device *dev = node->minor->dev; | |
187 | struct msm_drm_private *priv = dev->dev_private; | |
188 | struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); | |
189 | struct drm_printer p = drm_seq_file_printer(m); | |
190 | ||
191 | if (!mdp5_kms->smp) { | |
192 | drm_printf(&p, "no SMP pool\n"); | |
193 | return 0; | |
194 | } | |
195 | ||
196 | mdp5_smp_dump(mdp5_kms->smp, &p); | |
197 | ||
198 | return 0; | |
199 | } | |
200 | ||
201 | static struct drm_info_list mdp5_debugfs_list[] = { | |
202 | {"smp", smp_show }, | |
203 | }; | |
204 | ||
205 | static int mdp5_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor) | |
206 | { | |
207 | struct drm_device *dev = minor->dev; | |
208 | int ret; | |
209 | ||
210 | ret = drm_debugfs_create_files(mdp5_debugfs_list, | |
211 | ARRAY_SIZE(mdp5_debugfs_list), | |
212 | minor->debugfs_root, minor); | |
213 | ||
214 | if (ret) { | |
215 | dev_err(dev->dev, "could not install mdp5_debugfs_list\n"); | |
216 | return ret; | |
217 | } | |
218 | ||
219 | return 0; | |
220 | } | |
bc5289ee RC |
221 | #endif |
222 | ||
06c0dd96 RC |
223 | static const struct mdp_kms_funcs kms_funcs = { |
224 | .base = { | |
225 | .hw_init = mdp5_hw_init, | |
226 | .irq_preinstall = mdp5_irq_preinstall, | |
227 | .irq_postinstall = mdp5_irq_postinstall, | |
228 | .irq_uninstall = mdp5_irq_uninstall, | |
229 | .irq = mdp5_irq, | |
230 | .enable_vblank = mdp5_enable_vblank, | |
231 | .disable_vblank = mdp5_disable_vblank, | |
ac2a3fd3 | 232 | .swap_state = mdp5_swap_state, |
0b776d45 RC |
233 | .prepare_commit = mdp5_prepare_commit, |
234 | .complete_commit = mdp5_complete_commit, | |
0a5c9aad | 235 | .wait_for_crtc_commit_done = mdp5_wait_for_crtc_commit_done, |
06c0dd96 RC |
236 | .get_format = mdp_get_format, |
237 | .round_pixclk = mdp5_round_pixclk, | |
d5af49c9 | 238 | .set_split_display = mdp5_set_split_display, |
9c9f6f8d | 239 | .set_encoder_mode = mdp5_set_encoder_mode, |
392ae6e0 | 240 | .destroy = mdp5_kms_destroy, |
bc5289ee RC |
241 | #ifdef CONFIG_DEBUG_FS |
242 | .debugfs_init = mdp5_kms_debugfs_init, | |
bc5289ee | 243 | #endif |
06c0dd96 RC |
244 | }, |
245 | .set_irqmask = mdp5_set_irqmask, | |
246 | }; | |
247 | ||
248 | int mdp5_disable(struct mdp5_kms *mdp5_kms) | |
249 | { | |
250 | DBG(""); | |
251 | ||
252 | clk_disable_unprepare(mdp5_kms->ahb_clk); | |
253 | clk_disable_unprepare(mdp5_kms->axi_clk); | |
254 | clk_disable_unprepare(mdp5_kms->core_clk); | |
3a84f846 SV |
255 | if (mdp5_kms->lut_clk) |
256 | clk_disable_unprepare(mdp5_kms->lut_clk); | |
06c0dd96 RC |
257 | |
258 | return 0; | |
259 | } | |
260 | ||
261 | int mdp5_enable(struct mdp5_kms *mdp5_kms) | |
262 | { | |
263 | DBG(""); | |
264 | ||
265 | clk_prepare_enable(mdp5_kms->ahb_clk); | |
266 | clk_prepare_enable(mdp5_kms->axi_clk); | |
267 | clk_prepare_enable(mdp5_kms->core_clk); | |
3a84f846 SV |
268 | if (mdp5_kms->lut_clk) |
269 | clk_prepare_enable(mdp5_kms->lut_clk); | |
06c0dd96 RC |
270 | |
271 | return 0; | |
272 | } | |
273 | ||
5722a9e3 | 274 | static struct drm_encoder *construct_encoder(struct mdp5_kms *mdp5_kms, |
36d1364a AT |
275 | struct mdp5_interface *intf, |
276 | struct mdp5_ctl *ctl) | |
67ac0a2d SV |
277 | { |
278 | struct drm_device *dev = mdp5_kms->dev; | |
279 | struct msm_drm_private *priv = dev->dev_private; | |
280 | struct drm_encoder *encoder; | |
67ac0a2d | 281 | |
36d1364a | 282 | encoder = mdp5_encoder_init(dev, intf, ctl); |
67ac0a2d | 283 | if (IS_ERR(encoder)) { |
5722a9e3 HL |
284 | dev_err(dev->dev, "failed to construct encoder\n"); |
285 | return encoder; | |
67ac0a2d SV |
286 | } |
287 | ||
67ac0a2d SV |
288 | priv->encoders[priv->num_encoders++] = encoder; |
289 | ||
5722a9e3 HL |
290 | return encoder; |
291 | } | |
292 | ||
d5af49c9 HL |
293 | static int get_dsi_id_from_intf(const struct mdp5_cfg_hw *hw_cfg, int intf_num) |
294 | { | |
fe34464d SV |
295 | const enum mdp5_intf_type *intfs = hw_cfg->intf.connect; |
296 | const int intf_cnt = ARRAY_SIZE(hw_cfg->intf.connect); | |
d5af49c9 HL |
297 | int id = 0, i; |
298 | ||
299 | for (i = 0; i < intf_cnt; i++) { | |
300 | if (intfs[i] == INTF_DSI) { | |
301 | if (intf_num == i) | |
302 | return id; | |
303 | ||
304 | id++; | |
305 | } | |
306 | } | |
307 | ||
308 | return -EINVAL; | |
309 | } | |
310 | ||
36d1364a AT |
311 | static int modeset_init_intf(struct mdp5_kms *mdp5_kms, |
312 | struct mdp5_interface *intf) | |
5722a9e3 HL |
313 | { |
314 | struct drm_device *dev = mdp5_kms->dev; | |
315 | struct msm_drm_private *priv = dev->dev_private; | |
c71716b1 HL |
316 | struct mdp5_ctl_manager *ctlm = mdp5_kms->ctlm; |
317 | struct mdp5_ctl *ctl; | |
5722a9e3 HL |
318 | struct drm_encoder *encoder; |
319 | int ret = 0; | |
320 | ||
36d1364a | 321 | switch (intf->type) { |
5722a9e3 HL |
322 | case INTF_eDP: |
323 | if (!priv->edp) | |
324 | break; | |
325 | ||
36d1364a | 326 | ctl = mdp5_ctlm_request(ctlm, intf->num); |
c71716b1 HL |
327 | if (!ctl) { |
328 | ret = -EINVAL; | |
329 | break; | |
330 | } | |
331 | ||
36d1364a | 332 | encoder = construct_encoder(mdp5_kms, intf, ctl); |
5722a9e3 HL |
333 | if (IS_ERR(encoder)) { |
334 | ret = PTR_ERR(encoder); | |
335 | break; | |
336 | } | |
67ac0a2d | 337 | |
67ac0a2d | 338 | ret = msm_edp_modeset_init(priv->edp, dev, encoder); |
5722a9e3 HL |
339 | break; |
340 | case INTF_HDMI: | |
341 | if (!priv->hdmi) | |
342 | break; | |
343 | ||
36d1364a | 344 | ctl = mdp5_ctlm_request(ctlm, intf->num); |
c71716b1 HL |
345 | if (!ctl) { |
346 | ret = -EINVAL; | |
347 | break; | |
348 | } | |
349 | ||
36d1364a | 350 | encoder = construct_encoder(mdp5_kms, intf, ctl); |
5722a9e3 HL |
351 | if (IS_ERR(encoder)) { |
352 | ret = PTR_ERR(encoder); | |
353 | break; | |
354 | } | |
355 | ||
fcda50c8 | 356 | ret = msm_hdmi_modeset_init(priv->hdmi, dev, encoder); |
5722a9e3 | 357 | break; |
d5af49c9 HL |
358 | case INTF_DSI: |
359 | { | |
36d1364a AT |
360 | const struct mdp5_cfg_hw *hw_cfg = |
361 | mdp5_cfg_get_hw_config(mdp5_kms->cfg); | |
362 | int dsi_id = get_dsi_id_from_intf(hw_cfg, intf->num); | |
d5af49c9 HL |
363 | |
364 | if ((dsi_id >= ARRAY_SIZE(priv->dsi)) || (dsi_id < 0)) { | |
365 | dev_err(dev->dev, "failed to find dsi from intf %d\n", | |
36d1364a | 366 | intf->num); |
d5af49c9 HL |
367 | ret = -EINVAL; |
368 | break; | |
369 | } | |
370 | ||
371 | if (!priv->dsi[dsi_id]) | |
372 | break; | |
373 | ||
36d1364a | 374 | ctl = mdp5_ctlm_request(ctlm, intf->num); |
c71716b1 HL |
375 | if (!ctl) { |
376 | ret = -EINVAL; | |
377 | break; | |
378 | } | |
379 | ||
36d1364a | 380 | encoder = construct_encoder(mdp5_kms, intf, ctl); |
97e00119 AT |
381 | if (IS_ERR(encoder)) { |
382 | ret = PTR_ERR(encoder); | |
383 | break; | |
d5af49c9 HL |
384 | } |
385 | ||
97e00119 | 386 | ret = msm_dsi_modeset_init(priv->dsi[dsi_id], dev, encoder); |
d5af49c9 HL |
387 | break; |
388 | } | |
5722a9e3 | 389 | default: |
36d1364a | 390 | dev_err(dev->dev, "unknown intf: %d\n", intf->type); |
5722a9e3 HL |
391 | ret = -EINVAL; |
392 | break; | |
67ac0a2d SV |
393 | } |
394 | ||
395 | return ret; | |
396 | } | |
397 | ||
06c0dd96 RC |
398 | static int modeset_init(struct mdp5_kms *mdp5_kms) |
399 | { | |
06c0dd96 RC |
400 | struct drm_device *dev = mdp5_kms->dev; |
401 | struct msm_drm_private *priv = dev->dev_private; | |
2e362e17 | 402 | const struct mdp5_cfg_hw *hw_cfg; |
e5366ffe | 403 | unsigned int num_crtcs; |
bff8fba4 AT |
404 | int i, ret, pi = 0, ci = 0; |
405 | struct drm_plane *primary[MAX_BASES] = { NULL }; | |
406 | struct drm_plane *cursor[MAX_BASES] = { NULL }; | |
06c0dd96 | 407 | |
42238da8 | 408 | hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); |
2e362e17 | 409 | |
e5366ffe AT |
410 | /* |
411 | * Construct encoders and modeset initialize connector devices | |
412 | * for each external display interface. | |
413 | */ | |
36d1364a AT |
414 | for (i = 0; i < mdp5_kms->num_intfs; i++) { |
415 | ret = modeset_init_intf(mdp5_kms, mdp5_kms->intfs[i]); | |
e5366ffe AT |
416 | if (ret) |
417 | goto fail; | |
418 | } | |
419 | ||
420 | /* | |
421 | * We should ideally have less number of encoders (set up by parsing | |
422 | * the MDP5 interfaces) than the number of layer mixers present in HW, | |
423 | * but let's be safe here anyway | |
424 | */ | |
adfc0e63 | 425 | num_crtcs = min(priv->num_encoders, mdp5_kms->num_hwmixers); |
e5366ffe AT |
426 | |
427 | /* | |
428 | * Construct planes equaling the number of hw pipes, and CRTCs for the | |
429 | * N encoders set up by the driver. The first N planes become primary | |
c056b55d RC |
430 | * planes for the CRTCs, with the remainder as overlay planes: |
431 | */ | |
432 | for (i = 0; i < mdp5_kms->num_hwpipes; i++) { | |
bff8fba4 | 433 | struct mdp5_hw_pipe *hwpipe = mdp5_kms->hwpipes[i]; |
06c0dd96 | 434 | struct drm_plane *plane; |
5798c8e0 | 435 | enum drm_plane_type type; |
06c0dd96 | 436 | |
bff8fba4 | 437 | if (i < num_crtcs) |
5798c8e0 | 438 | type = DRM_PLANE_TYPE_PRIMARY; |
bff8fba4 AT |
439 | else if (hwpipe->caps & MDP_PIPE_CAP_CURSOR) |
440 | type = DRM_PLANE_TYPE_CURSOR; | |
5798c8e0 AT |
441 | else |
442 | type = DRM_PLANE_TYPE_OVERLAY; | |
443 | ||
444 | plane = mdp5_plane_init(dev, type); | |
06c0dd96 RC |
445 | if (IS_ERR(plane)) { |
446 | ret = PTR_ERR(plane); | |
c056b55d | 447 | dev_err(dev->dev, "failed to construct plane %d (%d)\n", i, ret); |
06c0dd96 RC |
448 | goto fail; |
449 | } | |
bc5289ee | 450 | priv->planes[priv->num_planes++] = plane; |
06c0dd96 | 451 | |
bff8fba4 AT |
452 | if (type == DRM_PLANE_TYPE_PRIMARY) |
453 | primary[pi++] = plane; | |
454 | if (type == DRM_PLANE_TYPE_CURSOR) | |
455 | cursor[ci++] = plane; | |
456 | } | |
457 | ||
458 | for (i = 0; i < num_crtcs; i++) { | |
459 | struct drm_crtc *crtc; | |
c056b55d | 460 | |
bff8fba4 | 461 | crtc = mdp5_crtc_init(dev, primary[i], cursor[i], i); |
06c0dd96 RC |
462 | if (IS_ERR(crtc)) { |
463 | ret = PTR_ERR(crtc); | |
c056b55d | 464 | dev_err(dev->dev, "failed to construct crtc %d (%d)\n", i, ret); |
06c0dd96 RC |
465 | goto fail; |
466 | } | |
467 | priv->crtcs[priv->num_crtcs++] = crtc; | |
468 | } | |
469 | ||
e5366ffe AT |
470 | /* |
471 | * Now that we know the number of crtcs we've created, set the possible | |
472 | * crtcs for the encoders | |
5722a9e3 | 473 | */ |
e5366ffe AT |
474 | for (i = 0; i < priv->num_encoders; i++) { |
475 | struct drm_encoder *encoder = priv->encoders[i]; | |
476 | ||
477 | encoder->possible_crtcs = (1 << priv->num_crtcs) - 1; | |
00453981 HL |
478 | } |
479 | ||
06c0dd96 RC |
480 | return 0; |
481 | ||
482 | fail: | |
483 | return ret; | |
484 | } | |
485 | ||
1dd0a0b1 AT |
486 | static void read_mdp_hw_revision(struct mdp5_kms *mdp5_kms, |
487 | u32 *major, u32 *minor) | |
488 | { | |
489 | u32 version; | |
490 | ||
491 | mdp5_enable(mdp5_kms); | |
7b59c7e4 | 492 | version = mdp5_read(mdp5_kms, REG_MDP5_HW_VERSION); |
1dd0a0b1 AT |
493 | mdp5_disable(mdp5_kms); |
494 | ||
7b59c7e4 AT |
495 | *major = FIELD(version, MDP5_HW_VERSION_MAJOR); |
496 | *minor = FIELD(version, MDP5_HW_VERSION_MINOR); | |
1dd0a0b1 AT |
497 | |
498 | DBG("MDP5 version v%d.%d", *major, *minor); | |
499 | } | |
500 | ||
06c0dd96 | 501 | static int get_clk(struct platform_device *pdev, struct clk **clkp, |
d40325b4 | 502 | const char *name, bool mandatory) |
06c0dd96 RC |
503 | { |
504 | struct device *dev = &pdev->dev; | |
505 | struct clk *clk = devm_clk_get(dev, name); | |
d40325b4 | 506 | if (IS_ERR(clk) && mandatory) { |
06c0dd96 RC |
507 | dev_err(dev, "failed to get %s (%ld)\n", name, PTR_ERR(clk)); |
508 | return PTR_ERR(clk); | |
509 | } | |
d40325b4 SV |
510 | if (IS_ERR(clk)) |
511 | DBG("skipping %s", name); | |
512 | else | |
513 | *clkp = clk; | |
514 | ||
06c0dd96 RC |
515 | return 0; |
516 | } | |
517 | ||
e2dd9f9f AT |
518 | static struct drm_encoder *get_encoder_from_crtc(struct drm_crtc *crtc) |
519 | { | |
520 | struct drm_device *dev = crtc->dev; | |
521 | struct drm_encoder *encoder; | |
522 | ||
523 | drm_for_each_encoder(encoder, dev) | |
524 | if (encoder->crtc == crtc) | |
525 | return encoder; | |
526 | ||
527 | return NULL; | |
528 | } | |
529 | ||
1bf6ad62 DV |
530 | static bool mdp5_get_scanoutpos(struct drm_device *dev, unsigned int pipe, |
531 | bool in_vblank_irq, int *vpos, int *hpos, | |
532 | ktime_t *stime, ktime_t *etime, | |
533 | const struct drm_display_mode *mode) | |
e2dd9f9f AT |
534 | { |
535 | struct msm_drm_private *priv = dev->dev_private; | |
536 | struct drm_crtc *crtc; | |
537 | struct drm_encoder *encoder; | |
538 | int line, vsw, vbp, vactive_start, vactive_end, vfp_end; | |
e2dd9f9f AT |
539 | |
540 | crtc = priv->crtcs[pipe]; | |
541 | if (!crtc) { | |
542 | DRM_ERROR("Invalid crtc %d\n", pipe); | |
1bf6ad62 | 543 | return false; |
e2dd9f9f AT |
544 | } |
545 | ||
546 | encoder = get_encoder_from_crtc(crtc); | |
547 | if (!encoder) { | |
548 | DRM_ERROR("no encoder found for crtc %d\n", pipe); | |
1bf6ad62 | 549 | return false; |
e2dd9f9f AT |
550 | } |
551 | ||
e2dd9f9f AT |
552 | vsw = mode->crtc_vsync_end - mode->crtc_vsync_start; |
553 | vbp = mode->crtc_vtotal - mode->crtc_vsync_end; | |
554 | ||
555 | /* | |
556 | * the line counter is 1 at the start of the VSYNC pulse and VTOTAL at | |
557 | * the end of VFP. Translate the porch values relative to the line | |
558 | * counter positions. | |
559 | */ | |
560 | ||
561 | vactive_start = vsw + vbp + 1; | |
562 | ||
563 | vactive_end = vactive_start + mode->crtc_vdisplay; | |
564 | ||
565 | /* last scan line before VSYNC */ | |
566 | vfp_end = mode->crtc_vtotal; | |
567 | ||
568 | if (stime) | |
569 | *stime = ktime_get(); | |
570 | ||
571 | line = mdp5_encoder_get_linecount(encoder); | |
572 | ||
573 | if (line < vactive_start) { | |
574 | line -= vactive_start; | |
e2dd9f9f AT |
575 | } else if (line > vactive_end) { |
576 | line = line - vfp_end - vactive_start; | |
e2dd9f9f AT |
577 | } else { |
578 | line -= vactive_start; | |
579 | } | |
580 | ||
581 | *vpos = line; | |
582 | *hpos = 0; | |
583 | ||
584 | if (etime) | |
585 | *etime = ktime_get(); | |
586 | ||
1bf6ad62 | 587 | return true; |
e2dd9f9f AT |
588 | } |
589 | ||
590 | static u32 mdp5_get_vblank_counter(struct drm_device *dev, unsigned int pipe) | |
591 | { | |
592 | struct msm_drm_private *priv = dev->dev_private; | |
593 | struct drm_crtc *crtc; | |
594 | struct drm_encoder *encoder; | |
595 | ||
596 | if (pipe < 0 || pipe >= priv->num_crtcs) | |
597 | return 0; | |
598 | ||
599 | crtc = priv->crtcs[pipe]; | |
600 | if (!crtc) | |
601 | return 0; | |
602 | ||
603 | encoder = get_encoder_from_crtc(crtc); | |
604 | if (!encoder) | |
605 | return 0; | |
606 | ||
607 | return mdp5_encoder_get_framecount(encoder); | |
608 | } | |
609 | ||
06c0dd96 | 610 | struct msm_kms *mdp5_kms_init(struct drm_device *dev) |
aec095ec AT |
611 | { |
612 | struct msm_drm_private *priv = dev->dev_private; | |
613 | struct platform_device *pdev; | |
614 | struct mdp5_kms *mdp5_kms; | |
615 | struct mdp5_cfg *config; | |
616 | struct msm_kms *kms; | |
667ce33e | 617 | struct msm_gem_address_space *aspace; |
aec095ec AT |
618 | int irq, i, ret; |
619 | ||
620 | /* priv->kms would have been populated by the MDP5 driver */ | |
621 | kms = priv->kms; | |
622 | if (!kms) | |
623 | return NULL; | |
624 | ||
625 | mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); | |
626 | ||
627 | mdp_kms_init(&mdp5_kms->base, &kms_funcs); | |
628 | ||
629 | pdev = mdp5_kms->pdev; | |
630 | ||
631 | irq = irq_of_parse_and_map(pdev->dev.of_node, 0); | |
632 | if (irq < 0) { | |
633 | ret = irq; | |
634 | dev_err(&pdev->dev, "failed to get irq: %d\n", ret); | |
635 | goto fail; | |
636 | } | |
637 | ||
638 | kms->irq = irq; | |
639 | ||
640 | config = mdp5_cfg_get_config(mdp5_kms->cfg); | |
641 | ||
642 | /* make sure things are off before attaching iommu (bootloader could | |
643 | * have left things on, in which case we'll start getting faults if | |
644 | * we don't disable): | |
645 | */ | |
646 | mdp5_enable(mdp5_kms); | |
647 | for (i = 0; i < MDP5_INTF_NUM_MAX; i++) { | |
648 | if (mdp5_cfg_intf_is_virtual(config->hw->intf.connect[i]) || | |
649 | !config->hw->intf.base[i]) | |
650 | continue; | |
651 | mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(i), 0); | |
652 | ||
653 | mdp5_write(mdp5_kms, REG_MDP5_INTF_FRAME_LINE_COUNT_EN(i), 0x3); | |
654 | } | |
655 | mdp5_disable(mdp5_kms); | |
656 | mdelay(16); | |
657 | ||
658 | if (config->platform.iommu) { | |
667ce33e RC |
659 | aspace = msm_gem_address_space_create(&pdev->dev, |
660 | config->platform.iommu, "mdp5"); | |
661 | if (IS_ERR(aspace)) { | |
662 | ret = PTR_ERR(aspace); | |
aec095ec AT |
663 | goto fail; |
664 | } | |
665 | ||
667ce33e RC |
666 | mdp5_kms->aspace = aspace; |
667 | ||
668 | ret = aspace->mmu->funcs->attach(aspace->mmu, iommu_ports, | |
aec095ec AT |
669 | ARRAY_SIZE(iommu_ports)); |
670 | if (ret) { | |
671 | dev_err(&pdev->dev, "failed to attach iommu: %d\n", | |
672 | ret); | |
aec095ec AT |
673 | goto fail; |
674 | } | |
675 | } else { | |
676 | dev_info(&pdev->dev, | |
677 | "no iommu, fallback to phys contig buffers for scanout\n"); | |
667ce33e | 678 | aspace = NULL;; |
aec095ec | 679 | } |
aec095ec | 680 | |
667ce33e | 681 | mdp5_kms->id = msm_register_address_space(dev, aspace); |
aec095ec AT |
682 | if (mdp5_kms->id < 0) { |
683 | ret = mdp5_kms->id; | |
684 | dev_err(&pdev->dev, "failed to register mdp5 iommu: %d\n", ret); | |
685 | goto fail; | |
686 | } | |
687 | ||
688 | ret = modeset_init(mdp5_kms); | |
689 | if (ret) { | |
690 | dev_err(&pdev->dev, "modeset_init failed: %d\n", ret); | |
691 | goto fail; | |
692 | } | |
693 | ||
694 | dev->mode_config.min_width = 0; | |
695 | dev->mode_config.min_height = 0; | |
9708ebbe RC |
696 | dev->mode_config.max_width = 0xffff; |
697 | dev->mode_config.max_height = 0xffff; | |
aec095ec | 698 | |
1bf6ad62 | 699 | dev->driver->get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos; |
aec095ec AT |
700 | dev->driver->get_scanout_position = mdp5_get_scanoutpos; |
701 | dev->driver->get_vblank_counter = mdp5_get_vblank_counter; | |
702 | dev->max_vblank_count = 0xffffffff; | |
703 | dev->vblank_disable_immediate = true; | |
704 | ||
705 | return kms; | |
706 | fail: | |
707 | if (kms) | |
392ae6e0 | 708 | mdp5_kms_destroy(kms); |
aec095ec AT |
709 | return ERR_PTR(ret); |
710 | } | |
711 | ||
1dd0a0b1 AT |
712 | static void mdp5_destroy(struct platform_device *pdev) |
713 | { | |
714 | struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev); | |
36d1364a | 715 | int i; |
1dd0a0b1 AT |
716 | |
717 | if (mdp5_kms->ctlm) | |
718 | mdp5_ctlm_destroy(mdp5_kms->ctlm); | |
719 | if (mdp5_kms->smp) | |
720 | mdp5_smp_destroy(mdp5_kms->smp); | |
721 | if (mdp5_kms->cfg) | |
722 | mdp5_cfg_destroy(mdp5_kms->cfg); | |
cd792726 | 723 | |
36d1364a AT |
724 | for (i = 0; i < mdp5_kms->num_intfs; i++) |
725 | kfree(mdp5_kms->intfs[i]); | |
726 | ||
cd792726 AT |
727 | if (mdp5_kms->rpm_enabled) |
728 | pm_runtime_disable(&pdev->dev); | |
ac2a3fd3 RC |
729 | |
730 | kfree(mdp5_kms->state); | |
1dd0a0b1 AT |
731 | } |
732 | ||
c056b55d RC |
733 | static int construct_pipes(struct mdp5_kms *mdp5_kms, int cnt, |
734 | const enum mdp5_pipe *pipes, const uint32_t *offsets, | |
735 | uint32_t caps) | |
736 | { | |
737 | struct drm_device *dev = mdp5_kms->dev; | |
738 | int i, ret; | |
739 | ||
740 | for (i = 0; i < cnt; i++) { | |
741 | struct mdp5_hw_pipe *hwpipe; | |
742 | ||
743 | hwpipe = mdp5_pipe_init(pipes[i], offsets[i], caps); | |
744 | if (IS_ERR(hwpipe)) { | |
745 | ret = PTR_ERR(hwpipe); | |
746 | dev_err(dev->dev, "failed to construct pipe for %s (%d)\n", | |
747 | pipe2name(pipes[i]), ret); | |
748 | return ret; | |
749 | } | |
750 | hwpipe->idx = mdp5_kms->num_hwpipes; | |
751 | mdp5_kms->hwpipes[mdp5_kms->num_hwpipes++] = hwpipe; | |
752 | } | |
753 | ||
754 | return 0; | |
755 | } | |
756 | ||
757 | static int hwpipe_init(struct mdp5_kms *mdp5_kms) | |
758 | { | |
759 | static const enum mdp5_pipe rgb_planes[] = { | |
760 | SSPP_RGB0, SSPP_RGB1, SSPP_RGB2, SSPP_RGB3, | |
761 | }; | |
762 | static const enum mdp5_pipe vig_planes[] = { | |
763 | SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3, | |
764 | }; | |
765 | static const enum mdp5_pipe dma_planes[] = { | |
766 | SSPP_DMA0, SSPP_DMA1, | |
767 | }; | |
bff8fba4 AT |
768 | static const enum mdp5_pipe cursor_planes[] = { |
769 | SSPP_CURSOR0, SSPP_CURSOR1, | |
770 | }; | |
c056b55d RC |
771 | const struct mdp5_cfg_hw *hw_cfg; |
772 | int ret; | |
773 | ||
774 | hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); | |
775 | ||
776 | /* Construct RGB pipes: */ | |
777 | ret = construct_pipes(mdp5_kms, hw_cfg->pipe_rgb.count, rgb_planes, | |
778 | hw_cfg->pipe_rgb.base, hw_cfg->pipe_rgb.caps); | |
779 | if (ret) | |
780 | return ret; | |
781 | ||
782 | /* Construct video (VIG) pipes: */ | |
783 | ret = construct_pipes(mdp5_kms, hw_cfg->pipe_vig.count, vig_planes, | |
784 | hw_cfg->pipe_vig.base, hw_cfg->pipe_vig.caps); | |
785 | if (ret) | |
786 | return ret; | |
787 | ||
788 | /* Construct DMA pipes: */ | |
789 | ret = construct_pipes(mdp5_kms, hw_cfg->pipe_dma.count, dma_planes, | |
790 | hw_cfg->pipe_dma.base, hw_cfg->pipe_dma.caps); | |
791 | if (ret) | |
792 | return ret; | |
793 | ||
bff8fba4 AT |
794 | /* Construct cursor pipes: */ |
795 | ret = construct_pipes(mdp5_kms, hw_cfg->pipe_cursor.count, | |
796 | cursor_planes, hw_cfg->pipe_cursor.base, | |
797 | hw_cfg->pipe_cursor.caps); | |
798 | if (ret) | |
799 | return ret; | |
800 | ||
c056b55d RC |
801 | return 0; |
802 | } | |
803 | ||
6803c606 AT |
804 | static int hwmixer_init(struct mdp5_kms *mdp5_kms) |
805 | { | |
806 | struct drm_device *dev = mdp5_kms->dev; | |
807 | const struct mdp5_cfg_hw *hw_cfg; | |
808 | int i, ret; | |
809 | ||
810 | hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); | |
811 | ||
812 | for (i = 0; i < hw_cfg->lm.count; i++) { | |
813 | struct mdp5_hw_mixer *mixer; | |
814 | ||
815 | mixer = mdp5_mixer_init(&hw_cfg->lm.instances[i]); | |
816 | if (IS_ERR(mixer)) { | |
817 | ret = PTR_ERR(mixer); | |
818 | dev_err(dev->dev, "failed to construct LM%d (%d)\n", | |
819 | i, ret); | |
820 | return ret; | |
821 | } | |
822 | ||
823 | mixer->idx = mdp5_kms->num_hwmixers; | |
824 | mdp5_kms->hwmixers[mdp5_kms->num_hwmixers++] = mixer; | |
825 | } | |
826 | ||
827 | return 0; | |
828 | } | |
829 | ||
36d1364a AT |
830 | static int interface_init(struct mdp5_kms *mdp5_kms) |
831 | { | |
832 | struct drm_device *dev = mdp5_kms->dev; | |
833 | const struct mdp5_cfg_hw *hw_cfg; | |
834 | const enum mdp5_intf_type *intf_types; | |
835 | int i; | |
836 | ||
837 | hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); | |
838 | intf_types = hw_cfg->intf.connect; | |
839 | ||
840 | for (i = 0; i < ARRAY_SIZE(hw_cfg->intf.connect); i++) { | |
841 | struct mdp5_interface *intf; | |
842 | ||
843 | if (intf_types[i] == INTF_DISABLED) | |
844 | continue; | |
845 | ||
846 | intf = kzalloc(sizeof(*intf), GFP_KERNEL); | |
847 | if (!intf) { | |
848 | dev_err(dev->dev, "failed to construct INTF%d\n", i); | |
849 | return -ENOMEM; | |
850 | } | |
851 | ||
852 | intf->num = i; | |
853 | intf->type = intf_types[i]; | |
854 | intf->mode = MDP5_INTF_MODE_NONE; | |
855 | intf->idx = mdp5_kms->num_intfs; | |
856 | mdp5_kms->intfs[mdp5_kms->num_intfs++] = intf; | |
857 | } | |
858 | ||
859 | return 0; | |
860 | } | |
861 | ||
1dd0a0b1 AT |
862 | static int mdp5_init(struct platform_device *pdev, struct drm_device *dev) |
863 | { | |
864 | struct msm_drm_private *priv = dev->dev_private; | |
865 | struct mdp5_kms *mdp5_kms; | |
866 | struct mdp5_cfg *config; | |
867 | u32 major, minor; | |
868 | int ret; | |
869 | ||
870 | mdp5_kms = devm_kzalloc(&pdev->dev, sizeof(*mdp5_kms), GFP_KERNEL); | |
871 | if (!mdp5_kms) { | |
872 | ret = -ENOMEM; | |
873 | goto fail; | |
874 | } | |
875 | ||
876 | platform_set_drvdata(pdev, mdp5_kms); | |
877 | ||
878 | spin_lock_init(&mdp5_kms->resource_lock); | |
879 | ||
880 | mdp5_kms->dev = dev; | |
881 | mdp5_kms->pdev = pdev; | |
882 | ||
ac2a3fd3 RC |
883 | drm_modeset_lock_init(&mdp5_kms->state_lock); |
884 | mdp5_kms->state = kzalloc(sizeof(*mdp5_kms->state), GFP_KERNEL); | |
885 | if (!mdp5_kms->state) { | |
886 | ret = -ENOMEM; | |
887 | goto fail; | |
888 | } | |
889 | ||
1dd0a0b1 AT |
890 | mdp5_kms->mmio = msm_ioremap(pdev, "mdp_phys", "MDP5"); |
891 | if (IS_ERR(mdp5_kms->mmio)) { | |
892 | ret = PTR_ERR(mdp5_kms->mmio); | |
893 | goto fail; | |
894 | } | |
895 | ||
896 | /* mandatory clocks: */ | |
897 | ret = get_clk(pdev, &mdp5_kms->axi_clk, "bus_clk", true); | |
898 | if (ret) | |
899 | goto fail; | |
900 | ret = get_clk(pdev, &mdp5_kms->ahb_clk, "iface_clk", true); | |
901 | if (ret) | |
902 | goto fail; | |
903 | ret = get_clk(pdev, &mdp5_kms->core_clk, "core_clk", true); | |
904 | if (ret) | |
905 | goto fail; | |
906 | ret = get_clk(pdev, &mdp5_kms->vsync_clk, "vsync_clk", true); | |
907 | if (ret) | |
908 | goto fail; | |
909 | ||
910 | /* optional clocks: */ | |
911 | get_clk(pdev, &mdp5_kms->lut_clk, "lut_clk", false); | |
912 | ||
913 | /* we need to set a default rate before enabling. Set a safe | |
914 | * rate first, then figure out hw revision, and then set a | |
915 | * more optimal rate: | |
916 | */ | |
917 | clk_set_rate(mdp5_kms->core_clk, 200000000); | |
918 | ||
cd792726 AT |
919 | pm_runtime_enable(&pdev->dev); |
920 | mdp5_kms->rpm_enabled = true; | |
921 | ||
1dd0a0b1 AT |
922 | read_mdp_hw_revision(mdp5_kms, &major, &minor); |
923 | ||
924 | mdp5_kms->cfg = mdp5_cfg_init(mdp5_kms, major, minor); | |
925 | if (IS_ERR(mdp5_kms->cfg)) { | |
926 | ret = PTR_ERR(mdp5_kms->cfg); | |
927 | mdp5_kms->cfg = NULL; | |
928 | goto fail; | |
929 | } | |
930 | ||
931 | config = mdp5_cfg_get_config(mdp5_kms->cfg); | |
932 | mdp5_kms->caps = config->hw->mdp.caps; | |
933 | ||
934 | /* TODO: compute core clock rate at runtime */ | |
935 | clk_set_rate(mdp5_kms->core_clk, config->hw->max_clk); | |
936 | ||
937 | /* | |
938 | * Some chipsets have a Shared Memory Pool (SMP), while others | |
939 | * have dedicated latency buffering per source pipe instead; | |
940 | * this section initializes the SMP: | |
941 | */ | |
942 | if (mdp5_kms->caps & MDP_CAP_SMP) { | |
49ec5b2e | 943 | mdp5_kms->smp = mdp5_smp_init(mdp5_kms, &config->hw->smp); |
1dd0a0b1 AT |
944 | if (IS_ERR(mdp5_kms->smp)) { |
945 | ret = PTR_ERR(mdp5_kms->smp); | |
946 | mdp5_kms->smp = NULL; | |
947 | goto fail; | |
948 | } | |
949 | } | |
950 | ||
951 | mdp5_kms->ctlm = mdp5_ctlm_init(dev, mdp5_kms->mmio, mdp5_kms->cfg); | |
952 | if (IS_ERR(mdp5_kms->ctlm)) { | |
953 | ret = PTR_ERR(mdp5_kms->ctlm); | |
954 | mdp5_kms->ctlm = NULL; | |
955 | goto fail; | |
956 | } | |
957 | ||
c056b55d RC |
958 | ret = hwpipe_init(mdp5_kms); |
959 | if (ret) | |
960 | goto fail; | |
961 | ||
6803c606 AT |
962 | ret = hwmixer_init(mdp5_kms); |
963 | if (ret) | |
964 | goto fail; | |
965 | ||
36d1364a AT |
966 | ret = interface_init(mdp5_kms); |
967 | if (ret) | |
968 | goto fail; | |
969 | ||
1dd0a0b1 AT |
970 | /* set uninit-ed kms */ |
971 | priv->kms = &mdp5_kms->base.base; | |
972 | ||
973 | return 0; | |
974 | fail: | |
975 | mdp5_destroy(pdev); | |
976 | return ret; | |
977 | } | |
978 | ||
979 | static int mdp5_bind(struct device *dev, struct device *master, void *data) | |
980 | { | |
981 | struct drm_device *ddev = dev_get_drvdata(master); | |
982 | struct platform_device *pdev = to_platform_device(dev); | |
983 | ||
984 | DBG(""); | |
985 | ||
986 | return mdp5_init(pdev, ddev); | |
987 | } | |
988 | ||
989 | static void mdp5_unbind(struct device *dev, struct device *master, | |
990 | void *data) | |
991 | { | |
992 | struct platform_device *pdev = to_platform_device(dev); | |
993 | ||
994 | mdp5_destroy(pdev); | |
995 | } | |
996 | ||
997 | static const struct component_ops mdp5_ops = { | |
998 | .bind = mdp5_bind, | |
999 | .unbind = mdp5_unbind, | |
1000 | }; | |
1001 | ||
1002 | static int mdp5_dev_probe(struct platform_device *pdev) | |
1003 | { | |
1004 | DBG(""); | |
1005 | return component_add(&pdev->dev, &mdp5_ops); | |
1006 | } | |
1007 | ||
1008 | static int mdp5_dev_remove(struct platform_device *pdev) | |
1009 | { | |
1010 | DBG(""); | |
1011 | component_del(&pdev->dev, &mdp5_ops); | |
1012 | return 0; | |
1013 | } | |
1014 | ||
96a611b5 AT |
1015 | static const struct of_device_id mdp5_dt_match[] = { |
1016 | { .compatible = "qcom,mdp5", }, | |
1017 | /* to support downstream DT files */ | |
1018 | { .compatible = "qcom,mdss_mdp", }, | |
1019 | {} | |
1020 | }; | |
1021 | MODULE_DEVICE_TABLE(of, mdp5_dt_match); | |
1022 | ||
1dd0a0b1 AT |
1023 | static struct platform_driver mdp5_driver = { |
1024 | .probe = mdp5_dev_probe, | |
1025 | .remove = mdp5_dev_remove, | |
1026 | .driver = { | |
1027 | .name = "msm_mdp", | |
96a611b5 | 1028 | .of_match_table = mdp5_dt_match, |
1dd0a0b1 AT |
1029 | }, |
1030 | }; | |
1031 | ||
1032 | void __init msm_mdp_register(void) | |
1033 | { | |
1034 | DBG(""); | |
1035 | platform_driver_register(&mdp5_driver); | |
1036 | } | |
1037 | ||
1038 | void __exit msm_mdp_unregister(void) | |
1039 | { | |
1040 | DBG(""); | |
1041 | platform_driver_unregister(&mdp5_driver); | |
1042 | } |