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Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
[linux-2.6-block.git] / drivers / gpu / drm / msm / mdp / mdp4 / mdp4_crtc.c
CommitLineData
c8afe684
RC		 1/*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#include "mdp4_kms.h"
19
20#include <drm/drm_mode.h>
21#include "drm_crtc.h"
22#include "drm_crtc_helper.h"
23#include "drm_flip_work.h"
24
25struct mdp4_crtc {
26 struct drm_crtc base;
27 char name[8];
c8afe684
RC		 28 int id;
29 int ovlp;
30 enum mdp4_dma dma;
31 bool enabled;
32
33 /* which mixer/encoder we route output to: */
34 int mixer;
35
36 struct {
37 spinlock_t lock;
38 bool stale;
39 uint32_t width, height;
aa1b0e59 40 uint32_t x, y;
c8afe684
RC		 41
42 /* next cursor to scan-out: */
43 uint32_t next_iova;
44 struct drm_gem_object *next_bo;
45
46 /* current cursor being scanned out: */
47 struct drm_gem_object *scanout_bo;
48 } cursor;
49
50
51 /* if there is a pending flip, these will be non-null: */
52 struct drm_pending_vblank_event *event;
c8afe684 53
0a5c9aad
HL		 54 /* Bits have been flushed at the last commit,
55 * used to decide if a vsync has happened since last commit.
56 */
57 u32 flushed_mask;
58
2a2b8fa6
RC		 59#define PENDING_CURSOR 0x1
60#define PENDING_FLIP 0x2
61 atomic_t pending;
62
c8afe684
RC		 63 /* for unref'ing cursor bo's after scanout completes: */
64 struct drm_flip_work unref_cursor_work;
65
9e0efa63
RC		 66 struct mdp_irq vblank;
67 struct mdp_irq err;
c8afe684
RC		 68};
69#define to_mdp4_crtc(x) container_of(x, struct mdp4_crtc, base)
70
71static struct mdp4_kms *get_kms(struct drm_crtc *crtc)
72{
73 struct msm_drm_private *priv = crtc->dev->dev_private;
9e0efa63 74 return to_mdp4_kms(to_mdp_kms(priv->kms));
c8afe684
RC		 75}
76
b69720c0 77static void request_pending(struct drm_crtc *crtc, uint32_t pending)
c8afe684
RC		 78{
79 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
c8afe684 80
b69720c0
RC		 81 atomic_or(pending, &mdp4_crtc->pending);
82 mdp_irq_register(&get_kms(crtc)->base, &mdp4_crtc->vblank);
83}
84
85static void crtc_flush(struct drm_crtc *crtc)
86{
87 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
88 struct mdp4_kms *mdp4_kms = get_kms(crtc);
bb6c018d
RC		 89 struct drm_plane *plane;
90 uint32_t flush = 0;
b69720c0 91
93b02beb 92 drm_atomic_crtc_for_each_plane(plane, crtc) {
bb6c018d
RC		 93 enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
94 flush |= pipe2flush(pipe_id);
b69720c0 95 }
bb6c018d 96
b69720c0
RC		 97 flush |= ovlp2flush(mdp4_crtc->ovlp);
98
99 DBG("%s: flush=%08x", mdp4_crtc->name, flush);
100
0a5c9aad
HL		 101 mdp4_crtc->flushed_mask = flush;
102
b69720c0
RC		 103 mdp4_write(mdp4_kms, REG_MDP4_OVERLAY_FLUSH, flush);
104}
105
2a2b8fa6
RC		 106/* if file!=NULL, this is preclose potential cancel-flip path */
107static void complete_flip(struct drm_crtc *crtc, struct drm_file *file)
c8afe684
RC		 108{
109 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
110 struct drm_device *dev = crtc->dev;
111 struct drm_pending_vblank_event *event;
112 unsigned long flags;
113
114 spin_lock_irqsave(&dev->event_lock, flags);
115 event = mdp4_crtc->event;
116 if (event) {
2a2b8fa6
RC		 117 /* if regular vblank case (!file) or if cancel-flip from
118 * preclose on file that requested flip, then send the
119 * event:
120 */
121 if (!file || (event->base.file_priv == file)) {
122 mdp4_crtc->event = NULL;
e27c54ff 123 DBG("%s: send event: %p", mdp4_crtc->name, event);
c8afe684 124 drm_send_vblank_event(dev, mdp4_crtc->id, event);
2a2b8fa6 125 }
c8afe684
RC		 126 }
127 spin_unlock_irqrestore(&dev->event_lock, flags);
128}
129
c8afe684
RC		 130static void unref_cursor_worker(struct drm_flip_work *work, void *val)
131{
132 struct mdp4_crtc *mdp4_crtc =
133 container_of(work, struct mdp4_crtc, unref_cursor_work);
134 struct mdp4_kms *mdp4_kms = get_kms(&mdp4_crtc->base);
135
136 msm_gem_put_iova(val, mdp4_kms->id);
137 drm_gem_object_unreference_unlocked(val);
138}
139
140static void mdp4_crtc_destroy(struct drm_crtc *crtc)
141{
142 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
c8afe684
RC		 143
144 drm_crtc_cleanup(crtc);
c8afe684
RC		 145 drm_flip_work_cleanup(&mdp4_crtc->unref_cursor_work);
146
147 kfree(mdp4_crtc);
148}
149
4dd14fe6
RC		 150/* statically (for now) map planes to mixer stage (z-order): */
151static const int idxs[] = {
152 [VG1] = 1,
153 [VG2] = 2,
154 [RGB1] = 0,
155 [RGB2] = 0,
156 [RGB3] = 0,
157 [VG3] = 3,
158 [VG4] = 4,
159
160};
161
162/* setup mixer config, for which we need to consider all crtc's and
163 * the planes attached to them
164 *
165 * TODO may possibly need some extra locking here
166 */
167static void setup_mixer(struct mdp4_kms *mdp4_kms)
c8afe684 168{
4dd14fe6
RC		 169 struct drm_mode_config *config = &mdp4_kms->dev->mode_config;
170 struct drm_crtc *crtc;
c8afe684 171 uint32_t mixer_cfg = 0;
facb4f4e 172 static const enum mdp_mixer_stage_id stages[] = {
a8623918
RC		 173 STAGE_BASE, STAGE0, STAGE1, STAGE2, STAGE3,
174 };
a8623918 175
4dd14fe6
RC		 176 list_for_each_entry(crtc, &config->crtc_list, head) {
177 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
178 struct drm_plane *plane;
c8afe684 179
93b02beb 180 drm_atomic_crtc_for_each_plane(plane, crtc) {
4dd14fe6
RC		 181 enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
182 int idx = idxs[pipe_id];
183 mixer_cfg = mixercfg(mixer_cfg, mdp4_crtc->mixer,
184 pipe_id, stages[idx]);
185 }
186 }
187
188 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, mixer_cfg);
189}
190
191static void blend_setup(struct drm_crtc *crtc)
192{
193 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
194 struct mdp4_kms *mdp4_kms = get_kms(crtc);
195 struct drm_plane *plane;
196 int i, ovlp = mdp4_crtc->ovlp;
197 bool alpha[4]= { false, false, false, false };
d65bd0e4 198
c8afe684
RC		 199 mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW0(ovlp), 0);
200 mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW1(ovlp), 0);
201 mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH0(ovlp), 0);
202 mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH1(ovlp), 0);
203
93b02beb 204 drm_atomic_crtc_for_each_plane(plane, crtc) {
bb6c018d
RC		 205 enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
206 int idx = idxs[pipe_id];
207 if (idx > 0) {
208 const struct mdp_format *format =
10a02eb6 209 to_mdp_format(msm_framebuffer_format(plane->fb));
bb6c018d 210 alpha[idx-1] = format->alpha_enable;
a8623918
RC		 211 }
212 }
213
c8afe684 214 for (i = 0; i < 4; i++) {
a8623918
RC		 215 uint32_t op;
216
217 if (alpha[i]) {
218 op = MDP4_OVLP_STAGE_OP_FG_ALPHA(FG_PIXEL) |
219 MDP4_OVLP_STAGE_OP_BG_ALPHA(FG_PIXEL) |
220 MDP4_OVLP_STAGE_OP_BG_INV_ALPHA;
221 } else {
222 op = MDP4_OVLP_STAGE_OP_FG_ALPHA(FG_CONST) |
223 MDP4_OVLP_STAGE_OP_BG_ALPHA(BG_CONST);
224 }
225
226 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_FG_ALPHA(ovlp, i), 0xff);
227 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_BG_ALPHA(ovlp, i), 0x00);
228 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_OP(ovlp, i), op);
229 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_CO3(ovlp, i), 1);
c8afe684
RC		 230 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW0(ovlp, i), 0);
231 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW1(ovlp, i), 0);
232 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(ovlp, i), 0);
233 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(ovlp, i), 0);
234 }
235
4dd14fe6 236 setup_mixer(mdp4_kms);
c8afe684
RC		 237}
238
e27c54ff 239static void mdp4_crtc_mode_set_nofb(struct drm_crtc *crtc)
c8afe684
RC		 240{
241 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
242 struct mdp4_kms *mdp4_kms = get_kms(crtc);
243 enum mdp4_dma dma = mdp4_crtc->dma;
e27c54ff
RC		 244 int ovlp = mdp4_crtc->ovlp;
245 struct drm_display_mode *mode;
246
247 if (WARN_ON(!crtc->state))
248 return;
c8afe684 249
e27c54ff 250 mode = &crtc->state->adjusted_mode;
c8afe684
RC		 251
252 DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
253 mdp4_crtc->name, mode->base.id, mode->name,
254 mode->vrefresh, mode->clock,
255 mode->hdisplay, mode->hsync_start,
256 mode->hsync_end, mode->htotal,
257 mode->vdisplay, mode->vsync_start,
258 mode->vsync_end, mode->vtotal,
259 mode->type, mode->flags);
260
261 mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_SIZE(dma),
262 MDP4_DMA_SRC_SIZE_WIDTH(mode->hdisplay) |
263 MDP4_DMA_SRC_SIZE_HEIGHT(mode->vdisplay));
264
265 /* take data from pipe: */
266 mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_BASE(dma), 0);
88ff1c2f 267 mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_STRIDE(dma), 0);
c8afe684
RC		 268 mdp4_write(mdp4_kms, REG_MDP4_DMA_DST_SIZE(dma),
269 MDP4_DMA_DST_SIZE_WIDTH(0) |
270 MDP4_DMA_DST_SIZE_HEIGHT(0));
271
272 mdp4_write(mdp4_kms, REG_MDP4_OVLP_BASE(ovlp), 0);
273 mdp4_write(mdp4_kms, REG_MDP4_OVLP_SIZE(ovlp),
274 MDP4_OVLP_SIZE_WIDTH(mode->hdisplay) |
275 MDP4_OVLP_SIZE_HEIGHT(mode->vdisplay));
88ff1c2f 276 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STRIDE(ovlp), 0);
c8afe684
RC		 277
278 mdp4_write(mdp4_kms, REG_MDP4_OVLP_CFG(ovlp), 1);
279
c8afe684
RC		 280 if (dma == DMA_E) {
281 mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(0), 0x00ff0000);
282 mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(1), 0x00ff0000);
283 mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(2), 0x00ff0000);
284 }
c8afe684
RC		 285}
286
0b776d45 287static void mdp4_crtc_disable(struct drm_crtc *crtc)
c8afe684
RC		 288{
289 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
0b776d45
RC		 290 struct mdp4_kms *mdp4_kms = get_kms(crtc);
291
c8afe684 292 DBG("%s", mdp4_crtc->name);
0b776d45
RC		 293
294 if (WARN_ON(!mdp4_crtc->enabled))
295 return;
296
297 mdp_irq_unregister(&mdp4_kms->base, &mdp4_crtc->err);
298 mdp4_disable(mdp4_kms);
299
300 mdp4_crtc->enabled = false;
c8afe684
RC		 301}
302
0b776d45 303static void mdp4_crtc_enable(struct drm_crtc *crtc)
c8afe684 304{
0b776d45
RC		 305 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
306 struct mdp4_kms *mdp4_kms = get_kms(crtc);
307
308 DBG("%s", mdp4_crtc->name);
309
310 if (WARN_ON(mdp4_crtc->enabled))
311 return;
312
313 mdp4_enable(mdp4_kms);
314 mdp_irq_register(&mdp4_kms->base, &mdp4_crtc->err);
315
c8afe684 316 crtc_flush(crtc);
0b776d45
RC		 317
318 mdp4_crtc->enabled = true;
c8afe684
RC		 319}
320
e27c54ff
RC		 321static int mdp4_crtc_atomic_check(struct drm_crtc *crtc,
322 struct drm_crtc_state *state)
c8afe684 323{
e27c54ff 324 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
e27c54ff 325 DBG("%s: check", mdp4_crtc->name);
e27c54ff 326 // TODO anything else to check?
b69720c0 327 return 0;
c8afe684
RC		 328}
329
613d2b27
ML		 330static void mdp4_crtc_atomic_begin(struct drm_crtc *crtc,
331 struct drm_crtc_state *old_crtc_state)
c8afe684 332{
e27c54ff
RC		 333 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
334 DBG("%s: begin", mdp4_crtc->name);
c8afe684
RC		 335}
336
613d2b27
ML		 337static void mdp4_crtc_atomic_flush(struct drm_crtc *crtc,
338 struct drm_crtc_state *old_crtc_state)
c8afe684
RC		 339{
340 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
341 struct drm_device *dev = crtc->dev;
2a2b8fa6 342 unsigned long flags;
c8afe684 343
f86afecf 344 DBG("%s: event: %p", mdp4_crtc->name, crtc->state->event);
c8afe684 345
e27c54ff 346 WARN_ON(mdp4_crtc->event);
c8afe684 347
2a2b8fa6 348 spin_lock_irqsave(&dev->event_lock, flags);
e27c54ff 349 mdp4_crtc->event = crtc->state->event;
2a2b8fa6
RC		 350 spin_unlock_irqrestore(&dev->event_lock, flags);
351
e27c54ff
RC		 352 blend_setup(crtc);
353 crtc_flush(crtc);
354 request_pending(crtc, PENDING_FLIP);
c8afe684
RC		 355}
356
c8afe684
RC		 357#define CURSOR_WIDTH 64
358#define CURSOR_HEIGHT 64
359
360/* called from IRQ to update cursor related registers (if needed). The
361 * cursor registers, other than x/y position, appear not to be double
362 * buffered, and changing them other than from vblank seems to trigger
363 * underflow.
364 */
365static void update_cursor(struct drm_crtc *crtc)
366{
367 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
aa1b0e59 368 struct mdp4_kms *mdp4_kms = get_kms(crtc);
c8afe684
RC		 369 enum mdp4_dma dma = mdp4_crtc->dma;
370 unsigned long flags;
371
372 spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags);
373 if (mdp4_crtc->cursor.stale) {
c8afe684
RC		 374 struct drm_gem_object *next_bo = mdp4_crtc->cursor.next_bo;
375 struct drm_gem_object *prev_bo = mdp4_crtc->cursor.scanout_bo;
376 uint32_t iova = mdp4_crtc->cursor.next_iova;
377
378 if (next_bo) {
379 /* take a obj ref + iova ref when we start scanning out: */
380 drm_gem_object_reference(next_bo);
381 msm_gem_get_iova_locked(next_bo, mdp4_kms->id, &iova);
382
383 /* enable cursor: */
384 mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_SIZE(dma),
385 MDP4_DMA_CURSOR_SIZE_WIDTH(mdp4_crtc->cursor.width) |
386 MDP4_DMA_CURSOR_SIZE_HEIGHT(mdp4_crtc->cursor.height));
387 mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma), iova);
388 mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BLEND_CONFIG(dma),
389 MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(CURSOR_ARGB) |
390 MDP4_DMA_CURSOR_BLEND_CONFIG_CURSOR_EN);
391 } else {
392 /* disable cursor: */
7d8d9f67
RC		 393 mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma),
394 mdp4_kms->blank_cursor_iova);
c8afe684
RC		 395 }
396
397 /* and drop the iova ref + obj rev when done scanning out: */
398 if (prev_bo)
399 drm_flip_work_queue(&mdp4_crtc->unref_cursor_work, prev_bo);
400
401 mdp4_crtc->cursor.scanout_bo = next_bo;
402 mdp4_crtc->cursor.stale = false;
403 }
aa1b0e59
RC		 404
405 mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_POS(dma),
406 MDP4_DMA_CURSOR_POS_X(mdp4_crtc->cursor.x) |
407 MDP4_DMA_CURSOR_POS_Y(mdp4_crtc->cursor.y));
408
c8afe684
RC		 409 spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags);
410}
411
412static int mdp4_crtc_cursor_set(struct drm_crtc *crtc,
413 struct drm_file *file_priv, uint32_t handle,
414 uint32_t width, uint32_t height)
415{
416 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
417 struct mdp4_kms *mdp4_kms = get_kms(crtc);
418 struct drm_device *dev = crtc->dev;
419 struct drm_gem_object *cursor_bo, *old_bo;
420 unsigned long flags;
421 uint32_t iova;
422 int ret;
423
424 if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) {
425 dev_err(dev->dev, "bad cursor size: %dx%d\n", width, height);
426 return -EINVAL;
427 }
428
429 if (handle) {
430 cursor_bo = drm_gem_object_lookup(dev, file_priv, handle);
431 if (!cursor_bo)
432 return -ENOENT;
433 } else {
434 cursor_bo = NULL;
435 }
436
437 if (cursor_bo) {
438 ret = msm_gem_get_iova(cursor_bo, mdp4_kms->id, &iova);
439 if (ret)
440 goto fail;
441 } else {
442 iova = 0;
443 }
444
445 spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags);
446 old_bo = mdp4_crtc->cursor.next_bo;
447 mdp4_crtc->cursor.next_bo = cursor_bo;
448 mdp4_crtc->cursor.next_iova = iova;
449 mdp4_crtc->cursor.width = width;
450 mdp4_crtc->cursor.height = height;
451 mdp4_crtc->cursor.stale = true;
452 spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags);
453
454 if (old_bo) {
455 /* drop our previous reference: */
7d8d9f67 456 drm_flip_work_queue(&mdp4_crtc->unref_cursor_work, old_bo);
c8afe684
RC		 457 }
458
2a2b8fa6
RC		 459 request_pending(crtc, PENDING_CURSOR);
460
c8afe684
RC		 461 return 0;
462
463fail:
464 drm_gem_object_unreference_unlocked(cursor_bo);
465 return ret;
466}
467
468static int mdp4_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
469{
470 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
aa1b0e59 471 unsigned long flags;
c8afe684 472
aa1b0e59
RC		 473 spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags);
474 mdp4_crtc->cursor.x = x;
475 mdp4_crtc->cursor.y = y;
476 spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags);
477
478 crtc_flush(crtc);
479 request_pending(crtc, PENDING_CURSOR);
c8afe684
RC		 480
481 return 0;
482}
483
484static const struct drm_crtc_funcs mdp4_crtc_funcs = {
e27c54ff 485 .set_config = drm_atomic_helper_set_config,
c8afe684 486 .destroy = mdp4_crtc_destroy,
e27c54ff 487 .page_flip = drm_atomic_helper_page_flip,
4103eef9 488 .set_property = drm_atomic_helper_crtc_set_property,
c8afe684
RC		 489 .cursor_set = mdp4_crtc_cursor_set,
490 .cursor_move = mdp4_crtc_cursor_move,
e27c54ff
RC		 491 .reset = drm_atomic_helper_crtc_reset,
492 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
493 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
c8afe684
RC		 494};
495
496static const struct drm_crtc_helper_funcs mdp4_crtc_helper_funcs = {
e27c54ff 497 .mode_set_nofb = mdp4_crtc_mode_set_nofb,
0b776d45
RC		 498 .disable = mdp4_crtc_disable,
499 .enable = mdp4_crtc_enable,
e27c54ff
RC		 500 .atomic_check = mdp4_crtc_atomic_check,
501 .atomic_begin = mdp4_crtc_atomic_begin,
502 .atomic_flush = mdp4_crtc_atomic_flush,
c8afe684
RC		 503};
504
9e0efa63 505static void mdp4_crtc_vblank_irq(struct mdp_irq *irq, uint32_t irqstatus)
c8afe684
RC		 506{
507 struct mdp4_crtc *mdp4_crtc = container_of(irq, struct mdp4_crtc, vblank);
508 struct drm_crtc *crtc = &mdp4_crtc->base;
509 struct msm_drm_private *priv = crtc->dev->dev_private;
2a2b8fa6 510 unsigned pending;
c8afe684 511
9e0efa63 512 mdp_irq_unregister(&get_kms(crtc)->base, &mdp4_crtc->vblank);
c8afe684 513
2a2b8fa6
RC		 514 pending = atomic_xchg(&mdp4_crtc->pending, 0);
515
516 if (pending & PENDING_FLIP) {
517 complete_flip(crtc, NULL);
2a2b8fa6
RC		 518 }
519
520 if (pending & PENDING_CURSOR) {
521 update_cursor(crtc);
522 drm_flip_work_commit(&mdp4_crtc->unref_cursor_work, priv->wq);
523 }
c8afe684
RC		 524}
525
9e0efa63 526static void mdp4_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus)
c8afe684
RC		 527{
528 struct mdp4_crtc *mdp4_crtc = container_of(irq, struct mdp4_crtc, err);
529 struct drm_crtc *crtc = &mdp4_crtc->base;
530 DBG("%s: error: %08x", mdp4_crtc->name, irqstatus);
531 crtc_flush(crtc);
532}
533
0a5c9aad
HL		 534static void mdp4_crtc_wait_for_flush_done(struct drm_crtc *crtc)
535{
536 struct drm_device *dev = crtc->dev;
537 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
538 struct mdp4_kms *mdp4_kms = get_kms(crtc);
539 int ret;
540
541 ret = drm_crtc_vblank_get(crtc);
542 if (ret)
543 return;
544
545 ret = wait_event_timeout(dev->vblank[drm_crtc_index(crtc)].queue,
546 !(mdp4_read(mdp4_kms, REG_MDP4_OVERLAY_FLUSH) &
547 mdp4_crtc->flushed_mask),
548 msecs_to_jiffies(50));
549 if (ret <= 0)
550 dev_warn(dev->dev, "vblank time out, crtc=%d\n", mdp4_crtc->id);
551
552 mdp4_crtc->flushed_mask = 0;
553
554 drm_crtc_vblank_put(crtc);
555}
556
c8afe684
RC		 557uint32_t mdp4_crtc_vblank(struct drm_crtc *crtc)
558{
559 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
560 return mdp4_crtc->vblank.irqmask;
561}
562
c8afe684
RC		 563/* set dma config, ie. the format the encoder wants. */
564void mdp4_crtc_set_config(struct drm_crtc *crtc, uint32_t config)
565{
566 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
567 struct mdp4_kms *mdp4_kms = get_kms(crtc);
568
569 mdp4_write(mdp4_kms, REG_MDP4_DMA_CONFIG(mdp4_crtc->dma), config);
570}
571
572/* set interface for routing crtc->encoder: */
d65bd0e4 573void mdp4_crtc_set_intf(struct drm_crtc *crtc, enum mdp4_intf intf, int mixer)
c8afe684
RC		 574{
575 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
576 struct mdp4_kms *mdp4_kms = get_kms(crtc);
577 uint32_t intf_sel;
578
579 intf_sel = mdp4_read(mdp4_kms, REG_MDP4_DISP_INTF_SEL);
580
581 switch (mdp4_crtc->dma) {
582 case DMA_P:
583 intf_sel &= ~MDP4_DISP_INTF_SEL_PRIM__MASK;
584 intf_sel |= MDP4_DISP_INTF_SEL_PRIM(intf);
585 break;
586 case DMA_S:
587 intf_sel &= ~MDP4_DISP_INTF_SEL_SEC__MASK;
588 intf_sel |= MDP4_DISP_INTF_SEL_SEC(intf);
589 break;
590 case DMA_E:
591 intf_sel &= ~MDP4_DISP_INTF_SEL_EXT__MASK;
592 intf_sel |= MDP4_DISP_INTF_SEL_EXT(intf);
593 break;
594 }
595
596 if (intf == INTF_DSI_VIDEO) {
597 intf_sel &= ~MDP4_DISP_INTF_SEL_DSI_CMD;
598 intf_sel |= MDP4_DISP_INTF_SEL_DSI_VIDEO;
c8afe684
RC		 599 } else if (intf == INTF_DSI_CMD) {
600 intf_sel &= ~MDP4_DISP_INTF_SEL_DSI_VIDEO;
601 intf_sel |= MDP4_DISP_INTF_SEL_DSI_CMD;
c8afe684
RC		 602 }
603
d65bd0e4
RC		 604 mdp4_crtc->mixer = mixer;
605
c8afe684
RC		 606 blend_setup(crtc);
607
608 DBG("%s: intf_sel=%08x", mdp4_crtc->name, intf_sel);
609
610 mdp4_write(mdp4_kms, REG_MDP4_DISP_INTF_SEL, intf_sel);
611}
612
0a5c9aad
HL		 613void mdp4_crtc_wait_for_commit_done(struct drm_crtc *crtc)
614{
615 /* wait_for_flush_done is the only case for now.
616 * Later we will have command mode CRTC to wait for
617 * other event.
618 */
619 mdp4_crtc_wait_for_flush_done(crtc);
620}
621
c8afe684
RC		 622static const char *dma_names[] = {
623 "DMA_P", "DMA_S", "DMA_E",
624};
625
626/* initialize crtc */
627struct drm_crtc *mdp4_crtc_init(struct drm_device *dev,
628 struct drm_plane *plane, int id, int ovlp_id,
629 enum mdp4_dma dma_id)
630{
631 struct drm_crtc *crtc = NULL;
632 struct mdp4_crtc *mdp4_crtc;
c8afe684
RC		 633
634 mdp4_crtc = kzalloc(sizeof(*mdp4_crtc), GFP_KERNEL);
d7f8db53
BB		 635 if (!mdp4_crtc)
636 return ERR_PTR(-ENOMEM);
c8afe684
RC		 637
638 crtc = &mdp4_crtc->base;
639
b69720c0 640 mdp4_crtc->id = id;
c8afe684
RC		 641
642 mdp4_crtc->ovlp = ovlp_id;
643 mdp4_crtc->dma = dma_id;
644
645 mdp4_crtc->vblank.irqmask = dma2irq(mdp4_crtc->dma);
646 mdp4_crtc->vblank.irq = mdp4_crtc_vblank_irq;
647
648 mdp4_crtc->err.irqmask = dma2err(mdp4_crtc->dma);
649 mdp4_crtc->err.irq = mdp4_crtc_err_irq;
650
651 snprintf(mdp4_crtc->name, sizeof(mdp4_crtc->name), "%s:%d",
652 dma_names[dma_id], ovlp_id);
653
654 spin_lock_init(&mdp4_crtc->cursor.lock);
655
d7f8db53 656 drm_flip_work_init(&mdp4_crtc->unref_cursor_work,
c8afe684
RC		 657 "unref cursor", unref_cursor_worker);
658
f9882876
VS		 659 drm_crtc_init_with_planes(dev, crtc, plane, NULL, &mdp4_crtc_funcs,
660 NULL);
c8afe684 661 drm_crtc_helper_add(crtc, &mdp4_crtc_helper_funcs);
bb6c018d 662 plane->crtc = crtc;
c8afe684 663
c8afe684 664 return crtc;
c8afe684 665}
Linux 6.x block layer and io_uring tree(s)