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c8afe684 RC |
1 | /* |
2 | * Copyright (C) 2013 Red Hat | |
3 | * Author: Rob Clark <robdclark@gmail.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | #ifndef __HDMI_CONNECTOR_H__ | |
19 | #define __HDMI_CONNECTOR_H__ | |
20 | ||
21 | #include <linux/i2c.h> | |
22 | #include <linux/clk.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/regulator/consumer.h> | |
c0c0d9ee | 25 | #include <linux/hdmi.h> |
c8afe684 RC |
26 | |
27 | #include "msm_drv.h" | |
28 | #include "hdmi.xml.h" | |
29 | ||
dc50f782 | 30 | #define HDMI_MAX_NUM_GPIO 6 |
c8afe684 RC |
31 | |
32 | struct hdmi_phy; | |
dada25bd | 33 | struct hdmi_platform_config; |
c8afe684 | 34 | |
dc50f782 AT |
35 | struct hdmi_gpio_data { |
36 | int num; | |
37 | bool output; | |
38 | int value; | |
39 | const char *label; | |
40 | }; | |
41 | ||
c0c0d9ee RC |
42 | struct hdmi_audio { |
43 | bool enabled; | |
44 | struct hdmi_audio_infoframe infoframe; | |
45 | int rate; | |
46 | }; | |
47 | ||
c6a57a50 | 48 | struct hdmi_hdcp_ctrl; |
49 | ||
c8afe684 RC |
50 | struct hdmi { |
51 | struct drm_device *dev; | |
52 | struct platform_device *pdev; | |
53 | ||
dada25bd | 54 | const struct hdmi_platform_config *config; |
c8afe684 | 55 | |
c0c0d9ee RC |
56 | /* audio state: */ |
57 | struct hdmi_audio audio; | |
58 | ||
59 | /* video state: */ | |
60 | bool power_on; | |
61 | unsigned long int pixclock; | |
62 | ||
dada25bd | 63 | void __iomem *mmio; |
c6a57a50 | 64 | void __iomem *qfprom_mmio; |
65 | phys_addr_t mmio_phy_addr; | |
c8afe684 | 66 | |
447fa529 SV |
67 | struct regulator **hpd_regs; |
68 | struct regulator **pwr_regs; | |
69 | struct clk **hpd_clks; | |
70 | struct clk **pwr_clks; | |
c8afe684 RC |
71 | |
72 | struct hdmi_phy *phy; | |
e00012b2 AT |
73 | struct device *phy_dev; |
74 | ||
c8afe684 RC |
75 | struct i2c_adapter *i2c; |
76 | struct drm_connector *connector; | |
a3376e3e RC |
77 | struct drm_bridge *bridge; |
78 | ||
79 | /* the encoder we are hooked to (outside of hdmi block) */ | |
80 | struct drm_encoder *encoder; | |
c8afe684 RC |
81 | |
82 | bool hdmi_mode; /* are we in hdmi mode? */ | |
83 | ||
84 | int irq; | |
c6a57a50 | 85 | struct workqueue_struct *workq; |
86 | ||
87 | struct hdmi_hdcp_ctrl *hdcp_ctrl; | |
88 | ||
89 | /* | |
90 | * spinlock to protect registers shared by different execution | |
91 | * REG_HDMI_CTRL | |
92 | * REG_HDMI_DDC_ARBITRATION | |
93 | * REG_HDMI_HDCP_INT_CTRL | |
94 | * REG_HDMI_HPD_CTRL | |
95 | */ | |
96 | spinlock_t reg_lock; | |
c8afe684 RC |
97 | }; |
98 | ||
99 | /* platform config data (ie. from DT, or pdata) */ | |
100 | struct hdmi_platform_config { | |
dada25bd | 101 | const char *mmio_name; |
c6a57a50 | 102 | const char *qfprom_mmio_name; |
dada25bd RC |
103 | |
104 | /* regulators that need to be on for hpd: */ | |
105 | const char **hpd_reg_names; | |
106 | int hpd_reg_cnt; | |
107 | ||
108 | /* regulators that need to be on for screen pwr: */ | |
109 | const char **pwr_reg_names; | |
110 | int pwr_reg_cnt; | |
111 | ||
112 | /* clks that need to be on for hpd: */ | |
113 | const char **hpd_clk_names; | |
b77f47e7 | 114 | const long unsigned *hpd_freq; |
dada25bd RC |
115 | int hpd_clk_cnt; |
116 | ||
117 | /* clks that need to be on for screen pwr (ie pixel clk): */ | |
118 | const char **pwr_clk_names; | |
119 | int pwr_clk_cnt; | |
120 | ||
121 | /* gpio's: */ | |
dc50f782 | 122 | struct hdmi_gpio_data gpios[HDMI_MAX_NUM_GPIO]; |
c8afe684 RC |
123 | }; |
124 | ||
fcda50c8 | 125 | void msm_hdmi_set_mode(struct hdmi *hdmi, bool power_on); |
c8afe684 RC |
126 | |
127 | static inline void hdmi_write(struct hdmi *hdmi, u32 reg, u32 data) | |
128 | { | |
129 | msm_writel(data, hdmi->mmio + reg); | |
130 | } | |
131 | ||
132 | static inline u32 hdmi_read(struct hdmi *hdmi, u32 reg) | |
133 | { | |
134 | return msm_readl(hdmi->mmio + reg); | |
135 | } | |
136 | ||
c6a57a50 | 137 | static inline u32 hdmi_qfprom_read(struct hdmi *hdmi, u32 reg) |
138 | { | |
139 | return msm_readl(hdmi->qfprom_mmio + reg); | |
140 | } | |
141 | ||
c8afe684 | 142 | /* |
15b4a452 | 143 | * hdmi phy: |
c8afe684 | 144 | */ |
c8afe684 | 145 | |
15b4a452 AT |
146 | enum hdmi_phy_type { |
147 | MSM_HDMI_PHY_8x60, | |
148 | MSM_HDMI_PHY_8960, | |
149 | MSM_HDMI_PHY_8x74, | |
e17afdce | 150 | MSM_HDMI_PHY_8996, |
15b4a452 AT |
151 | MSM_HDMI_PHY_MAX, |
152 | }; | |
153 | ||
154 | struct hdmi_phy_cfg { | |
155 | enum hdmi_phy_type type; | |
156 | void (*powerup)(struct hdmi_phy *phy, unsigned long int pixclock); | |
157 | void (*powerdown)(struct hdmi_phy *phy); | |
158 | const char * const *reg_names; | |
159 | int num_regs; | |
160 | const char * const *clk_names; | |
161 | int num_clks; | |
162 | }; | |
163 | ||
fcda50c8 AB |
164 | extern const struct hdmi_phy_cfg msm_hdmi_phy_8x60_cfg; |
165 | extern const struct hdmi_phy_cfg msm_hdmi_phy_8960_cfg; | |
166 | extern const struct hdmi_phy_cfg msm_hdmi_phy_8x74_cfg; | |
167 | extern const struct hdmi_phy_cfg msm_hdmi_phy_8996_cfg; | |
15b4a452 | 168 | |
c8afe684 | 169 | struct hdmi_phy { |
15b4a452 AT |
170 | struct platform_device *pdev; |
171 | void __iomem *mmio; | |
172 | struct hdmi_phy_cfg *cfg; | |
c8afe684 | 173 | const struct hdmi_phy_funcs *funcs; |
15b4a452 AT |
174 | struct regulator **regs; |
175 | struct clk **clks; | |
c8afe684 RC |
176 | }; |
177 | ||
15b4a452 AT |
178 | static inline void hdmi_phy_write(struct hdmi_phy *phy, u32 reg, u32 data) |
179 | { | |
180 | msm_writel(data, phy->mmio + reg); | |
181 | } | |
182 | ||
183 | static inline u32 hdmi_phy_read(struct hdmi_phy *phy, u32 reg) | |
184 | { | |
185 | return msm_readl(phy->mmio + reg); | |
186 | } | |
187 | ||
fcda50c8 AB |
188 | int msm_hdmi_phy_resource_enable(struct hdmi_phy *phy); |
189 | void msm_hdmi_phy_resource_disable(struct hdmi_phy *phy); | |
190 | void msm_hdmi_phy_powerup(struct hdmi_phy *phy, unsigned long int pixclock); | |
191 | void msm_hdmi_phy_powerdown(struct hdmi_phy *phy); | |
192 | void __init msm_hdmi_phy_driver_register(void); | |
193 | void __exit msm_hdmi_phy_driver_unregister(void); | |
15b4a452 | 194 | |
ea184891 | 195 | #ifdef CONFIG_COMMON_CLK |
fcda50c8 AB |
196 | int msm_hdmi_pll_8960_init(struct platform_device *pdev); |
197 | int msm_hdmi_pll_8996_init(struct platform_device *pdev); | |
ea184891 | 198 | #else |
0a69509f | 199 | static inline int msm_hdmi_pll_8960_init(struct platform_device *pdev) |
ea184891 AT |
200 | { |
201 | return -ENODEV; | |
202 | } | |
e17afdce | 203 | |
fcda50c8 | 204 | static inline int msm_hdmi_pll_8996_init(struct platform_device *pdev) |
e17afdce AT |
205 | { |
206 | return -ENODEV; | |
207 | } | |
ea184891 AT |
208 | #endif |
209 | ||
c0c0d9ee RC |
210 | /* |
211 | * audio: | |
212 | */ | |
213 | ||
fcda50c8 AB |
214 | int msm_hdmi_audio_update(struct hdmi *hdmi); |
215 | int msm_hdmi_audio_info_setup(struct hdmi *hdmi, bool enabled, | |
c0c0d9ee RC |
216 | uint32_t num_of_channels, uint32_t channel_allocation, |
217 | uint32_t level_shift, bool down_mix); | |
fcda50c8 | 218 | void msm_hdmi_audio_set_sample_rate(struct hdmi *hdmi, int rate); |
c0c0d9ee RC |
219 | |
220 | ||
a3376e3e RC |
221 | /* |
222 | * hdmi bridge: | |
223 | */ | |
224 | ||
fcda50c8 AB |
225 | struct drm_bridge *msm_hdmi_bridge_init(struct hdmi *hdmi); |
226 | void msm_hdmi_bridge_destroy(struct drm_bridge *bridge); | |
a3376e3e | 227 | |
c8afe684 RC |
228 | /* |
229 | * hdmi connector: | |
230 | */ | |
231 | ||
fcda50c8 AB |
232 | void msm_hdmi_connector_irq(struct drm_connector *connector); |
233 | struct drm_connector *msm_hdmi_connector_init(struct hdmi *hdmi); | |
c8afe684 RC |
234 | |
235 | /* | |
236 | * i2c adapter for ddc: | |
237 | */ | |
238 | ||
fcda50c8 AB |
239 | void msm_hdmi_i2c_irq(struct i2c_adapter *i2c); |
240 | void msm_hdmi_i2c_destroy(struct i2c_adapter *i2c); | |
241 | struct i2c_adapter *msm_hdmi_i2c_init(struct hdmi *hdmi); | |
c8afe684 | 242 | |
c6a57a50 | 243 | /* |
244 | * hdcp | |
245 | */ | |
fcda50c8 AB |
246 | struct hdmi_hdcp_ctrl *msm_hdmi_hdcp_init(struct hdmi *hdmi); |
247 | void msm_hdmi_hdcp_destroy(struct hdmi *hdmi); | |
248 | void msm_hdmi_hdcp_on(struct hdmi_hdcp_ctrl *hdcp_ctrl); | |
249 | void msm_hdmi_hdcp_off(struct hdmi_hdcp_ctrl *hdcp_ctrl); | |
250 | void msm_hdmi_hdcp_irq(struct hdmi_hdcp_ctrl *hdcp_ctrl); | |
c6a57a50 | 251 | |
c8afe684 | 252 | #endif /* __HDMI_CONNECTOR_H__ */ |