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drm/msm/dsi: Move PHY operations out of host
[linux-2.6-block.git] / drivers / gpu / drm / msm / dsi / dsi_host.c
CommitLineData
a689554b
HL		 1/*
2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/clk.h>
15#include <linux/delay.h>
16#include <linux/err.h>
17#include <linux/gpio.h>
964a0754 18#include <linux/gpio/consumer.h>
a689554b
HL		 19#include <linux/interrupt.h>
20#include <linux/of_device.h>
21#include <linux/of_gpio.h>
22#include <linux/of_irq.h>
ab8909b0 23#include <linux/pinctrl/consumer.h>
f7009d26 24#include <linux/of_graph.h>
a689554b
HL		 25#include <linux/regulator/consumer.h>
26#include <linux/spinlock.h>
0c7df47f
AT		 27#include <linux/mfd/syscon.h>
28#include <linux/regmap.h>
a689554b
HL		 29#include <video/mipi_display.h>
30
31#include "dsi.h"
32#include "dsi.xml.h"
0c7df47f 33#include "sfpb.xml.h"
d248b61f 34#include "dsi_cfg.h"
a689554b
HL		 35
36static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor)
37{
38 u32 ver;
a689554b
HL		 39
40 if (!major || !minor)
41 return -EINVAL;
42
648d5063
AT		 43 /*
44 * From DSI6G(v3), addition of a 6G_HW_VERSION register at offset 0
a689554b 45 * makes all other registers 4-byte shifted down.
648d5063
AT		 46 *
47 * In order to identify between DSI6G(v3) and beyond, and DSIv2 and
48 * older, we read the DSI_VERSION register without any shift(offset
49 * 0x1f0). In the case of DSIv2, this hast to be a non-zero value. In
50 * the case of DSI6G, this has to be zero (the offset points to a
51 * scratch register which we never touch)
a689554b 52 */
648d5063
AT		 53
54 ver = msm_readl(base + REG_DSI_VERSION);
55 if (ver) {
56 /* older dsi host, there is no register shift */
a689554b
HL		 57 ver = FIELD(ver, DSI_VERSION_MAJOR);
58 if (ver <= MSM_DSI_VER_MAJOR_V2) {
59 /* old versions */
60 *major = ver;
61 *minor = 0;
62 return 0;
63 } else {
64 return -EINVAL;
65 }
66 } else {
648d5063
AT		 67 /*
68 * newer host, offset 0 has 6G_HW_VERSION, the rest of the
69 * registers are shifted down, read DSI_VERSION again with
70 * the shifted offset
71 */
a689554b
HL		 72 ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION);
73 ver = FIELD(ver, DSI_VERSION_MAJOR);
74 if (ver == MSM_DSI_VER_MAJOR_6G) {
75 /* 6G version */
76 *major = ver;
648d5063 77 *minor = msm_readl(base + REG_DSI_6G_HW_VERSION);
a689554b
HL		 78 return 0;
79 } else {
80 return -EINVAL;
81 }
82 }
83}
84
85#define DSI_ERR_STATE_ACK 0x0000
86#define DSI_ERR_STATE_TIMEOUT 0x0001
87#define DSI_ERR_STATE_DLN0_PHY 0x0002
88#define DSI_ERR_STATE_FIFO 0x0004
89#define DSI_ERR_STATE_MDP_FIFO_UNDERFLOW 0x0008
90#define DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION 0x0010
91#define DSI_ERR_STATE_PLL_UNLOCKED 0x0020
92
93#define DSI_CLK_CTRL_ENABLE_CLKS \
94 (DSI_CLK_CTRL_AHBS_HCLK_ON | DSI_CLK_CTRL_AHBM_SCLK_ON | \
95 DSI_CLK_CTRL_PCLK_ON | DSI_CLK_CTRL_DSICLK_ON | \
96 DSI_CLK_CTRL_BYTECLK_ON | DSI_CLK_CTRL_ESCCLK_ON | \
97 DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK)
98
99struct msm_dsi_host {
100 struct mipi_dsi_host base;
101
102 struct platform_device *pdev;
103 struct drm_device *dev;
104
105 int id;
106
107 void __iomem *ctrl_base;
ec31abf6 108 struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX];
6e0eb52e
AT		 109
110 struct clk *bus_clks[DSI_BUS_CLK_MAX];
111
a689554b
HL		 112 struct clk *byte_clk;
113 struct clk *esc_clk;
114 struct clk *pixel_clk;
9d32c498
HL		 115 struct clk *byte_clk_src;
116 struct clk *pixel_clk_src;
117
a689554b 118 u32 byte_clk_rate;
4bfa9748
AT		 119 u32 esc_clk_rate;
120
121 /* DSI v2 specific clocks */
122 struct clk *src_clk;
123 struct clk *esc_clk_src;
124 struct clk *dsi_clk_src;
125
126 u32 src_clk_rate;
a689554b
HL		 127
128 struct gpio_desc *disp_en_gpio;
129 struct gpio_desc *te_gpio;
130
d248b61f 131 const struct msm_dsi_cfg_handler *cfg_hnd;
a689554b
HL		 132
133 struct completion dma_comp;
134 struct completion video_comp;
135 struct mutex dev_mutex;
136 struct mutex cmd_mutex;
137 struct mutex clk_mutex;
138 spinlock_t intr_lock; /* Protect interrupt ctrl register */
139
140 u32 err_work_state;
141 struct work_struct err_work;
8d23ea40 142 struct work_struct hpd_work;
a689554b
HL		 143 struct workqueue_struct *workqueue;
144
4ff9d4cb 145 /* DSI 6G TX buffer*/
a689554b 146 struct drm_gem_object *tx_gem_obj;
4ff9d4cb
AT		 147
148 /* DSI v2 TX buffer */
149 void *tx_buf;
150 dma_addr_t tx_buf_paddr;
151
152 int tx_size;
153
a689554b
HL		 154 u8 *rx_buf;
155
0c7df47f
AT		 156 struct regmap *sfpb;
157
a689554b
HL		 158 struct drm_display_mode *mode;
159
a9ddac9c
AT		 160 /* connected device info */
161 struct device_node *device_node;
a689554b
HL		 162 unsigned int channel;
163 unsigned int lanes;
164 enum mipi_dsi_pixel_format format;
165 unsigned long mode_flags;
166
26f7d1f4
AT		 167 /* lane data parsed via DT */
168 int dlane_swap;
169 int num_data_lanes;
170
a689554b
HL		 171 u32 dma_cmd_ctrl_restore;
172
173 bool registered;
174 bool power_on;
175 int irq;
176};
177
178static u32 dsi_get_bpp(const enum mipi_dsi_pixel_format fmt)
179{
180 switch (fmt) {
181 case MIPI_DSI_FMT_RGB565: return 16;
182 case MIPI_DSI_FMT_RGB666_PACKED: return 18;
183 case MIPI_DSI_FMT_RGB666:
184 case MIPI_DSI_FMT_RGB888:
185 default: return 24;
186 }
187}
188
189static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg)
190{
d248b61f 191 return msm_readl(msm_host->ctrl_base + reg);
a689554b
HL		 192}
193static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data)
194{
d248b61f 195 msm_writel(data, msm_host->ctrl_base + reg);
a689554b
HL		 196}
197
198static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host);
199static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host);
200
d248b61f
HL		 201static const struct msm_dsi_cfg_handler *dsi_get_config(
202 struct msm_dsi_host *msm_host)
a689554b 203{
d248b61f 204 const struct msm_dsi_cfg_handler *cfg_hnd = NULL;
31c92767 205 struct device *dev = &msm_host->pdev->dev;
a689554b 206 struct regulator *gdsc_reg;
31c92767 207 struct clk *ahb_clk;
d248b61f 208 int ret;
a689554b
HL		 209 u32 major = 0, minor = 0;
210
31c92767 211 gdsc_reg = regulator_get(dev, "gdsc");
bdc80de2 212 if (IS_ERR(gdsc_reg)) {
a689554b 213 pr_err("%s: cannot get gdsc\n", __func__);
d248b61f 214 goto exit;
a689554b 215 }
31c92767
AT		 216
217 ahb_clk = clk_get(dev, "iface_clk");
218 if (IS_ERR(ahb_clk)) {
219 pr_err("%s: cannot get interface clock\n", __func__);
220 goto put_gdsc;
221 }
222
a689554b
HL		 223 ret = regulator_enable(gdsc_reg);
224 if (ret) {
225 pr_err("%s: unable to enable gdsc\n", __func__);
31c92767 226 goto put_clk;
a689554b 227 }
31c92767
AT		 228
229 ret = clk_prepare_enable(ahb_clk);
a689554b
HL		 230 if (ret) {
231 pr_err("%s: unable to enable ahb_clk\n", __func__);
d248b61f 232 goto disable_gdsc;
a689554b
HL		 233 }
234
235 ret = dsi_get_version(msm_host->ctrl_base, &major, &minor);
a689554b
HL		 236 if (ret) {
237 pr_err("%s: Invalid version\n", __func__);
d248b61f 238 goto disable_clks;
a689554b
HL		 239 }
240
d248b61f 241 cfg_hnd = msm_dsi_cfg_get(major, minor);
a689554b 242
d248b61f
HL		 243 DBG("%s: Version %x:%x\n", __func__, major, minor);
244
245disable_clks:
31c92767 246 clk_disable_unprepare(ahb_clk);
d248b61f
HL		 247disable_gdsc:
248 regulator_disable(gdsc_reg);
31c92767
AT		 249put_clk:
250 clk_put(ahb_clk);
d248b61f
HL		 251put_gdsc:
252 regulator_put(gdsc_reg);
253exit:
254 return cfg_hnd;
a689554b
HL		 255}
256
257static inline struct msm_dsi_host *to_msm_dsi_host(struct mipi_dsi_host *host)
258{
259 return container_of(host, struct msm_dsi_host, base);
260}
261
262static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host)
263{
264 struct regulator_bulk_data *s = msm_host->supplies;
d248b61f
HL		 265 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
266 int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
a689554b
HL		 267 int i;
268
269 DBG("");
270 for (i = num - 1; i >= 0; i--)
271 if (regs[i].disable_load >= 0)
2c33ce00
DA		 272 regulator_set_load(s[i].consumer,
273 regs[i].disable_load);
a689554b
HL		 274
275 regulator_bulk_disable(num, s);
276}
277
278static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host)
279{
280 struct regulator_bulk_data *s = msm_host->supplies;
d248b61f
HL		 281 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
282 int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
a689554b
HL		 283 int ret, i;
284
285 DBG("");
286 for (i = 0; i < num; i++) {
287 if (regs[i].enable_load >= 0) {
2c33ce00
DA		 288 ret = regulator_set_load(s[i].consumer,
289 regs[i].enable_load);
a689554b
HL		 290 if (ret < 0) {
291 pr_err("regulator %d set op mode failed, %d\n",
292 i, ret);
293 goto fail;
294 }
295 }
296 }
297
298 ret = regulator_bulk_enable(num, s);
299 if (ret < 0) {
300 pr_err("regulator enable failed, %d\n", ret);
301 goto fail;
302 }
303
304 return 0;
305
306fail:
307 for (i--; i >= 0; i--)
2c33ce00 308 regulator_set_load(s[i].consumer, regs[i].disable_load);
a689554b
HL		 309 return ret;
310}
311
312static int dsi_regulator_init(struct msm_dsi_host *msm_host)
313{
314 struct regulator_bulk_data *s = msm_host->supplies;
d248b61f
HL		 315 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
316 int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
a689554b
HL		 317 int i, ret;
318
319 for (i = 0; i < num; i++)
320 s[i].supply = regs[i].name;
321
322 ret = devm_regulator_bulk_get(&msm_host->pdev->dev, num, s);
323 if (ret < 0) {
324 pr_err("%s: failed to init regulator, ret=%d\n",
325 __func__, ret);
326 return ret;
327 }
328
a689554b
HL		 329 return 0;
330}
331
332static int dsi_clk_init(struct msm_dsi_host *msm_host)
333{
334 struct device *dev = &msm_host->pdev->dev;
4bfa9748
AT		 335 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
336 const struct msm_dsi_config *cfg = cfg_hnd->cfg;
6e0eb52e
AT		 337 int i, ret = 0;
338
339 /* get bus clocks */
340 for (i = 0; i < cfg->num_bus_clks; i++) {
341 msm_host->bus_clks[i] = devm_clk_get(dev,
342 cfg->bus_clk_names[i]);
343 if (IS_ERR(msm_host->bus_clks[i])) {
344 ret = PTR_ERR(msm_host->bus_clks[i]);
345 pr_err("%s: Unable to get %s, ret = %d\n",
346 __func__, cfg->bus_clk_names[i], ret);
347 goto exit;
348 }
a689554b
HL		 349 }
350
6e0eb52e 351 /* get link and source clocks */
a689554b
HL		 352 msm_host->byte_clk = devm_clk_get(dev, "byte_clk");
353 if (IS_ERR(msm_host->byte_clk)) {
354 ret = PTR_ERR(msm_host->byte_clk);
355 pr_err("%s: can't find dsi_byte_clk. ret=%d\n",
356 __func__, ret);
357 msm_host->byte_clk = NULL;
358 goto exit;
359 }
360
361 msm_host->pixel_clk = devm_clk_get(dev, "pixel_clk");
362 if (IS_ERR(msm_host->pixel_clk)) {
363 ret = PTR_ERR(msm_host->pixel_clk);
364 pr_err("%s: can't find dsi_pixel_clk. ret=%d\n",
365 __func__, ret);
366 msm_host->pixel_clk = NULL;
367 goto exit;
368 }
369
370 msm_host->esc_clk = devm_clk_get(dev, "core_clk");
371 if (IS_ERR(msm_host->esc_clk)) {
372 ret = PTR_ERR(msm_host->esc_clk);
373 pr_err("%s: can't find dsi_esc_clk. ret=%d\n",
374 __func__, ret);
375 msm_host->esc_clk = NULL;
376 goto exit;
377 }
378
e6c4c78c
AT		 379 msm_host->byte_clk_src = clk_get_parent(msm_host->byte_clk);
380 if (!msm_host->byte_clk_src) {
381 ret = -ENODEV;
9d32c498 382 pr_err("%s: can't find byte_clk_src. ret=%d\n", __func__, ret);
9d32c498
HL		 383 goto exit;
384 }
385
e6c4c78c
AT		 386 msm_host->pixel_clk_src = clk_get_parent(msm_host->pixel_clk);
387 if (!msm_host->pixel_clk_src) {
388 ret = -ENODEV;
9d32c498 389 pr_err("%s: can't find pixel_clk_src. ret=%d\n", __func__, ret);
4bfa9748 390 goto exit;
9d32c498
HL		 391 }
392
4bfa9748
AT		 393 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_V2) {
394 msm_host->src_clk = devm_clk_get(dev, "src_clk");
395 if (IS_ERR(msm_host->src_clk)) {
396 ret = PTR_ERR(msm_host->src_clk);
397 pr_err("%s: can't find dsi_src_clk. ret=%d\n",
398 __func__, ret);
399 msm_host->src_clk = NULL;
400 goto exit;
401 }
402
403 msm_host->esc_clk_src = clk_get_parent(msm_host->esc_clk);
404 if (!msm_host->esc_clk_src) {
405 ret = -ENODEV;
406 pr_err("%s: can't get esc_clk_src. ret=%d\n",
407 __func__, ret);
408 goto exit;
409 }
410
411 msm_host->dsi_clk_src = clk_get_parent(msm_host->src_clk);
412 if (!msm_host->dsi_clk_src) {
413 ret = -ENODEV;
414 pr_err("%s: can't get dsi_clk_src. ret=%d\n",
415 __func__, ret);
416 }
417 }
a689554b
HL		 418exit:
419 return ret;
420}
421
422static int dsi_bus_clk_enable(struct msm_dsi_host *msm_host)
423{
6e0eb52e
AT		 424 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg;
425 int i, ret;
a689554b
HL		 426
427 DBG("id=%d", msm_host->id);
428
6e0eb52e
AT		 429 for (i = 0; i < cfg->num_bus_clks; i++) {
430 ret = clk_prepare_enable(msm_host->bus_clks[i]);
431 if (ret) {
432 pr_err("%s: failed to enable bus clock %d ret %d\n",
433 __func__, i, ret);
434 goto err;
435 }
a689554b
HL		 436 }
437
438 return 0;
6e0eb52e
AT		 439err:
440 for (; i > 0; i--)
441 clk_disable_unprepare(msm_host->bus_clks[i]);
a689554b 442
a689554b
HL		 443 return ret;
444}
445
446static void dsi_bus_clk_disable(struct msm_dsi_host *msm_host)
447{
6e0eb52e
AT		 448 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg;
449 int i;
450
a689554b 451 DBG("");
6e0eb52e
AT		 452
453 for (i = cfg->num_bus_clks - 1; i >= 0; i--)
454 clk_disable_unprepare(msm_host->bus_clks[i]);
a689554b
HL		 455}
456
4bfa9748 457static int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host)
a689554b
HL		 458{
459 int ret;
460
461 DBG("Set clk rates: pclk=%d, byteclk=%d",
462 msm_host->mode->clock, msm_host->byte_clk_rate);
463
464 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate);
465 if (ret) {
466 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret);
467 goto error;
468 }
469
470 ret = clk_set_rate(msm_host->pixel_clk, msm_host->mode->clock * 1000);
471 if (ret) {
472 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
473 goto error;
474 }
475
476 ret = clk_prepare_enable(msm_host->esc_clk);
477 if (ret) {
478 pr_err("%s: Failed to enable dsi esc clk\n", __func__);
479 goto error;
480 }
481
482 ret = clk_prepare_enable(msm_host->byte_clk);
483 if (ret) {
484 pr_err("%s: Failed to enable dsi byte clk\n", __func__);
485 goto byte_clk_err;
486 }
487
488 ret = clk_prepare_enable(msm_host->pixel_clk);
489 if (ret) {
490 pr_err("%s: Failed to enable dsi pixel clk\n", __func__);
491 goto pixel_clk_err;
492 }
493
494 return 0;
495
496pixel_clk_err:
497 clk_disable_unprepare(msm_host->byte_clk);
498byte_clk_err:
499 clk_disable_unprepare(msm_host->esc_clk);
500error:
501 return ret;
502}
503
4bfa9748 504static int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host)
a689554b 505{
4bfa9748
AT		 506 int ret;
507
508 DBG("Set clk rates: pclk=%d, byteclk=%d, esc_clk=%d, dsi_src_clk=%d",
509 msm_host->mode->clock, msm_host->byte_clk_rate,
510 msm_host->esc_clk_rate, msm_host->src_clk_rate);
511
512 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate);
513 if (ret) {
514 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret);
515 goto error;
516 }
517
518 ret = clk_set_rate(msm_host->esc_clk, msm_host->esc_clk_rate);
519 if (ret) {
520 pr_err("%s: Failed to set rate esc clk, %d\n", __func__, ret);
521 goto error;
522 }
523
524 ret = clk_set_rate(msm_host->src_clk, msm_host->src_clk_rate);
525 if (ret) {
526 pr_err("%s: Failed to set rate src clk, %d\n", __func__, ret);
527 goto error;
528 }
529
530 ret = clk_set_rate(msm_host->pixel_clk, msm_host->mode->clock * 1000);
531 if (ret) {
532 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
533 goto error;
534 }
535
536 ret = clk_prepare_enable(msm_host->byte_clk);
537 if (ret) {
538 pr_err("%s: Failed to enable dsi byte clk\n", __func__);
539 goto error;
540 }
541
542 ret = clk_prepare_enable(msm_host->esc_clk);
543 if (ret) {
544 pr_err("%s: Failed to enable dsi esc clk\n", __func__);
545 goto esc_clk_err;
546 }
547
548 ret = clk_prepare_enable(msm_host->src_clk);
549 if (ret) {
550 pr_err("%s: Failed to enable dsi src clk\n", __func__);
551 goto src_clk_err;
552 }
553
554 ret = clk_prepare_enable(msm_host->pixel_clk);
555 if (ret) {
556 pr_err("%s: Failed to enable dsi pixel clk\n", __func__);
557 goto pixel_clk_err;
558 }
559
560 return 0;
561
562pixel_clk_err:
563 clk_disable_unprepare(msm_host->src_clk);
564src_clk_err:
a689554b 565 clk_disable_unprepare(msm_host->esc_clk);
4bfa9748 566esc_clk_err:
a689554b 567 clk_disable_unprepare(msm_host->byte_clk);
4bfa9748
AT		 568error:
569 return ret;
570}
571
572static int dsi_link_clk_enable(struct msm_dsi_host *msm_host)
573{
574 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
575
576 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G)
577 return dsi_link_clk_enable_6g(msm_host);
578 else
579 return dsi_link_clk_enable_v2(msm_host);
580}
581
582static void dsi_link_clk_disable(struct msm_dsi_host *msm_host)
583{
584 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
585
586 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) {
587 clk_disable_unprepare(msm_host->esc_clk);
588 clk_disable_unprepare(msm_host->pixel_clk);
589 clk_disable_unprepare(msm_host->byte_clk);
590 } else {
591 clk_disable_unprepare(msm_host->pixel_clk);
592 clk_disable_unprepare(msm_host->src_clk);
593 clk_disable_unprepare(msm_host->esc_clk);
594 clk_disable_unprepare(msm_host->byte_clk);
595 }
a689554b
HL		 596}
597
598static int dsi_clk_ctrl(struct msm_dsi_host *msm_host, bool enable)
599{
600 int ret = 0;
601
602 mutex_lock(&msm_host->clk_mutex);
603 if (enable) {
604 ret = dsi_bus_clk_enable(msm_host);
605 if (ret) {
606 pr_err("%s: Can not enable bus clk, %d\n",
607 __func__, ret);
608 goto unlock_ret;
609 }
610 ret = dsi_link_clk_enable(msm_host);
611 if (ret) {
612 pr_err("%s: Can not enable link clk, %d\n",
613 __func__, ret);
614 dsi_bus_clk_disable(msm_host);
615 goto unlock_ret;
616 }
617 } else {
618 dsi_link_clk_disable(msm_host);
619 dsi_bus_clk_disable(msm_host);
620 }
621
622unlock_ret:
623 mutex_unlock(&msm_host->clk_mutex);
624 return ret;
625}
626
627static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host)
628{
629 struct drm_display_mode *mode = msm_host->mode;
4bfa9748 630 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
a689554b
HL		 631 u8 lanes = msm_host->lanes;
632 u32 bpp = dsi_get_bpp(msm_host->format);
633 u32 pclk_rate;
634
635 if (!mode) {
636 pr_err("%s: mode not set\n", __func__);
637 return -EINVAL;
638 }
639
640 pclk_rate = mode->clock * 1000;
641 if (lanes > 0) {
642 msm_host->byte_clk_rate = (pclk_rate * bpp) / (8 * lanes);
643 } else {
644 pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__);
645 msm_host->byte_clk_rate = (pclk_rate * bpp) / 8;
646 }
647
648 DBG("pclk=%d, bclk=%d", pclk_rate, msm_host->byte_clk_rate);
649
4bfa9748
AT		 650 msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk);
651
652 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_V2) {
653 unsigned int esc_mhz, esc_div;
654 unsigned long byte_mhz;
655
656 msm_host->src_clk_rate = (pclk_rate * bpp) / 8;
657
658 /*
659 * esc clock is byte clock followed by a 4 bit divider,
660 * we need to find an escape clock frequency within the
661 * mipi DSI spec range within the maximum divider limit
662 * We iterate here between an escape clock frequencey
663 * between 20 Mhz to 5 Mhz and pick up the first one
664 * that can be supported by our divider
665 */
666
667 byte_mhz = msm_host->byte_clk_rate / 1000000;
668
669 for (esc_mhz = 20; esc_mhz >= 5; esc_mhz--) {
670 esc_div = DIV_ROUND_UP(byte_mhz, esc_mhz);
671
672 /*
673 * TODO: Ideally, we shouldn't know what sort of divider
674 * is available in mmss_cc, we're just assuming that
675 * it'll always be a 4 bit divider. Need to come up with
676 * a better way here.
677 */
678 if (esc_div >= 1 && esc_div <= 16)
679 break;
680 }
681
682 if (esc_mhz < 5)
683 return -EINVAL;
684
685 msm_host->esc_clk_rate = msm_host->byte_clk_rate / esc_div;
686
687 DBG("esc=%d, src=%d", msm_host->esc_clk_rate,
688 msm_host->src_clk_rate);
689 }
690
a689554b
HL		 691 return 0;
692}
693
a689554b
HL		 694static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable)
695{
696 u32 intr;
697 unsigned long flags;
698
699 spin_lock_irqsave(&msm_host->intr_lock, flags);
700 intr = dsi_read(msm_host, REG_DSI_INTR_CTRL);
701
702 if (enable)
703 intr |= mask;
704 else
705 intr &= ~mask;
706
707 DBG("intr=%x enable=%d", intr, enable);
708
709 dsi_write(msm_host, REG_DSI_INTR_CTRL, intr);
710 spin_unlock_irqrestore(&msm_host->intr_lock, flags);
711}
712
713static inline enum dsi_traffic_mode dsi_get_traffic_mode(const u32 mode_flags)
714{
715 if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
716 return BURST_MODE;
717 else if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
718 return NON_BURST_SYNCH_PULSE;
719
720 return NON_BURST_SYNCH_EVENT;
721}
722
723static inline enum dsi_vid_dst_format dsi_get_vid_fmt(
724 const enum mipi_dsi_pixel_format mipi_fmt)
725{
726 switch (mipi_fmt) {
727 case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888;
728 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666_LOOSE;
729 case MIPI_DSI_FMT_RGB666_PACKED: return VID_DST_FORMAT_RGB666;
730 case MIPI_DSI_FMT_RGB565: return VID_DST_FORMAT_RGB565;
731 default: return VID_DST_FORMAT_RGB888;
732 }
733}
734
735static inline enum dsi_cmd_dst_format dsi_get_cmd_fmt(
736 const enum mipi_dsi_pixel_format mipi_fmt)
737{
738 switch (mipi_fmt) {
739 case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888;
740 case MIPI_DSI_FMT_RGB666_PACKED:
741 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666;
742 case MIPI_DSI_FMT_RGB565: return CMD_DST_FORMAT_RGB565;
743 default: return CMD_DST_FORMAT_RGB888;
744 }
745}
746
747static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
dceac340 748 struct msm_dsi_phy_shared_timings *phy_shared_timings)
a689554b
HL		 749{
750 u32 flags = msm_host->mode_flags;
751 enum mipi_dsi_pixel_format mipi_fmt = msm_host->format;
d248b61f 752 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
a689554b
HL		 753 u32 data = 0;
754
755 if (!enable) {
756 dsi_write(msm_host, REG_DSI_CTRL, 0);
757 return;
758 }
759
760 if (flags & MIPI_DSI_MODE_VIDEO) {
761 if (flags & MIPI_DSI_MODE_VIDEO_HSE)
762 data |= DSI_VID_CFG0_PULSE_MODE_HSA_HE;
763 if (flags & MIPI_DSI_MODE_VIDEO_HFP)
764 data |= DSI_VID_CFG0_HFP_POWER_STOP;
765 if (flags & MIPI_DSI_MODE_VIDEO_HBP)
766 data |= DSI_VID_CFG0_HBP_POWER_STOP;
767 if (flags & MIPI_DSI_MODE_VIDEO_HSA)
768 data |= DSI_VID_CFG0_HSA_POWER_STOP;
769 /* Always set low power stop mode for BLLP
770 * to let command engine send packets
771 */
772 data |= DSI_VID_CFG0_EOF_BLLP_POWER_STOP |
773 DSI_VID_CFG0_BLLP_POWER_STOP;
774 data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags));
775 data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt));
776 data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel);
777 dsi_write(msm_host, REG_DSI_VID_CFG0, data);
778
779 /* Do not swap RGB colors */
780 data = DSI_VID_CFG1_RGB_SWAP(SWAP_RGB);
781 dsi_write(msm_host, REG_DSI_VID_CFG1, 0);
782 } else {
783 /* Do not swap RGB colors */
784 data = DSI_CMD_CFG0_RGB_SWAP(SWAP_RGB);
785 data |= DSI_CMD_CFG0_DST_FORMAT(dsi_get_cmd_fmt(mipi_fmt));
786 dsi_write(msm_host, REG_DSI_CMD_CFG0, data);
787
788 data = DSI_CMD_CFG1_WR_MEM_START(MIPI_DCS_WRITE_MEMORY_START) |
789 DSI_CMD_CFG1_WR_MEM_CONTINUE(
790 MIPI_DCS_WRITE_MEMORY_CONTINUE);
791 /* Always insert DCS command */
792 data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND;
793 dsi_write(msm_host, REG_DSI_CMD_CFG1, data);
794 }
795
796 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL,
797 DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER |
798 DSI_CMD_DMA_CTRL_LOW_POWER);
799
800 data = 0;
801 /* Always assume dedicated TE pin */
802 data |= DSI_TRIG_CTRL_TE;
803 data |= DSI_TRIG_CTRL_MDP_TRIGGER(TRIGGER_NONE);
804 data |= DSI_TRIG_CTRL_DMA_TRIGGER(TRIGGER_SW);
805 data |= DSI_TRIG_CTRL_STREAM(msm_host->channel);
d248b61f
HL		 806 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
807 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_2))
a689554b
HL		 808 data |= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME;
809 dsi_write(msm_host, REG_DSI_TRIG_CTRL, data);
810
dceac340
HL		 811 data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(phy_shared_timings->clk_post) |
812 DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(phy_shared_timings->clk_pre);
a689554b
HL		 813 dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data);
814
dceac340
HL		 815 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
816 (cfg_hnd->minor > MSM_DSI_6G_VER_MINOR_V1_0) &&
817 phy_shared_timings->clk_pre_inc_by_2)
818 dsi_write(msm_host, REG_DSI_T_CLK_PRE_EXTEND,
819 DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK);
820
a689554b
HL		 821 data = 0;
822 if (!(flags & MIPI_DSI_MODE_EOT_PACKET))
823 data |= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND;
824 dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data);
825
826 /* allow only ack-err-status to generate interrupt */
827 dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0);
828
829 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1);
830
831 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
832
833 data = DSI_CTRL_CLK_EN;
834
835 DBG("lane number=%d", msm_host->lanes);
26f7d1f4
AT		 836 data |= ((DSI_CTRL_LANE0 << msm_host->lanes) - DSI_CTRL_LANE0);
837
838 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL,
839 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host->dlane_swap));
65c5e542
AT		 840
841 if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
842 dsi_write(msm_host, REG_DSI_LANE_CTRL,
843 DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST);
844
a689554b
HL		 845 data |= DSI_CTRL_ENABLE;
846
847 dsi_write(msm_host, REG_DSI_CTRL, data);
848}
849
850static void dsi_timing_setup(struct msm_dsi_host *msm_host)
851{
852 struct drm_display_mode *mode = msm_host->mode;
853 u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */
854 u32 h_total = mode->htotal;
855 u32 v_total = mode->vtotal;
856 u32 hs_end = mode->hsync_end - mode->hsync_start;
857 u32 vs_end = mode->vsync_end - mode->vsync_start;
858 u32 ha_start = h_total - mode->hsync_start;
859 u32 ha_end = ha_start + mode->hdisplay;
860 u32 va_start = v_total - mode->vsync_start;
861 u32 va_end = va_start + mode->vdisplay;
862 u32 wc;
863
864 DBG("");
865
866 if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) {
867 dsi_write(msm_host, REG_DSI_ACTIVE_H,
868 DSI_ACTIVE_H_START(ha_start) |
869 DSI_ACTIVE_H_END(ha_end));
870 dsi_write(msm_host, REG_DSI_ACTIVE_V,
871 DSI_ACTIVE_V_START(va_start) |
872 DSI_ACTIVE_V_END(va_end));
873 dsi_write(msm_host, REG_DSI_TOTAL,
874 DSI_TOTAL_H_TOTAL(h_total - 1) |
875 DSI_TOTAL_V_TOTAL(v_total - 1));
876
877 dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC,
878 DSI_ACTIVE_HSYNC_START(hs_start) |
879 DSI_ACTIVE_HSYNC_END(hs_end));
880 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0);
881 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS,
882 DSI_ACTIVE_VSYNC_VPOS_START(vs_start) |
883 DSI_ACTIVE_VSYNC_VPOS_END(vs_end));
884 } else { /* command mode */
885 /* image data and 1 byte write_memory_start cmd */
886 wc = mode->hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
887
888 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_CTRL,
889 DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(wc) |
890 DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL(
891 msm_host->channel) |
892 DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE(
893 MIPI_DSI_DCS_LONG_WRITE));
894
895 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_TOTAL,
896 DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(mode->hdisplay) |
897 DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(mode->vdisplay));
898 }
899}
900
901static void dsi_sw_reset(struct msm_dsi_host *msm_host)
902{
903 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
904 wmb(); /* clocks need to be enabled before reset */
905
906 dsi_write(msm_host, REG_DSI_RESET, 1);
907 wmb(); /* make sure reset happen */
908 dsi_write(msm_host, REG_DSI_RESET, 0);
909}
910
911static void dsi_op_mode_config(struct msm_dsi_host *msm_host,
912 bool video_mode, bool enable)
913{
914 u32 dsi_ctrl;
915
916 dsi_ctrl = dsi_read(msm_host, REG_DSI_CTRL);
917
918 if (!enable) {
919 dsi_ctrl &= ~(DSI_CTRL_ENABLE | DSI_CTRL_VID_MODE_EN |
920 DSI_CTRL_CMD_MODE_EN);
921 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE |
922 DSI_IRQ_MASK_VIDEO_DONE, 0);
923 } else {
924 if (video_mode) {
925 dsi_ctrl |= DSI_CTRL_VID_MODE_EN;
926 } else { /* command mode */
927 dsi_ctrl |= DSI_CTRL_CMD_MODE_EN;
928 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE, 1);
929 }
930 dsi_ctrl |= DSI_CTRL_ENABLE;
931 }
932
933 dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl);
934}
935
936static void dsi_set_tx_power_mode(int mode, struct msm_dsi_host *msm_host)
937{
938 u32 data;
939
940 data = dsi_read(msm_host, REG_DSI_CMD_DMA_CTRL);
941
942 if (mode == 0)
943 data &= ~DSI_CMD_DMA_CTRL_LOW_POWER;
944 else
945 data |= DSI_CMD_DMA_CTRL_LOW_POWER;
946
947 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data);
948}
949
950static void dsi_wait4video_done(struct msm_dsi_host *msm_host)
951{
952 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1);
953
954 reinit_completion(&msm_host->video_comp);
955
956 wait_for_completion_timeout(&msm_host->video_comp,
957 msecs_to_jiffies(70));
958
959 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0);
960}
961
962static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host)
963{
964 if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO))
965 return;
966
967 if (msm_host->power_on) {
968 dsi_wait4video_done(msm_host);
969 /* delay 4 ms to skip BLLP */
970 usleep_range(2000, 4000);
971 }
972}
973
974/* dsi_cmd */
975static int dsi_tx_buf_alloc(struct msm_dsi_host *msm_host, int size)
976{
977 struct drm_device *dev = msm_host->dev;
4ff9d4cb 978 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
a689554b 979 int ret;
78babc16 980 uint64_t iova;
a689554b 981
4ff9d4cb
AT		 982 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) {
983 mutex_lock(&dev->struct_mutex);
984 msm_host->tx_gem_obj = msm_gem_new(dev, size, MSM_BO_UNCACHED);
985 if (IS_ERR(msm_host->tx_gem_obj)) {
986 ret = PTR_ERR(msm_host->tx_gem_obj);
987 pr_err("%s: failed to allocate gem, %d\n",
988 __func__, ret);
989 msm_host->tx_gem_obj = NULL;
990 mutex_unlock(&dev->struct_mutex);
991 return ret;
992 }
993
994 ret = msm_gem_get_iova_locked(msm_host->tx_gem_obj, 0, &iova);
beb107f3 995 mutex_unlock(&dev->struct_mutex);
4ff9d4cb
AT		 996 if (ret) {
997 pr_err("%s: failed to get iova, %d\n", __func__, ret);
998 return ret;
999 }
a689554b 1000
4ff9d4cb
AT		 1001 if (iova & 0x07) {
1002 pr_err("%s: buf NOT 8 bytes aligned\n", __func__);
1003 return -EINVAL;
1004 }
a689554b 1005
4ff9d4cb
AT		 1006 msm_host->tx_size = msm_host->tx_gem_obj->size;
1007 } else {
1008 msm_host->tx_buf = dma_alloc_coherent(dev->dev, size,
1009 &msm_host->tx_buf_paddr, GFP_KERNEL);
1010 if (!msm_host->tx_buf) {
1011 ret = -ENOMEM;
1012 pr_err("%s: failed to allocate tx buf, %d\n",
1013 __func__, ret);
1014 return ret;
1015 }
1016
1017 msm_host->tx_size = size;
a689554b
HL		 1018 }
1019
1020 return 0;
1021}
1022
1023static void dsi_tx_buf_free(struct msm_dsi_host *msm_host)
1024{
1025 struct drm_device *dev = msm_host->dev;
1026
1027 if (msm_host->tx_gem_obj) {
1028 msm_gem_put_iova(msm_host->tx_gem_obj, 0);
1029 mutex_lock(&dev->struct_mutex);
1030 msm_gem_free_object(msm_host->tx_gem_obj);
1031 msm_host->tx_gem_obj = NULL;
1032 mutex_unlock(&dev->struct_mutex);
1033 }
4ff9d4cb
AT		 1034
1035 if (msm_host->tx_buf)
1036 dma_free_coherent(dev->dev, msm_host->tx_size, msm_host->tx_buf,
1037 msm_host->tx_buf_paddr);
a689554b
HL		 1038}
1039
1040/*
1041 * prepare cmd buffer to be txed
1042 */
4ff9d4cb
AT		 1043static int dsi_cmd_dma_add(struct msm_dsi_host *msm_host,
1044 const struct mipi_dsi_msg *msg)
a689554b 1045{
4ff9d4cb 1046 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
a689554b
HL		 1047 struct mipi_dsi_packet packet;
1048 int len;
1049 int ret;
1050 u8 *data;
1051
1052 ret = mipi_dsi_create_packet(&packet, msg);
1053 if (ret) {
1054 pr_err("%s: create packet failed, %d\n", __func__, ret);
1055 return ret;
1056 }
1057 len = (packet.size + 3) & (~0x3);
1058
4ff9d4cb 1059 if (len > msm_host->tx_size) {
a689554b
HL		 1060 pr_err("%s: packet size is too big\n", __func__);
1061 return -EINVAL;
1062 }
1063
4ff9d4cb 1064 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) {
18f23049 1065 data = msm_gem_get_vaddr(msm_host->tx_gem_obj);
4ff9d4cb
AT		 1066 if (IS_ERR(data)) {
1067 ret = PTR_ERR(data);
1068 pr_err("%s: get vaddr failed, %d\n", __func__, ret);
1069 return ret;
1070 }
1071 } else {
1072 data = msm_host->tx_buf;
a689554b
HL		 1073 }
1074
1075 /* MSM specific command format in memory */
1076 data[0] = packet.header[1];
1077 data[1] = packet.header[2];
1078 data[2] = packet.header[0];
1079 data[3] = BIT(7); /* Last packet */
1080 if (mipi_dsi_packet_format_is_long(msg->type))
1081 data[3] |= BIT(6);
1082 if (msg->rx_buf && msg->rx_len)
1083 data[3] |= BIT(5);
1084
1085 /* Long packet */
1086 if (packet.payload && packet.payload_length)
1087 memcpy(data + 4, packet.payload, packet.payload_length);
1088
1089 /* Append 0xff to the end */
1090 if (packet.size < len)
1091 memset(data + packet.size, 0xff, len - packet.size);
1092
18f23049
RC		 1093 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G)
1094 msm_gem_put_vaddr(msm_host->tx_gem_obj);
1095
a689554b
HL		 1096 return len;
1097}
1098
1099/*
1100 * dsi_short_read1_resp: 1 parameter
1101 */
1102static int dsi_short_read1_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1103{
1104 u8 *data = msg->rx_buf;
1105 if (data && (msg->rx_len >= 1)) {
1106 *data = buf[1]; /* strip out dcs type */
1107 return 1;
1108 } else {
981371f3 1109 pr_err("%s: read data does not match with rx_buf len %zu\n",
a689554b
HL		 1110 __func__, msg->rx_len);
1111 return -EINVAL;
1112 }
1113}
1114
1115/*
1116 * dsi_short_read2_resp: 2 parameter
1117 */
1118static int dsi_short_read2_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1119{
1120 u8 *data = msg->rx_buf;
1121 if (data && (msg->rx_len >= 2)) {
1122 data[0] = buf[1]; /* strip out dcs type */
1123 data[1] = buf[2];
1124 return 2;
1125 } else {
981371f3 1126 pr_err("%s: read data does not match with rx_buf len %zu\n",
a689554b
HL		 1127 __func__, msg->rx_len);
1128 return -EINVAL;
1129 }
1130}
1131
1132static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1133{
1134 /* strip out 4 byte dcs header */
1135 if (msg->rx_buf && msg->rx_len)
1136 memcpy(msg->rx_buf, buf + 4, msg->rx_len);
1137
1138 return msg->rx_len;
1139}
1140
a689554b
HL		 1141static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len)
1142{
4ff9d4cb 1143 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
a689554b 1144 int ret;
78babc16 1145 uint64_t dma_base;
a689554b
HL		 1146 bool triggered;
1147
4ff9d4cb
AT		 1148 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) {
1149 ret = msm_gem_get_iova(msm_host->tx_gem_obj, 0, &dma_base);
1150 if (ret) {
1151 pr_err("%s: failed to get iova: %d\n", __func__, ret);
1152 return ret;
1153 }
1154 } else {
1155 dma_base = msm_host->tx_buf_paddr;
a689554b
HL		 1156 }
1157
1158 reinit_completion(&msm_host->dma_comp);
1159
1160 dsi_wait4video_eng_busy(msm_host);
1161
1162 triggered = msm_dsi_manager_cmd_xfer_trigger(
4ff9d4cb 1163 msm_host->id, dma_base, len);
a689554b
HL		 1164 if (triggered) {
1165 ret = wait_for_completion_timeout(&msm_host->dma_comp,
1166 msecs_to_jiffies(200));
1167 DBG("ret=%d", ret);
1168 if (ret == 0)
1169 ret = -ETIMEDOUT;
1170 else
1171 ret = len;
1172 } else
1173 ret = len;
1174
1175 return ret;
1176}
1177
1178static int dsi_cmd_dma_rx(struct msm_dsi_host *msm_host,
1179 u8 *buf, int rx_byte, int pkt_size)
1180{
1181 u32 *lp, *temp, data;
1182 int i, j = 0, cnt;
a689554b
HL		 1183 u32 read_cnt;
1184 u8 reg[16];
1185 int repeated_bytes = 0;
1186 int buf_offset = buf - msm_host->rx_buf;
1187
1188 lp = (u32 *)buf;
1189 temp = (u32 *)reg;
1190 cnt = (rx_byte + 3) >> 2;
1191 if (cnt > 4)
1192 cnt = 4; /* 4 x 32 bits registers only */
1193
ec1936eb
HL		 1194 if (rx_byte == 4)
1195 read_cnt = 4;
1196 else
1197 read_cnt = pkt_size + 6;
a689554b
HL		 1198
1199 /*
1200 * In case of multiple reads from the panel, after the first read, there
1201 * is possibility that there are some bytes in the payload repeating in
1202 * the RDBK_DATA registers. Since we read all the parameters from the
1203 * panel right from the first byte for every pass. We need to skip the
1204 * repeating bytes and then append the new parameters to the rx buffer.
1205 */
1206 if (read_cnt > 16) {
1207 int bytes_shifted;
1208 /* Any data more than 16 bytes will be shifted out.
1209 * The temp read buffer should already contain these bytes.
1210 * The remaining bytes in read buffer are the repeated bytes.
1211 */
1212 bytes_shifted = read_cnt - 16;
1213 repeated_bytes = buf_offset - bytes_shifted;
1214 }
1215
1216 for (i = cnt - 1; i >= 0; i--) {
1217 data = dsi_read(msm_host, REG_DSI_RDBK_DATA(i));
1218 *temp++ = ntohl(data); /* to host byte order */
1219 DBG("data = 0x%x and ntohl(data) = 0x%x", data, ntohl(data));
1220 }
1221
1222 for (i = repeated_bytes; i < 16; i++)
1223 buf[j++] = reg[i];
1224
1225 return j;
1226}
1227
1228static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host,
1229 const struct mipi_dsi_msg *msg)
1230{
1231 int len, ret;
1232 int bllp_len = msm_host->mode->hdisplay *
1233 dsi_get_bpp(msm_host->format) / 8;
1234
4ff9d4cb 1235 len = dsi_cmd_dma_add(msm_host, msg);
a689554b
HL		 1236 if (!len) {
1237 pr_err("%s: failed to add cmd type = 0x%x\n",
1238 __func__, msg->type);
1239 return -EINVAL;
1240 }
1241
1242 /* for video mode, do not send cmds more than
1243 * one pixel line, since it only transmit it
1244 * during BLLP.
1245 */
1246 /* TODO: if the command is sent in LP mode, the bit rate is only
1247 * half of esc clk rate. In this case, if the video is already
1248 * actively streaming, we need to check more carefully if the
1249 * command can be fit into one BLLP.
1250 */
1251 if ((msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && (len > bllp_len)) {
1252 pr_err("%s: cmd cannot fit into BLLP period, len=%d\n",
1253 __func__, len);
1254 return -EINVAL;
1255 }
1256
1257 ret = dsi_cmd_dma_tx(msm_host, len);
1258 if (ret < len) {
1259 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d\n",
1260 __func__, msg->type, (*(u8 *)(msg->tx_buf)), len);
1261 return -ECOMM;
1262 }
1263
1264 return len;
1265}
1266
1267static void dsi_sw_reset_restore(struct msm_dsi_host *msm_host)
1268{
1269 u32 data0, data1;
1270
1271 data0 = dsi_read(msm_host, REG_DSI_CTRL);
1272 data1 = data0;
1273 data1 &= ~DSI_CTRL_ENABLE;
1274 dsi_write(msm_host, REG_DSI_CTRL, data1);
1275 /*
1276 * dsi controller need to be disabled before
1277 * clocks turned on
1278 */
1279 wmb();
1280
1281 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
1282 wmb(); /* make sure clocks enabled */
1283
1284 /* dsi controller can only be reset while clocks are running */
1285 dsi_write(msm_host, REG_DSI_RESET, 1);
1286 wmb(); /* make sure reset happen */
1287 dsi_write(msm_host, REG_DSI_RESET, 0);
1288 wmb(); /* controller out of reset */
1289 dsi_write(msm_host, REG_DSI_CTRL, data0);
1290 wmb(); /* make sure dsi controller enabled again */
1291}
1292
8d23ea40
AT		 1293static void dsi_hpd_worker(struct work_struct *work)
1294{
1295 struct msm_dsi_host *msm_host =
1296 container_of(work, struct msm_dsi_host, hpd_work);
1297
1298 drm_helper_hpd_irq_event(msm_host->dev);
1299}
1300
a689554b
HL		 1301static void dsi_err_worker(struct work_struct *work)
1302{
1303 struct msm_dsi_host *msm_host =
1304 container_of(work, struct msm_dsi_host, err_work);
1305 u32 status = msm_host->err_work_state;
1306
ff431fa4 1307 pr_err_ratelimited("%s: status=%x\n", __func__, status);
a689554b
HL		 1308 if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW)
1309 dsi_sw_reset_restore(msm_host);
1310
1311 /* It is safe to clear here because error irq is disabled. */
1312 msm_host->err_work_state = 0;
1313
1314 /* enable dsi error interrupt */
1315 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1);
1316}
1317
1318static void dsi_ack_err_status(struct msm_dsi_host *msm_host)
1319{
1320 u32 status;
1321
1322 status = dsi_read(msm_host, REG_DSI_ACK_ERR_STATUS);
1323
1324 if (status) {
1325 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status);
1326 /* Writing of an extra 0 needed to clear error bits */
1327 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0);
1328 msm_host->err_work_state |= DSI_ERR_STATE_ACK;
1329 }
1330}
1331
1332static void dsi_timeout_status(struct msm_dsi_host *msm_host)
1333{
1334 u32 status;
1335
1336 status = dsi_read(msm_host, REG_DSI_TIMEOUT_STATUS);
1337
1338 if (status) {
1339 dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status);
1340 msm_host->err_work_state |= DSI_ERR_STATE_TIMEOUT;
1341 }
1342}
1343
1344static void dsi_dln0_phy_err(struct msm_dsi_host *msm_host)
1345{
1346 u32 status;
1347
1348 status = dsi_read(msm_host, REG_DSI_DLN0_PHY_ERR);
1349
01199361
AT		 1350 if (status & (DSI_DLN0_PHY_ERR_DLN0_ERR_ESC |
1351 DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC |
1352 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL |
1353 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 |
1354 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1)) {
a689554b
HL		 1355 dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status);
1356 msm_host->err_work_state |= DSI_ERR_STATE_DLN0_PHY;
1357 }
1358}
1359
1360static void dsi_fifo_status(struct msm_dsi_host *msm_host)
1361{
1362 u32 status;
1363
1364 status = dsi_read(msm_host, REG_DSI_FIFO_STATUS);
1365
1366 /* fifo underflow, overflow */
1367 if (status) {
1368 dsi_write(msm_host, REG_DSI_FIFO_STATUS, status);
1369 msm_host->err_work_state |= DSI_ERR_STATE_FIFO;
1370 if (status & DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW)
1371 msm_host->err_work_state |=
1372 DSI_ERR_STATE_MDP_FIFO_UNDERFLOW;
1373 }
1374}
1375
1376static void dsi_status(struct msm_dsi_host *msm_host)
1377{
1378 u32 status;
1379
1380 status = dsi_read(msm_host, REG_DSI_STATUS0);
1381
1382 if (status & DSI_STATUS0_INTERLEAVE_OP_CONTENTION) {
1383 dsi_write(msm_host, REG_DSI_STATUS0, status);
1384 msm_host->err_work_state |=
1385 DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION;
1386 }
1387}
1388
1389static void dsi_clk_status(struct msm_dsi_host *msm_host)
1390{
1391 u32 status;
1392
1393 status = dsi_read(msm_host, REG_DSI_CLK_STATUS);
1394
1395 if (status & DSI_CLK_STATUS_PLL_UNLOCKED) {
1396 dsi_write(msm_host, REG_DSI_CLK_STATUS, status);
1397 msm_host->err_work_state |= DSI_ERR_STATE_PLL_UNLOCKED;
1398 }
1399}
1400
1401static void dsi_error(struct msm_dsi_host *msm_host)
1402{
1403 /* disable dsi error interrupt */
1404 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 0);
1405
1406 dsi_clk_status(msm_host);
1407 dsi_fifo_status(msm_host);
1408 dsi_ack_err_status(msm_host);
1409 dsi_timeout_status(msm_host);
1410 dsi_status(msm_host);
1411 dsi_dln0_phy_err(msm_host);
1412
1413 queue_work(msm_host->workqueue, &msm_host->err_work);
1414}
1415
1416static irqreturn_t dsi_host_irq(int irq, void *ptr)
1417{
1418 struct msm_dsi_host *msm_host = ptr;
1419 u32 isr;
1420 unsigned long flags;
1421
1422 if (!msm_host->ctrl_base)
1423 return IRQ_HANDLED;
1424
1425 spin_lock_irqsave(&msm_host->intr_lock, flags);
1426 isr = dsi_read(msm_host, REG_DSI_INTR_CTRL);
1427 dsi_write(msm_host, REG_DSI_INTR_CTRL, isr);
1428 spin_unlock_irqrestore(&msm_host->intr_lock, flags);
1429
1430 DBG("isr=0x%x, id=%d", isr, msm_host->id);
1431
1432 if (isr & DSI_IRQ_ERROR)
1433 dsi_error(msm_host);
1434
1435 if (isr & DSI_IRQ_VIDEO_DONE)
1436 complete(&msm_host->video_comp);
1437
1438 if (isr & DSI_IRQ_CMD_DMA_DONE)
1439 complete(&msm_host->dma_comp);
1440
1441 return IRQ_HANDLED;
1442}
1443
1444static int dsi_host_init_panel_gpios(struct msm_dsi_host *msm_host,
1445 struct device *panel_device)
1446{
9590e69d
UKK		 1447 msm_host->disp_en_gpio = devm_gpiod_get_optional(panel_device,
1448 "disp-enable",
1449 GPIOD_OUT_LOW);
a689554b
HL		 1450 if (IS_ERR(msm_host->disp_en_gpio)) {
1451 DBG("cannot get disp-enable-gpios %ld",
1452 PTR_ERR(msm_host->disp_en_gpio));
9590e69d 1453 return PTR_ERR(msm_host->disp_en_gpio);
a689554b
HL		 1454 }
1455
60d05cb4
AT		 1456 msm_host->te_gpio = devm_gpiod_get_optional(panel_device, "disp-te",
1457 GPIOD_IN);
a689554b
HL		 1458 if (IS_ERR(msm_host->te_gpio)) {
1459 DBG("cannot get disp-te-gpios %ld", PTR_ERR(msm_host->te_gpio));
9590e69d 1460 return PTR_ERR(msm_host->te_gpio);
a689554b
HL		 1461 }
1462
1463 return 0;
1464}
1465
1466static int dsi_host_attach(struct mipi_dsi_host *host,
1467 struct mipi_dsi_device *dsi)
1468{
1469 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1470 int ret;
1471
26f7d1f4
AT		 1472 if (dsi->lanes > msm_host->num_data_lanes)
1473 return -EINVAL;
1474
a689554b
HL		 1475 msm_host->channel = dsi->channel;
1476 msm_host->lanes = dsi->lanes;
1477 msm_host->format = dsi->format;
1478 msm_host->mode_flags = dsi->mode_flags;
1479
9c9f6f8d
AT		 1480 msm_dsi_manager_attach_dsi_device(msm_host->id, dsi->mode_flags);
1481
a689554b
HL		 1482 /* Some gpios defined in panel DT need to be controlled by host */
1483 ret = dsi_host_init_panel_gpios(msm_host, &dsi->dev);
1484 if (ret)
1485 return ret;
1486
1487 DBG("id=%d", msm_host->id);
1488 if (msm_host->dev)
8d23ea40 1489 queue_work(msm_host->workqueue, &msm_host->hpd_work);
a689554b
HL		 1490
1491 return 0;
1492}
1493
1494static int dsi_host_detach(struct mipi_dsi_host *host,
1495 struct mipi_dsi_device *dsi)
1496{
1497 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1498
a9ddac9c 1499 msm_host->device_node = NULL;
a689554b
HL		 1500
1501 DBG("id=%d", msm_host->id);
1502 if (msm_host->dev)
8d23ea40 1503 queue_work(msm_host->workqueue, &msm_host->hpd_work);
a689554b
HL		 1504
1505 return 0;
1506}
1507
1508static ssize_t dsi_host_transfer(struct mipi_dsi_host *host,
1509 const struct mipi_dsi_msg *msg)
1510{
1511 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1512 int ret;
1513
1514 if (!msg || !msm_host->power_on)
1515 return -EINVAL;
1516
1517 mutex_lock(&msm_host->cmd_mutex);
1518 ret = msm_dsi_manager_cmd_xfer(msm_host->id, msg);
1519 mutex_unlock(&msm_host->cmd_mutex);
1520
1521 return ret;
1522}
1523
1524static struct mipi_dsi_host_ops dsi_host_ops = {
1525 .attach = dsi_host_attach,
1526 .detach = dsi_host_detach,
1527 .transfer = dsi_host_transfer,
1528};
1529
26f7d1f4
AT		 1530/*
1531 * List of supported physical to logical lane mappings.
1532 * For example, the 2nd entry represents the following mapping:
1533 *
1534 * "3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3;
1535 */
1536static const int supported_data_lane_swaps[][4] = {
1537 { 0, 1, 2, 3 },
1538 { 3, 0, 1, 2 },
1539 { 2, 3, 0, 1 },
1540 { 1, 2, 3, 0 },
1541 { 0, 3, 2, 1 },
1542 { 1, 0, 3, 2 },
1543 { 2, 1, 0, 3 },
1544 { 3, 2, 1, 0 },
1545};
1546
1547static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host,
1548 struct device_node *ep)
1549{
1550 struct device *dev = &msm_host->pdev->dev;
1551 struct property *prop;
1552 u32 lane_map[4];
1553 int ret, i, len, num_lanes;
1554
60282cea 1555 prop = of_find_property(ep, "data-lanes", &len);
26f7d1f4 1556 if (!prop) {
a1b1a4f7
AT		 1557 dev_dbg(dev,
1558 "failed to find data lane mapping, using default\n");
1559 return 0;
26f7d1f4
AT		 1560 }
1561
1562 num_lanes = len / sizeof(u32);
1563
1564 if (num_lanes < 1 || num_lanes > 4) {
1565 dev_err(dev, "bad number of data lanes\n");
1566 return -EINVAL;
1567 }
1568
1569 msm_host->num_data_lanes = num_lanes;
1570
60282cea 1571 ret = of_property_read_u32_array(ep, "data-lanes", lane_map,
26f7d1f4
AT		 1572 num_lanes);
1573 if (ret) {
1574 dev_err(dev, "failed to read lane data\n");
1575 return ret;
1576 }
1577
1578 /*
1579 * compare DT specified physical-logical lane mappings with the ones
1580 * supported by hardware
1581 */
1582 for (i = 0; i < ARRAY_SIZE(supported_data_lane_swaps); i++) {
1583 const int *swap = supported_data_lane_swaps[i];
1584 int j;
1585
60282cea
AT		 1586 /*
1587 * the data-lanes array we get from DT has a logical->physical
1588 * mapping. The "data lane swap" register field represents
1589 * supported configurations in a physical->logical mapping.
1590 * Translate the DT mapping to what we understand and find a
1591 * configuration that works.
1592 */
26f7d1f4 1593 for (j = 0; j < num_lanes; j++) {
60282cea
AT		 1594 if (lane_map[j] < 0 || lane_map[j] > 3)
1595 dev_err(dev, "bad physical lane entry %u\n",
1596 lane_map[j]);
1597
1598 if (swap[lane_map[j]] != j)
26f7d1f4
AT		 1599 break;
1600 }
1601
1602 if (j == num_lanes) {
1603 msm_host->dlane_swap = i;
1604 return 0;
1605 }
1606 }
1607
1608 return -EINVAL;
1609}
1610
f7009d26
AT		 1611static int dsi_host_parse_dt(struct msm_dsi_host *msm_host)
1612{
1613 struct device *dev = &msm_host->pdev->dev;
1614 struct device_node *np = dev->of_node;
a9ddac9c 1615 struct device_node *endpoint, *device_node;
a1b1a4f7 1616 int ret = 0;
f7009d26 1617
f7009d26 1618 /*
b9ac76f6
AT		 1619 * Get the endpoint of the output port of the DSI host. In our case,
1620 * this is mapped to port number with reg = 1. Don't return an error if
1621 * the remote endpoint isn't defined. It's possible that there is
1622 * nothing connected to the dsi output.
f7009d26 1623 */
b9ac76f6 1624 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1);
f7009d26
AT		 1625 if (!endpoint) {
1626 dev_dbg(dev, "%s: no endpoint\n", __func__);
1627 return 0;
1628 }
1629
26f7d1f4
AT		 1630 ret = dsi_host_parse_lane_data(msm_host, endpoint);
1631 if (ret) {
1632 dev_err(dev, "%s: invalid lane configuration %d\n",
1633 __func__, ret);
1634 goto err;
1635 }
1636
f7009d26 1637 /* Get panel node from the output port's endpoint data */
a9ddac9c
AT		 1638 device_node = of_graph_get_remote_port_parent(endpoint);
1639 if (!device_node) {
a1b1a4f7 1640 dev_dbg(dev, "%s: no valid device\n", __func__);
26f7d1f4 1641 goto err;
f7009d26
AT		 1642 }
1643
a9ddac9c 1644 msm_host->device_node = device_node;
f7009d26 1645
0c7df47f
AT		 1646 if (of_property_read_bool(np, "syscon-sfpb")) {
1647 msm_host->sfpb = syscon_regmap_lookup_by_phandle(np,
1648 "syscon-sfpb");
1649 if (IS_ERR(msm_host->sfpb)) {
1650 dev_err(dev, "%s: failed to get sfpb regmap\n",
1651 __func__);
26f7d1f4 1652 ret = PTR_ERR(msm_host->sfpb);
0c7df47f
AT		 1653 }
1654 }
1655
26f7d1f4
AT		 1656 of_node_put(device_node);
1657
1658err:
1659 of_node_put(endpoint);
1660
1661 return ret;
f7009d26
AT		 1662}
1663
32280d66
AT		 1664static int dsi_host_get_id(struct msm_dsi_host *msm_host)
1665{
1666 struct platform_device *pdev = msm_host->pdev;
1667 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg;
1668 struct resource *res;
1669 int i;
1670
1671 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dsi_ctrl");
1672 if (!res)
1673 return -EINVAL;
1674
1675 for (i = 0; i < cfg->num_dsi; i++) {
1676 if (cfg->io_start[i] == res->start)
1677 return i;
1678 }
1679
1680 return -EINVAL;
1681}
1682
a689554b
HL		 1683int msm_dsi_host_init(struct msm_dsi *msm_dsi)
1684{
1685 struct msm_dsi_host *msm_host = NULL;
1686 struct platform_device *pdev = msm_dsi->pdev;
1687 int ret;
1688
1689 msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL);
1690 if (!msm_host) {
1691 pr_err("%s: FAILED: cannot alloc dsi host\n",
1692 __func__);
1693 ret = -ENOMEM;
1694 goto fail;
1695 }
1696
f7009d26
AT		 1697 msm_host->pdev = pdev;
1698
1699 ret = dsi_host_parse_dt(msm_host);
a689554b 1700 if (ret) {
f7009d26 1701 pr_err("%s: failed to parse dt\n", __func__);
a689554b
HL		 1702 goto fail;
1703 }
a689554b 1704
a689554b
HL		 1705 msm_host->ctrl_base = msm_ioremap(pdev, "dsi_ctrl", "DSI CTRL");
1706 if (IS_ERR(msm_host->ctrl_base)) {
1707 pr_err("%s: unable to map Dsi ctrl base\n", __func__);
1708 ret = PTR_ERR(msm_host->ctrl_base);
1709 goto fail;
1710 }
1711
d248b61f
HL		 1712 msm_host->cfg_hnd = dsi_get_config(msm_host);
1713 if (!msm_host->cfg_hnd) {
a689554b
HL		 1714 ret = -EINVAL;
1715 pr_err("%s: get config failed\n", __func__);
1716 goto fail;
1717 }
1718
32280d66
AT		 1719 msm_host->id = dsi_host_get_id(msm_host);
1720 if (msm_host->id < 0) {
1721 ret = msm_host->id;
1722 pr_err("%s: unable to identify DSI host index\n", __func__);
1723 goto fail;
1724 }
1725
d248b61f
HL		 1726 /* fixup base address by io offset */
1727 msm_host->ctrl_base += msm_host->cfg_hnd->cfg->io_offset;
1728
a689554b
HL		 1729 ret = dsi_regulator_init(msm_host);
1730 if (ret) {
1731 pr_err("%s: regulator init failed\n", __func__);
1732 goto fail;
1733 }
1734
31c92767
AT		 1735 ret = dsi_clk_init(msm_host);
1736 if (ret) {
1737 pr_err("%s: unable to initialize dsi clks\n", __func__);
1738 goto fail;
1739 }
1740
a689554b
HL		 1741 msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL);
1742 if (!msm_host->rx_buf) {
1743 pr_err("%s: alloc rx temp buf failed\n", __func__);
1744 goto fail;
1745 }
1746
1747 init_completion(&msm_host->dma_comp);
1748 init_completion(&msm_host->video_comp);
1749 mutex_init(&msm_host->dev_mutex);
1750 mutex_init(&msm_host->cmd_mutex);
1751 mutex_init(&msm_host->clk_mutex);
1752 spin_lock_init(&msm_host->intr_lock);
1753
1754 /* setup workqueue */
1755 msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0);
1756 INIT_WORK(&msm_host->err_work, dsi_err_worker);
8d23ea40 1757 INIT_WORK(&msm_host->hpd_work, dsi_hpd_worker);
a689554b 1758
a689554b
HL		 1759 msm_dsi->host = &msm_host->base;
1760 msm_dsi->id = msm_host->id;
1761
1762 DBG("Dsi Host %d initialized", msm_host->id);
1763 return 0;
1764
1765fail:
1766 return ret;
1767}
1768
1769void msm_dsi_host_destroy(struct mipi_dsi_host *host)
1770{
1771 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1772
1773 DBG("");
1774 dsi_tx_buf_free(msm_host);
1775 if (msm_host->workqueue) {
1776 flush_workqueue(msm_host->workqueue);
1777 destroy_workqueue(msm_host->workqueue);
1778 msm_host->workqueue = NULL;
1779 }
1780
1781 mutex_destroy(&msm_host->clk_mutex);
1782 mutex_destroy(&msm_host->cmd_mutex);
1783 mutex_destroy(&msm_host->dev_mutex);
1784}
1785
1786int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
1787 struct drm_device *dev)
1788{
1789 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1790 struct platform_device *pdev = msm_host->pdev;
1791 int ret;
1792
1793 msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1794 if (msm_host->irq < 0) {
1795 ret = msm_host->irq;
1796 dev_err(dev->dev, "failed to get irq: %d\n", ret);
1797 return ret;
1798 }
1799
1800 ret = devm_request_irq(&pdev->dev, msm_host->irq,
1801 dsi_host_irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
1802 "dsi_isr", msm_host);
1803 if (ret < 0) {
1804 dev_err(&pdev->dev, "failed to request IRQ%u: %d\n",
1805 msm_host->irq, ret);
1806 return ret;
1807 }
1808
1809 msm_host->dev = dev;
1810 ret = dsi_tx_buf_alloc(msm_host, SZ_4K);
1811 if (ret) {
1812 pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret);
1813 return ret;
1814 }
1815
1816 return 0;
1817}
1818
1819int msm_dsi_host_register(struct mipi_dsi_host *host, bool check_defer)
1820{
1821 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
a689554b
HL		 1822 int ret;
1823
1824 /* Register mipi dsi host */
1825 if (!msm_host->registered) {
1826 host->dev = &msm_host->pdev->dev;
1827 host->ops = &dsi_host_ops;
1828 ret = mipi_dsi_host_register(host);
1829 if (ret)
1830 return ret;
1831
1832 msm_host->registered = true;
1833
1834 /* If the panel driver has not been probed after host register,
1835 * we should defer the host's probe.
1836 * It makes sure panel is connected when fbcon detects
1837 * connector status and gets the proper display mode to
1838 * create framebuffer.
f7009d26
AT		 1839 * Don't try to defer if there is nothing connected to the dsi
1840 * output
a689554b 1841 */
a9ddac9c
AT		 1842 if (check_defer && msm_host->device_node) {
1843 if (!of_drm_find_panel(msm_host->device_node))
c118e290
AT		 1844 if (!of_drm_find_bridge(msm_host->device_node))
1845 return -EPROBE_DEFER;
a689554b
HL		 1846 }
1847 }
1848
1849 return 0;
1850}
1851
1852void msm_dsi_host_unregister(struct mipi_dsi_host *host)
1853{
1854 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1855
1856 if (msm_host->registered) {
1857 mipi_dsi_host_unregister(host);
1858 host->dev = NULL;
1859 host->ops = NULL;
1860 msm_host->registered = false;
1861 }
1862}
1863
1864int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host,
1865 const struct mipi_dsi_msg *msg)
1866{
1867 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1868
1869 /* TODO: make sure dsi_cmd_mdp is idle.
1870 * Since DSI6G v1.2.0, we can set DSI_TRIG_CTRL.BLOCK_DMA_WITHIN_FRAME
1871 * to ask H/W to wait until cmd mdp is idle. S/W wait is not needed.
1872 * How to handle the old versions? Wait for mdp cmd done?
1873 */
1874
1875 /*
1876 * mdss interrupt is generated in mdp core clock domain
1877 * mdp clock need to be enabled to receive dsi interrupt
1878 */
1879 dsi_clk_ctrl(msm_host, 1);
1880
1881 /* TODO: vote for bus bandwidth */
1882
1883 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM))
1884 dsi_set_tx_power_mode(0, msm_host);
1885
1886 msm_host->dma_cmd_ctrl_restore = dsi_read(msm_host, REG_DSI_CTRL);
1887 dsi_write(msm_host, REG_DSI_CTRL,
1888 msm_host->dma_cmd_ctrl_restore |
1889 DSI_CTRL_CMD_MODE_EN |
1890 DSI_CTRL_ENABLE);
1891 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 1);
1892
1893 return 0;
1894}
1895
1896void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host,
1897 const struct mipi_dsi_msg *msg)
1898{
1899 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1900
1901 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 0);
1902 dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore);
1903
1904 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM))
1905 dsi_set_tx_power_mode(1, msm_host);
1906
1907 /* TODO: unvote for bus bandwidth */
1908
1909 dsi_clk_ctrl(msm_host, 0);
1910}
1911
1912int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host,
1913 const struct mipi_dsi_msg *msg)
1914{
1915 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1916
1917 return dsi_cmds2buf_tx(msm_host, msg);
1918}
1919
1920int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host,
1921 const struct mipi_dsi_msg *msg)
1922{
1923 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
d248b61f 1924 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
a689554b
HL		 1925 int data_byte, rx_byte, dlen, end;
1926 int short_response, diff, pkt_size, ret = 0;
1927 char cmd;
1928 int rlen = msg->rx_len;
1929 u8 *buf;
1930
1931 if (rlen <= 2) {
1932 short_response = 1;
1933 pkt_size = rlen;
1934 rx_byte = 4;
1935 } else {
1936 short_response = 0;
1937 data_byte = 10; /* first read */
1938 if (rlen < data_byte)
1939 pkt_size = rlen;
1940 else
1941 pkt_size = data_byte;
1942 rx_byte = data_byte + 6; /* 4 header + 2 crc */
1943 }
1944
1945 buf = msm_host->rx_buf;
1946 end = 0;
1947 while (!end) {
1948 u8 tx[2] = {pkt_size & 0xff, pkt_size >> 8};
1949 struct mipi_dsi_msg max_pkt_size_msg = {
1950 .channel = msg->channel,
1951 .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE,
1952 .tx_len = 2,
1953 .tx_buf = tx,
1954 };
1955
1956 DBG("rlen=%d pkt_size=%d rx_byte=%d",
1957 rlen, pkt_size, rx_byte);
1958
1959 ret = dsi_cmds2buf_tx(msm_host, &max_pkt_size_msg);
1960 if (ret < 2) {
1961 pr_err("%s: Set max pkt size failed, %d\n",
1962 __func__, ret);
1963 return -EINVAL;
1964 }
1965
d248b61f
HL		 1966 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
1967 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_1)) {
a689554b
HL		 1968 /* Clear the RDBK_DATA registers */
1969 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL,
1970 DSI_RDBK_DATA_CTRL_CLR);
1971 wmb(); /* make sure the RDBK registers are cleared */
1972 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0);
1973 wmb(); /* release cleared status before transfer */
1974 }
1975
1976 ret = dsi_cmds2buf_tx(msm_host, msg);
1977 if (ret < msg->tx_len) {
1978 pr_err("%s: Read cmd Tx failed, %d\n", __func__, ret);
1979 return ret;
1980 }
1981
1982 /*
1983 * once cmd_dma_done interrupt received,
1984 * return data from client is ready and stored
1985 * at RDBK_DATA register already
1986 * since rx fifo is 16 bytes, dcs header is kept at first loop,
1987 * after that dcs header lost during shift into registers
1988 */
1989 dlen = dsi_cmd_dma_rx(msm_host, buf, rx_byte, pkt_size);
1990
1991 if (dlen <= 0)
1992 return 0;
1993
1994 if (short_response)
1995 break;
1996
1997 if (rlen <= data_byte) {
1998 diff = data_byte - rlen;
1999 end = 1;
2000 } else {
2001 diff = 0;
2002 rlen -= data_byte;
2003 }
2004
2005 if (!end) {
2006 dlen -= 2; /* 2 crc */
2007 dlen -= diff;
2008 buf += dlen; /* next start position */
2009 data_byte = 14; /* NOT first read */
2010 if (rlen < data_byte)
2011 pkt_size += rlen;
2012 else
2013 pkt_size += data_byte;
2014 DBG("buf=%p dlen=%d diff=%d", buf, dlen, diff);
2015 }
2016 }
2017
2018 /*
2019 * For single Long read, if the requested rlen < 10,
2020 * we need to shift the start position of rx
2021 * data buffer to skip the bytes which are not
2022 * updated.
2023 */
2024 if (pkt_size < 10 && !short_response)
2025 buf = msm_host->rx_buf + (10 - rlen);
2026 else
2027 buf = msm_host->rx_buf;
2028
2029 cmd = buf[0];
2030 switch (cmd) {
2031 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
2032 pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__);
2033 ret = 0;
651ad3f5 2034 break;
a689554b
HL		 2035 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
2036 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
2037 ret = dsi_short_read1_resp(buf, msg);
2038 break;
2039 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
2040 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
2041 ret = dsi_short_read2_resp(buf, msg);
2042 break;
2043 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
2044 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
2045 ret = dsi_long_read_resp(buf, msg);
2046 break;
2047 default:
2048 pr_warn("%s:Invalid response cmd\n", __func__);
2049 ret = 0;
2050 }
2051
2052 return ret;
2053}
2054
4ff9d4cb
AT		 2055void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base,
2056 u32 len)
a689554b
HL		 2057{
2058 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2059
4ff9d4cb 2060 dsi_write(msm_host, REG_DSI_DMA_BASE, dma_base);
a689554b
HL		 2061 dsi_write(msm_host, REG_DSI_DMA_LEN, len);
2062 dsi_write(msm_host, REG_DSI_TRIG_DMA, 1);
2063
2064 /* Make sure trigger happens */
2065 wmb();
2066}
2067
9d32c498
HL		 2068int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host,
2069 struct msm_dsi_pll *src_pll)
2070{
2071 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
4bfa9748 2072 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
9d32c498
HL		 2073 struct clk *byte_clk_provider, *pixel_clk_provider;
2074 int ret;
2075
2076 ret = msm_dsi_pll_get_clk_provider(src_pll,
2077 &byte_clk_provider, &pixel_clk_provider);
2078 if (ret) {
2079 pr_info("%s: can't get provider from pll, don't set parent\n",
2080 __func__);
2081 return 0;
2082 }
2083
2084 ret = clk_set_parent(msm_host->byte_clk_src, byte_clk_provider);
2085 if (ret) {
2086 pr_err("%s: can't set parent to byte_clk_src. ret=%d\n",
2087 __func__, ret);
2088 goto exit;
2089 }
2090
2091 ret = clk_set_parent(msm_host->pixel_clk_src, pixel_clk_provider);
2092 if (ret) {
2093 pr_err("%s: can't set parent to pixel_clk_src. ret=%d\n",
2094 __func__, ret);
2095 goto exit;
2096 }
2097
4bfa9748
AT		 2098 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_V2) {
2099 ret = clk_set_parent(msm_host->dsi_clk_src, pixel_clk_provider);
2100 if (ret) {
2101 pr_err("%s: can't set parent to dsi_clk_src. ret=%d\n",
2102 __func__, ret);
2103 goto exit;
2104 }
2105
2106 ret = clk_set_parent(msm_host->esc_clk_src, byte_clk_provider);
2107 if (ret) {
2108 pr_err("%s: can't set parent to esc_clk_src. ret=%d\n",
2109 __func__, ret);
2110 goto exit;
2111 }
2112 }
2113
9d32c498
HL		 2114exit:
2115 return ret;
2116}
2117
34d9545b
AT		 2118void msm_dsi_host_reset_phy(struct mipi_dsi_host *host)
2119{
2120 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2121
2122 DBG("");
2123 dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET);
2124 /* Make sure fully reset */
2125 wmb();
2126 udelay(1000);
2127 dsi_write(msm_host, REG_DSI_PHY_RESET, 0);
2128 udelay(100);
2129}
2130
b62aa70a
HL		 2131void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host,
2132 struct msm_dsi_phy_clk_request *clk_req)
2133{
2134 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2135
2136 clk_req->bitclk_rate = msm_host->byte_clk_rate * 8;
2137 clk_req->escclk_rate = msm_host->esc_clk_rate;
2138}
2139
a689554b
HL		 2140int msm_dsi_host_enable(struct mipi_dsi_host *host)
2141{
2142 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2143
2144 dsi_op_mode_config(msm_host,
2145 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), true);
2146
2147 /* TODO: clock should be turned off for command mode,
2148 * and only turned on before MDP START.
2149 * This part of code should be enabled once mdp driver support it.
2150 */
2151 /* if (msm_panel->mode == MSM_DSI_CMD_MODE)
2152 dsi_clk_ctrl(msm_host, 0); */
2153
2154 return 0;
2155}
2156
2157int msm_dsi_host_disable(struct mipi_dsi_host *host)
2158{
2159 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2160
2161 dsi_op_mode_config(msm_host,
2162 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), false);
2163
2164 /* Since we have disabled INTF, the video engine won't stop so that
2165 * the cmd engine will be blocked.
2166 * Reset to disable video engine so that we can send off cmd.
2167 */
2168 dsi_sw_reset(msm_host);
2169
2170 return 0;
2171}
2172
0c7df47f
AT		 2173static void msm_dsi_sfpb_config(struct msm_dsi_host *msm_host, bool enable)
2174{
2175 enum sfpb_ahb_arb_master_port_en en;
2176
2177 if (!msm_host->sfpb)
2178 return;
2179
2180 en = enable ? SFPB_MASTER_PORT_ENABLE : SFPB_MASTER_PORT_DISABLE;
2181
2182 regmap_update_bits(msm_host->sfpb, REG_SFPB_GPREG,
2183 SFPB_GPREG_MASTER_PORT_EN__MASK,
2184 SFPB_GPREG_MASTER_PORT_EN(en));
2185}
2186
b62aa70a
HL		 2187int msm_dsi_host_power_on(struct mipi_dsi_host *host,
2188 struct msm_dsi_phy_shared_timings *phy_shared_timings)
a689554b
HL		 2189{
2190 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
a689554b
HL		 2191 int ret = 0;
2192
2193 mutex_lock(&msm_host->dev_mutex);
2194 if (msm_host->power_on) {
2195 DBG("dsi host already on");
2196 goto unlock_ret;
2197 }
2198
0c7df47f
AT		 2199 msm_dsi_sfpb_config(msm_host, true);
2200
a689554b
HL		 2201 ret = dsi_host_regulator_enable(msm_host);
2202 if (ret) {
2203 pr_err("%s:Failed to enable vregs.ret=%d\n",
2204 __func__, ret);
2205 goto unlock_ret;
2206 }
2207
a689554b
HL		 2208 ret = dsi_clk_ctrl(msm_host, 1);
2209 if (ret) {
2210 pr_err("%s: failed to enable clocks. ret=%d\n", __func__, ret);
2211 goto fail_disable_reg;
2212 }
2213
ab8909b0
HL		 2214 ret = pinctrl_pm_select_default_state(&msm_host->pdev->dev);
2215 if (ret) {
2216 pr_err("%s: failed to set pinctrl default state, %d\n",
2217 __func__, ret);
2218 goto fail_disable_clk;
2219 }
2220
a689554b
HL		 2221 dsi_timing_setup(msm_host);
2222 dsi_sw_reset(msm_host);
b62aa70a 2223 dsi_ctrl_config(msm_host, true, phy_shared_timings);
a689554b
HL		 2224
2225 if (msm_host->disp_en_gpio)
2226 gpiod_set_value(msm_host->disp_en_gpio, 1);
2227
2228 msm_host->power_on = true;
2229 mutex_unlock(&msm_host->dev_mutex);
2230
2231 return 0;
2232
ab8909b0
HL		 2233fail_disable_clk:
2234 dsi_clk_ctrl(msm_host, 0);
a689554b
HL		 2235fail_disable_reg:
2236 dsi_host_regulator_disable(msm_host);
2237unlock_ret:
2238 mutex_unlock(&msm_host->dev_mutex);
2239 return ret;
2240}
2241
2242int msm_dsi_host_power_off(struct mipi_dsi_host *host)
2243{
2244 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2245
2246 mutex_lock(&msm_host->dev_mutex);
2247 if (!msm_host->power_on) {
2248 DBG("dsi host already off");
2249 goto unlock_ret;
2250 }
2251
dceac340 2252 dsi_ctrl_config(msm_host, false, NULL);
a689554b
HL		 2253
2254 if (msm_host->disp_en_gpio)
2255 gpiod_set_value(msm_host->disp_en_gpio, 0);
2256
ab8909b0
HL		 2257 pinctrl_pm_select_sleep_state(&msm_host->pdev->dev);
2258
a689554b
HL		 2259 dsi_clk_ctrl(msm_host, 0);
2260
2261 dsi_host_regulator_disable(msm_host);
2262
0c7df47f
AT		 2263 msm_dsi_sfpb_config(msm_host, false);
2264
a689554b
HL		 2265 DBG("-");
2266
2267 msm_host->power_on = false;
2268
2269unlock_ret:
2270 mutex_unlock(&msm_host->dev_mutex);
2271 return 0;
2272}
2273
2274int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host,
2275 struct drm_display_mode *mode)
2276{
2277 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
b62aa70a 2278 int ret;
a689554b
HL		 2279
2280 if (msm_host->mode) {
2281 drm_mode_destroy(msm_host->dev, msm_host->mode);
2282 msm_host->mode = NULL;
2283 }
2284
2285 msm_host->mode = drm_mode_duplicate(msm_host->dev, mode);
2abe1f25 2286 if (!msm_host->mode) {
a689554b 2287 pr_err("%s: cannot duplicate mode\n", __func__);
2abe1f25 2288 return -ENOMEM;
a689554b
HL		 2289 }
2290
b62aa70a
HL		 2291 ret = dsi_calc_clk_rate(msm_host);
2292 if (ret) {
2293 pr_err("%s: unable to calc clk rate, %d\n", __func__, ret);
2294 return ret;
2295 }
2296
a689554b
HL		 2297 return 0;
2298}
2299
2300struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host,
2301 unsigned long *panel_flags)
2302{
2303 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2304 struct drm_panel *panel;
2305
a9ddac9c 2306 panel = of_drm_find_panel(msm_host->device_node);
a689554b
HL		 2307 if (panel_flags)
2308 *panel_flags = msm_host->mode_flags;
2309
2310 return panel;
2311}
2312
c118e290
AT		 2313struct drm_bridge *msm_dsi_host_get_bridge(struct mipi_dsi_host *host)
2314{
2315 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2316
2317 return of_drm_find_bridge(msm_host->device_node);
2318}
Linux 6.x block layer and io_uring tree(s)