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drm/msm: Set different display size limitation on each target
[linux-2.6-block.git] / drivers / gpu / drm / msm / dsi / dsi_host.c
CommitLineData
a689554b
HL		 1/*
2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/clk.h>
15#include <linux/delay.h>
16#include <linux/err.h>
17#include <linux/gpio.h>
964a0754 18#include <linux/gpio/consumer.h>
a689554b
HL		 19#include <linux/interrupt.h>
20#include <linux/of_device.h>
21#include <linux/of_gpio.h>
22#include <linux/of_irq.h>
ab8909b0 23#include <linux/pinctrl/consumer.h>
a689554b
HL		 24#include <linux/regulator/consumer.h>
25#include <linux/spinlock.h>
26#include <video/mipi_display.h>
27
28#include "dsi.h"
29#include "dsi.xml.h"
30
31#define MSM_DSI_VER_MAJOR_V2 0x02
32#define MSM_DSI_VER_MAJOR_6G 0x03
33#define MSM_DSI_6G_VER_MINOR_V1_0 0x10000000
34#define MSM_DSI_6G_VER_MINOR_V1_1 0x10010000
35#define MSM_DSI_6G_VER_MINOR_V1_1_1 0x10010001
36#define MSM_DSI_6G_VER_MINOR_V1_2 0x10020000
dcefc117 37#define MSM_DSI_6G_VER_MINOR_V1_3 0x10030000
a689554b
HL		 38#define MSM_DSI_6G_VER_MINOR_V1_3_1 0x10030001
39
40#define DSI_6G_REG_SHIFT 4
41
a689554b
HL		 42struct dsi_config {
43 u32 major;
44 u32 minor;
45 u32 io_offset;
a689554b
HL		 46 struct dsi_reg_config reg_cfg;
47};
48
49static const struct dsi_config dsi_cfgs[] = {
ec31abf6 50 {MSM_DSI_VER_MAJOR_V2, 0, 0, {0,} },
a689554b
HL		 51 { /* 8974 v1 */
52 .major = MSM_DSI_VER_MAJOR_6G,
53 .minor = MSM_DSI_6G_VER_MINOR_V1_0,
54 .io_offset = DSI_6G_REG_SHIFT,
a689554b
HL		 55 .reg_cfg = {
56 .num = 4,
57 .regs = {
58 {"gdsc", -1, -1, -1, -1},
59 {"vdd", 3000000, 3000000, 150000, 100},
60 {"vdda", 1200000, 1200000, 100000, 100},
61 {"vddio", 1800000, 1800000, 100000, 100},
62 },
63 },
64 },
65 { /* 8974 v2 */
66 .major = MSM_DSI_VER_MAJOR_6G,
67 .minor = MSM_DSI_6G_VER_MINOR_V1_1,
68 .io_offset = DSI_6G_REG_SHIFT,
a689554b
HL		 69 .reg_cfg = {
70 .num = 4,
71 .regs = {
72 {"gdsc", -1, -1, -1, -1},
73 {"vdd", 3000000, 3000000, 150000, 100},
74 {"vdda", 1200000, 1200000, 100000, 100},
75 {"vddio", 1800000, 1800000, 100000, 100},
76 },
77 },
78 },
79 { /* 8974 v3 */
80 .major = MSM_DSI_VER_MAJOR_6G,
81 .minor = MSM_DSI_6G_VER_MINOR_V1_1_1,
82 .io_offset = DSI_6G_REG_SHIFT,
a689554b
HL		 83 .reg_cfg = {
84 .num = 4,
85 .regs = {
86 {"gdsc", -1, -1, -1, -1},
87 {"vdd", 3000000, 3000000, 150000, 100},
88 {"vdda", 1200000, 1200000, 100000, 100},
89 {"vddio", 1800000, 1800000, 100000, 100},
90 },
91 },
92 },
93 { /* 8084 */
94 .major = MSM_DSI_VER_MAJOR_6G,
95 .minor = MSM_DSI_6G_VER_MINOR_V1_2,
96 .io_offset = DSI_6G_REG_SHIFT,
a689554b
HL		 97 .reg_cfg = {
98 .num = 4,
99 .regs = {
100 {"gdsc", -1, -1, -1, -1},
101 {"vdd", 3000000, 3000000, 150000, 100},
102 {"vdda", 1200000, 1200000, 100000, 100},
103 {"vddio", 1800000, 1800000, 100000, 100},
104 },
105 },
106 },
107 { /* 8916 */
108 .major = MSM_DSI_VER_MAJOR_6G,
109 .minor = MSM_DSI_6G_VER_MINOR_V1_3_1,
110 .io_offset = DSI_6G_REG_SHIFT,
a689554b
HL		 111 .reg_cfg = {
112 .num = 4,
113 .regs = {
114 {"gdsc", -1, -1, -1, -1},
115 {"vdd", 2850000, 2850000, 100000, 100},
116 {"vdda", 1200000, 1200000, 100000, 100},
117 {"vddio", 1800000, 1800000, 100000, 100},
118 },
119 },
120 },
dcefc117
HL		 121 { /* 8x94 */
122 .major = MSM_DSI_VER_MAJOR_6G,
123 .minor = MSM_DSI_6G_VER_MINOR_V1_3,
124 .io_offset = DSI_6G_REG_SHIFT,
125 .reg_cfg = {
126 .num = 7,
127 .regs = {
128 {"gdsc", -1, -1, -1, -1},
129 {"vdda", 1250000, 1250000, 100000, 100},
130 {"vddio", 1800000, 1800000, 100000, 100},
131 {"vcca", 1000000, 1000000, 10000, 100},
132 {"vdd", 1800000, 1800000, 100000, 100},
133 {"lab_reg", -1, -1, -1, -1},
134 {"ibb_reg", -1, -1, -1, -1},
135 },
136 }
137 },
a689554b
HL		 138};
139
140static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor)
141{
142 u32 ver;
143 u32 ver_6g;
144
145 if (!major || !minor)
146 return -EINVAL;
147
148 /* From DSI6G(v3), addition of a 6G_HW_VERSION register at offset 0
149 * makes all other registers 4-byte shifted down.
150 */
151 ver_6g = msm_readl(base + REG_DSI_6G_HW_VERSION);
152 if (ver_6g == 0) {
153 ver = msm_readl(base + REG_DSI_VERSION);
154 ver = FIELD(ver, DSI_VERSION_MAJOR);
155 if (ver <= MSM_DSI_VER_MAJOR_V2) {
156 /* old versions */
157 *major = ver;
158 *minor = 0;
159 return 0;
160 } else {
161 return -EINVAL;
162 }
163 } else {
164 ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION);
165 ver = FIELD(ver, DSI_VERSION_MAJOR);
166 if (ver == MSM_DSI_VER_MAJOR_6G) {
167 /* 6G version */
168 *major = ver;
169 *minor = ver_6g;
170 return 0;
171 } else {
172 return -EINVAL;
173 }
174 }
175}
176
177#define DSI_ERR_STATE_ACK 0x0000
178#define DSI_ERR_STATE_TIMEOUT 0x0001
179#define DSI_ERR_STATE_DLN0_PHY 0x0002
180#define DSI_ERR_STATE_FIFO 0x0004
181#define DSI_ERR_STATE_MDP_FIFO_UNDERFLOW 0x0008
182#define DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION 0x0010
183#define DSI_ERR_STATE_PLL_UNLOCKED 0x0020
184
185#define DSI_CLK_CTRL_ENABLE_CLKS \
186 (DSI_CLK_CTRL_AHBS_HCLK_ON | DSI_CLK_CTRL_AHBM_SCLK_ON | \
187 DSI_CLK_CTRL_PCLK_ON | DSI_CLK_CTRL_DSICLK_ON | \
188 DSI_CLK_CTRL_BYTECLK_ON | DSI_CLK_CTRL_ESCCLK_ON | \
189 DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK)
190
191struct msm_dsi_host {
192 struct mipi_dsi_host base;
193
194 struct platform_device *pdev;
195 struct drm_device *dev;
196
197 int id;
198
199 void __iomem *ctrl_base;
ec31abf6 200 struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX];
a689554b
HL		 201 struct clk *mdp_core_clk;
202 struct clk *ahb_clk;
203 struct clk *axi_clk;
204 struct clk *mmss_misc_ahb_clk;
205 struct clk *byte_clk;
206 struct clk *esc_clk;
207 struct clk *pixel_clk;
9d32c498
HL		 208 struct clk *byte_clk_src;
209 struct clk *pixel_clk_src;
210
a689554b
HL		 211 u32 byte_clk_rate;
212
213 struct gpio_desc *disp_en_gpio;
214 struct gpio_desc *te_gpio;
215
216 const struct dsi_config *cfg;
217
218 struct completion dma_comp;
219 struct completion video_comp;
220 struct mutex dev_mutex;
221 struct mutex cmd_mutex;
222 struct mutex clk_mutex;
223 spinlock_t intr_lock; /* Protect interrupt ctrl register */
224
225 u32 err_work_state;
226 struct work_struct err_work;
227 struct workqueue_struct *workqueue;
228
229 struct drm_gem_object *tx_gem_obj;
230 u8 *rx_buf;
231
232 struct drm_display_mode *mode;
233
234 /* Panel info */
235 struct device_node *panel_node;
236 unsigned int channel;
237 unsigned int lanes;
238 enum mipi_dsi_pixel_format format;
239 unsigned long mode_flags;
240
241 u32 dma_cmd_ctrl_restore;
242
243 bool registered;
244 bool power_on;
245 int irq;
246};
247
248static u32 dsi_get_bpp(const enum mipi_dsi_pixel_format fmt)
249{
250 switch (fmt) {
251 case MIPI_DSI_FMT_RGB565: return 16;
252 case MIPI_DSI_FMT_RGB666_PACKED: return 18;
253 case MIPI_DSI_FMT_RGB666:
254 case MIPI_DSI_FMT_RGB888:
255 default: return 24;
256 }
257}
258
259static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg)
260{
261 return msm_readl(msm_host->ctrl_base + msm_host->cfg->io_offset + reg);
262}
263static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data)
264{
265 msm_writel(data, msm_host->ctrl_base + msm_host->cfg->io_offset + reg);
266}
267
268static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host);
269static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host);
270
271static const struct dsi_config *dsi_get_config(struct msm_dsi_host *msm_host)
272{
273 const struct dsi_config *cfg;
274 struct regulator *gdsc_reg;
275 int i, ret;
276 u32 major = 0, minor = 0;
277
278 gdsc_reg = regulator_get(&msm_host->pdev->dev, "gdsc");
bdc80de2 279 if (IS_ERR(gdsc_reg)) {
a689554b
HL		 280 pr_err("%s: cannot get gdsc\n", __func__);
281 goto fail;
282 }
283 ret = regulator_enable(gdsc_reg);
284 if (ret) {
285 pr_err("%s: unable to enable gdsc\n", __func__);
286 regulator_put(gdsc_reg);
287 goto fail;
288 }
289 ret = clk_prepare_enable(msm_host->ahb_clk);
290 if (ret) {
291 pr_err("%s: unable to enable ahb_clk\n", __func__);
292 regulator_disable(gdsc_reg);
293 regulator_put(gdsc_reg);
294 goto fail;
295 }
296
297 ret = dsi_get_version(msm_host->ctrl_base, &major, &minor);
298
299 clk_disable_unprepare(msm_host->ahb_clk);
300 regulator_disable(gdsc_reg);
301 regulator_put(gdsc_reg);
302 if (ret) {
303 pr_err("%s: Invalid version\n", __func__);
304 goto fail;
305 }
306
307 for (i = 0; i < ARRAY_SIZE(dsi_cfgs); i++) {
308 cfg = dsi_cfgs + i;
309 if ((cfg->major == major) && (cfg->minor == minor))
310 return cfg;
311 }
312 pr_err("%s: Version %x:%x not support\n", __func__, major, minor);
313
314fail:
315 return NULL;
316}
317
318static inline struct msm_dsi_host *to_msm_dsi_host(struct mipi_dsi_host *host)
319{
320 return container_of(host, struct msm_dsi_host, base);
321}
322
323static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host)
324{
325 struct regulator_bulk_data *s = msm_host->supplies;
326 const struct dsi_reg_entry *regs = msm_host->cfg->reg_cfg.regs;
327 int num = msm_host->cfg->reg_cfg.num;
328 int i;
329
330 DBG("");
331 for (i = num - 1; i >= 0; i--)
332 if (regs[i].disable_load >= 0)
2c33ce00
DA		 333 regulator_set_load(s[i].consumer,
334 regs[i].disable_load);
a689554b
HL		 335
336 regulator_bulk_disable(num, s);
337}
338
339static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host)
340{
341 struct regulator_bulk_data *s = msm_host->supplies;
342 const struct dsi_reg_entry *regs = msm_host->cfg->reg_cfg.regs;
343 int num = msm_host->cfg->reg_cfg.num;
344 int ret, i;
345
346 DBG("");
347 for (i = 0; i < num; i++) {
348 if (regs[i].enable_load >= 0) {
2c33ce00
DA		 349 ret = regulator_set_load(s[i].consumer,
350 regs[i].enable_load);
a689554b
HL		 351 if (ret < 0) {
352 pr_err("regulator %d set op mode failed, %d\n",
353 i, ret);
354 goto fail;
355 }
356 }
357 }
358
359 ret = regulator_bulk_enable(num, s);
360 if (ret < 0) {
361 pr_err("regulator enable failed, %d\n", ret);
362 goto fail;
363 }
364
365 return 0;
366
367fail:
368 for (i--; i >= 0; i--)
2c33ce00 369 regulator_set_load(s[i].consumer, regs[i].disable_load);
a689554b
HL		 370 return ret;
371}
372
373static int dsi_regulator_init(struct msm_dsi_host *msm_host)
374{
375 struct regulator_bulk_data *s = msm_host->supplies;
376 const struct dsi_reg_entry *regs = msm_host->cfg->reg_cfg.regs;
377 int num = msm_host->cfg->reg_cfg.num;
378 int i, ret;
379
380 for (i = 0; i < num; i++)
381 s[i].supply = regs[i].name;
382
383 ret = devm_regulator_bulk_get(&msm_host->pdev->dev, num, s);
384 if (ret < 0) {
385 pr_err("%s: failed to init regulator, ret=%d\n",
386 __func__, ret);
387 return ret;
388 }
389
390 for (i = 0; i < num; i++) {
391 if ((regs[i].min_voltage >= 0) && (regs[i].max_voltage >= 0)) {
392 ret = regulator_set_voltage(s[i].consumer,
393 regs[i].min_voltage, regs[i].max_voltage);
394 if (ret < 0) {
395 pr_err("regulator %d set voltage failed, %d\n",
396 i, ret);
397 return ret;
398 }
399 }
400 }
401
402 return 0;
403}
404
405static int dsi_clk_init(struct msm_dsi_host *msm_host)
406{
407 struct device *dev = &msm_host->pdev->dev;
408 int ret = 0;
409
410 msm_host->mdp_core_clk = devm_clk_get(dev, "mdp_core_clk");
411 if (IS_ERR(msm_host->mdp_core_clk)) {
412 ret = PTR_ERR(msm_host->mdp_core_clk);
413 pr_err("%s: Unable to get mdp core clk. ret=%d\n",
414 __func__, ret);
415 goto exit;
416 }
417
418 msm_host->ahb_clk = devm_clk_get(dev, "iface_clk");
419 if (IS_ERR(msm_host->ahb_clk)) {
420 ret = PTR_ERR(msm_host->ahb_clk);
421 pr_err("%s: Unable to get mdss ahb clk. ret=%d\n",
422 __func__, ret);
423 goto exit;
424 }
425
426 msm_host->axi_clk = devm_clk_get(dev, "bus_clk");
427 if (IS_ERR(msm_host->axi_clk)) {
428 ret = PTR_ERR(msm_host->axi_clk);
429 pr_err("%s: Unable to get axi bus clk. ret=%d\n",
430 __func__, ret);
431 goto exit;
432 }
433
434 msm_host->mmss_misc_ahb_clk = devm_clk_get(dev, "core_mmss_clk");
435 if (IS_ERR(msm_host->mmss_misc_ahb_clk)) {
436 ret = PTR_ERR(msm_host->mmss_misc_ahb_clk);
437 pr_err("%s: Unable to get mmss misc ahb clk. ret=%d\n",
438 __func__, ret);
439 goto exit;
440 }
441
442 msm_host->byte_clk = devm_clk_get(dev, "byte_clk");
443 if (IS_ERR(msm_host->byte_clk)) {
444 ret = PTR_ERR(msm_host->byte_clk);
445 pr_err("%s: can't find dsi_byte_clk. ret=%d\n",
446 __func__, ret);
447 msm_host->byte_clk = NULL;
448 goto exit;
449 }
450
451 msm_host->pixel_clk = devm_clk_get(dev, "pixel_clk");
452 if (IS_ERR(msm_host->pixel_clk)) {
453 ret = PTR_ERR(msm_host->pixel_clk);
454 pr_err("%s: can't find dsi_pixel_clk. ret=%d\n",
455 __func__, ret);
456 msm_host->pixel_clk = NULL;
457 goto exit;
458 }
459
460 msm_host->esc_clk = devm_clk_get(dev, "core_clk");
461 if (IS_ERR(msm_host->esc_clk)) {
462 ret = PTR_ERR(msm_host->esc_clk);
463 pr_err("%s: can't find dsi_esc_clk. ret=%d\n",
464 __func__, ret);
465 msm_host->esc_clk = NULL;
466 goto exit;
467 }
468
9d32c498
HL		 469 msm_host->byte_clk_src = devm_clk_get(dev, "byte_clk_src");
470 if (IS_ERR(msm_host->byte_clk_src)) {
471 ret = PTR_ERR(msm_host->byte_clk_src);
472 pr_err("%s: can't find byte_clk_src. ret=%d\n", __func__, ret);
473 msm_host->byte_clk_src = NULL;
474 goto exit;
475 }
476
477 msm_host->pixel_clk_src = devm_clk_get(dev, "pixel_clk_src");
478 if (IS_ERR(msm_host->pixel_clk_src)) {
479 ret = PTR_ERR(msm_host->pixel_clk_src);
480 pr_err("%s: can't find pixel_clk_src. ret=%d\n", __func__, ret);
481 msm_host->pixel_clk_src = NULL;
482 goto exit;
483 }
484
a689554b
HL		 485exit:
486 return ret;
487}
488
489static int dsi_bus_clk_enable(struct msm_dsi_host *msm_host)
490{
491 int ret;
492
493 DBG("id=%d", msm_host->id);
494
495 ret = clk_prepare_enable(msm_host->mdp_core_clk);
496 if (ret) {
497 pr_err("%s: failed to enable mdp_core_clock, %d\n",
498 __func__, ret);
499 goto core_clk_err;
500 }
501
502 ret = clk_prepare_enable(msm_host->ahb_clk);
503 if (ret) {
504 pr_err("%s: failed to enable ahb clock, %d\n", __func__, ret);
505 goto ahb_clk_err;
506 }
507
508 ret = clk_prepare_enable(msm_host->axi_clk);
509 if (ret) {
510 pr_err("%s: failed to enable ahb clock, %d\n", __func__, ret);
511 goto axi_clk_err;
512 }
513
514 ret = clk_prepare_enable(msm_host->mmss_misc_ahb_clk);
515 if (ret) {
516 pr_err("%s: failed to enable mmss misc ahb clk, %d\n",
517 __func__, ret);
518 goto misc_ahb_clk_err;
519 }
520
521 return 0;
522
523misc_ahb_clk_err:
524 clk_disable_unprepare(msm_host->axi_clk);
525axi_clk_err:
526 clk_disable_unprepare(msm_host->ahb_clk);
527ahb_clk_err:
528 clk_disable_unprepare(msm_host->mdp_core_clk);
529core_clk_err:
530 return ret;
531}
532
533static void dsi_bus_clk_disable(struct msm_dsi_host *msm_host)
534{
535 DBG("");
536 clk_disable_unprepare(msm_host->mmss_misc_ahb_clk);
537 clk_disable_unprepare(msm_host->axi_clk);
538 clk_disable_unprepare(msm_host->ahb_clk);
539 clk_disable_unprepare(msm_host->mdp_core_clk);
540}
541
542static int dsi_link_clk_enable(struct msm_dsi_host *msm_host)
543{
544 int ret;
545
546 DBG("Set clk rates: pclk=%d, byteclk=%d",
547 msm_host->mode->clock, msm_host->byte_clk_rate);
548
549 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate);
550 if (ret) {
551 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret);
552 goto error;
553 }
554
555 ret = clk_set_rate(msm_host->pixel_clk, msm_host->mode->clock * 1000);
556 if (ret) {
557 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
558 goto error;
559 }
560
561 ret = clk_prepare_enable(msm_host->esc_clk);
562 if (ret) {
563 pr_err("%s: Failed to enable dsi esc clk\n", __func__);
564 goto error;
565 }
566
567 ret = clk_prepare_enable(msm_host->byte_clk);
568 if (ret) {
569 pr_err("%s: Failed to enable dsi byte clk\n", __func__);
570 goto byte_clk_err;
571 }
572
573 ret = clk_prepare_enable(msm_host->pixel_clk);
574 if (ret) {
575 pr_err("%s: Failed to enable dsi pixel clk\n", __func__);
576 goto pixel_clk_err;
577 }
578
579 return 0;
580
581pixel_clk_err:
582 clk_disable_unprepare(msm_host->byte_clk);
583byte_clk_err:
584 clk_disable_unprepare(msm_host->esc_clk);
585error:
586 return ret;
587}
588
589static void dsi_link_clk_disable(struct msm_dsi_host *msm_host)
590{
591 clk_disable_unprepare(msm_host->esc_clk);
592 clk_disable_unprepare(msm_host->pixel_clk);
593 clk_disable_unprepare(msm_host->byte_clk);
594}
595
596static int dsi_clk_ctrl(struct msm_dsi_host *msm_host, bool enable)
597{
598 int ret = 0;
599
600 mutex_lock(&msm_host->clk_mutex);
601 if (enable) {
602 ret = dsi_bus_clk_enable(msm_host);
603 if (ret) {
604 pr_err("%s: Can not enable bus clk, %d\n",
605 __func__, ret);
606 goto unlock_ret;
607 }
608 ret = dsi_link_clk_enable(msm_host);
609 if (ret) {
610 pr_err("%s: Can not enable link clk, %d\n",
611 __func__, ret);
612 dsi_bus_clk_disable(msm_host);
613 goto unlock_ret;
614 }
615 } else {
616 dsi_link_clk_disable(msm_host);
617 dsi_bus_clk_disable(msm_host);
618 }
619
620unlock_ret:
621 mutex_unlock(&msm_host->clk_mutex);
622 return ret;
623}
624
625static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host)
626{
627 struct drm_display_mode *mode = msm_host->mode;
628 u8 lanes = msm_host->lanes;
629 u32 bpp = dsi_get_bpp(msm_host->format);
630 u32 pclk_rate;
631
632 if (!mode) {
633 pr_err("%s: mode not set\n", __func__);
634 return -EINVAL;
635 }
636
637 pclk_rate = mode->clock * 1000;
638 if (lanes > 0) {
639 msm_host->byte_clk_rate = (pclk_rate * bpp) / (8 * lanes);
640 } else {
641 pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__);
642 msm_host->byte_clk_rate = (pclk_rate * bpp) / 8;
643 }
644
645 DBG("pclk=%d, bclk=%d", pclk_rate, msm_host->byte_clk_rate);
646
647 return 0;
648}
649
650static void dsi_phy_sw_reset(struct msm_dsi_host *msm_host)
651{
652 DBG("");
653 dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET);
654 /* Make sure fully reset */
655 wmb();
656 udelay(1000);
657 dsi_write(msm_host, REG_DSI_PHY_RESET, 0);
658 udelay(100);
659}
660
661static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable)
662{
663 u32 intr;
664 unsigned long flags;
665
666 spin_lock_irqsave(&msm_host->intr_lock, flags);
667 intr = dsi_read(msm_host, REG_DSI_INTR_CTRL);
668
669 if (enable)
670 intr |= mask;
671 else
672 intr &= ~mask;
673
674 DBG("intr=%x enable=%d", intr, enable);
675
676 dsi_write(msm_host, REG_DSI_INTR_CTRL, intr);
677 spin_unlock_irqrestore(&msm_host->intr_lock, flags);
678}
679
680static inline enum dsi_traffic_mode dsi_get_traffic_mode(const u32 mode_flags)
681{
682 if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
683 return BURST_MODE;
684 else if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
685 return NON_BURST_SYNCH_PULSE;
686
687 return NON_BURST_SYNCH_EVENT;
688}
689
690static inline enum dsi_vid_dst_format dsi_get_vid_fmt(
691 const enum mipi_dsi_pixel_format mipi_fmt)
692{
693 switch (mipi_fmt) {
694 case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888;
695 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666_LOOSE;
696 case MIPI_DSI_FMT_RGB666_PACKED: return VID_DST_FORMAT_RGB666;
697 case MIPI_DSI_FMT_RGB565: return VID_DST_FORMAT_RGB565;
698 default: return VID_DST_FORMAT_RGB888;
699 }
700}
701
702static inline enum dsi_cmd_dst_format dsi_get_cmd_fmt(
703 const enum mipi_dsi_pixel_format mipi_fmt)
704{
705 switch (mipi_fmt) {
706 case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888;
707 case MIPI_DSI_FMT_RGB666_PACKED:
708 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666;
709 case MIPI_DSI_FMT_RGB565: return CMD_DST_FORMAT_RGB565;
710 default: return CMD_DST_FORMAT_RGB888;
711 }
712}
713
714static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
715 u32 clk_pre, u32 clk_post)
716{
717 u32 flags = msm_host->mode_flags;
718 enum mipi_dsi_pixel_format mipi_fmt = msm_host->format;
719 u32 data = 0;
720
721 if (!enable) {
722 dsi_write(msm_host, REG_DSI_CTRL, 0);
723 return;
724 }
725
726 if (flags & MIPI_DSI_MODE_VIDEO) {
727 if (flags & MIPI_DSI_MODE_VIDEO_HSE)
728 data |= DSI_VID_CFG0_PULSE_MODE_HSA_HE;
729 if (flags & MIPI_DSI_MODE_VIDEO_HFP)
730 data |= DSI_VID_CFG0_HFP_POWER_STOP;
731 if (flags & MIPI_DSI_MODE_VIDEO_HBP)
732 data |= DSI_VID_CFG0_HBP_POWER_STOP;
733 if (flags & MIPI_DSI_MODE_VIDEO_HSA)
734 data |= DSI_VID_CFG0_HSA_POWER_STOP;
735 /* Always set low power stop mode for BLLP
736 * to let command engine send packets
737 */
738 data |= DSI_VID_CFG0_EOF_BLLP_POWER_STOP |
739 DSI_VID_CFG0_BLLP_POWER_STOP;
740 data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags));
741 data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt));
742 data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel);
743 dsi_write(msm_host, REG_DSI_VID_CFG0, data);
744
745 /* Do not swap RGB colors */
746 data = DSI_VID_CFG1_RGB_SWAP(SWAP_RGB);
747 dsi_write(msm_host, REG_DSI_VID_CFG1, 0);
748 } else {
749 /* Do not swap RGB colors */
750 data = DSI_CMD_CFG0_RGB_SWAP(SWAP_RGB);
751 data |= DSI_CMD_CFG0_DST_FORMAT(dsi_get_cmd_fmt(mipi_fmt));
752 dsi_write(msm_host, REG_DSI_CMD_CFG0, data);
753
754 data = DSI_CMD_CFG1_WR_MEM_START(MIPI_DCS_WRITE_MEMORY_START) |
755 DSI_CMD_CFG1_WR_MEM_CONTINUE(
756 MIPI_DCS_WRITE_MEMORY_CONTINUE);
757 /* Always insert DCS command */
758 data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND;
759 dsi_write(msm_host, REG_DSI_CMD_CFG1, data);
760 }
761
762 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL,
763 DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER |
764 DSI_CMD_DMA_CTRL_LOW_POWER);
765
766 data = 0;
767 /* Always assume dedicated TE pin */
768 data |= DSI_TRIG_CTRL_TE;
769 data |= DSI_TRIG_CTRL_MDP_TRIGGER(TRIGGER_NONE);
770 data |= DSI_TRIG_CTRL_DMA_TRIGGER(TRIGGER_SW);
771 data |= DSI_TRIG_CTRL_STREAM(msm_host->channel);
772 if ((msm_host->cfg->major == MSM_DSI_VER_MAJOR_6G) &&
773 (msm_host->cfg->minor >= MSM_DSI_6G_VER_MINOR_V1_2))
774 data |= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME;
775 dsi_write(msm_host, REG_DSI_TRIG_CTRL, data);
776
777 data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(clk_post) |
778 DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(clk_pre);
779 dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data);
780
781 data = 0;
782 if (!(flags & MIPI_DSI_MODE_EOT_PACKET))
783 data |= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND;
784 dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data);
785
786 /* allow only ack-err-status to generate interrupt */
787 dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0);
788
789 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1);
790
791 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
792
793 data = DSI_CTRL_CLK_EN;
794
795 DBG("lane number=%d", msm_host->lanes);
796 if (msm_host->lanes == 2) {
797 data |= DSI_CTRL_LANE1 | DSI_CTRL_LANE2;
798 /* swap lanes for 2-lane panel for better performance */
799 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL,
800 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(LANE_SWAP_1230));
801 } else {
802 /* Take 4 lanes as default */
803 data |= DSI_CTRL_LANE0 | DSI_CTRL_LANE1 | DSI_CTRL_LANE2 |
804 DSI_CTRL_LANE3;
805 /* Do not swap lanes for 4-lane panel */
806 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL,
807 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(LANE_SWAP_0123));
808 }
65c5e542
AT		 809
810 if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
811 dsi_write(msm_host, REG_DSI_LANE_CTRL,
812 DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST);
813
a689554b
HL		 814 data |= DSI_CTRL_ENABLE;
815
816 dsi_write(msm_host, REG_DSI_CTRL, data);
817}
818
819static void dsi_timing_setup(struct msm_dsi_host *msm_host)
820{
821 struct drm_display_mode *mode = msm_host->mode;
822 u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */
823 u32 h_total = mode->htotal;
824 u32 v_total = mode->vtotal;
825 u32 hs_end = mode->hsync_end - mode->hsync_start;
826 u32 vs_end = mode->vsync_end - mode->vsync_start;
827 u32 ha_start = h_total - mode->hsync_start;
828 u32 ha_end = ha_start + mode->hdisplay;
829 u32 va_start = v_total - mode->vsync_start;
830 u32 va_end = va_start + mode->vdisplay;
831 u32 wc;
832
833 DBG("");
834
835 if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) {
836 dsi_write(msm_host, REG_DSI_ACTIVE_H,
837 DSI_ACTIVE_H_START(ha_start) |
838 DSI_ACTIVE_H_END(ha_end));
839 dsi_write(msm_host, REG_DSI_ACTIVE_V,
840 DSI_ACTIVE_V_START(va_start) |
841 DSI_ACTIVE_V_END(va_end));
842 dsi_write(msm_host, REG_DSI_TOTAL,
843 DSI_TOTAL_H_TOTAL(h_total - 1) |
844 DSI_TOTAL_V_TOTAL(v_total - 1));
845
846 dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC,
847 DSI_ACTIVE_HSYNC_START(hs_start) |
848 DSI_ACTIVE_HSYNC_END(hs_end));
849 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0);
850 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS,
851 DSI_ACTIVE_VSYNC_VPOS_START(vs_start) |
852 DSI_ACTIVE_VSYNC_VPOS_END(vs_end));
853 } else { /* command mode */
854 /* image data and 1 byte write_memory_start cmd */
855 wc = mode->hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
856
857 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_CTRL,
858 DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(wc) |
859 DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL(
860 msm_host->channel) |
861 DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE(
862 MIPI_DSI_DCS_LONG_WRITE));
863
864 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_TOTAL,
865 DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(mode->hdisplay) |
866 DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(mode->vdisplay));
867 }
868}
869
870static void dsi_sw_reset(struct msm_dsi_host *msm_host)
871{
872 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
873 wmb(); /* clocks need to be enabled before reset */
874
875 dsi_write(msm_host, REG_DSI_RESET, 1);
876 wmb(); /* make sure reset happen */
877 dsi_write(msm_host, REG_DSI_RESET, 0);
878}
879
880static void dsi_op_mode_config(struct msm_dsi_host *msm_host,
881 bool video_mode, bool enable)
882{
883 u32 dsi_ctrl;
884
885 dsi_ctrl = dsi_read(msm_host, REG_DSI_CTRL);
886
887 if (!enable) {
888 dsi_ctrl &= ~(DSI_CTRL_ENABLE | DSI_CTRL_VID_MODE_EN |
889 DSI_CTRL_CMD_MODE_EN);
890 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE |
891 DSI_IRQ_MASK_VIDEO_DONE, 0);
892 } else {
893 if (video_mode) {
894 dsi_ctrl |= DSI_CTRL_VID_MODE_EN;
895 } else { /* command mode */
896 dsi_ctrl |= DSI_CTRL_CMD_MODE_EN;
897 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE, 1);
898 }
899 dsi_ctrl |= DSI_CTRL_ENABLE;
900 }
901
902 dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl);
903}
904
905static void dsi_set_tx_power_mode(int mode, struct msm_dsi_host *msm_host)
906{
907 u32 data;
908
909 data = dsi_read(msm_host, REG_DSI_CMD_DMA_CTRL);
910
911 if (mode == 0)
912 data &= ~DSI_CMD_DMA_CTRL_LOW_POWER;
913 else
914 data |= DSI_CMD_DMA_CTRL_LOW_POWER;
915
916 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data);
917}
918
919static void dsi_wait4video_done(struct msm_dsi_host *msm_host)
920{
921 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1);
922
923 reinit_completion(&msm_host->video_comp);
924
925 wait_for_completion_timeout(&msm_host->video_comp,
926 msecs_to_jiffies(70));
927
928 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0);
929}
930
931static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host)
932{
933 if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO))
934 return;
935
936 if (msm_host->power_on) {
937 dsi_wait4video_done(msm_host);
938 /* delay 4 ms to skip BLLP */
939 usleep_range(2000, 4000);
940 }
941}
942
943/* dsi_cmd */
944static int dsi_tx_buf_alloc(struct msm_dsi_host *msm_host, int size)
945{
946 struct drm_device *dev = msm_host->dev;
947 int ret;
948 u32 iova;
949
950 mutex_lock(&dev->struct_mutex);
951 msm_host->tx_gem_obj = msm_gem_new(dev, size, MSM_BO_UNCACHED);
952 if (IS_ERR(msm_host->tx_gem_obj)) {
953 ret = PTR_ERR(msm_host->tx_gem_obj);
954 pr_err("%s: failed to allocate gem, %d\n", __func__, ret);
955 msm_host->tx_gem_obj = NULL;
956 mutex_unlock(&dev->struct_mutex);
957 return ret;
958 }
959
960 ret = msm_gem_get_iova_locked(msm_host->tx_gem_obj, 0, &iova);
961 if (ret) {
962 pr_err("%s: failed to get iova, %d\n", __func__, ret);
963 return ret;
964 }
965 mutex_unlock(&dev->struct_mutex);
966
967 if (iova & 0x07) {
968 pr_err("%s: buf NOT 8 bytes aligned\n", __func__);
969 return -EINVAL;
970 }
971
972 return 0;
973}
974
975static void dsi_tx_buf_free(struct msm_dsi_host *msm_host)
976{
977 struct drm_device *dev = msm_host->dev;
978
979 if (msm_host->tx_gem_obj) {
980 msm_gem_put_iova(msm_host->tx_gem_obj, 0);
981 mutex_lock(&dev->struct_mutex);
982 msm_gem_free_object(msm_host->tx_gem_obj);
983 msm_host->tx_gem_obj = NULL;
984 mutex_unlock(&dev->struct_mutex);
985 }
986}
987
988/*
989 * prepare cmd buffer to be txed
990 */
991static int dsi_cmd_dma_add(struct drm_gem_object *tx_gem,
992 const struct mipi_dsi_msg *msg)
993{
994 struct mipi_dsi_packet packet;
995 int len;
996 int ret;
997 u8 *data;
998
999 ret = mipi_dsi_create_packet(&packet, msg);
1000 if (ret) {
1001 pr_err("%s: create packet failed, %d\n", __func__, ret);
1002 return ret;
1003 }
1004 len = (packet.size + 3) & (~0x3);
1005
1006 if (len > tx_gem->size) {
1007 pr_err("%s: packet size is too big\n", __func__);
1008 return -EINVAL;
1009 }
1010
1011 data = msm_gem_vaddr(tx_gem);
1012
1013 if (IS_ERR(data)) {
1014 ret = PTR_ERR(data);
1015 pr_err("%s: get vaddr failed, %d\n", __func__, ret);
1016 return ret;
1017 }
1018
1019 /* MSM specific command format in memory */
1020 data[0] = packet.header[1];
1021 data[1] = packet.header[2];
1022 data[2] = packet.header[0];
1023 data[3] = BIT(7); /* Last packet */
1024 if (mipi_dsi_packet_format_is_long(msg->type))
1025 data[3] |= BIT(6);
1026 if (msg->rx_buf && msg->rx_len)
1027 data[3] |= BIT(5);
1028
1029 /* Long packet */
1030 if (packet.payload && packet.payload_length)
1031 memcpy(data + 4, packet.payload, packet.payload_length);
1032
1033 /* Append 0xff to the end */
1034 if (packet.size < len)
1035 memset(data + packet.size, 0xff, len - packet.size);
1036
1037 return len;
1038}
1039
1040/*
1041 * dsi_short_read1_resp: 1 parameter
1042 */
1043static int dsi_short_read1_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1044{
1045 u8 *data = msg->rx_buf;
1046 if (data && (msg->rx_len >= 1)) {
1047 *data = buf[1]; /* strip out dcs type */
1048 return 1;
1049 } else {
981371f3 1050 pr_err("%s: read data does not match with rx_buf len %zu\n",
a689554b
HL		 1051 __func__, msg->rx_len);
1052 return -EINVAL;
1053 }
1054}
1055
1056/*
1057 * dsi_short_read2_resp: 2 parameter
1058 */
1059static int dsi_short_read2_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1060{
1061 u8 *data = msg->rx_buf;
1062 if (data && (msg->rx_len >= 2)) {
1063 data[0] = buf[1]; /* strip out dcs type */
1064 data[1] = buf[2];
1065 return 2;
1066 } else {
981371f3 1067 pr_err("%s: read data does not match with rx_buf len %zu\n",
a689554b
HL		 1068 __func__, msg->rx_len);
1069 return -EINVAL;
1070 }
1071}
1072
1073static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1074{
1075 /* strip out 4 byte dcs header */
1076 if (msg->rx_buf && msg->rx_len)
1077 memcpy(msg->rx_buf, buf + 4, msg->rx_len);
1078
1079 return msg->rx_len;
1080}
1081
1082
1083static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len)
1084{
1085 int ret;
1086 u32 iova;
1087 bool triggered;
1088
1089 ret = msm_gem_get_iova(msm_host->tx_gem_obj, 0, &iova);
1090 if (ret) {
1091 pr_err("%s: failed to get iova: %d\n", __func__, ret);
1092 return ret;
1093 }
1094
1095 reinit_completion(&msm_host->dma_comp);
1096
1097 dsi_wait4video_eng_busy(msm_host);
1098
1099 triggered = msm_dsi_manager_cmd_xfer_trigger(
1100 msm_host->id, iova, len);
1101 if (triggered) {
1102 ret = wait_for_completion_timeout(&msm_host->dma_comp,
1103 msecs_to_jiffies(200));
1104 DBG("ret=%d", ret);
1105 if (ret == 0)
1106 ret = -ETIMEDOUT;
1107 else
1108 ret = len;
1109 } else
1110 ret = len;
1111
1112 return ret;
1113}
1114
1115static int dsi_cmd_dma_rx(struct msm_dsi_host *msm_host,
1116 u8 *buf, int rx_byte, int pkt_size)
1117{
1118 u32 *lp, *temp, data;
1119 int i, j = 0, cnt;
a689554b
HL		 1120 u32 read_cnt;
1121 u8 reg[16];
1122 int repeated_bytes = 0;
1123 int buf_offset = buf - msm_host->rx_buf;
1124
1125 lp = (u32 *)buf;
1126 temp = (u32 *)reg;
1127 cnt = (rx_byte + 3) >> 2;
1128 if (cnt > 4)
1129 cnt = 4; /* 4 x 32 bits registers only */
1130
ec1936eb
HL		 1131 if (rx_byte == 4)
1132 read_cnt = 4;
1133 else
1134 read_cnt = pkt_size + 6;
a689554b
HL		 1135
1136 /*
1137 * In case of multiple reads from the panel, after the first read, there
1138 * is possibility that there are some bytes in the payload repeating in
1139 * the RDBK_DATA registers. Since we read all the parameters from the
1140 * panel right from the first byte for every pass. We need to skip the
1141 * repeating bytes and then append the new parameters to the rx buffer.
1142 */
1143 if (read_cnt > 16) {
1144 int bytes_shifted;
1145 /* Any data more than 16 bytes will be shifted out.
1146 * The temp read buffer should already contain these bytes.
1147 * The remaining bytes in read buffer are the repeated bytes.
1148 */
1149 bytes_shifted = read_cnt - 16;
1150 repeated_bytes = buf_offset - bytes_shifted;
1151 }
1152
1153 for (i = cnt - 1; i >= 0; i--) {
1154 data = dsi_read(msm_host, REG_DSI_RDBK_DATA(i));
1155 *temp++ = ntohl(data); /* to host byte order */
1156 DBG("data = 0x%x and ntohl(data) = 0x%x", data, ntohl(data));
1157 }
1158
1159 for (i = repeated_bytes; i < 16; i++)
1160 buf[j++] = reg[i];
1161
1162 return j;
1163}
1164
1165static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host,
1166 const struct mipi_dsi_msg *msg)
1167{
1168 int len, ret;
1169 int bllp_len = msm_host->mode->hdisplay *
1170 dsi_get_bpp(msm_host->format) / 8;
1171
1172 len = dsi_cmd_dma_add(msm_host->tx_gem_obj, msg);
1173 if (!len) {
1174 pr_err("%s: failed to add cmd type = 0x%x\n",
1175 __func__, msg->type);
1176 return -EINVAL;
1177 }
1178
1179 /* for video mode, do not send cmds more than
1180 * one pixel line, since it only transmit it
1181 * during BLLP.
1182 */
1183 /* TODO: if the command is sent in LP mode, the bit rate is only
1184 * half of esc clk rate. In this case, if the video is already
1185 * actively streaming, we need to check more carefully if the
1186 * command can be fit into one BLLP.
1187 */
1188 if ((msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && (len > bllp_len)) {
1189 pr_err("%s: cmd cannot fit into BLLP period, len=%d\n",
1190 __func__, len);
1191 return -EINVAL;
1192 }
1193
1194 ret = dsi_cmd_dma_tx(msm_host, len);
1195 if (ret < len) {
1196 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d\n",
1197 __func__, msg->type, (*(u8 *)(msg->tx_buf)), len);
1198 return -ECOMM;
1199 }
1200
1201 return len;
1202}
1203
1204static void dsi_sw_reset_restore(struct msm_dsi_host *msm_host)
1205{
1206 u32 data0, data1;
1207
1208 data0 = dsi_read(msm_host, REG_DSI_CTRL);
1209 data1 = data0;
1210 data1 &= ~DSI_CTRL_ENABLE;
1211 dsi_write(msm_host, REG_DSI_CTRL, data1);
1212 /*
1213 * dsi controller need to be disabled before
1214 * clocks turned on
1215 */
1216 wmb();
1217
1218 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
1219 wmb(); /* make sure clocks enabled */
1220
1221 /* dsi controller can only be reset while clocks are running */
1222 dsi_write(msm_host, REG_DSI_RESET, 1);
1223 wmb(); /* make sure reset happen */
1224 dsi_write(msm_host, REG_DSI_RESET, 0);
1225 wmb(); /* controller out of reset */
1226 dsi_write(msm_host, REG_DSI_CTRL, data0);
1227 wmb(); /* make sure dsi controller enabled again */
1228}
1229
1230static void dsi_err_worker(struct work_struct *work)
1231{
1232 struct msm_dsi_host *msm_host =
1233 container_of(work, struct msm_dsi_host, err_work);
1234 u32 status = msm_host->err_work_state;
1235
ff431fa4 1236 pr_err_ratelimited("%s: status=%x\n", __func__, status);
a689554b
HL		 1237 if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW)
1238 dsi_sw_reset_restore(msm_host);
1239
1240 /* It is safe to clear here because error irq is disabled. */
1241 msm_host->err_work_state = 0;
1242
1243 /* enable dsi error interrupt */
1244 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1);
1245}
1246
1247static void dsi_ack_err_status(struct msm_dsi_host *msm_host)
1248{
1249 u32 status;
1250
1251 status = dsi_read(msm_host, REG_DSI_ACK_ERR_STATUS);
1252
1253 if (status) {
1254 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status);
1255 /* Writing of an extra 0 needed to clear error bits */
1256 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0);
1257 msm_host->err_work_state |= DSI_ERR_STATE_ACK;
1258 }
1259}
1260
1261static void dsi_timeout_status(struct msm_dsi_host *msm_host)
1262{
1263 u32 status;
1264
1265 status = dsi_read(msm_host, REG_DSI_TIMEOUT_STATUS);
1266
1267 if (status) {
1268 dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status);
1269 msm_host->err_work_state |= DSI_ERR_STATE_TIMEOUT;
1270 }
1271}
1272
1273static void dsi_dln0_phy_err(struct msm_dsi_host *msm_host)
1274{
1275 u32 status;
1276
1277 status = dsi_read(msm_host, REG_DSI_DLN0_PHY_ERR);
1278
1279 if (status) {
1280 dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status);
1281 msm_host->err_work_state |= DSI_ERR_STATE_DLN0_PHY;
1282 }
1283}
1284
1285static void dsi_fifo_status(struct msm_dsi_host *msm_host)
1286{
1287 u32 status;
1288
1289 status = dsi_read(msm_host, REG_DSI_FIFO_STATUS);
1290
1291 /* fifo underflow, overflow */
1292 if (status) {
1293 dsi_write(msm_host, REG_DSI_FIFO_STATUS, status);
1294 msm_host->err_work_state |= DSI_ERR_STATE_FIFO;
1295 if (status & DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW)
1296 msm_host->err_work_state |=
1297 DSI_ERR_STATE_MDP_FIFO_UNDERFLOW;
1298 }
1299}
1300
1301static void dsi_status(struct msm_dsi_host *msm_host)
1302{
1303 u32 status;
1304
1305 status = dsi_read(msm_host, REG_DSI_STATUS0);
1306
1307 if (status & DSI_STATUS0_INTERLEAVE_OP_CONTENTION) {
1308 dsi_write(msm_host, REG_DSI_STATUS0, status);
1309 msm_host->err_work_state |=
1310 DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION;
1311 }
1312}
1313
1314static void dsi_clk_status(struct msm_dsi_host *msm_host)
1315{
1316 u32 status;
1317
1318 status = dsi_read(msm_host, REG_DSI_CLK_STATUS);
1319
1320 if (status & DSI_CLK_STATUS_PLL_UNLOCKED) {
1321 dsi_write(msm_host, REG_DSI_CLK_STATUS, status);
1322 msm_host->err_work_state |= DSI_ERR_STATE_PLL_UNLOCKED;
1323 }
1324}
1325
1326static void dsi_error(struct msm_dsi_host *msm_host)
1327{
1328 /* disable dsi error interrupt */
1329 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 0);
1330
1331 dsi_clk_status(msm_host);
1332 dsi_fifo_status(msm_host);
1333 dsi_ack_err_status(msm_host);
1334 dsi_timeout_status(msm_host);
1335 dsi_status(msm_host);
1336 dsi_dln0_phy_err(msm_host);
1337
1338 queue_work(msm_host->workqueue, &msm_host->err_work);
1339}
1340
1341static irqreturn_t dsi_host_irq(int irq, void *ptr)
1342{
1343 struct msm_dsi_host *msm_host = ptr;
1344 u32 isr;
1345 unsigned long flags;
1346
1347 if (!msm_host->ctrl_base)
1348 return IRQ_HANDLED;
1349
1350 spin_lock_irqsave(&msm_host->intr_lock, flags);
1351 isr = dsi_read(msm_host, REG_DSI_INTR_CTRL);
1352 dsi_write(msm_host, REG_DSI_INTR_CTRL, isr);
1353 spin_unlock_irqrestore(&msm_host->intr_lock, flags);
1354
1355 DBG("isr=0x%x, id=%d", isr, msm_host->id);
1356
1357 if (isr & DSI_IRQ_ERROR)
1358 dsi_error(msm_host);
1359
1360 if (isr & DSI_IRQ_VIDEO_DONE)
1361 complete(&msm_host->video_comp);
1362
1363 if (isr & DSI_IRQ_CMD_DMA_DONE)
1364 complete(&msm_host->dma_comp);
1365
1366 return IRQ_HANDLED;
1367}
1368
1369static int dsi_host_init_panel_gpios(struct msm_dsi_host *msm_host,
1370 struct device *panel_device)
1371{
9590e69d
UKK		 1372 msm_host->disp_en_gpio = devm_gpiod_get_optional(panel_device,
1373 "disp-enable",
1374 GPIOD_OUT_LOW);
a689554b
HL		 1375 if (IS_ERR(msm_host->disp_en_gpio)) {
1376 DBG("cannot get disp-enable-gpios %ld",
1377 PTR_ERR(msm_host->disp_en_gpio));
9590e69d 1378 return PTR_ERR(msm_host->disp_en_gpio);
a689554b
HL		 1379 }
1380
9590e69d 1381 msm_host->te_gpio = devm_gpiod_get(panel_device, "disp-te", GPIOD_IN);
a689554b
HL		 1382 if (IS_ERR(msm_host->te_gpio)) {
1383 DBG("cannot get disp-te-gpios %ld", PTR_ERR(msm_host->te_gpio));
9590e69d 1384 return PTR_ERR(msm_host->te_gpio);
a689554b
HL		 1385 }
1386
1387 return 0;
1388}
1389
1390static int dsi_host_attach(struct mipi_dsi_host *host,
1391 struct mipi_dsi_device *dsi)
1392{
1393 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1394 int ret;
1395
1396 msm_host->channel = dsi->channel;
1397 msm_host->lanes = dsi->lanes;
1398 msm_host->format = dsi->format;
1399 msm_host->mode_flags = dsi->mode_flags;
1400
1401 msm_host->panel_node = dsi->dev.of_node;
1402
1403 /* Some gpios defined in panel DT need to be controlled by host */
1404 ret = dsi_host_init_panel_gpios(msm_host, &dsi->dev);
1405 if (ret)
1406 return ret;
1407
1408 DBG("id=%d", msm_host->id);
1409 if (msm_host->dev)
1410 drm_helper_hpd_irq_event(msm_host->dev);
1411
1412 return 0;
1413}
1414
1415static int dsi_host_detach(struct mipi_dsi_host *host,
1416 struct mipi_dsi_device *dsi)
1417{
1418 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1419
1420 msm_host->panel_node = NULL;
1421
1422 DBG("id=%d", msm_host->id);
1423 if (msm_host->dev)
1424 drm_helper_hpd_irq_event(msm_host->dev);
1425
1426 return 0;
1427}
1428
1429static ssize_t dsi_host_transfer(struct mipi_dsi_host *host,
1430 const struct mipi_dsi_msg *msg)
1431{
1432 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1433 int ret;
1434
1435 if (!msg || !msm_host->power_on)
1436 return -EINVAL;
1437
1438 mutex_lock(&msm_host->cmd_mutex);
1439 ret = msm_dsi_manager_cmd_xfer(msm_host->id, msg);
1440 mutex_unlock(&msm_host->cmd_mutex);
1441
1442 return ret;
1443}
1444
1445static struct mipi_dsi_host_ops dsi_host_ops = {
1446 .attach = dsi_host_attach,
1447 .detach = dsi_host_detach,
1448 .transfer = dsi_host_transfer,
1449};
1450
1451int msm_dsi_host_init(struct msm_dsi *msm_dsi)
1452{
1453 struct msm_dsi_host *msm_host = NULL;
1454 struct platform_device *pdev = msm_dsi->pdev;
1455 int ret;
1456
1457 msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL);
1458 if (!msm_host) {
1459 pr_err("%s: FAILED: cannot alloc dsi host\n",
1460 __func__);
1461 ret = -ENOMEM;
1462 goto fail;
1463 }
1464
1465 ret = of_property_read_u32(pdev->dev.of_node,
1466 "qcom,dsi-host-index", &msm_host->id);
1467 if (ret) {
1468 dev_err(&pdev->dev,
1469 "%s: host index not specified, ret=%d\n",
1470 __func__, ret);
1471 goto fail;
1472 }
1473 msm_host->pdev = pdev;
1474
1475 ret = dsi_clk_init(msm_host);
1476 if (ret) {
1477 pr_err("%s: unable to initialize dsi clks\n", __func__);
1478 goto fail;
1479 }
1480
1481 msm_host->ctrl_base = msm_ioremap(pdev, "dsi_ctrl", "DSI CTRL");
1482 if (IS_ERR(msm_host->ctrl_base)) {
1483 pr_err("%s: unable to map Dsi ctrl base\n", __func__);
1484 ret = PTR_ERR(msm_host->ctrl_base);
1485 goto fail;
1486 }
1487
1488 msm_host->cfg = dsi_get_config(msm_host);
1489 if (!msm_host->cfg) {
1490 ret = -EINVAL;
1491 pr_err("%s: get config failed\n", __func__);
1492 goto fail;
1493 }
1494
1495 ret = dsi_regulator_init(msm_host);
1496 if (ret) {
1497 pr_err("%s: regulator init failed\n", __func__);
1498 goto fail;
1499 }
1500
1501 msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL);
1502 if (!msm_host->rx_buf) {
1503 pr_err("%s: alloc rx temp buf failed\n", __func__);
1504 goto fail;
1505 }
1506
1507 init_completion(&msm_host->dma_comp);
1508 init_completion(&msm_host->video_comp);
1509 mutex_init(&msm_host->dev_mutex);
1510 mutex_init(&msm_host->cmd_mutex);
1511 mutex_init(&msm_host->clk_mutex);
1512 spin_lock_init(&msm_host->intr_lock);
1513
1514 /* setup workqueue */
1515 msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0);
1516 INIT_WORK(&msm_host->err_work, dsi_err_worker);
1517
a689554b
HL		 1518 msm_dsi->host = &msm_host->base;
1519 msm_dsi->id = msm_host->id;
1520
1521 DBG("Dsi Host %d initialized", msm_host->id);
1522 return 0;
1523
1524fail:
1525 return ret;
1526}
1527
1528void msm_dsi_host_destroy(struct mipi_dsi_host *host)
1529{
1530 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1531
1532 DBG("");
1533 dsi_tx_buf_free(msm_host);
1534 if (msm_host->workqueue) {
1535 flush_workqueue(msm_host->workqueue);
1536 destroy_workqueue(msm_host->workqueue);
1537 msm_host->workqueue = NULL;
1538 }
1539
1540 mutex_destroy(&msm_host->clk_mutex);
1541 mutex_destroy(&msm_host->cmd_mutex);
1542 mutex_destroy(&msm_host->dev_mutex);
1543}
1544
1545int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
1546 struct drm_device *dev)
1547{
1548 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1549 struct platform_device *pdev = msm_host->pdev;
1550 int ret;
1551
1552 msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1553 if (msm_host->irq < 0) {
1554 ret = msm_host->irq;
1555 dev_err(dev->dev, "failed to get irq: %d\n", ret);
1556 return ret;
1557 }
1558
1559 ret = devm_request_irq(&pdev->dev, msm_host->irq,
1560 dsi_host_irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
1561 "dsi_isr", msm_host);
1562 if (ret < 0) {
1563 dev_err(&pdev->dev, "failed to request IRQ%u: %d\n",
1564 msm_host->irq, ret);
1565 return ret;
1566 }
1567
1568 msm_host->dev = dev;
1569 ret = dsi_tx_buf_alloc(msm_host, SZ_4K);
1570 if (ret) {
1571 pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret);
1572 return ret;
1573 }
1574
1575 return 0;
1576}
1577
1578int msm_dsi_host_register(struct mipi_dsi_host *host, bool check_defer)
1579{
1580 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1581 struct device_node *node;
1582 int ret;
1583
1584 /* Register mipi dsi host */
1585 if (!msm_host->registered) {
1586 host->dev = &msm_host->pdev->dev;
1587 host->ops = &dsi_host_ops;
1588 ret = mipi_dsi_host_register(host);
1589 if (ret)
1590 return ret;
1591
1592 msm_host->registered = true;
1593
1594 /* If the panel driver has not been probed after host register,
1595 * we should defer the host's probe.
1596 * It makes sure panel is connected when fbcon detects
1597 * connector status and gets the proper display mode to
1598 * create framebuffer.
1599 */
1600 if (check_defer) {
1601 node = of_get_child_by_name(msm_host->pdev->dev.of_node,
1602 "panel");
1603 if (node) {
1604 if (!of_drm_find_panel(node))
1605 return -EPROBE_DEFER;
1606 }
1607 }
1608 }
1609
1610 return 0;
1611}
1612
1613void msm_dsi_host_unregister(struct mipi_dsi_host *host)
1614{
1615 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1616
1617 if (msm_host->registered) {
1618 mipi_dsi_host_unregister(host);
1619 host->dev = NULL;
1620 host->ops = NULL;
1621 msm_host->registered = false;
1622 }
1623}
1624
1625int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host,
1626 const struct mipi_dsi_msg *msg)
1627{
1628 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1629
1630 /* TODO: make sure dsi_cmd_mdp is idle.
1631 * Since DSI6G v1.2.0, we can set DSI_TRIG_CTRL.BLOCK_DMA_WITHIN_FRAME
1632 * to ask H/W to wait until cmd mdp is idle. S/W wait is not needed.
1633 * How to handle the old versions? Wait for mdp cmd done?
1634 */
1635
1636 /*
1637 * mdss interrupt is generated in mdp core clock domain
1638 * mdp clock need to be enabled to receive dsi interrupt
1639 */
1640 dsi_clk_ctrl(msm_host, 1);
1641
1642 /* TODO: vote for bus bandwidth */
1643
1644 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM))
1645 dsi_set_tx_power_mode(0, msm_host);
1646
1647 msm_host->dma_cmd_ctrl_restore = dsi_read(msm_host, REG_DSI_CTRL);
1648 dsi_write(msm_host, REG_DSI_CTRL,
1649 msm_host->dma_cmd_ctrl_restore |
1650 DSI_CTRL_CMD_MODE_EN |
1651 DSI_CTRL_ENABLE);
1652 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 1);
1653
1654 return 0;
1655}
1656
1657void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host,
1658 const struct mipi_dsi_msg *msg)
1659{
1660 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1661
1662 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 0);
1663 dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore);
1664
1665 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM))
1666 dsi_set_tx_power_mode(1, msm_host);
1667
1668 /* TODO: unvote for bus bandwidth */
1669
1670 dsi_clk_ctrl(msm_host, 0);
1671}
1672
1673int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host,
1674 const struct mipi_dsi_msg *msg)
1675{
1676 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1677
1678 return dsi_cmds2buf_tx(msm_host, msg);
1679}
1680
1681int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host,
1682 const struct mipi_dsi_msg *msg)
1683{
1684 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1685 int data_byte, rx_byte, dlen, end;
1686 int short_response, diff, pkt_size, ret = 0;
1687 char cmd;
1688 int rlen = msg->rx_len;
1689 u8 *buf;
1690
1691 if (rlen <= 2) {
1692 short_response = 1;
1693 pkt_size = rlen;
1694 rx_byte = 4;
1695 } else {
1696 short_response = 0;
1697 data_byte = 10; /* first read */
1698 if (rlen < data_byte)
1699 pkt_size = rlen;
1700 else
1701 pkt_size = data_byte;
1702 rx_byte = data_byte + 6; /* 4 header + 2 crc */
1703 }
1704
1705 buf = msm_host->rx_buf;
1706 end = 0;
1707 while (!end) {
1708 u8 tx[2] = {pkt_size & 0xff, pkt_size >> 8};
1709 struct mipi_dsi_msg max_pkt_size_msg = {
1710 .channel = msg->channel,
1711 .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE,
1712 .tx_len = 2,
1713 .tx_buf = tx,
1714 };
1715
1716 DBG("rlen=%d pkt_size=%d rx_byte=%d",
1717 rlen, pkt_size, rx_byte);
1718
1719 ret = dsi_cmds2buf_tx(msm_host, &max_pkt_size_msg);
1720 if (ret < 2) {
1721 pr_err("%s: Set max pkt size failed, %d\n",
1722 __func__, ret);
1723 return -EINVAL;
1724 }
1725
1726 if ((msm_host->cfg->major == MSM_DSI_VER_MAJOR_6G) &&
1727 (msm_host->cfg->minor >= MSM_DSI_6G_VER_MINOR_V1_1)) {
1728 /* Clear the RDBK_DATA registers */
1729 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL,
1730 DSI_RDBK_DATA_CTRL_CLR);
1731 wmb(); /* make sure the RDBK registers are cleared */
1732 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0);
1733 wmb(); /* release cleared status before transfer */
1734 }
1735
1736 ret = dsi_cmds2buf_tx(msm_host, msg);
1737 if (ret < msg->tx_len) {
1738 pr_err("%s: Read cmd Tx failed, %d\n", __func__, ret);
1739 return ret;
1740 }
1741
1742 /*
1743 * once cmd_dma_done interrupt received,
1744 * return data from client is ready and stored
1745 * at RDBK_DATA register already
1746 * since rx fifo is 16 bytes, dcs header is kept at first loop,
1747 * after that dcs header lost during shift into registers
1748 */
1749 dlen = dsi_cmd_dma_rx(msm_host, buf, rx_byte, pkt_size);
1750
1751 if (dlen <= 0)
1752 return 0;
1753
1754 if (short_response)
1755 break;
1756
1757 if (rlen <= data_byte) {
1758 diff = data_byte - rlen;
1759 end = 1;
1760 } else {
1761 diff = 0;
1762 rlen -= data_byte;
1763 }
1764
1765 if (!end) {
1766 dlen -= 2; /* 2 crc */
1767 dlen -= diff;
1768 buf += dlen; /* next start position */
1769 data_byte = 14; /* NOT first read */
1770 if (rlen < data_byte)
1771 pkt_size += rlen;
1772 else
1773 pkt_size += data_byte;
1774 DBG("buf=%p dlen=%d diff=%d", buf, dlen, diff);
1775 }
1776 }
1777
1778 /*
1779 * For single Long read, if the requested rlen < 10,
1780 * we need to shift the start position of rx
1781 * data buffer to skip the bytes which are not
1782 * updated.
1783 */
1784 if (pkt_size < 10 && !short_response)
1785 buf = msm_host->rx_buf + (10 - rlen);
1786 else
1787 buf = msm_host->rx_buf;
1788
1789 cmd = buf[0];
1790 switch (cmd) {
1791 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1792 pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__);
1793 ret = 0;
651ad3f5 1794 break;
a689554b
HL		 1795 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
1796 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
1797 ret = dsi_short_read1_resp(buf, msg);
1798 break;
1799 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
1800 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
1801 ret = dsi_short_read2_resp(buf, msg);
1802 break;
1803 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
1804 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
1805 ret = dsi_long_read_resp(buf, msg);
1806 break;
1807 default:
1808 pr_warn("%s:Invalid response cmd\n", __func__);
1809 ret = 0;
1810 }
1811
1812 return ret;
1813}
1814
1815void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 iova, u32 len)
1816{
1817 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1818
1819 dsi_write(msm_host, REG_DSI_DMA_BASE, iova);
1820 dsi_write(msm_host, REG_DSI_DMA_LEN, len);
1821 dsi_write(msm_host, REG_DSI_TRIG_DMA, 1);
1822
1823 /* Make sure trigger happens */
1824 wmb();
1825}
1826
9d32c498
HL		 1827int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host,
1828 struct msm_dsi_pll *src_pll)
1829{
1830 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1831 struct clk *byte_clk_provider, *pixel_clk_provider;
1832 int ret;
1833
1834 ret = msm_dsi_pll_get_clk_provider(src_pll,
1835 &byte_clk_provider, &pixel_clk_provider);
1836 if (ret) {
1837 pr_info("%s: can't get provider from pll, don't set parent\n",
1838 __func__);
1839 return 0;
1840 }
1841
1842 ret = clk_set_parent(msm_host->byte_clk_src, byte_clk_provider);
1843 if (ret) {
1844 pr_err("%s: can't set parent to byte_clk_src. ret=%d\n",
1845 __func__, ret);
1846 goto exit;
1847 }
1848
1849 ret = clk_set_parent(msm_host->pixel_clk_src, pixel_clk_provider);
1850 if (ret) {
1851 pr_err("%s: can't set parent to pixel_clk_src. ret=%d\n",
1852 __func__, ret);
1853 goto exit;
1854 }
1855
1856exit:
1857 return ret;
1858}
1859
a689554b
HL		 1860int msm_dsi_host_enable(struct mipi_dsi_host *host)
1861{
1862 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1863
1864 dsi_op_mode_config(msm_host,
1865 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), true);
1866
1867 /* TODO: clock should be turned off for command mode,
1868 * and only turned on before MDP START.
1869 * This part of code should be enabled once mdp driver support it.
1870 */
1871 /* if (msm_panel->mode == MSM_DSI_CMD_MODE)
1872 dsi_clk_ctrl(msm_host, 0); */
1873
1874 return 0;
1875}
1876
1877int msm_dsi_host_disable(struct mipi_dsi_host *host)
1878{
1879 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1880
1881 dsi_op_mode_config(msm_host,
1882 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), false);
1883
1884 /* Since we have disabled INTF, the video engine won't stop so that
1885 * the cmd engine will be blocked.
1886 * Reset to disable video engine so that we can send off cmd.
1887 */
1888 dsi_sw_reset(msm_host);
1889
1890 return 0;
1891}
1892
1893int msm_dsi_host_power_on(struct mipi_dsi_host *host)
1894{
1895 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1896 u32 clk_pre = 0, clk_post = 0;
1897 int ret = 0;
1898
1899 mutex_lock(&msm_host->dev_mutex);
1900 if (msm_host->power_on) {
1901 DBG("dsi host already on");
1902 goto unlock_ret;
1903 }
1904
1905 ret = dsi_calc_clk_rate(msm_host);
1906 if (ret) {
1907 pr_err("%s: unable to calc clk rate, %d\n", __func__, ret);
1908 goto unlock_ret;
1909 }
1910
1911 ret = dsi_host_regulator_enable(msm_host);
1912 if (ret) {
1913 pr_err("%s:Failed to enable vregs.ret=%d\n",
1914 __func__, ret);
1915 goto unlock_ret;
1916 }
1917
1918 ret = dsi_bus_clk_enable(msm_host);
1919 if (ret) {
1920 pr_err("%s: failed to enable bus clocks, %d\n", __func__, ret);
1921 goto fail_disable_reg;
1922 }
1923
1924 dsi_phy_sw_reset(msm_host);
1925 ret = msm_dsi_manager_phy_enable(msm_host->id,
1926 msm_host->byte_clk_rate * 8,
1927 clk_get_rate(msm_host->esc_clk),
1928 &clk_pre, &clk_post);
1929 dsi_bus_clk_disable(msm_host);
1930 if (ret) {
1931 pr_err("%s: failed to enable phy, %d\n", __func__, ret);
1932 goto fail_disable_reg;
1933 }
1934
1935 ret = dsi_clk_ctrl(msm_host, 1);
1936 if (ret) {
1937 pr_err("%s: failed to enable clocks. ret=%d\n", __func__, ret);
1938 goto fail_disable_reg;
1939 }
1940
ab8909b0
HL		 1941 ret = pinctrl_pm_select_default_state(&msm_host->pdev->dev);
1942 if (ret) {
1943 pr_err("%s: failed to set pinctrl default state, %d\n",
1944 __func__, ret);
1945 goto fail_disable_clk;
1946 }
1947
a689554b
HL		 1948 dsi_timing_setup(msm_host);
1949 dsi_sw_reset(msm_host);
1950 dsi_ctrl_config(msm_host, true, clk_pre, clk_post);
1951
1952 if (msm_host->disp_en_gpio)
1953 gpiod_set_value(msm_host->disp_en_gpio, 1);
1954
1955 msm_host->power_on = true;
1956 mutex_unlock(&msm_host->dev_mutex);
1957
1958 return 0;
1959
ab8909b0
HL		 1960fail_disable_clk:
1961 dsi_clk_ctrl(msm_host, 0);
a689554b
HL		 1962fail_disable_reg:
1963 dsi_host_regulator_disable(msm_host);
1964unlock_ret:
1965 mutex_unlock(&msm_host->dev_mutex);
1966 return ret;
1967}
1968
1969int msm_dsi_host_power_off(struct mipi_dsi_host *host)
1970{
1971 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1972
1973 mutex_lock(&msm_host->dev_mutex);
1974 if (!msm_host->power_on) {
1975 DBG("dsi host already off");
1976 goto unlock_ret;
1977 }
1978
1979 dsi_ctrl_config(msm_host, false, 0, 0);
1980
1981 if (msm_host->disp_en_gpio)
1982 gpiod_set_value(msm_host->disp_en_gpio, 0);
1983
ab8909b0
HL		 1984 pinctrl_pm_select_sleep_state(&msm_host->pdev->dev);
1985
a689554b
HL		 1986 msm_dsi_manager_phy_disable(msm_host->id);
1987
1988 dsi_clk_ctrl(msm_host, 0);
1989
1990 dsi_host_regulator_disable(msm_host);
1991
1992 DBG("-");
1993
1994 msm_host->power_on = false;
1995
1996unlock_ret:
1997 mutex_unlock(&msm_host->dev_mutex);
1998 return 0;
1999}
2000
2001int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host,
2002 struct drm_display_mode *mode)
2003{
2004 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2005
2006 if (msm_host->mode) {
2007 drm_mode_destroy(msm_host->dev, msm_host->mode);
2008 msm_host->mode = NULL;
2009 }
2010
2011 msm_host->mode = drm_mode_duplicate(msm_host->dev, mode);
2012 if (IS_ERR(msm_host->mode)) {
2013 pr_err("%s: cannot duplicate mode\n", __func__);
2014 return PTR_ERR(msm_host->mode);
2015 }
2016
2017 return 0;
2018}
2019
2020struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host,
2021 unsigned long *panel_flags)
2022{
2023 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2024 struct drm_panel *panel;
2025
2026 panel = of_drm_find_panel(msm_host->panel_node);
2027 if (panel_flags)
2028 *panel_flags = msm_host->mode_flags;
2029
2030 return panel;
2031}
2032
Linux 6.x block layer and io_uring tree(s)