Commit | Line | Data |
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97fb5e8d | 1 | // SPDX-License-Identifier: GPL-2.0-only |
a689554b HL |
2 | /* |
3 | * Copyright (c) 2015, The Linux Foundation. All rights reserved. | |
a689554b HL |
4 | */ |
5 | ||
6 | #include <linux/clk.h> | |
7 | #include <linux/delay.h> | |
feea39a8 | 8 | #include <linux/dma-mapping.h> |
a689554b | 9 | #include <linux/err.h> |
964a0754 | 10 | #include <linux/gpio/consumer.h> |
a689554b | 11 | #include <linux/interrupt.h> |
feea39a8 | 12 | #include <linux/mfd/syscon.h> |
722d4f06 | 13 | #include <linux/of.h> |
feea39a8 | 14 | #include <linux/of_graph.h> |
a689554b | 15 | #include <linux/of_irq.h> |
ab8909b0 | 16 | #include <linux/pinctrl/consumer.h> |
32d3e0fe | 17 | #include <linux/pm_opp.h> |
feea39a8 | 18 | #include <linux/regmap.h> |
a689554b HL |
19 | #include <linux/regulator/consumer.h> |
20 | #include <linux/spinlock.h> | |
feea39a8 | 21 | |
a689554b HL |
22 | #include <video/mipi_display.h> |
23 | ||
c3a1aabc | 24 | #include <drm/display/drm_dsc_helper.h> |
53b93c0f MV |
25 | #include <drm/drm_of.h> |
26 | ||
a689554b HL |
27 | #include "dsi.h" |
28 | #include "dsi.xml.h" | |
0c7df47f | 29 | #include "sfpb.xml.h" |
d248b61f | 30 | #include "dsi_cfg.h" |
ed1498f7 | 31 | #include "msm_dsc_helper.h" |
f59f62d5 | 32 | #include "msm_kms.h" |
8f642378 | 33 | #include "msm_gem.h" |
5ac17838 | 34 | #include "phy/dsi_phy.h" |
a689554b | 35 | |
78e31c42 JH |
36 | #define DSI_RESET_TOGGLE_DELAY_MS 20 |
37 | ||
d2c277c6 | 38 | static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc); |
b9080324 | 39 | |
a689554b HL |
40 | static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor) |
41 | { | |
42 | u32 ver; | |
a689554b HL |
43 | |
44 | if (!major || !minor) | |
45 | return -EINVAL; | |
46 | ||
648d5063 AT |
47 | /* |
48 | * From DSI6G(v3), addition of a 6G_HW_VERSION register at offset 0 | |
a689554b | 49 | * makes all other registers 4-byte shifted down. |
648d5063 AT |
50 | * |
51 | * In order to identify between DSI6G(v3) and beyond, and DSIv2 and | |
52 | * older, we read the DSI_VERSION register without any shift(offset | |
53 | * 0x1f0). In the case of DSIv2, this hast to be a non-zero value. In | |
54 | * the case of DSI6G, this has to be zero (the offset points to a | |
55 | * scratch register which we never touch) | |
a689554b | 56 | */ |
648d5063 AT |
57 | |
58 | ver = msm_readl(base + REG_DSI_VERSION); | |
59 | if (ver) { | |
60 | /* older dsi host, there is no register shift */ | |
a689554b HL |
61 | ver = FIELD(ver, DSI_VERSION_MAJOR); |
62 | if (ver <= MSM_DSI_VER_MAJOR_V2) { | |
63 | /* old versions */ | |
64 | *major = ver; | |
65 | *minor = 0; | |
66 | return 0; | |
67 | } else { | |
68 | return -EINVAL; | |
69 | } | |
70 | } else { | |
648d5063 AT |
71 | /* |
72 | * newer host, offset 0 has 6G_HW_VERSION, the rest of the | |
73 | * registers are shifted down, read DSI_VERSION again with | |
74 | * the shifted offset | |
75 | */ | |
a689554b HL |
76 | ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION); |
77 | ver = FIELD(ver, DSI_VERSION_MAJOR); | |
78 | if (ver == MSM_DSI_VER_MAJOR_6G) { | |
79 | /* 6G version */ | |
80 | *major = ver; | |
648d5063 | 81 | *minor = msm_readl(base + REG_DSI_6G_HW_VERSION); |
a689554b HL |
82 | return 0; |
83 | } else { | |
84 | return -EINVAL; | |
85 | } | |
86 | } | |
87 | } | |
88 | ||
89 | #define DSI_ERR_STATE_ACK 0x0000 | |
90 | #define DSI_ERR_STATE_TIMEOUT 0x0001 | |
91 | #define DSI_ERR_STATE_DLN0_PHY 0x0002 | |
92 | #define DSI_ERR_STATE_FIFO 0x0004 | |
93 | #define DSI_ERR_STATE_MDP_FIFO_UNDERFLOW 0x0008 | |
94 | #define DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION 0x0010 | |
95 | #define DSI_ERR_STATE_PLL_UNLOCKED 0x0020 | |
96 | ||
97 | #define DSI_CLK_CTRL_ENABLE_CLKS \ | |
98 | (DSI_CLK_CTRL_AHBS_HCLK_ON | DSI_CLK_CTRL_AHBM_SCLK_ON | \ | |
99 | DSI_CLK_CTRL_PCLK_ON | DSI_CLK_CTRL_DSICLK_ON | \ | |
100 | DSI_CLK_CTRL_BYTECLK_ON | DSI_CLK_CTRL_ESCCLK_ON | \ | |
101 | DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK) | |
102 | ||
103 | struct msm_dsi_host { | |
104 | struct mipi_dsi_host base; | |
105 | ||
106 | struct platform_device *pdev; | |
107 | struct drm_device *dev; | |
108 | ||
109 | int id; | |
110 | ||
111 | void __iomem *ctrl_base; | |
bac2c6a6 | 112 | phys_addr_t ctrl_size; |
d8810a66 | 113 | struct regulator_bulk_data *supplies; |
6e0eb52e | 114 | |
d9fbb54d DB |
115 | int num_bus_clks; |
116 | struct clk_bulk_data bus_clks[DSI_BUS_CLK_MAX]; | |
6e0eb52e | 117 | |
a689554b HL |
118 | struct clk *byte_clk; |
119 | struct clk *esc_clk; | |
120 | struct clk *pixel_clk; | |
c1d97083 | 121 | struct clk *byte_intf_clk; |
9d32c498 | 122 | |
409af447 | 123 | unsigned long byte_clk_rate; |
1d5e01df | 124 | unsigned long byte_intf_clk_rate; |
409af447 JZ |
125 | unsigned long pixel_clk_rate; |
126 | unsigned long esc_clk_rate; | |
4bfa9748 AT |
127 | |
128 | /* DSI v2 specific clocks */ | |
129 | struct clk *src_clk; | |
4bfa9748 | 130 | |
409af447 | 131 | unsigned long src_clk_rate; |
a689554b HL |
132 | |
133 | struct gpio_desc *disp_en_gpio; | |
134 | struct gpio_desc *te_gpio; | |
135 | ||
d248b61f | 136 | const struct msm_dsi_cfg_handler *cfg_hnd; |
a689554b HL |
137 | |
138 | struct completion dma_comp; | |
139 | struct completion video_comp; | |
140 | struct mutex dev_mutex; | |
141 | struct mutex cmd_mutex; | |
a689554b HL |
142 | spinlock_t intr_lock; /* Protect interrupt ctrl register */ |
143 | ||
144 | u32 err_work_state; | |
145 | struct work_struct err_work; | |
146 | struct workqueue_struct *workqueue; | |
147 | ||
4ff9d4cb | 148 | /* DSI 6G TX buffer*/ |
a689554b | 149 | struct drm_gem_object *tx_gem_obj; |
4ff9d4cb AT |
150 | |
151 | /* DSI v2 TX buffer */ | |
152 | void *tx_buf; | |
153 | dma_addr_t tx_buf_paddr; | |
154 | ||
155 | int tx_size; | |
156 | ||
a689554b HL |
157 | u8 *rx_buf; |
158 | ||
0c7df47f AT |
159 | struct regmap *sfpb; |
160 | ||
a689554b | 161 | struct drm_display_mode *mode; |
4b2b1b36 | 162 | struct drm_dsc_config *dsc; |
a689554b | 163 | |
a9ddac9c | 164 | /* connected device info */ |
a689554b HL |
165 | unsigned int channel; |
166 | unsigned int lanes; | |
167 | enum mipi_dsi_pixel_format format; | |
168 | unsigned long mode_flags; | |
169 | ||
26f7d1f4 AT |
170 | /* lane data parsed via DT */ |
171 | int dlane_swap; | |
172 | int num_data_lanes; | |
173 | ||
5ac17838 JM |
174 | /* from phy DT */ |
175 | bool cphy_mode; | |
176 | ||
a689554b HL |
177 | u32 dma_cmd_ctrl_restore; |
178 | ||
179 | bool registered; | |
180 | bool power_on; | |
9c5638d7 | 181 | bool enabled; |
a689554b HL |
182 | int irq; |
183 | }; | |
184 | ||
185 | static u32 dsi_get_bpp(const enum mipi_dsi_pixel_format fmt) | |
186 | { | |
187 | switch (fmt) { | |
188 | case MIPI_DSI_FMT_RGB565: return 16; | |
189 | case MIPI_DSI_FMT_RGB666_PACKED: return 18; | |
190 | case MIPI_DSI_FMT_RGB666: | |
191 | case MIPI_DSI_FMT_RGB888: | |
192 | default: return 24; | |
193 | } | |
194 | } | |
195 | ||
196 | static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg) | |
197 | { | |
d248b61f | 198 | return msm_readl(msm_host->ctrl_base + reg); |
a689554b HL |
199 | } |
200 | static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data) | |
201 | { | |
d248b61f | 202 | msm_writel(data, msm_host->ctrl_base + reg); |
a689554b HL |
203 | } |
204 | ||
d248b61f HL |
205 | static const struct msm_dsi_cfg_handler *dsi_get_config( |
206 | struct msm_dsi_host *msm_host) | |
a689554b | 207 | { |
d248b61f | 208 | const struct msm_dsi_cfg_handler *cfg_hnd = NULL; |
31c92767 | 209 | struct device *dev = &msm_host->pdev->dev; |
31c92767 | 210 | struct clk *ahb_clk; |
d248b61f | 211 | int ret; |
a689554b HL |
212 | u32 major = 0, minor = 0; |
213 | ||
29a1157c | 214 | ahb_clk = msm_clk_get(msm_host->pdev, "iface"); |
31c92767 AT |
215 | if (IS_ERR(ahb_clk)) { |
216 | pr_err("%s: cannot get interface clock\n", __func__); | |
b93cc4b2 | 217 | goto exit; |
31c92767 AT |
218 | } |
219 | ||
f6be1121 AT |
220 | pm_runtime_get_sync(dev); |
221 | ||
31c92767 | 222 | ret = clk_prepare_enable(ahb_clk); |
a689554b HL |
223 | if (ret) { |
224 | pr_err("%s: unable to enable ahb_clk\n", __func__); | |
b93cc4b2 | 225 | goto runtime_put; |
a689554b HL |
226 | } |
227 | ||
228 | ret = dsi_get_version(msm_host->ctrl_base, &major, &minor); | |
a689554b HL |
229 | if (ret) { |
230 | pr_err("%s: Invalid version\n", __func__); | |
d248b61f | 231 | goto disable_clks; |
a689554b HL |
232 | } |
233 | ||
d248b61f | 234 | cfg_hnd = msm_dsi_cfg_get(major, minor); |
a689554b | 235 | |
d248b61f HL |
236 | DBG("%s: Version %x:%x\n", __func__, major, minor); |
237 | ||
238 | disable_clks: | |
31c92767 | 239 | clk_disable_unprepare(ahb_clk); |
b93cc4b2 | 240 | runtime_put: |
a18a0ea0 | 241 | pm_runtime_put_sync(dev); |
d248b61f HL |
242 | exit: |
243 | return cfg_hnd; | |
a689554b HL |
244 | } |
245 | ||
246 | static inline struct msm_dsi_host *to_msm_dsi_host(struct mipi_dsi_host *host) | |
247 | { | |
248 | return container_of(host, struct msm_dsi_host, base); | |
249 | } | |
250 | ||
c4d8cfe5 SS |
251 | int dsi_clk_init_v2(struct msm_dsi_host *msm_host) |
252 | { | |
253 | struct platform_device *pdev = msm_host->pdev; | |
254 | int ret = 0; | |
255 | ||
256 | msm_host->src_clk = msm_clk_get(pdev, "src"); | |
257 | ||
258 | if (IS_ERR(msm_host->src_clk)) { | |
259 | ret = PTR_ERR(msm_host->src_clk); | |
260 | pr_err("%s: can't find src clock. ret=%d\n", | |
261 | __func__, ret); | |
262 | msm_host->src_clk = NULL; | |
263 | return ret; | |
264 | } | |
265 | ||
c4d8cfe5 SS |
266 | return ret; |
267 | } | |
268 | ||
269 | int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host) | |
270 | { | |
271 | struct platform_device *pdev = msm_host->pdev; | |
272 | int ret = 0; | |
273 | ||
274 | msm_host->byte_intf_clk = msm_clk_get(pdev, "byte_intf"); | |
275 | if (IS_ERR(msm_host->byte_intf_clk)) { | |
276 | ret = PTR_ERR(msm_host->byte_intf_clk); | |
277 | pr_err("%s: can't find byte_intf clock. ret=%d\n", | |
278 | __func__, ret); | |
279 | } | |
280 | ||
281 | return ret; | |
282 | } | |
283 | ||
a689554b HL |
284 | static int dsi_clk_init(struct msm_dsi_host *msm_host) |
285 | { | |
db9a3750 | 286 | struct platform_device *pdev = msm_host->pdev; |
4bfa9748 AT |
287 | const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; |
288 | const struct msm_dsi_config *cfg = cfg_hnd->cfg; | |
6e0eb52e AT |
289 | int i, ret = 0; |
290 | ||
291 | /* get bus clocks */ | |
d9fbb54d DB |
292 | for (i = 0; i < cfg->num_bus_clks; i++) |
293 | msm_host->bus_clks[i].id = cfg->bus_clk_names[i]; | |
294 | msm_host->num_bus_clks = cfg->num_bus_clks; | |
295 | ||
296 | ret = devm_clk_bulk_get(&pdev->dev, msm_host->num_bus_clks, msm_host->bus_clks); | |
297 | if (ret < 0) { | |
298 | dev_err(&pdev->dev, "Unable to get clocks, ret = %d\n", ret); | |
299 | goto exit; | |
a689554b HL |
300 | } |
301 | ||
6e0eb52e | 302 | /* get link and source clocks */ |
db9a3750 | 303 | msm_host->byte_clk = msm_clk_get(pdev, "byte"); |
a689554b HL |
304 | if (IS_ERR(msm_host->byte_clk)) { |
305 | ret = PTR_ERR(msm_host->byte_clk); | |
db9a3750 | 306 | pr_err("%s: can't find dsi_byte clock. ret=%d\n", |
a689554b HL |
307 | __func__, ret); |
308 | msm_host->byte_clk = NULL; | |
309 | goto exit; | |
310 | } | |
311 | ||
db9a3750 | 312 | msm_host->pixel_clk = msm_clk_get(pdev, "pixel"); |
a689554b HL |
313 | if (IS_ERR(msm_host->pixel_clk)) { |
314 | ret = PTR_ERR(msm_host->pixel_clk); | |
db9a3750 | 315 | pr_err("%s: can't find dsi_pixel clock. ret=%d\n", |
a689554b HL |
316 | __func__, ret); |
317 | msm_host->pixel_clk = NULL; | |
318 | goto exit; | |
319 | } | |
320 | ||
db9a3750 | 321 | msm_host->esc_clk = msm_clk_get(pdev, "core"); |
a689554b HL |
322 | if (IS_ERR(msm_host->esc_clk)) { |
323 | ret = PTR_ERR(msm_host->esc_clk); | |
db9a3750 | 324 | pr_err("%s: can't find dsi_esc clock. ret=%d\n", |
a689554b HL |
325 | __func__, ret); |
326 | msm_host->esc_clk = NULL; | |
327 | goto exit; | |
328 | } | |
329 | ||
8f7ca540 SS |
330 | if (cfg_hnd->ops->clk_init_ver) |
331 | ret = cfg_hnd->ops->clk_init_ver(msm_host); | |
a689554b HL |
332 | exit: |
333 | return ret; | |
334 | } | |
335 | ||
f54ca1a0 AT |
336 | int msm_dsi_runtime_suspend(struct device *dev) |
337 | { | |
338 | struct platform_device *pdev = to_platform_device(dev); | |
339 | struct msm_dsi *msm_dsi = platform_get_drvdata(pdev); | |
340 | struct mipi_dsi_host *host = msm_dsi->host; | |
341 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
342 | ||
343 | if (!msm_host->cfg_hnd) | |
344 | return 0; | |
345 | ||
d9fbb54d | 346 | clk_bulk_disable_unprepare(msm_host->num_bus_clks, msm_host->bus_clks); |
f54ca1a0 AT |
347 | |
348 | return 0; | |
349 | } | |
350 | ||
351 | int msm_dsi_runtime_resume(struct device *dev) | |
352 | { | |
353 | struct platform_device *pdev = to_platform_device(dev); | |
354 | struct msm_dsi *msm_dsi = platform_get_drvdata(pdev); | |
355 | struct mipi_dsi_host *host = msm_dsi->host; | |
356 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
357 | ||
358 | if (!msm_host->cfg_hnd) | |
359 | return 0; | |
360 | ||
d9fbb54d | 361 | return clk_bulk_prepare_enable(msm_host->num_bus_clks, msm_host->bus_clks); |
f54ca1a0 AT |
362 | } |
363 | ||
6b16f05a | 364 | int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host) |
a689554b HL |
365 | { |
366 | int ret; | |
367 | ||
409af447 | 368 | DBG("Set clk rates: pclk=%d, byteclk=%lu", |
a689554b HL |
369 | msm_host->mode->clock, msm_host->byte_clk_rate); |
370 | ||
32d3e0fe RN |
371 | ret = dev_pm_opp_set_rate(&msm_host->pdev->dev, |
372 | msm_host->byte_clk_rate); | |
a689554b | 373 | if (ret) { |
32d3e0fe | 374 | pr_err("%s: dev_pm_opp_set_rate failed %d\n", __func__, ret); |
6b16f05a | 375 | return ret; |
a689554b HL |
376 | } |
377 | ||
ed9976a0 | 378 | ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); |
a689554b HL |
379 | if (ret) { |
380 | pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); | |
6b16f05a | 381 | return ret; |
a689554b HL |
382 | } |
383 | ||
c1d97083 | 384 | if (msm_host->byte_intf_clk) { |
1d5e01df | 385 | ret = clk_set_rate(msm_host->byte_intf_clk, msm_host->byte_intf_clk_rate); |
c1d97083 AT |
386 | if (ret) { |
387 | pr_err("%s: Failed to set rate byte intf clk, %d\n", | |
388 | __func__, ret); | |
6b16f05a | 389 | return ret; |
c1d97083 AT |
390 | } |
391 | } | |
392 | ||
6b16f05a RC |
393 | return 0; |
394 | } | |
395 | ||
396 | ||
397 | int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host) | |
398 | { | |
399 | int ret; | |
400 | ||
a689554b HL |
401 | ret = clk_prepare_enable(msm_host->esc_clk); |
402 | if (ret) { | |
403 | pr_err("%s: Failed to enable dsi esc clk\n", __func__); | |
404 | goto error; | |
405 | } | |
406 | ||
407 | ret = clk_prepare_enable(msm_host->byte_clk); | |
408 | if (ret) { | |
409 | pr_err("%s: Failed to enable dsi byte clk\n", __func__); | |
410 | goto byte_clk_err; | |
411 | } | |
412 | ||
413 | ret = clk_prepare_enable(msm_host->pixel_clk); | |
414 | if (ret) { | |
415 | pr_err("%s: Failed to enable dsi pixel clk\n", __func__); | |
416 | goto pixel_clk_err; | |
417 | } | |
418 | ||
993247ff XW |
419 | ret = clk_prepare_enable(msm_host->byte_intf_clk); |
420 | if (ret) { | |
421 | pr_err("%s: Failed to enable byte intf clk\n", | |
422 | __func__); | |
423 | goto byte_intf_clk_err; | |
c1d97083 AT |
424 | } |
425 | ||
a689554b HL |
426 | return 0; |
427 | ||
c1d97083 AT |
428 | byte_intf_clk_err: |
429 | clk_disable_unprepare(msm_host->pixel_clk); | |
a689554b HL |
430 | pixel_clk_err: |
431 | clk_disable_unprepare(msm_host->byte_clk); | |
432 | byte_clk_err: | |
433 | clk_disable_unprepare(msm_host->esc_clk); | |
434 | error: | |
435 | return ret; | |
436 | } | |
437 | ||
6b16f05a | 438 | int dsi_link_clk_set_rate_v2(struct msm_dsi_host *msm_host) |
a689554b | 439 | { |
4bfa9748 AT |
440 | int ret; |
441 | ||
409af447 | 442 | DBG("Set clk rates: pclk=%d, byteclk=%lu, esc_clk=%lu, dsi_src_clk=%lu", |
4bfa9748 AT |
443 | msm_host->mode->clock, msm_host->byte_clk_rate, |
444 | msm_host->esc_clk_rate, msm_host->src_clk_rate); | |
445 | ||
446 | ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate); | |
447 | if (ret) { | |
448 | pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret); | |
6b16f05a | 449 | return ret; |
4bfa9748 AT |
450 | } |
451 | ||
452 | ret = clk_set_rate(msm_host->esc_clk, msm_host->esc_clk_rate); | |
453 | if (ret) { | |
454 | pr_err("%s: Failed to set rate esc clk, %d\n", __func__, ret); | |
6b16f05a | 455 | return ret; |
4bfa9748 AT |
456 | } |
457 | ||
458 | ret = clk_set_rate(msm_host->src_clk, msm_host->src_clk_rate); | |
459 | if (ret) { | |
460 | pr_err("%s: Failed to set rate src clk, %d\n", __func__, ret); | |
6b16f05a | 461 | return ret; |
4bfa9748 AT |
462 | } |
463 | ||
ed9976a0 | 464 | ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); |
4bfa9748 AT |
465 | if (ret) { |
466 | pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); | |
6b16f05a | 467 | return ret; |
4bfa9748 AT |
468 | } |
469 | ||
6b16f05a RC |
470 | return 0; |
471 | } | |
472 | ||
473 | int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host) | |
474 | { | |
475 | int ret; | |
476 | ||
4bfa9748 AT |
477 | ret = clk_prepare_enable(msm_host->byte_clk); |
478 | if (ret) { | |
479 | pr_err("%s: Failed to enable dsi byte clk\n", __func__); | |
480 | goto error; | |
481 | } | |
482 | ||
483 | ret = clk_prepare_enable(msm_host->esc_clk); | |
484 | if (ret) { | |
485 | pr_err("%s: Failed to enable dsi esc clk\n", __func__); | |
486 | goto esc_clk_err; | |
487 | } | |
488 | ||
489 | ret = clk_prepare_enable(msm_host->src_clk); | |
490 | if (ret) { | |
491 | pr_err("%s: Failed to enable dsi src clk\n", __func__); | |
492 | goto src_clk_err; | |
493 | } | |
494 | ||
495 | ret = clk_prepare_enable(msm_host->pixel_clk); | |
496 | if (ret) { | |
497 | pr_err("%s: Failed to enable dsi pixel clk\n", __func__); | |
498 | goto pixel_clk_err; | |
499 | } | |
500 | ||
501 | return 0; | |
502 | ||
503 | pixel_clk_err: | |
504 | clk_disable_unprepare(msm_host->src_clk); | |
505 | src_clk_err: | |
a689554b | 506 | clk_disable_unprepare(msm_host->esc_clk); |
4bfa9748 | 507 | esc_clk_err: |
a689554b | 508 | clk_disable_unprepare(msm_host->byte_clk); |
4bfa9748 AT |
509 | error: |
510 | return ret; | |
511 | } | |
512 | ||
c4d8cfe5 SS |
513 | void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host) |
514 | { | |
32d3e0fe RN |
515 | /* Drop the performance state vote */ |
516 | dev_pm_opp_set_rate(&msm_host->pdev->dev, 0); | |
c4d8cfe5 SS |
517 | clk_disable_unprepare(msm_host->esc_clk); |
518 | clk_disable_unprepare(msm_host->pixel_clk); | |
993247ff | 519 | clk_disable_unprepare(msm_host->byte_intf_clk); |
c4d8cfe5 SS |
520 | clk_disable_unprepare(msm_host->byte_clk); |
521 | } | |
522 | ||
523 | void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host) | |
524 | { | |
525 | clk_disable_unprepare(msm_host->pixel_clk); | |
526 | clk_disable_unprepare(msm_host->src_clk); | |
527 | clk_disable_unprepare(msm_host->esc_clk); | |
528 | clk_disable_unprepare(msm_host->byte_clk); | |
529 | } | |
530 | ||
7c9e4a55 JZ |
531 | static unsigned long dsi_adjust_pclk_for_compression(const struct drm_display_mode *mode, |
532 | const struct drm_dsc_config *dsc) | |
533 | { | |
534 | int new_hdisplay = DIV_ROUND_UP(mode->hdisplay * drm_dsc_get_bpp_int(dsc), | |
535 | dsc->bits_per_component * 3); | |
536 | ||
537 | int new_htotal = mode->htotal - mode->hdisplay + new_hdisplay; | |
538 | ||
539 | return new_htotal * mode->vtotal * drm_mode_vrefresh(mode); | |
540 | } | |
541 | ||
542 | static unsigned long dsi_get_pclk_rate(const struct drm_display_mode *mode, | |
543 | const struct drm_dsc_config *dsc, bool is_bonded_dsi) | |
c4d8cfe5 | 544 | { |
409af447 | 545 | unsigned long pclk_rate; |
c4d8cfe5 SS |
546 | |
547 | pclk_rate = mode->clock * 1000; | |
ed9976a0 | 548 | |
7c9e4a55 JZ |
549 | if (dsc) |
550 | pclk_rate = dsi_adjust_pclk_for_compression(mode, dsc); | |
551 | ||
ed9976a0 | 552 | /* |
6183606d | 553 | * For bonded DSI mode, the current DRM mode has the complete width of the |
ed9976a0 | 554 | * panel. Since, the complete panel is driven by two DSI controllers, |
a6bcddbc | 555 | * the clock rates have to be split between the two dsi controllers. |
ed9976a0 CU |
556 | * Adjust the byte and pixel clock rates for each dsi host accordingly. |
557 | */ | |
6183606d | 558 | if (is_bonded_dsi) |
ed9976a0 CU |
559 | pclk_rate /= 2; |
560 | ||
a6bcddbc SP |
561 | return pclk_rate; |
562 | } | |
563 | ||
03f7b782 AK |
564 | unsigned long dsi_byte_clk_get_rate(struct mipi_dsi_host *host, bool is_bonded_dsi, |
565 | const struct drm_display_mode *mode) | |
a6bcddbc | 566 | { |
03f7b782 | 567 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); |
a6bcddbc SP |
568 | u8 lanes = msm_host->lanes; |
569 | u32 bpp = dsi_get_bpp(msm_host->format); | |
7c9e4a55 | 570 | unsigned long pclk_rate = dsi_get_pclk_rate(mode, msm_host->dsc, is_bonded_dsi); |
374918d2 | 571 | unsigned long pclk_bpp; |
a6bcddbc SP |
572 | |
573 | if (lanes == 0) { | |
c4d8cfe5 | 574 | pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__); |
a6bcddbc | 575 | lanes = 1; |
c4d8cfe5 SS |
576 | } |
577 | ||
5ac17838 JM |
578 | /* CPHY "byte_clk" is in units of 16 bits */ |
579 | if (msm_host->cphy_mode) | |
374918d2 | 580 | pclk_bpp = mult_frac(pclk_rate, bpp, 16 * lanes); |
5ac17838 | 581 | else |
374918d2 | 582 | pclk_bpp = mult_frac(pclk_rate, bpp, 8 * lanes); |
c4d8cfe5 | 583 | |
03f7b782 AK |
584 | return pclk_bpp; |
585 | } | |
586 | ||
587 | static void dsi_calc_pclk(struct msm_dsi_host *msm_host, bool is_bonded_dsi) | |
588 | { | |
7c9e4a55 | 589 | msm_host->pixel_clk_rate = dsi_get_pclk_rate(msm_host->mode, msm_host->dsc, is_bonded_dsi); |
03f7b782 AK |
590 | msm_host->byte_clk_rate = dsi_byte_clk_get_rate(&msm_host->base, is_bonded_dsi, |
591 | msm_host->mode); | |
a6bcddbc | 592 | |
409af447 | 593 | DBG("pclk=%lu, bclk=%lu", msm_host->pixel_clk_rate, |
a6bcddbc SP |
594 | msm_host->byte_clk_rate); |
595 | ||
596 | } | |
597 | ||
6183606d | 598 | int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_bonded_dsi) |
a6bcddbc SP |
599 | { |
600 | if (!msm_host->mode) { | |
601 | pr_err("%s: mode not set\n", __func__); | |
602 | return -EINVAL; | |
603 | } | |
c4d8cfe5 | 604 | |
6183606d | 605 | dsi_calc_pclk(msm_host, is_bonded_dsi); |
a6bcddbc | 606 | msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk); |
c4d8cfe5 SS |
607 | return 0; |
608 | } | |
609 | ||
6183606d | 610 | int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi) |
c4d8cfe5 | 611 | { |
c4d8cfe5 | 612 | u32 bpp = dsi_get_bpp(msm_host->format); |
c4d8cfe5 SS |
613 | unsigned int esc_mhz, esc_div; |
614 | unsigned long byte_mhz; | |
615 | ||
6183606d | 616 | dsi_calc_pclk(msm_host, is_bonded_dsi); |
c4d8cfe5 | 617 | |
374918d2 | 618 | msm_host->src_clk_rate = mult_frac(msm_host->pixel_clk_rate, bpp, 8); |
c4d8cfe5 SS |
619 | |
620 | /* | |
621 | * esc clock is byte clock followed by a 4 bit divider, | |
622 | * we need to find an escape clock frequency within the | |
623 | * mipi DSI spec range within the maximum divider limit | |
624 | * We iterate here between an escape clock frequencey | |
625 | * between 20 Mhz to 5 Mhz and pick up the first one | |
626 | * that can be supported by our divider | |
627 | */ | |
628 | ||
629 | byte_mhz = msm_host->byte_clk_rate / 1000000; | |
630 | ||
631 | for (esc_mhz = 20; esc_mhz >= 5; esc_mhz--) { | |
632 | esc_div = DIV_ROUND_UP(byte_mhz, esc_mhz); | |
633 | ||
634 | /* | |
635 | * TODO: Ideally, we shouldn't know what sort of divider | |
636 | * is available in mmss_cc, we're just assuming that | |
637 | * it'll always be a 4 bit divider. Need to come up with | |
638 | * a better way here. | |
639 | */ | |
640 | if (esc_div >= 1 && esc_div <= 16) | |
641 | break; | |
642 | } | |
643 | ||
644 | if (esc_mhz < 5) | |
645 | return -EINVAL; | |
646 | ||
647 | msm_host->esc_clk_rate = msm_host->byte_clk_rate / esc_div; | |
648 | ||
409af447 | 649 | DBG("esc=%lu, src=%lu", msm_host->esc_clk_rate, |
c4d8cfe5 SS |
650 | msm_host->src_clk_rate); |
651 | ||
652 | return 0; | |
653 | } | |
654 | ||
a689554b HL |
655 | static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable) |
656 | { | |
657 | u32 intr; | |
658 | unsigned long flags; | |
659 | ||
660 | spin_lock_irqsave(&msm_host->intr_lock, flags); | |
661 | intr = dsi_read(msm_host, REG_DSI_INTR_CTRL); | |
662 | ||
663 | if (enable) | |
664 | intr |= mask; | |
665 | else | |
666 | intr &= ~mask; | |
667 | ||
668 | DBG("intr=%x enable=%d", intr, enable); | |
669 | ||
670 | dsi_write(msm_host, REG_DSI_INTR_CTRL, intr); | |
671 | spin_unlock_irqrestore(&msm_host->intr_lock, flags); | |
672 | } | |
673 | ||
674 | static inline enum dsi_traffic_mode dsi_get_traffic_mode(const u32 mode_flags) | |
675 | { | |
676 | if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) | |
677 | return BURST_MODE; | |
678 | else if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) | |
679 | return NON_BURST_SYNCH_PULSE; | |
680 | ||
681 | return NON_BURST_SYNCH_EVENT; | |
682 | } | |
683 | ||
684 | static inline enum dsi_vid_dst_format dsi_get_vid_fmt( | |
685 | const enum mipi_dsi_pixel_format mipi_fmt) | |
686 | { | |
687 | switch (mipi_fmt) { | |
688 | case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888; | |
689 | case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666_LOOSE; | |
690 | case MIPI_DSI_FMT_RGB666_PACKED: return VID_DST_FORMAT_RGB666; | |
691 | case MIPI_DSI_FMT_RGB565: return VID_DST_FORMAT_RGB565; | |
692 | default: return VID_DST_FORMAT_RGB888; | |
693 | } | |
694 | } | |
695 | ||
696 | static inline enum dsi_cmd_dst_format dsi_get_cmd_fmt( | |
697 | const enum mipi_dsi_pixel_format mipi_fmt) | |
698 | { | |
699 | switch (mipi_fmt) { | |
700 | case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888; | |
701 | case MIPI_DSI_FMT_RGB666_PACKED: | |
cf606fe3 | 702 | case MIPI_DSI_FMT_RGB666: return CMD_DST_FORMAT_RGB666; |
a689554b HL |
703 | case MIPI_DSI_FMT_RGB565: return CMD_DST_FORMAT_RGB565; |
704 | default: return CMD_DST_FORMAT_RGB888; | |
705 | } | |
706 | } | |
707 | ||
452c46cc DB |
708 | static void dsi_ctrl_disable(struct msm_dsi_host *msm_host) |
709 | { | |
710 | dsi_write(msm_host, REG_DSI_CTRL, 0); | |
711 | } | |
712 | ||
713 | static void dsi_ctrl_enable(struct msm_dsi_host *msm_host, | |
858c595a | 714 | struct msm_dsi_phy_shared_timings *phy_shared_timings, struct msm_dsi_phy *phy) |
a689554b HL |
715 | { |
716 | u32 flags = msm_host->mode_flags; | |
717 | enum mipi_dsi_pixel_format mipi_fmt = msm_host->format; | |
d248b61f | 718 | const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; |
e3ff6881 | 719 | u32 data = 0, lane_ctrl = 0; |
a689554b | 720 | |
a689554b HL |
721 | if (flags & MIPI_DSI_MODE_VIDEO) { |
722 | if (flags & MIPI_DSI_MODE_VIDEO_HSE) | |
723 | data |= DSI_VID_CFG0_PULSE_MODE_HSA_HE; | |
0f3b68b6 | 724 | if (flags & MIPI_DSI_MODE_VIDEO_NO_HFP) |
a689554b | 725 | data |= DSI_VID_CFG0_HFP_POWER_STOP; |
0f3b68b6 | 726 | if (flags & MIPI_DSI_MODE_VIDEO_NO_HBP) |
a689554b | 727 | data |= DSI_VID_CFG0_HBP_POWER_STOP; |
0f3b68b6 | 728 | if (flags & MIPI_DSI_MODE_VIDEO_NO_HSA) |
a689554b HL |
729 | data |= DSI_VID_CFG0_HSA_POWER_STOP; |
730 | /* Always set low power stop mode for BLLP | |
731 | * to let command engine send packets | |
732 | */ | |
733 | data |= DSI_VID_CFG0_EOF_BLLP_POWER_STOP | | |
734 | DSI_VID_CFG0_BLLP_POWER_STOP; | |
735 | data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags)); | |
736 | data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt)); | |
737 | data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel); | |
738 | dsi_write(msm_host, REG_DSI_VID_CFG0, data); | |
739 | ||
740 | /* Do not swap RGB colors */ | |
741 | data = DSI_VID_CFG1_RGB_SWAP(SWAP_RGB); | |
742 | dsi_write(msm_host, REG_DSI_VID_CFG1, 0); | |
743 | } else { | |
744 | /* Do not swap RGB colors */ | |
745 | data = DSI_CMD_CFG0_RGB_SWAP(SWAP_RGB); | |
746 | data |= DSI_CMD_CFG0_DST_FORMAT(dsi_get_cmd_fmt(mipi_fmt)); | |
747 | dsi_write(msm_host, REG_DSI_CMD_CFG0, data); | |
748 | ||
749 | data = DSI_CMD_CFG1_WR_MEM_START(MIPI_DCS_WRITE_MEMORY_START) | | |
750 | DSI_CMD_CFG1_WR_MEM_CONTINUE( | |
751 | MIPI_DCS_WRITE_MEMORY_CONTINUE); | |
752 | /* Always insert DCS command */ | |
753 | data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND; | |
754 | dsi_write(msm_host, REG_DSI_CMD_CFG1, data); | |
b173a7dc JZ |
755 | |
756 | if (msm_host->cfg_hnd->major == MSM_DSI_VER_MAJOR_6G && | |
757 | msm_host->cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_3) { | |
758 | data = dsi_read(msm_host, REG_DSI_CMD_MODE_MDP_CTRL2); | |
759 | data |= DSI_CMD_MODE_MDP_CTRL2_BURST_MODE; | |
760 | dsi_write(msm_host, REG_DSI_CMD_MODE_MDP_CTRL2, data); | |
761 | } | |
a689554b HL |
762 | } |
763 | ||
764 | dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, | |
765 | DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER | | |
766 | DSI_CMD_DMA_CTRL_LOW_POWER); | |
767 | ||
768 | data = 0; | |
769 | /* Always assume dedicated TE pin */ | |
770 | data |= DSI_TRIG_CTRL_TE; | |
771 | data |= DSI_TRIG_CTRL_MDP_TRIGGER(TRIGGER_NONE); | |
772 | data |= DSI_TRIG_CTRL_DMA_TRIGGER(TRIGGER_SW); | |
773 | data |= DSI_TRIG_CTRL_STREAM(msm_host->channel); | |
d248b61f HL |
774 | if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && |
775 | (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_2)) | |
a689554b HL |
776 | data |= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME; |
777 | dsi_write(msm_host, REG_DSI_TRIG_CTRL, data); | |
778 | ||
dceac340 HL |
779 | data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(phy_shared_timings->clk_post) | |
780 | DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(phy_shared_timings->clk_pre); | |
a689554b HL |
781 | dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data); |
782 | ||
dceac340 HL |
783 | if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && |
784 | (cfg_hnd->minor > MSM_DSI_6G_VER_MINOR_V1_0) && | |
785 | phy_shared_timings->clk_pre_inc_by_2) | |
786 | dsi_write(msm_host, REG_DSI_T_CLK_PRE_EXTEND, | |
787 | DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK); | |
788 | ||
a689554b | 789 | data = 0; |
0f3b68b6 | 790 | if (!(flags & MIPI_DSI_MODE_NO_EOT_PACKET)) |
a689554b HL |
791 | data |= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND; |
792 | dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data); | |
793 | ||
794 | /* allow only ack-err-status to generate interrupt */ | |
795 | dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0); | |
796 | ||
797 | dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1); | |
798 | ||
799 | dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); | |
800 | ||
801 | data = DSI_CTRL_CLK_EN; | |
802 | ||
803 | DBG("lane number=%d", msm_host->lanes); | |
26f7d1f4 AT |
804 | data |= ((DSI_CTRL_LANE0 << msm_host->lanes) - DSI_CTRL_LANE0); |
805 | ||
806 | dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL, | |
807 | DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host->dlane_swap)); | |
65c5e542 | 808 | |
e3ff6881 H |
809 | if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) { |
810 | lane_ctrl = dsi_read(msm_host, REG_DSI_LANE_CTRL); | |
858c595a | 811 | |
452c46cc | 812 | if (msm_dsi_phy_set_continuous_clock(phy, true)) |
858c595a DB |
813 | lane_ctrl &= ~DSI_LANE_CTRL_HS_REQ_SEL_PHY; |
814 | ||
65c5e542 | 815 | dsi_write(msm_host, REG_DSI_LANE_CTRL, |
e3ff6881 H |
816 | lane_ctrl | DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST); |
817 | } | |
65c5e542 | 818 | |
a689554b HL |
819 | data |= DSI_CTRL_ENABLE; |
820 | ||
821 | dsi_write(msm_host, REG_DSI_CTRL, data); | |
5ac17838 JM |
822 | |
823 | if (msm_host->cphy_mode) | |
824 | dsi_write(msm_host, REG_DSI_CPHY_MODE_CTRL, BIT(0)); | |
a689554b HL |
825 | } |
826 | ||
08802f51 VK |
827 | static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mode, u32 hdisplay) |
828 | { | |
4b2b1b36 | 829 | struct drm_dsc_config *dsc = msm_host->dsc; |
170ffca8 | 830 | u32 reg, reg_ctrl, reg_ctrl2; |
08802f51 VK |
831 | u32 slice_per_intf, total_bytes_per_intf; |
832 | u32 pkt_per_line; | |
08802f51 VK |
833 | u32 eol_byte_num; |
834 | ||
835 | /* first calculate dsc parameters and then program | |
836 | * compress mode registers | |
837 | */ | |
ed1498f7 | 838 | slice_per_intf = msm_dsc_get_slices_per_intf(dsc, hdisplay); |
08802f51 | 839 | |
e443459e | 840 | total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf; |
08802f51 VK |
841 | |
842 | eol_byte_num = total_bytes_per_intf % 3; | |
155fa3a9 JZ |
843 | |
844 | /* | |
845 | * Typically, pkt_per_line = slice_per_intf * slice_per_pkt. | |
846 | * | |
847 | * Since the current driver only supports slice_per_pkt = 1, | |
848 | * pkt_per_line will be equal to slice per intf for now. | |
849 | */ | |
850 | pkt_per_line = slice_per_intf; | |
08802f51 VK |
851 | |
852 | if (is_cmd_mode) /* packet data type */ | |
853 | reg = DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(MIPI_DSI_DCS_LONG_WRITE); | |
854 | else | |
855 | reg = DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE(MIPI_DSI_COMPRESSED_PIXEL_STREAM); | |
856 | ||
857 | /* DSI_VIDEO_COMPRESSION_MODE & DSI_COMMAND_COMPRESSION_MODE | |
858 | * registers have similar offsets, so for below common code use | |
859 | * DSI_VIDEO_COMPRESSION_MODE_XXXX for setting bits | |
860 | */ | |
861 | reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE(pkt_per_line >> 1); | |
862 | reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM(eol_byte_num); | |
863 | reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EN; | |
864 | ||
865 | if (is_cmd_mode) { | |
866 | reg_ctrl = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL); | |
867 | reg_ctrl2 = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2); | |
868 | ||
666a68a7 | 869 | reg_ctrl &= ~0xffff; |
08802f51 | 870 | reg_ctrl |= reg; |
666a68a7 DB |
871 | |
872 | reg_ctrl2 &= ~DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__MASK; | |
e443459e | 873 | reg_ctrl2 |= DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH(dsc->slice_chunk_size); |
08802f51 | 874 | |
666a68a7 | 875 | dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL, reg_ctrl); |
08802f51 VK |
876 | dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2, reg_ctrl2); |
877 | } else { | |
878 | dsi_write(msm_host, REG_DSI_VIDEO_COMPRESSION_MODE_CTRL, reg); | |
879 | } | |
880 | } | |
881 | ||
6183606d | 882 | static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) |
a689554b HL |
883 | { |
884 | struct drm_display_mode *mode = msm_host->mode; | |
885 | u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */ | |
886 | u32 h_total = mode->htotal; | |
887 | u32 v_total = mode->vtotal; | |
888 | u32 hs_end = mode->hsync_end - mode->hsync_start; | |
889 | u32 vs_end = mode->vsync_end - mode->vsync_start; | |
890 | u32 ha_start = h_total - mode->hsync_start; | |
891 | u32 ha_end = ha_start + mode->hdisplay; | |
892 | u32 va_start = v_total - mode->vsync_start; | |
893 | u32 va_end = va_start + mode->vdisplay; | |
ed9976a0 | 894 | u32 hdisplay = mode->hdisplay; |
a689554b | 895 | u32 wc; |
d2c277c6 | 896 | int ret; |
a689554b HL |
897 | |
898 | DBG(""); | |
899 | ||
ed9976a0 | 900 | /* |
6183606d | 901 | * For bonded DSI mode, the current DRM mode has |
ed9976a0 CU |
902 | * the complete width of the panel. Since, the complete |
903 | * panel is driven by two DSI controllers, the horizontal | |
904 | * timings have to be split between the two dsi controllers. | |
905 | * Adjust the DSI host timing values accordingly. | |
906 | */ | |
6183606d | 907 | if (is_bonded_dsi) { |
ed9976a0 CU |
908 | h_total /= 2; |
909 | hs_end /= 2; | |
910 | ha_start /= 2; | |
911 | ha_end /= 2; | |
912 | hdisplay /= 2; | |
913 | } | |
914 | ||
08802f51 | 915 | if (msm_host->dsc) { |
4b2b1b36 | 916 | struct drm_dsc_config *dsc = msm_host->dsc; |
08802f51 VK |
917 | |
918 | /* update dsc params with timing params */ | |
919 | if (!dsc || !mode->hdisplay || !mode->vdisplay) { | |
920 | pr_err("DSI: invalid input: pic_width: %d pic_height: %d\n", | |
921 | mode->hdisplay, mode->vdisplay); | |
922 | return; | |
923 | } | |
924 | ||
4b2b1b36 DB |
925 | dsc->pic_width = mode->hdisplay; |
926 | dsc->pic_height = mode->vdisplay; | |
927 | DBG("Mode %dx%d\n", dsc->pic_width, dsc->pic_height); | |
08802f51 VK |
928 | |
929 | /* we do the calculations for dsc parameters here so that | |
930 | * panel can use these parameters | |
931 | */ | |
d2c277c6 MS |
932 | ret = dsi_populate_dsc_params(msm_host, dsc); |
933 | if (ret) | |
934 | return; | |
08802f51 VK |
935 | |
936 | /* Divide the display by 3 but keep back/font porch and | |
937 | * pulse width same | |
938 | */ | |
939 | h_total -= hdisplay; | |
21bf6171 | 940 | hdisplay = DIV_ROUND_UP(msm_dsc_get_bytes_per_line(msm_host->dsc), 3); |
08802f51 VK |
941 | h_total += hdisplay; |
942 | ha_end = ha_start + hdisplay; | |
943 | } | |
944 | ||
a689554b | 945 | if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) { |
08802f51 VK |
946 | if (msm_host->dsc) |
947 | dsi_update_dsc_timing(msm_host, false, mode->hdisplay); | |
948 | ||
a689554b HL |
949 | dsi_write(msm_host, REG_DSI_ACTIVE_H, |
950 | DSI_ACTIVE_H_START(ha_start) | | |
951 | DSI_ACTIVE_H_END(ha_end)); | |
952 | dsi_write(msm_host, REG_DSI_ACTIVE_V, | |
953 | DSI_ACTIVE_V_START(va_start) | | |
954 | DSI_ACTIVE_V_END(va_end)); | |
955 | dsi_write(msm_host, REG_DSI_TOTAL, | |
956 | DSI_TOTAL_H_TOTAL(h_total - 1) | | |
957 | DSI_TOTAL_V_TOTAL(v_total - 1)); | |
958 | ||
959 | dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC, | |
960 | DSI_ACTIVE_HSYNC_START(hs_start) | | |
961 | DSI_ACTIVE_HSYNC_END(hs_end)); | |
962 | dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0); | |
963 | dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS, | |
964 | DSI_ACTIVE_VSYNC_VPOS_START(vs_start) | | |
965 | DSI_ACTIVE_VSYNC_VPOS_END(vs_end)); | |
966 | } else { /* command mode */ | |
08802f51 VK |
967 | if (msm_host->dsc) |
968 | dsi_update_dsc_timing(msm_host, true, mode->hdisplay); | |
969 | ||
a689554b | 970 | /* image data and 1 byte write_memory_start cmd */ |
08802f51 VK |
971 | if (!msm_host->dsc) |
972 | wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1; | |
973 | else | |
155fa3a9 JZ |
974 | /* |
975 | * When DSC is enabled, WC = slice_chunk_size * slice_per_pkt + 1. | |
976 | * Currently, the driver only supports default value of slice_per_pkt = 1 | |
977 | * | |
978 | * TODO: Expand mipi_dsi_device struct to hold slice_per_pkt info | |
979 | * and adjust DSC math to account for slice_per_pkt. | |
980 | */ | |
981 | wc = msm_host->dsc->slice_chunk_size + 1; | |
a689554b | 982 | |
c28c82e9 RC |
983 | dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL, |
984 | DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) | | |
985 | DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL( | |
a689554b | 986 | msm_host->channel) | |
c28c82e9 | 987 | DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE( |
a689554b HL |
988 | MIPI_DSI_DCS_LONG_WRITE)); |
989 | ||
c28c82e9 RC |
990 | dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_TOTAL, |
991 | DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(hdisplay) | | |
992 | DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(mode->vdisplay)); | |
a689554b HL |
993 | } |
994 | } | |
995 | ||
996 | static void dsi_sw_reset(struct msm_dsi_host *msm_host) | |
997 | { | |
4f0718bf VL |
998 | u32 ctrl; |
999 | ||
1000 | ctrl = dsi_read(msm_host, REG_DSI_CTRL); | |
1001 | ||
1002 | if (ctrl & DSI_CTRL_ENABLE) { | |
1003 | dsi_write(msm_host, REG_DSI_CTRL, ctrl & ~DSI_CTRL_ENABLE); | |
1004 | /* | |
1005 | * dsi controller need to be disabled before | |
1006 | * clocks turned on | |
1007 | */ | |
1008 | wmb(); | |
1009 | } | |
1010 | ||
a689554b HL |
1011 | dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); |
1012 | wmb(); /* clocks need to be enabled before reset */ | |
1013 | ||
4f0718bf | 1014 | /* dsi controller can only be reset while clocks are running */ |
a689554b | 1015 | dsi_write(msm_host, REG_DSI_RESET, 1); |
78e31c42 | 1016 | msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */ |
a689554b | 1017 | dsi_write(msm_host, REG_DSI_RESET, 0); |
4f0718bf VL |
1018 | wmb(); /* controller out of reset */ |
1019 | ||
1020 | if (ctrl & DSI_CTRL_ENABLE) { | |
1021 | dsi_write(msm_host, REG_DSI_CTRL, ctrl); | |
1022 | wmb(); /* make sure dsi controller enabled again */ | |
1023 | } | |
a689554b HL |
1024 | } |
1025 | ||
1026 | static void dsi_op_mode_config(struct msm_dsi_host *msm_host, | |
1027 | bool video_mode, bool enable) | |
1028 | { | |
1029 | u32 dsi_ctrl; | |
1030 | ||
1031 | dsi_ctrl = dsi_read(msm_host, REG_DSI_CTRL); | |
1032 | ||
1033 | if (!enable) { | |
1034 | dsi_ctrl &= ~(DSI_CTRL_ENABLE | DSI_CTRL_VID_MODE_EN | | |
1035 | DSI_CTRL_CMD_MODE_EN); | |
1036 | dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE | | |
1037 | DSI_IRQ_MASK_VIDEO_DONE, 0); | |
1038 | } else { | |
1039 | if (video_mode) { | |
1040 | dsi_ctrl |= DSI_CTRL_VID_MODE_EN; | |
1041 | } else { /* command mode */ | |
1042 | dsi_ctrl |= DSI_CTRL_CMD_MODE_EN; | |
1043 | dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE, 1); | |
1044 | } | |
1045 | dsi_ctrl |= DSI_CTRL_ENABLE; | |
1046 | } | |
1047 | ||
1048 | dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl); | |
1049 | } | |
1050 | ||
1051 | static void dsi_set_tx_power_mode(int mode, struct msm_dsi_host *msm_host) | |
1052 | { | |
1053 | u32 data; | |
1054 | ||
1055 | data = dsi_read(msm_host, REG_DSI_CMD_DMA_CTRL); | |
1056 | ||
1057 | if (mode == 0) | |
1058 | data &= ~DSI_CMD_DMA_CTRL_LOW_POWER; | |
1059 | else | |
1060 | data |= DSI_CMD_DMA_CTRL_LOW_POWER; | |
1061 | ||
1062 | dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data); | |
1063 | } | |
1064 | ||
1065 | static void dsi_wait4video_done(struct msm_dsi_host *msm_host) | |
1066 | { | |
79ebc86c AK |
1067 | u32 ret = 0; |
1068 | struct device *dev = &msm_host->pdev->dev; | |
1069 | ||
a689554b HL |
1070 | dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1); |
1071 | ||
1072 | reinit_completion(&msm_host->video_comp); | |
1073 | ||
79ebc86c | 1074 | ret = wait_for_completion_timeout(&msm_host->video_comp, |
a689554b HL |
1075 | msecs_to_jiffies(70)); |
1076 | ||
9a4a153b | 1077 | if (ret == 0) |
6a41da17 | 1078 | DRM_DEV_ERROR(dev, "wait for video done timed out\n"); |
79ebc86c | 1079 | |
a689554b HL |
1080 | dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0); |
1081 | } | |
1082 | ||
1083 | static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host) | |
1084 | { | |
ab483e3a AK |
1085 | u32 data; |
1086 | ||
a689554b HL |
1087 | if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO)) |
1088 | return; | |
1089 | ||
ab483e3a AK |
1090 | data = dsi_read(msm_host, REG_DSI_STATUS0); |
1091 | ||
1092 | /* if video mode engine is not busy, its because | |
1093 | * either timing engine was not turned on or the | |
1094 | * DSI controller has finished transmitting the video | |
1095 | * data already, so no need to wait in those cases | |
1096 | */ | |
1097 | if (!(data & DSI_STATUS0_VIDEO_MODE_ENGINE_BUSY)) | |
1098 | return; | |
1099 | ||
9c5638d7 | 1100 | if (msm_host->power_on && msm_host->enabled) { |
a689554b HL |
1101 | dsi_wait4video_done(msm_host); |
1102 | /* delay 4 ms to skip BLLP */ | |
1103 | usleep_range(2000, 4000); | |
1104 | } | |
1105 | } | |
1106 | ||
c4d8cfe5 SS |
1107 | int dsi_tx_buf_alloc_6g(struct msm_dsi_host *msm_host, int size) |
1108 | { | |
1109 | struct drm_device *dev = msm_host->dev; | |
1110 | struct msm_drm_private *priv = dev->dev_private; | |
1111 | uint64_t iova; | |
1112 | u8 *data; | |
1113 | ||
a5fc7aa9 | 1114 | data = msm_gem_kernel_new(dev, size, MSM_BO_WC, |
c4d8cfe5 SS |
1115 | priv->kms->aspace, |
1116 | &msm_host->tx_gem_obj, &iova); | |
1117 | ||
1118 | if (IS_ERR(data)) { | |
1119 | msm_host->tx_gem_obj = NULL; | |
1120 | return PTR_ERR(data); | |
1121 | } | |
1122 | ||
0815d774 JC |
1123 | msm_gem_object_set_name(msm_host->tx_gem_obj, "tx_gem"); |
1124 | ||
c4d8cfe5 SS |
1125 | msm_host->tx_size = msm_host->tx_gem_obj->size; |
1126 | ||
1127 | return 0; | |
1128 | } | |
1129 | ||
1130 | int dsi_tx_buf_alloc_v2(struct msm_dsi_host *msm_host, int size) | |
1131 | { | |
1132 | struct drm_device *dev = msm_host->dev; | |
1133 | ||
1134 | msm_host->tx_buf = dma_alloc_coherent(dev->dev, size, | |
1135 | &msm_host->tx_buf_paddr, GFP_KERNEL); | |
1136 | if (!msm_host->tx_buf) | |
1137 | return -ENOMEM; | |
1138 | ||
1139 | msm_host->tx_size = size; | |
1140 | ||
1141 | return 0; | |
1142 | } | |
1143 | ||
a689554b HL |
1144 | static void dsi_tx_buf_free(struct msm_dsi_host *msm_host) |
1145 | { | |
1146 | struct drm_device *dev = msm_host->dev; | |
74d3a3a7 SP |
1147 | struct msm_drm_private *priv; |
1148 | ||
1149 | /* | |
1150 | * This is possible if we're tearing down before we've had a chance to | |
1151 | * fully initialize. A very real possibility if our probe is deferred, | |
1152 | * in which case we'll hit msm_dsi_host_destroy() without having run | |
1153 | * through the dsi_tx_buf_alloc(). | |
1154 | */ | |
1155 | if (!dev) | |
1156 | return; | |
a689554b | 1157 | |
74d3a3a7 | 1158 | priv = dev->dev_private; |
a689554b | 1159 | if (msm_host->tx_gem_obj) { |
7ad0e8cf | 1160 | msm_gem_unpin_iova(msm_host->tx_gem_obj, priv->kms->aspace); |
f7d33950 | 1161 | drm_gem_object_put(msm_host->tx_gem_obj); |
a689554b | 1162 | msm_host->tx_gem_obj = NULL; |
a689554b | 1163 | } |
4ff9d4cb AT |
1164 | |
1165 | if (msm_host->tx_buf) | |
1166 | dma_free_coherent(dev->dev, msm_host->tx_size, msm_host->tx_buf, | |
1167 | msm_host->tx_buf_paddr); | |
a689554b HL |
1168 | } |
1169 | ||
c4d8cfe5 SS |
1170 | void *dsi_tx_buf_get_6g(struct msm_dsi_host *msm_host) |
1171 | { | |
1172 | return msm_gem_get_vaddr(msm_host->tx_gem_obj); | |
1173 | } | |
1174 | ||
1175 | void *dsi_tx_buf_get_v2(struct msm_dsi_host *msm_host) | |
1176 | { | |
1177 | return msm_host->tx_buf; | |
1178 | } | |
1179 | ||
1180 | void dsi_tx_buf_put_6g(struct msm_dsi_host *msm_host) | |
1181 | { | |
1182 | msm_gem_put_vaddr(msm_host->tx_gem_obj); | |
1183 | } | |
1184 | ||
a689554b HL |
1185 | /* |
1186 | * prepare cmd buffer to be txed | |
1187 | */ | |
4ff9d4cb AT |
1188 | static int dsi_cmd_dma_add(struct msm_dsi_host *msm_host, |
1189 | const struct mipi_dsi_msg *msg) | |
a689554b | 1190 | { |
4ff9d4cb | 1191 | const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; |
a689554b HL |
1192 | struct mipi_dsi_packet packet; |
1193 | int len; | |
1194 | int ret; | |
1195 | u8 *data; | |
1196 | ||
1197 | ret = mipi_dsi_create_packet(&packet, msg); | |
1198 | if (ret) { | |
1199 | pr_err("%s: create packet failed, %d\n", __func__, ret); | |
1200 | return ret; | |
1201 | } | |
1202 | len = (packet.size + 3) & (~0x3); | |
1203 | ||
4ff9d4cb | 1204 | if (len > msm_host->tx_size) { |
a689554b HL |
1205 | pr_err("%s: packet size is too big\n", __func__); |
1206 | return -EINVAL; | |
1207 | } | |
1208 | ||
8f7ca540 SS |
1209 | data = cfg_hnd->ops->tx_buf_get(msm_host); |
1210 | if (IS_ERR(data)) { | |
1211 | ret = PTR_ERR(data); | |
1212 | pr_err("%s: get vaddr failed, %d\n", __func__, ret); | |
1213 | return ret; | |
a689554b HL |
1214 | } |
1215 | ||
1216 | /* MSM specific command format in memory */ | |
1217 | data[0] = packet.header[1]; | |
1218 | data[1] = packet.header[2]; | |
1219 | data[2] = packet.header[0]; | |
1220 | data[3] = BIT(7); /* Last packet */ | |
1221 | if (mipi_dsi_packet_format_is_long(msg->type)) | |
1222 | data[3] |= BIT(6); | |
1223 | if (msg->rx_buf && msg->rx_len) | |
1224 | data[3] |= BIT(5); | |
1225 | ||
1226 | /* Long packet */ | |
1227 | if (packet.payload && packet.payload_length) | |
1228 | memcpy(data + 4, packet.payload, packet.payload_length); | |
1229 | ||
1230 | /* Append 0xff to the end */ | |
1231 | if (packet.size < len) | |
1232 | memset(data + packet.size, 0xff, len - packet.size); | |
1233 | ||
8f7ca540 SS |
1234 | if (cfg_hnd->ops->tx_buf_put) |
1235 | cfg_hnd->ops->tx_buf_put(msm_host); | |
18f23049 | 1236 | |
a689554b HL |
1237 | return len; |
1238 | } | |
1239 | ||
1240 | /* | |
1241 | * dsi_short_read1_resp: 1 parameter | |
1242 | */ | |
1243 | static int dsi_short_read1_resp(u8 *buf, const struct mipi_dsi_msg *msg) | |
1244 | { | |
1245 | u8 *data = msg->rx_buf; | |
1246 | if (data && (msg->rx_len >= 1)) { | |
1247 | *data = buf[1]; /* strip out dcs type */ | |
1248 | return 1; | |
1249 | } else { | |
981371f3 | 1250 | pr_err("%s: read data does not match with rx_buf len %zu\n", |
a689554b HL |
1251 | __func__, msg->rx_len); |
1252 | return -EINVAL; | |
1253 | } | |
1254 | } | |
1255 | ||
1256 | /* | |
1257 | * dsi_short_read2_resp: 2 parameter | |
1258 | */ | |
1259 | static int dsi_short_read2_resp(u8 *buf, const struct mipi_dsi_msg *msg) | |
1260 | { | |
1261 | u8 *data = msg->rx_buf; | |
1262 | if (data && (msg->rx_len >= 2)) { | |
1263 | data[0] = buf[1]; /* strip out dcs type */ | |
1264 | data[1] = buf[2]; | |
1265 | return 2; | |
1266 | } else { | |
981371f3 | 1267 | pr_err("%s: read data does not match with rx_buf len %zu\n", |
a689554b HL |
1268 | __func__, msg->rx_len); |
1269 | return -EINVAL; | |
1270 | } | |
1271 | } | |
1272 | ||
1273 | static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg) | |
1274 | { | |
1275 | /* strip out 4 byte dcs header */ | |
1276 | if (msg->rx_buf && msg->rx_len) | |
1277 | memcpy(msg->rx_buf, buf + 4, msg->rx_len); | |
1278 | ||
1279 | return msg->rx_len; | |
1280 | } | |
1281 | ||
c4d8cfe5 SS |
1282 | int dsi_dma_base_get_6g(struct msm_dsi_host *msm_host, uint64_t *dma_base) |
1283 | { | |
1284 | struct drm_device *dev = msm_host->dev; | |
1285 | struct msm_drm_private *priv = dev->dev_private; | |
1286 | ||
1287 | if (!dma_base) | |
1288 | return -EINVAL; | |
1289 | ||
9fe041f6 | 1290 | return msm_gem_get_and_pin_iova(msm_host->tx_gem_obj, |
c4d8cfe5 SS |
1291 | priv->kms->aspace, dma_base); |
1292 | } | |
1293 | ||
1294 | int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t *dma_base) | |
1295 | { | |
1296 | if (!dma_base) | |
1297 | return -EINVAL; | |
1298 | ||
1299 | *dma_base = msm_host->tx_buf_paddr; | |
1300 | return 0; | |
1301 | } | |
1302 | ||
a689554b HL |
1303 | static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len) |
1304 | { | |
4ff9d4cb | 1305 | const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; |
a689554b | 1306 | int ret; |
78babc16 | 1307 | uint64_t dma_base; |
a689554b HL |
1308 | bool triggered; |
1309 | ||
8f7ca540 SS |
1310 | ret = cfg_hnd->ops->dma_base_get(msm_host, &dma_base); |
1311 | if (ret) { | |
1312 | pr_err("%s: failed to get iova: %d\n", __func__, ret); | |
1313 | return ret; | |
a689554b HL |
1314 | } |
1315 | ||
1316 | reinit_completion(&msm_host->dma_comp); | |
1317 | ||
1318 | dsi_wait4video_eng_busy(msm_host); | |
1319 | ||
1320 | triggered = msm_dsi_manager_cmd_xfer_trigger( | |
4ff9d4cb | 1321 | msm_host->id, dma_base, len); |
a689554b HL |
1322 | if (triggered) { |
1323 | ret = wait_for_completion_timeout(&msm_host->dma_comp, | |
1324 | msecs_to_jiffies(200)); | |
1325 | DBG("ret=%d", ret); | |
1326 | if (ret == 0) | |
1327 | ret = -ETIMEDOUT; | |
1328 | else | |
1329 | ret = len; | |
1330 | } else | |
1331 | ret = len; | |
1332 | ||
1333 | return ret; | |
1334 | } | |
1335 | ||
1336 | static int dsi_cmd_dma_rx(struct msm_dsi_host *msm_host, | |
1337 | u8 *buf, int rx_byte, int pkt_size) | |
1338 | { | |
2e3cc607 | 1339 | u32 *temp, data; |
a689554b | 1340 | int i, j = 0, cnt; |
a689554b HL |
1341 | u32 read_cnt; |
1342 | u8 reg[16]; | |
1343 | int repeated_bytes = 0; | |
1344 | int buf_offset = buf - msm_host->rx_buf; | |
1345 | ||
a689554b HL |
1346 | temp = (u32 *)reg; |
1347 | cnt = (rx_byte + 3) >> 2; | |
1348 | if (cnt > 4) | |
1349 | cnt = 4; /* 4 x 32 bits registers only */ | |
1350 | ||
ec1936eb HL |
1351 | if (rx_byte == 4) |
1352 | read_cnt = 4; | |
1353 | else | |
1354 | read_cnt = pkt_size + 6; | |
a689554b HL |
1355 | |
1356 | /* | |
1357 | * In case of multiple reads from the panel, after the first read, there | |
1358 | * is possibility that there are some bytes in the payload repeating in | |
1359 | * the RDBK_DATA registers. Since we read all the parameters from the | |
1360 | * panel right from the first byte for every pass. We need to skip the | |
1361 | * repeating bytes and then append the new parameters to the rx buffer. | |
1362 | */ | |
1363 | if (read_cnt > 16) { | |
1364 | int bytes_shifted; | |
1365 | /* Any data more than 16 bytes will be shifted out. | |
1366 | * The temp read buffer should already contain these bytes. | |
1367 | * The remaining bytes in read buffer are the repeated bytes. | |
1368 | */ | |
1369 | bytes_shifted = read_cnt - 16; | |
1370 | repeated_bytes = buf_offset - bytes_shifted; | |
1371 | } | |
1372 | ||
1373 | for (i = cnt - 1; i >= 0; i--) { | |
1374 | data = dsi_read(msm_host, REG_DSI_RDBK_DATA(i)); | |
1375 | *temp++ = ntohl(data); /* to host byte order */ | |
1376 | DBG("data = 0x%x and ntohl(data) = 0x%x", data, ntohl(data)); | |
1377 | } | |
1378 | ||
1379 | for (i = repeated_bytes; i < 16; i++) | |
1380 | buf[j++] = reg[i]; | |
1381 | ||
1382 | return j; | |
1383 | } | |
1384 | ||
1385 | static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host, | |
1386 | const struct mipi_dsi_msg *msg) | |
1387 | { | |
1388 | int len, ret; | |
1389 | int bllp_len = msm_host->mode->hdisplay * | |
1390 | dsi_get_bpp(msm_host->format) / 8; | |
1391 | ||
4ff9d4cb | 1392 | len = dsi_cmd_dma_add(msm_host, msg); |
f0e7e9ed | 1393 | if (len < 0) { |
a689554b HL |
1394 | pr_err("%s: failed to add cmd type = 0x%x\n", |
1395 | __func__, msg->type); | |
f0e7e9ed | 1396 | return len; |
a689554b HL |
1397 | } |
1398 | ||
1399 | /* for video mode, do not send cmds more than | |
1400 | * one pixel line, since it only transmit it | |
1401 | * during BLLP. | |
1402 | */ | |
1403 | /* TODO: if the command is sent in LP mode, the bit rate is only | |
1404 | * half of esc clk rate. In this case, if the video is already | |
1405 | * actively streaming, we need to check more carefully if the | |
1406 | * command can be fit into one BLLP. | |
1407 | */ | |
1408 | if ((msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && (len > bllp_len)) { | |
1409 | pr_err("%s: cmd cannot fit into BLLP period, len=%d\n", | |
1410 | __func__, len); | |
1411 | return -EINVAL; | |
1412 | } | |
1413 | ||
1414 | ret = dsi_cmd_dma_tx(msm_host, len); | |
f0e7e9ed DB |
1415 | if (ret < 0) { |
1416 | pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d, ret=%d\n", | |
1417 | __func__, msg->type, (*(u8 *)(msg->tx_buf)), len, ret); | |
1418 | return ret; | |
1419 | } else if (ret < len) { | |
1420 | pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, ret=%d len=%d\n", | |
1421 | __func__, msg->type, (*(u8 *)(msg->tx_buf)), ret, len); | |
1422 | return -EIO; | |
a689554b HL |
1423 | } |
1424 | ||
1425 | return len; | |
1426 | } | |
1427 | ||
a689554b HL |
1428 | static void dsi_err_worker(struct work_struct *work) |
1429 | { | |
1430 | struct msm_dsi_host *msm_host = | |
1431 | container_of(work, struct msm_dsi_host, err_work); | |
1432 | u32 status = msm_host->err_work_state; | |
1433 | ||
ff431fa4 | 1434 | pr_err_ratelimited("%s: status=%x\n", __func__, status); |
a689554b | 1435 | if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW) |
4f0718bf | 1436 | dsi_sw_reset(msm_host); |
a689554b HL |
1437 | |
1438 | /* It is safe to clear here because error irq is disabled. */ | |
1439 | msm_host->err_work_state = 0; | |
1440 | ||
1441 | /* enable dsi error interrupt */ | |
1442 | dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1); | |
1443 | } | |
1444 | ||
1445 | static void dsi_ack_err_status(struct msm_dsi_host *msm_host) | |
1446 | { | |
1447 | u32 status; | |
1448 | ||
1449 | status = dsi_read(msm_host, REG_DSI_ACK_ERR_STATUS); | |
1450 | ||
1451 | if (status) { | |
1452 | dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status); | |
1453 | /* Writing of an extra 0 needed to clear error bits */ | |
1454 | dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0); | |
1455 | msm_host->err_work_state |= DSI_ERR_STATE_ACK; | |
1456 | } | |
1457 | } | |
1458 | ||
1459 | static void dsi_timeout_status(struct msm_dsi_host *msm_host) | |
1460 | { | |
1461 | u32 status; | |
1462 | ||
1463 | status = dsi_read(msm_host, REG_DSI_TIMEOUT_STATUS); | |
1464 | ||
1465 | if (status) { | |
1466 | dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status); | |
1467 | msm_host->err_work_state |= DSI_ERR_STATE_TIMEOUT; | |
1468 | } | |
1469 | } | |
1470 | ||
1471 | static void dsi_dln0_phy_err(struct msm_dsi_host *msm_host) | |
1472 | { | |
1473 | u32 status; | |
1474 | ||
1475 | status = dsi_read(msm_host, REG_DSI_DLN0_PHY_ERR); | |
1476 | ||
01199361 AT |
1477 | if (status & (DSI_DLN0_PHY_ERR_DLN0_ERR_ESC | |
1478 | DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC | | |
1479 | DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL | | |
1480 | DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 | | |
1481 | DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1)) { | |
a689554b HL |
1482 | dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status); |
1483 | msm_host->err_work_state |= DSI_ERR_STATE_DLN0_PHY; | |
1484 | } | |
1485 | } | |
1486 | ||
1487 | static void dsi_fifo_status(struct msm_dsi_host *msm_host) | |
1488 | { | |
1489 | u32 status; | |
1490 | ||
1491 | status = dsi_read(msm_host, REG_DSI_FIFO_STATUS); | |
1492 | ||
1493 | /* fifo underflow, overflow */ | |
1494 | if (status) { | |
1495 | dsi_write(msm_host, REG_DSI_FIFO_STATUS, status); | |
1496 | msm_host->err_work_state |= DSI_ERR_STATE_FIFO; | |
1497 | if (status & DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW) | |
1498 | msm_host->err_work_state |= | |
1499 | DSI_ERR_STATE_MDP_FIFO_UNDERFLOW; | |
1500 | } | |
1501 | } | |
1502 | ||
1503 | static void dsi_status(struct msm_dsi_host *msm_host) | |
1504 | { | |
1505 | u32 status; | |
1506 | ||
1507 | status = dsi_read(msm_host, REG_DSI_STATUS0); | |
1508 | ||
1509 | if (status & DSI_STATUS0_INTERLEAVE_OP_CONTENTION) { | |
1510 | dsi_write(msm_host, REG_DSI_STATUS0, status); | |
1511 | msm_host->err_work_state |= | |
1512 | DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION; | |
1513 | } | |
1514 | } | |
1515 | ||
1516 | static void dsi_clk_status(struct msm_dsi_host *msm_host) | |
1517 | { | |
1518 | u32 status; | |
1519 | ||
1520 | status = dsi_read(msm_host, REG_DSI_CLK_STATUS); | |
1521 | ||
1522 | if (status & DSI_CLK_STATUS_PLL_UNLOCKED) { | |
1523 | dsi_write(msm_host, REG_DSI_CLK_STATUS, status); | |
1524 | msm_host->err_work_state |= DSI_ERR_STATE_PLL_UNLOCKED; | |
1525 | } | |
1526 | } | |
1527 | ||
1528 | static void dsi_error(struct msm_dsi_host *msm_host) | |
1529 | { | |
1530 | /* disable dsi error interrupt */ | |
1531 | dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 0); | |
1532 | ||
1533 | dsi_clk_status(msm_host); | |
1534 | dsi_fifo_status(msm_host); | |
1535 | dsi_ack_err_status(msm_host); | |
1536 | dsi_timeout_status(msm_host); | |
1537 | dsi_status(msm_host); | |
1538 | dsi_dln0_phy_err(msm_host); | |
1539 | ||
1540 | queue_work(msm_host->workqueue, &msm_host->err_work); | |
1541 | } | |
1542 | ||
1543 | static irqreturn_t dsi_host_irq(int irq, void *ptr) | |
1544 | { | |
1545 | struct msm_dsi_host *msm_host = ptr; | |
1546 | u32 isr; | |
1547 | unsigned long flags; | |
1548 | ||
1549 | if (!msm_host->ctrl_base) | |
1550 | return IRQ_HANDLED; | |
1551 | ||
1552 | spin_lock_irqsave(&msm_host->intr_lock, flags); | |
1553 | isr = dsi_read(msm_host, REG_DSI_INTR_CTRL); | |
1554 | dsi_write(msm_host, REG_DSI_INTR_CTRL, isr); | |
1555 | spin_unlock_irqrestore(&msm_host->intr_lock, flags); | |
1556 | ||
1557 | DBG("isr=0x%x, id=%d", isr, msm_host->id); | |
1558 | ||
1559 | if (isr & DSI_IRQ_ERROR) | |
1560 | dsi_error(msm_host); | |
1561 | ||
1562 | if (isr & DSI_IRQ_VIDEO_DONE) | |
1563 | complete(&msm_host->video_comp); | |
1564 | ||
1565 | if (isr & DSI_IRQ_CMD_DMA_DONE) | |
1566 | complete(&msm_host->dma_comp); | |
1567 | ||
1568 | return IRQ_HANDLED; | |
1569 | } | |
1570 | ||
1571 | static int dsi_host_init_panel_gpios(struct msm_dsi_host *msm_host, | |
1572 | struct device *panel_device) | |
1573 | { | |
9590e69d UKK |
1574 | msm_host->disp_en_gpio = devm_gpiod_get_optional(panel_device, |
1575 | "disp-enable", | |
1576 | GPIOD_OUT_LOW); | |
a689554b HL |
1577 | if (IS_ERR(msm_host->disp_en_gpio)) { |
1578 | DBG("cannot get disp-enable-gpios %ld", | |
1579 | PTR_ERR(msm_host->disp_en_gpio)); | |
9590e69d | 1580 | return PTR_ERR(msm_host->disp_en_gpio); |
a689554b HL |
1581 | } |
1582 | ||
60d05cb4 AT |
1583 | msm_host->te_gpio = devm_gpiod_get_optional(panel_device, "disp-te", |
1584 | GPIOD_IN); | |
a689554b HL |
1585 | if (IS_ERR(msm_host->te_gpio)) { |
1586 | DBG("cannot get disp-te-gpios %ld", PTR_ERR(msm_host->te_gpio)); | |
9590e69d | 1587 | return PTR_ERR(msm_host->te_gpio); |
a689554b HL |
1588 | } |
1589 | ||
1590 | return 0; | |
1591 | } | |
1592 | ||
1593 | static int dsi_host_attach(struct mipi_dsi_host *host, | |
1594 | struct mipi_dsi_device *dsi) | |
1595 | { | |
1596 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
1597 | int ret; | |
1598 | ||
26f7d1f4 AT |
1599 | if (dsi->lanes > msm_host->num_data_lanes) |
1600 | return -EINVAL; | |
1601 | ||
a689554b HL |
1602 | msm_host->channel = dsi->channel; |
1603 | msm_host->lanes = dsi->lanes; | |
1604 | msm_host->format = dsi->format; | |
1605 | msm_host->mode_flags = dsi->mode_flags; | |
574922e6 DB |
1606 | if (dsi->dsc) |
1607 | msm_host->dsc = dsi->dsc; | |
a689554b | 1608 | |
a689554b HL |
1609 | /* Some gpios defined in panel DT need to be controlled by host */ |
1610 | ret = dsi_host_init_panel_gpios(msm_host, &dsi->dev); | |
1611 | if (ret) | |
1612 | return ret; | |
1613 | ||
8f59ee9a RC |
1614 | ret = dsi_dev_attach(msm_host->pdev); |
1615 | if (ret) | |
1616 | return ret; | |
1617 | ||
a689554b | 1618 | DBG("id=%d", msm_host->id); |
a689554b HL |
1619 | |
1620 | return 0; | |
1621 | } | |
1622 | ||
1623 | static int dsi_host_detach(struct mipi_dsi_host *host, | |
1624 | struct mipi_dsi_device *dsi) | |
1625 | { | |
1626 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
1627 | ||
8f59ee9a RC |
1628 | dsi_dev_detach(msm_host->pdev); |
1629 | ||
a689554b | 1630 | DBG("id=%d", msm_host->id); |
a689554b HL |
1631 | |
1632 | return 0; | |
1633 | } | |
1634 | ||
1635 | static ssize_t dsi_host_transfer(struct mipi_dsi_host *host, | |
1636 | const struct mipi_dsi_msg *msg) | |
1637 | { | |
1638 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
1639 | int ret; | |
1640 | ||
1641 | if (!msg || !msm_host->power_on) | |
1642 | return -EINVAL; | |
1643 | ||
1644 | mutex_lock(&msm_host->cmd_mutex); | |
1645 | ret = msm_dsi_manager_cmd_xfer(msm_host->id, msg); | |
1646 | mutex_unlock(&msm_host->cmd_mutex); | |
1647 | ||
1648 | return ret; | |
1649 | } | |
1650 | ||
8b6947a8 | 1651 | static const struct mipi_dsi_host_ops dsi_host_ops = { |
a689554b HL |
1652 | .attach = dsi_host_attach, |
1653 | .detach = dsi_host_detach, | |
1654 | .transfer = dsi_host_transfer, | |
1655 | }; | |
1656 | ||
26f7d1f4 AT |
1657 | /* |
1658 | * List of supported physical to logical lane mappings. | |
1659 | * For example, the 2nd entry represents the following mapping: | |
1660 | * | |
1661 | * "3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3; | |
1662 | */ | |
1663 | static const int supported_data_lane_swaps[][4] = { | |
1664 | { 0, 1, 2, 3 }, | |
1665 | { 3, 0, 1, 2 }, | |
1666 | { 2, 3, 0, 1 }, | |
1667 | { 1, 2, 3, 0 }, | |
1668 | { 0, 3, 2, 1 }, | |
1669 | { 1, 0, 3, 2 }, | |
1670 | { 2, 1, 0, 3 }, | |
1671 | { 3, 2, 1, 0 }, | |
1672 | }; | |
1673 | ||
1674 | static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host, | |
1675 | struct device_node *ep) | |
1676 | { | |
1677 | struct device *dev = &msm_host->pdev->dev; | |
1678 | struct property *prop; | |
1679 | u32 lane_map[4]; | |
1680 | int ret, i, len, num_lanes; | |
1681 | ||
60282cea | 1682 | prop = of_find_property(ep, "data-lanes", &len); |
26f7d1f4 | 1683 | if (!prop) { |
6a41da17 | 1684 | DRM_DEV_DEBUG(dev, |
a1b1a4f7 | 1685 | "failed to find data lane mapping, using default\n"); |
cd92cc18 PC |
1686 | /* Set the number of date lanes to 4 by default. */ |
1687 | msm_host->num_data_lanes = 4; | |
a1b1a4f7 | 1688 | return 0; |
26f7d1f4 AT |
1689 | } |
1690 | ||
185443ef MV |
1691 | num_lanes = drm_of_get_data_lanes_count(ep, 1, 4); |
1692 | if (num_lanes < 0) { | |
6a41da17 | 1693 | DRM_DEV_ERROR(dev, "bad number of data lanes\n"); |
185443ef | 1694 | return num_lanes; |
26f7d1f4 AT |
1695 | } |
1696 | ||
1697 | msm_host->num_data_lanes = num_lanes; | |
1698 | ||
60282cea | 1699 | ret = of_property_read_u32_array(ep, "data-lanes", lane_map, |
26f7d1f4 AT |
1700 | num_lanes); |
1701 | if (ret) { | |
6a41da17 | 1702 | DRM_DEV_ERROR(dev, "failed to read lane data\n"); |
26f7d1f4 AT |
1703 | return ret; |
1704 | } | |
1705 | ||
1706 | /* | |
1707 | * compare DT specified physical-logical lane mappings with the ones | |
1708 | * supported by hardware | |
1709 | */ | |
1710 | for (i = 0; i < ARRAY_SIZE(supported_data_lane_swaps); i++) { | |
1711 | const int *swap = supported_data_lane_swaps[i]; | |
1712 | int j; | |
1713 | ||
60282cea AT |
1714 | /* |
1715 | * the data-lanes array we get from DT has a logical->physical | |
1716 | * mapping. The "data lane swap" register field represents | |
1717 | * supported configurations in a physical->logical mapping. | |
1718 | * Translate the DT mapping to what we understand and find a | |
1719 | * configuration that works. | |
1720 | */ | |
26f7d1f4 | 1721 | for (j = 0; j < num_lanes; j++) { |
60282cea | 1722 | if (lane_map[j] < 0 || lane_map[j] > 3) |
6a41da17 | 1723 | DRM_DEV_ERROR(dev, "bad physical lane entry %u\n", |
60282cea AT |
1724 | lane_map[j]); |
1725 | ||
1726 | if (swap[lane_map[j]] != j) | |
26f7d1f4 AT |
1727 | break; |
1728 | } | |
1729 | ||
1730 | if (j == num_lanes) { | |
1731 | msm_host->dlane_swap = i; | |
1732 | return 0; | |
1733 | } | |
1734 | } | |
1735 | ||
1736 | return -EINVAL; | |
1737 | } | |
1738 | ||
d2c277c6 | 1739 | static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc) |
b9080324 | 1740 | { |
49fd30a7 | 1741 | int ret; |
d2c277c6 MS |
1742 | |
1743 | if (dsc->bits_per_pixel & 0xf) { | |
1744 | DRM_DEV_ERROR(&msm_host->pdev->dev, "DSI does not support fractional bits_per_pixel\n"); | |
1745 | return -EINVAL; | |
1746 | } | |
b9080324 | 1747 | |
d053fbc4 MS |
1748 | if (dsc->bits_per_component != 8) { |
1749 | DRM_DEV_ERROR(&msm_host->pdev->dev, "DSI does not support bits_per_component != 8 yet\n"); | |
1750 | return -EOPNOTSUPP; | |
1751 | } | |
1752 | ||
4b2b1b36 DB |
1753 | dsc->simple_422 = 0; |
1754 | dsc->convert_rgb = 1; | |
1755 | dsc->vbr_enable = 0; | |
b9080324 | 1756 | |
49fd30a7 DB |
1757 | drm_dsc_set_const_params(dsc); |
1758 | drm_dsc_set_rc_buf_thresh(dsc); | |
b9080324 | 1759 | |
49fd30a7 DB |
1760 | /* handle only bpp = bpc = 8, pre-SCR panels */ |
1761 | ret = drm_dsc_setup_rc_params(dsc, DRM_DSC_1_1_PRE_SCR); | |
1762 | if (ret) { | |
1763 | DRM_DEV_ERROR(&msm_host->pdev->dev, "could not find DSC RC parameters\n"); | |
1764 | return ret; | |
b9080324 VK |
1765 | } |
1766 | ||
ed1498f7 | 1767 | dsc->initial_scale_value = drm_dsc_initial_scale_value(dsc); |
4b2b1b36 | 1768 | dsc->line_buf_depth = dsc->bits_per_component + 1; |
b9080324 | 1769 | |
c3a1aabc | 1770 | return drm_dsc_compute_rc_parameters(dsc); |
b9080324 VK |
1771 | } |
1772 | ||
f7009d26 AT |
1773 | static int dsi_host_parse_dt(struct msm_dsi_host *msm_host) |
1774 | { | |
1775 | struct device *dev = &msm_host->pdev->dev; | |
1776 | struct device_node *np = dev->of_node; | |
682493e4 | 1777 | struct device_node *endpoint; |
a1b1a4f7 | 1778 | int ret = 0; |
f7009d26 | 1779 | |
f7009d26 | 1780 | /* |
b9ac76f6 AT |
1781 | * Get the endpoint of the output port of the DSI host. In our case, |
1782 | * this is mapped to port number with reg = 1. Don't return an error if | |
1783 | * the remote endpoint isn't defined. It's possible that there is | |
1784 | * nothing connected to the dsi output. | |
f7009d26 | 1785 | */ |
b9ac76f6 | 1786 | endpoint = of_graph_get_endpoint_by_regs(np, 1, -1); |
f7009d26 | 1787 | if (!endpoint) { |
6a41da17 | 1788 | DRM_DEV_DEBUG(dev, "%s: no endpoint\n", __func__); |
f7009d26 AT |
1789 | return 0; |
1790 | } | |
1791 | ||
26f7d1f4 AT |
1792 | ret = dsi_host_parse_lane_data(msm_host, endpoint); |
1793 | if (ret) { | |
6a41da17 | 1794 | DRM_DEV_ERROR(dev, "%s: invalid lane configuration %d\n", |
26f7d1f4 | 1795 | __func__, ret); |
feb085ec | 1796 | ret = -EINVAL; |
26f7d1f4 AT |
1797 | goto err; |
1798 | } | |
1799 | ||
0c7df47f AT |
1800 | if (of_property_read_bool(np, "syscon-sfpb")) { |
1801 | msm_host->sfpb = syscon_regmap_lookup_by_phandle(np, | |
1802 | "syscon-sfpb"); | |
1803 | if (IS_ERR(msm_host->sfpb)) { | |
6a41da17 | 1804 | DRM_DEV_ERROR(dev, "%s: failed to get sfpb regmap\n", |
0c7df47f | 1805 | __func__); |
26f7d1f4 | 1806 | ret = PTR_ERR(msm_host->sfpb); |
0c7df47f AT |
1807 | } |
1808 | } | |
1809 | ||
26f7d1f4 AT |
1810 | err: |
1811 | of_node_put(endpoint); | |
1812 | ||
1813 | return ret; | |
f7009d26 AT |
1814 | } |
1815 | ||
32280d66 AT |
1816 | static int dsi_host_get_id(struct msm_dsi_host *msm_host) |
1817 | { | |
1818 | struct platform_device *pdev = msm_host->pdev; | |
1819 | const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg; | |
1820 | struct resource *res; | |
ff83e76b | 1821 | int i, j; |
32280d66 AT |
1822 | |
1823 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dsi_ctrl"); | |
1824 | if (!res) | |
1825 | return -EINVAL; | |
1826 | ||
ff83e76b KD |
1827 | for (i = 0; i < VARIANTS_MAX; i++) |
1828 | for (j = 0; j < DSI_MAX; j++) | |
1829 | if (cfg->io_start[i][j] == res->start) | |
1830 | return j; | |
32280d66 AT |
1831 | |
1832 | return -EINVAL; | |
1833 | } | |
1834 | ||
a689554b HL |
1835 | int msm_dsi_host_init(struct msm_dsi *msm_dsi) |
1836 | { | |
1837 | struct msm_dsi_host *msm_host = NULL; | |
1838 | struct platform_device *pdev = msm_dsi->pdev; | |
d8810a66 | 1839 | const struct msm_dsi_config *cfg; |
a689554b HL |
1840 | int ret; |
1841 | ||
1842 | msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL); | |
1843 | if (!msm_host) { | |
d61980ad | 1844 | return -ENOMEM; |
a689554b HL |
1845 | } |
1846 | ||
f7009d26 | 1847 | msm_host->pdev = pdev; |
f54ca1a0 | 1848 | msm_dsi->host = &msm_host->base; |
f7009d26 AT |
1849 | |
1850 | ret = dsi_host_parse_dt(msm_host); | |
a689554b | 1851 | if (ret) { |
f7009d26 | 1852 | pr_err("%s: failed to parse dt\n", __func__); |
d61980ad | 1853 | return ret; |
a689554b | 1854 | } |
a689554b | 1855 | |
c0e745d7 | 1856 | msm_host->ctrl_base = msm_ioremap_size(pdev, "dsi_ctrl", &msm_host->ctrl_size); |
a689554b HL |
1857 | if (IS_ERR(msm_host->ctrl_base)) { |
1858 | pr_err("%s: unable to map Dsi ctrl base\n", __func__); | |
d61980ad | 1859 | return PTR_ERR(msm_host->ctrl_base); |
a689554b HL |
1860 | } |
1861 | ||
f6be1121 AT |
1862 | pm_runtime_enable(&pdev->dev); |
1863 | ||
d248b61f HL |
1864 | msm_host->cfg_hnd = dsi_get_config(msm_host); |
1865 | if (!msm_host->cfg_hnd) { | |
a689554b | 1866 | pr_err("%s: get config failed\n", __func__); |
d61980ad | 1867 | return -EINVAL; |
a689554b | 1868 | } |
d8810a66 | 1869 | cfg = msm_host->cfg_hnd->cfg; |
a689554b | 1870 | |
32280d66 AT |
1871 | msm_host->id = dsi_host_get_id(msm_host); |
1872 | if (msm_host->id < 0) { | |
32280d66 | 1873 | pr_err("%s: unable to identify DSI host index\n", __func__); |
d61980ad | 1874 | return msm_host->id; |
32280d66 AT |
1875 | } |
1876 | ||
d248b61f | 1877 | /* fixup base address by io offset */ |
d8810a66 | 1878 | msm_host->ctrl_base += cfg->io_offset; |
d248b61f | 1879 | |
d8810a66 DA |
1880 | ret = devm_regulator_bulk_get_const(&pdev->dev, cfg->num_regulators, |
1881 | cfg->regulator_data, | |
1882 | &msm_host->supplies); | |
1883 | if (ret) | |
d61980ad | 1884 | return ret; |
a689554b | 1885 | |
31c92767 AT |
1886 | ret = dsi_clk_init(msm_host); |
1887 | if (ret) { | |
1888 | pr_err("%s: unable to initialize dsi clks\n", __func__); | |
d61980ad | 1889 | return ret; |
31c92767 AT |
1890 | } |
1891 | ||
a689554b HL |
1892 | msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL); |
1893 | if (!msm_host->rx_buf) { | |
1894 | pr_err("%s: alloc rx temp buf failed\n", __func__); | |
d61980ad | 1895 | return -ENOMEM; |
a689554b HL |
1896 | } |
1897 | ||
11120e93 YL |
1898 | ret = devm_pm_opp_set_clkname(&pdev->dev, "byte"); |
1899 | if (ret) | |
1900 | return ret; | |
32d3e0fe | 1901 | /* OPP table is optional */ |
11120e93 | 1902 | ret = devm_pm_opp_of_add_table(&pdev->dev); |
6400a8e8 | 1903 | if (ret && ret != -ENODEV) { |
32d3e0fe | 1904 | dev_err(&pdev->dev, "invalid OPP table in device tree\n"); |
32d3e0fe RN |
1905 | return ret; |
1906 | } | |
1907 | ||
bf94ec09 | 1908 | msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); |
6a1d4c79 DC |
1909 | if (!msm_host->irq) { |
1910 | dev_err(&pdev->dev, "failed to get irq\n"); | |
1911 | return -EINVAL; | |
bf94ec09 DB |
1912 | } |
1913 | ||
1914 | /* do not autoenable, will be enabled later */ | |
1915 | ret = devm_request_irq(&pdev->dev, msm_host->irq, dsi_host_irq, | |
24b176d8 | 1916 | IRQF_TRIGGER_HIGH | IRQF_NO_AUTOEN, |
bf94ec09 DB |
1917 | "dsi_isr", msm_host); |
1918 | if (ret < 0) { | |
1919 | dev_err(&pdev->dev, "failed to request IRQ%u: %d\n", | |
1920 | msm_host->irq, ret); | |
1921 | return ret; | |
1922 | } | |
1923 | ||
a689554b HL |
1924 | init_completion(&msm_host->dma_comp); |
1925 | init_completion(&msm_host->video_comp); | |
1926 | mutex_init(&msm_host->dev_mutex); | |
1927 | mutex_init(&msm_host->cmd_mutex); | |
a689554b HL |
1928 | spin_lock_init(&msm_host->intr_lock); |
1929 | ||
1930 | /* setup workqueue */ | |
1931 | msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0); | |
115906ca JJ |
1932 | if (!msm_host->workqueue) |
1933 | return -ENOMEM; | |
1934 | ||
a689554b HL |
1935 | INIT_WORK(&msm_host->err_work, dsi_err_worker); |
1936 | ||
a689554b HL |
1937 | msm_dsi->id = msm_host->id; |
1938 | ||
1939 | DBG("Dsi Host %d initialized", msm_host->id); | |
1940 | return 0; | |
a689554b HL |
1941 | } |
1942 | ||
1943 | void msm_dsi_host_destroy(struct mipi_dsi_host *host) | |
1944 | { | |
1945 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
1946 | ||
1947 | DBG(""); | |
1948 | dsi_tx_buf_free(msm_host); | |
1949 | if (msm_host->workqueue) { | |
a689554b HL |
1950 | destroy_workqueue(msm_host->workqueue); |
1951 | msm_host->workqueue = NULL; | |
1952 | } | |
1953 | ||
a689554b HL |
1954 | mutex_destroy(&msm_host->cmd_mutex); |
1955 | mutex_destroy(&msm_host->dev_mutex); | |
f6be1121 AT |
1956 | |
1957 | pm_runtime_disable(&msm_host->pdev->dev); | |
a689554b HL |
1958 | } |
1959 | ||
1960 | int msm_dsi_host_modeset_init(struct mipi_dsi_host *host, | |
1961 | struct drm_device *dev) | |
1962 | { | |
1963 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
8f7ca540 | 1964 | const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; |
a689554b HL |
1965 | int ret; |
1966 | ||
a689554b | 1967 | msm_host->dev = dev; |
0f40ba48 | 1968 | |
8f7ca540 | 1969 | ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K); |
a689554b HL |
1970 | if (ret) { |
1971 | pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret); | |
1972 | return ret; | |
1973 | } | |
1974 | ||
1975 | return 0; | |
1976 | } | |
1977 | ||
8f59ee9a | 1978 | int msm_dsi_host_register(struct mipi_dsi_host *host) |
a689554b HL |
1979 | { |
1980 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
a689554b HL |
1981 | int ret; |
1982 | ||
1983 | /* Register mipi dsi host */ | |
1984 | if (!msm_host->registered) { | |
1985 | host->dev = &msm_host->pdev->dev; | |
1986 | host->ops = &dsi_host_ops; | |
1987 | ret = mipi_dsi_host_register(host); | |
1988 | if (ret) | |
1989 | return ret; | |
1990 | ||
1991 | msm_host->registered = true; | |
a689554b HL |
1992 | } |
1993 | ||
1994 | return 0; | |
1995 | } | |
1996 | ||
1997 | void msm_dsi_host_unregister(struct mipi_dsi_host *host) | |
1998 | { | |
1999 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
2000 | ||
2001 | if (msm_host->registered) { | |
2002 | mipi_dsi_host_unregister(host); | |
2003 | host->dev = NULL; | |
2004 | host->ops = NULL; | |
2005 | msm_host->registered = false; | |
2006 | } | |
2007 | } | |
2008 | ||
2009 | int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host, | |
2010 | const struct mipi_dsi_msg *msg) | |
2011 | { | |
2012 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
8f7ca540 | 2013 | const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; |
a689554b HL |
2014 | |
2015 | /* TODO: make sure dsi_cmd_mdp is idle. | |
2016 | * Since DSI6G v1.2.0, we can set DSI_TRIG_CTRL.BLOCK_DMA_WITHIN_FRAME | |
2017 | * to ask H/W to wait until cmd mdp is idle. S/W wait is not needed. | |
2018 | * How to handle the old versions? Wait for mdp cmd done? | |
2019 | */ | |
2020 | ||
2021 | /* | |
2022 | * mdss interrupt is generated in mdp core clock domain | |
2023 | * mdp clock need to be enabled to receive dsi interrupt | |
2024 | */ | |
f6be1121 | 2025 | pm_runtime_get_sync(&msm_host->pdev->dev); |
6b16f05a | 2026 | cfg_hnd->ops->link_clk_set_rate(msm_host); |
8f7ca540 | 2027 | cfg_hnd->ops->link_clk_enable(msm_host); |
a689554b HL |
2028 | |
2029 | /* TODO: vote for bus bandwidth */ | |
2030 | ||
2031 | if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) | |
2032 | dsi_set_tx_power_mode(0, msm_host); | |
2033 | ||
2034 | msm_host->dma_cmd_ctrl_restore = dsi_read(msm_host, REG_DSI_CTRL); | |
2035 | dsi_write(msm_host, REG_DSI_CTRL, | |
2036 | msm_host->dma_cmd_ctrl_restore | | |
2037 | DSI_CTRL_CMD_MODE_EN | | |
2038 | DSI_CTRL_ENABLE); | |
2039 | dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 1); | |
2040 | ||
2041 | return 0; | |
2042 | } | |
2043 | ||
2044 | void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host, | |
2045 | const struct mipi_dsi_msg *msg) | |
2046 | { | |
2047 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
8f7ca540 | 2048 | const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; |
a689554b HL |
2049 | |
2050 | dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 0); | |
2051 | dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore); | |
2052 | ||
2053 | if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) | |
2054 | dsi_set_tx_power_mode(1, msm_host); | |
2055 | ||
2056 | /* TODO: unvote for bus bandwidth */ | |
2057 | ||
8f7ca540 | 2058 | cfg_hnd->ops->link_clk_disable(msm_host); |
f3d5d7cc | 2059 | pm_runtime_put(&msm_host->pdev->dev); |
a689554b HL |
2060 | } |
2061 | ||
2062 | int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host, | |
2063 | const struct mipi_dsi_msg *msg) | |
2064 | { | |
2065 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
2066 | ||
2067 | return dsi_cmds2buf_tx(msm_host, msg); | |
2068 | } | |
2069 | ||
2070 | int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host, | |
2071 | const struct mipi_dsi_msg *msg) | |
2072 | { | |
2073 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
d248b61f | 2074 | const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; |
a689554b HL |
2075 | int data_byte, rx_byte, dlen, end; |
2076 | int short_response, diff, pkt_size, ret = 0; | |
2077 | char cmd; | |
2078 | int rlen = msg->rx_len; | |
2079 | u8 *buf; | |
2080 | ||
2081 | if (rlen <= 2) { | |
2082 | short_response = 1; | |
2083 | pkt_size = rlen; | |
2084 | rx_byte = 4; | |
2085 | } else { | |
2086 | short_response = 0; | |
2087 | data_byte = 10; /* first read */ | |
2088 | if (rlen < data_byte) | |
2089 | pkt_size = rlen; | |
2090 | else | |
2091 | pkt_size = data_byte; | |
2092 | rx_byte = data_byte + 6; /* 4 header + 2 crc */ | |
2093 | } | |
2094 | ||
2095 | buf = msm_host->rx_buf; | |
2096 | end = 0; | |
2097 | while (!end) { | |
2098 | u8 tx[2] = {pkt_size & 0xff, pkt_size >> 8}; | |
2099 | struct mipi_dsi_msg max_pkt_size_msg = { | |
2100 | .channel = msg->channel, | |
2101 | .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, | |
2102 | .tx_len = 2, | |
2103 | .tx_buf = tx, | |
2104 | }; | |
2105 | ||
2106 | DBG("rlen=%d pkt_size=%d rx_byte=%d", | |
2107 | rlen, pkt_size, rx_byte); | |
2108 | ||
2109 | ret = dsi_cmds2buf_tx(msm_host, &max_pkt_size_msg); | |
2110 | if (ret < 2) { | |
2111 | pr_err("%s: Set max pkt size failed, %d\n", | |
2112 | __func__, ret); | |
2113 | return -EINVAL; | |
2114 | } | |
2115 | ||
d248b61f HL |
2116 | if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && |
2117 | (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_1)) { | |
a689554b HL |
2118 | /* Clear the RDBK_DATA registers */ |
2119 | dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, | |
2120 | DSI_RDBK_DATA_CTRL_CLR); | |
2121 | wmb(); /* make sure the RDBK registers are cleared */ | |
2122 | dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0); | |
2123 | wmb(); /* release cleared status before transfer */ | |
2124 | } | |
2125 | ||
2126 | ret = dsi_cmds2buf_tx(msm_host, msg); | |
f0e7e9ed | 2127 | if (ret < 0) { |
a689554b HL |
2128 | pr_err("%s: Read cmd Tx failed, %d\n", __func__, ret); |
2129 | return ret; | |
f0e7e9ed DB |
2130 | } else if (ret < msg->tx_len) { |
2131 | pr_err("%s: Read cmd Tx failed, too short: %d\n", __func__, ret); | |
2132 | return -ECOMM; | |
a689554b HL |
2133 | } |
2134 | ||
2135 | /* | |
2136 | * once cmd_dma_done interrupt received, | |
2137 | * return data from client is ready and stored | |
2138 | * at RDBK_DATA register already | |
2139 | * since rx fifo is 16 bytes, dcs header is kept at first loop, | |
2140 | * after that dcs header lost during shift into registers | |
2141 | */ | |
2142 | dlen = dsi_cmd_dma_rx(msm_host, buf, rx_byte, pkt_size); | |
2143 | ||
2144 | if (dlen <= 0) | |
2145 | return 0; | |
2146 | ||
2147 | if (short_response) | |
2148 | break; | |
2149 | ||
2150 | if (rlen <= data_byte) { | |
2151 | diff = data_byte - rlen; | |
2152 | end = 1; | |
2153 | } else { | |
2154 | diff = 0; | |
2155 | rlen -= data_byte; | |
2156 | } | |
2157 | ||
2158 | if (!end) { | |
2159 | dlen -= 2; /* 2 crc */ | |
2160 | dlen -= diff; | |
2161 | buf += dlen; /* next start position */ | |
2162 | data_byte = 14; /* NOT first read */ | |
2163 | if (rlen < data_byte) | |
2164 | pkt_size += rlen; | |
2165 | else | |
2166 | pkt_size += data_byte; | |
2167 | DBG("buf=%p dlen=%d diff=%d", buf, dlen, diff); | |
2168 | } | |
2169 | } | |
2170 | ||
2171 | /* | |
2172 | * For single Long read, if the requested rlen < 10, | |
2173 | * we need to shift the start position of rx | |
2174 | * data buffer to skip the bytes which are not | |
2175 | * updated. | |
2176 | */ | |
2177 | if (pkt_size < 10 && !short_response) | |
2178 | buf = msm_host->rx_buf + (10 - rlen); | |
2179 | else | |
2180 | buf = msm_host->rx_buf; | |
2181 | ||
2182 | cmd = buf[0]; | |
2183 | switch (cmd) { | |
2184 | case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: | |
2185 | pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__); | |
2186 | ret = 0; | |
651ad3f5 | 2187 | break; |
a689554b HL |
2188 | case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: |
2189 | case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: | |
2190 | ret = dsi_short_read1_resp(buf, msg); | |
2191 | break; | |
2192 | case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: | |
2193 | case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: | |
2194 | ret = dsi_short_read2_resp(buf, msg); | |
2195 | break; | |
2196 | case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE: | |
2197 | case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE: | |
2198 | ret = dsi_long_read_resp(buf, msg); | |
2199 | break; | |
2200 | default: | |
2201 | pr_warn("%s:Invalid response cmd\n", __func__); | |
2202 | ret = 0; | |
2203 | } | |
2204 | ||
2205 | return ret; | |
2206 | } | |
2207 | ||
4ff9d4cb AT |
2208 | void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base, |
2209 | u32 len) | |
a689554b HL |
2210 | { |
2211 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
2212 | ||
4ff9d4cb | 2213 | dsi_write(msm_host, REG_DSI_DMA_BASE, dma_base); |
a689554b HL |
2214 | dsi_write(msm_host, REG_DSI_DMA_LEN, len); |
2215 | dsi_write(msm_host, REG_DSI_TRIG_DMA, 1); | |
2216 | ||
2217 | /* Make sure trigger happens */ | |
2218 | wmb(); | |
2219 | } | |
2220 | ||
a817a950 DB |
2221 | void msm_dsi_host_set_phy_mode(struct mipi_dsi_host *host, |
2222 | struct msm_dsi_phy *src_phy) | |
2223 | { | |
2224 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
2225 | ||
2226 | msm_host->cphy_mode = src_phy->cphy_mode; | |
2227 | } | |
2228 | ||
34d9545b AT |
2229 | void msm_dsi_host_reset_phy(struct mipi_dsi_host *host) |
2230 | { | |
2231 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
2232 | ||
2233 | DBG(""); | |
2234 | dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET); | |
2235 | /* Make sure fully reset */ | |
2236 | wmb(); | |
2237 | udelay(1000); | |
2238 | dsi_write(msm_host, REG_DSI_PHY_RESET, 0); | |
2239 | udelay(100); | |
2240 | } | |
2241 | ||
b62aa70a | 2242 | void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host, |
ed9976a0 | 2243 | struct msm_dsi_phy_clk_request *clk_req, |
6183606d | 2244 | bool is_bonded_dsi) |
b62aa70a HL |
2245 | { |
2246 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
8f7ca540 | 2247 | const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; |
d4cea38e AT |
2248 | int ret; |
2249 | ||
6183606d | 2250 | ret = cfg_hnd->ops->calc_clk_rate(msm_host, is_bonded_dsi); |
d4cea38e AT |
2251 | if (ret) { |
2252 | pr_err("%s: unable to calc clk rate, %d\n", __func__, ret); | |
2253 | return; | |
2254 | } | |
b62aa70a | 2255 | |
5ac17838 JM |
2256 | /* CPHY transmits 16 bits over 7 clock cycles |
2257 | * "byte_clk" is in units of 16-bits (see dsi_calc_pclk), | |
2258 | * so multiply by 7 to get the "bitclk rate" | |
2259 | */ | |
2260 | if (msm_host->cphy_mode) | |
2261 | clk_req->bitclk_rate = msm_host->byte_clk_rate * 7; | |
2262 | else | |
2263 | clk_req->bitclk_rate = msm_host->byte_clk_rate * 8; | |
b62aa70a HL |
2264 | clk_req->escclk_rate = msm_host->esc_clk_rate; |
2265 | } | |
2266 | ||
bf94ec09 DB |
2267 | void msm_dsi_host_enable_irq(struct mipi_dsi_host *host) |
2268 | { | |
2269 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
2270 | ||
2271 | enable_irq(msm_host->irq); | |
2272 | } | |
2273 | ||
2274 | void msm_dsi_host_disable_irq(struct mipi_dsi_host *host) | |
2275 | { | |
2276 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
2277 | ||
2278 | disable_irq(msm_host->irq); | |
2279 | } | |
2280 | ||
a689554b HL |
2281 | int msm_dsi_host_enable(struct mipi_dsi_host *host) |
2282 | { | |
2283 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
2284 | ||
2285 | dsi_op_mode_config(msm_host, | |
2286 | !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), true); | |
2287 | ||
2288 | /* TODO: clock should be turned off for command mode, | |
2289 | * and only turned on before MDP START. | |
2290 | * This part of code should be enabled once mdp driver support it. | |
2291 | */ | |
f54ca1a0 AT |
2292 | /* if (msm_panel->mode == MSM_DSI_CMD_MODE) { |
2293 | * dsi_link_clk_disable(msm_host); | |
f3d5d7cc | 2294 | * pm_runtime_put(&msm_host->pdev->dev); |
f54ca1a0 AT |
2295 | * } |
2296 | */ | |
9c5638d7 | 2297 | msm_host->enabled = true; |
a689554b HL |
2298 | return 0; |
2299 | } | |
2300 | ||
2301 | int msm_dsi_host_disable(struct mipi_dsi_host *host) | |
2302 | { | |
2303 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
2304 | ||
9c5638d7 | 2305 | msm_host->enabled = false; |
a689554b HL |
2306 | dsi_op_mode_config(msm_host, |
2307 | !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), false); | |
2308 | ||
2309 | /* Since we have disabled INTF, the video engine won't stop so that | |
2310 | * the cmd engine will be blocked. | |
2311 | * Reset to disable video engine so that we can send off cmd. | |
2312 | */ | |
2313 | dsi_sw_reset(msm_host); | |
2314 | ||
2315 | return 0; | |
2316 | } | |
2317 | ||
0c7df47f AT |
2318 | static void msm_dsi_sfpb_config(struct msm_dsi_host *msm_host, bool enable) |
2319 | { | |
2320 | enum sfpb_ahb_arb_master_port_en en; | |
2321 | ||
2322 | if (!msm_host->sfpb) | |
2323 | return; | |
2324 | ||
2325 | en = enable ? SFPB_MASTER_PORT_ENABLE : SFPB_MASTER_PORT_DISABLE; | |
2326 | ||
2327 | regmap_update_bits(msm_host->sfpb, REG_SFPB_GPREG, | |
2328 | SFPB_GPREG_MASTER_PORT_EN__MASK, | |
2329 | SFPB_GPREG_MASTER_PORT_EN(en)); | |
2330 | } | |
2331 | ||
b62aa70a | 2332 | int msm_dsi_host_power_on(struct mipi_dsi_host *host, |
ed9976a0 | 2333 | struct msm_dsi_phy_shared_timings *phy_shared_timings, |
858c595a | 2334 | bool is_bonded_dsi, struct msm_dsi_phy *phy) |
a689554b HL |
2335 | { |
2336 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
8f7ca540 | 2337 | const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; |
a689554b HL |
2338 | int ret = 0; |
2339 | ||
2340 | mutex_lock(&msm_host->dev_mutex); | |
2341 | if (msm_host->power_on) { | |
2342 | DBG("dsi host already on"); | |
2343 | goto unlock_ret; | |
2344 | } | |
2345 | ||
1d5e01df DB |
2346 | msm_host->byte_intf_clk_rate = msm_host->byte_clk_rate; |
2347 | if (phy_shared_timings->byte_intf_clk_div_2) | |
2348 | msm_host->byte_intf_clk_rate /= 2; | |
2349 | ||
0c7df47f AT |
2350 | msm_dsi_sfpb_config(msm_host, true); |
2351 | ||
d8810a66 | 2352 | ret = regulator_bulk_enable(msm_host->cfg_hnd->cfg->num_regulators, |
0587e9aa | 2353 | msm_host->supplies); |
a689554b HL |
2354 | if (ret) { |
2355 | pr_err("%s:Failed to enable vregs.ret=%d\n", | |
2356 | __func__, ret); | |
2357 | goto unlock_ret; | |
2358 | } | |
2359 | ||
f6be1121 | 2360 | pm_runtime_get_sync(&msm_host->pdev->dev); |
6b16f05a RC |
2361 | ret = cfg_hnd->ops->link_clk_set_rate(msm_host); |
2362 | if (!ret) | |
2363 | ret = cfg_hnd->ops->link_clk_enable(msm_host); | |
a689554b | 2364 | if (ret) { |
f54ca1a0 AT |
2365 | pr_err("%s: failed to enable link clocks. ret=%d\n", |
2366 | __func__, ret); | |
a689554b HL |
2367 | goto fail_disable_reg; |
2368 | } | |
2369 | ||
ab8909b0 HL |
2370 | ret = pinctrl_pm_select_default_state(&msm_host->pdev->dev); |
2371 | if (ret) { | |
2372 | pr_err("%s: failed to set pinctrl default state, %d\n", | |
2373 | __func__, ret); | |
2374 | goto fail_disable_clk; | |
2375 | } | |
2376 | ||
6183606d | 2377 | dsi_timing_setup(msm_host, is_bonded_dsi); |
a689554b | 2378 | dsi_sw_reset(msm_host); |
452c46cc | 2379 | dsi_ctrl_enable(msm_host, phy_shared_timings, phy); |
a689554b HL |
2380 | |
2381 | if (msm_host->disp_en_gpio) | |
2382 | gpiod_set_value(msm_host->disp_en_gpio, 1); | |
2383 | ||
2384 | msm_host->power_on = true; | |
2385 | mutex_unlock(&msm_host->dev_mutex); | |
2386 | ||
2387 | return 0; | |
2388 | ||
ab8909b0 | 2389 | fail_disable_clk: |
8f7ca540 | 2390 | cfg_hnd->ops->link_clk_disable(msm_host); |
f3d5d7cc | 2391 | pm_runtime_put(&msm_host->pdev->dev); |
a689554b | 2392 | fail_disable_reg: |
d8810a66 | 2393 | regulator_bulk_disable(msm_host->cfg_hnd->cfg->num_regulators, |
0587e9aa | 2394 | msm_host->supplies); |
a689554b HL |
2395 | unlock_ret: |
2396 | mutex_unlock(&msm_host->dev_mutex); | |
2397 | return ret; | |
2398 | } | |
2399 | ||
2400 | int msm_dsi_host_power_off(struct mipi_dsi_host *host) | |
2401 | { | |
2402 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
8f7ca540 | 2403 | const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; |
a689554b HL |
2404 | |
2405 | mutex_lock(&msm_host->dev_mutex); | |
2406 | if (!msm_host->power_on) { | |
2407 | DBG("dsi host already off"); | |
2408 | goto unlock_ret; | |
2409 | } | |
2410 | ||
452c46cc | 2411 | dsi_ctrl_disable(msm_host); |
a689554b HL |
2412 | |
2413 | if (msm_host->disp_en_gpio) | |
2414 | gpiod_set_value(msm_host->disp_en_gpio, 0); | |
2415 | ||
ab8909b0 HL |
2416 | pinctrl_pm_select_sleep_state(&msm_host->pdev->dev); |
2417 | ||
8f7ca540 | 2418 | cfg_hnd->ops->link_clk_disable(msm_host); |
f3d5d7cc | 2419 | pm_runtime_put(&msm_host->pdev->dev); |
a689554b | 2420 | |
d8810a66 | 2421 | regulator_bulk_disable(msm_host->cfg_hnd->cfg->num_regulators, |
0587e9aa | 2422 | msm_host->supplies); |
a689554b | 2423 | |
0c7df47f AT |
2424 | msm_dsi_sfpb_config(msm_host, false); |
2425 | ||
a689554b HL |
2426 | DBG("-"); |
2427 | ||
2428 | msm_host->power_on = false; | |
2429 | ||
2430 | unlock_ret: | |
2431 | mutex_unlock(&msm_host->dev_mutex); | |
2432 | return 0; | |
2433 | } | |
2434 | ||
2435 | int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host, | |
63f8f3ba | 2436 | const struct drm_display_mode *mode) |
a689554b HL |
2437 | { |
2438 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
2439 | ||
2440 | if (msm_host->mode) { | |
2441 | drm_mode_destroy(msm_host->dev, msm_host->mode); | |
2442 | msm_host->mode = NULL; | |
2443 | } | |
2444 | ||
2445 | msm_host->mode = drm_mode_duplicate(msm_host->dev, mode); | |
2abe1f25 | 2446 | if (!msm_host->mode) { |
a689554b | 2447 | pr_err("%s: cannot duplicate mode\n", __func__); |
2abe1f25 | 2448 | return -ENOMEM; |
a689554b HL |
2449 | } |
2450 | ||
2451 | return 0; | |
2452 | } | |
2453 | ||
89f1bfc4 VK |
2454 | enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host, |
2455 | const struct drm_display_mode *mode) | |
2456 | { | |
2457 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
4b2b1b36 | 2458 | struct drm_dsc_config *dsc = msm_host->dsc; |
89f1bfc4 VK |
2459 | int pic_width = mode->hdisplay; |
2460 | int pic_height = mode->vdisplay; | |
2461 | ||
2462 | if (!msm_host->dsc) | |
2463 | return MODE_OK; | |
2464 | ||
4b2b1b36 | 2465 | if (pic_width % dsc->slice_width) { |
89f1bfc4 | 2466 | pr_err("DSI: pic_width %d has to be multiple of slice %d\n", |
4b2b1b36 | 2467 | pic_width, dsc->slice_width); |
89f1bfc4 VK |
2468 | return MODE_H_ILLEGAL; |
2469 | } | |
2470 | ||
4b2b1b36 | 2471 | if (pic_height % dsc->slice_height) { |
89f1bfc4 | 2472 | pr_err("DSI: pic_height %d has to be multiple of slice %d\n", |
4b2b1b36 | 2473 | pic_height, dsc->slice_height); |
89f1bfc4 VK |
2474 | return MODE_V_ILLEGAL; |
2475 | } | |
2476 | ||
2477 | return MODE_OK; | |
2478 | } | |
2479 | ||
e3a91f89 SP |
2480 | unsigned long msm_dsi_host_get_mode_flags(struct mipi_dsi_host *host) |
2481 | { | |
2482 | return to_msm_dsi_host(host)->mode_flags; | |
a689554b HL |
2483 | } |
2484 | ||
eb9d6c7e | 2485 | void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_host *host) |
9d30a4bc AK |
2486 | { |
2487 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
9d30a4bc AK |
2488 | |
2489 | pm_runtime_get_sync(&msm_host->pdev->dev); | |
2490 | ||
bac2c6a6 | 2491 | msm_disp_snapshot_add_block(disp_state, msm_host->ctrl_size, |
9d30a4bc AK |
2492 | msm_host->ctrl_base, "dsi%d_ctrl", msm_host->id); |
2493 | ||
2494 | pm_runtime_put_sync(&msm_host->pdev->dev); | |
2495 | } | |
5e2a72d4 AK |
2496 | |
2497 | static void msm_dsi_host_video_test_pattern_setup(struct msm_dsi_host *msm_host) | |
2498 | { | |
2499 | u32 reg; | |
2500 | ||
2501 | reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); | |
2502 | ||
2503 | dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_VIDEO_INIT_VAL, 0xff); | |
2504 | /* draw checkered rectangle pattern */ | |
2505 | dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL, | |
2506 | DSI_TPG_MAIN_CONTROL_CHECKERED_RECTANGLE_PATTERN); | |
2507 | /* use 24-bit RGB test pttern */ | |
2508 | dsi_write(msm_host, REG_DSI_TPG_VIDEO_CONFIG, | |
2509 | DSI_TPG_VIDEO_CONFIG_BPP(VIDEO_CONFIG_24BPP) | | |
2510 | DSI_TPG_VIDEO_CONFIG_RGB); | |
2511 | ||
2512 | reg |= DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL(VID_MDSS_GENERAL_PATTERN); | |
2513 | dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg); | |
2514 | ||
2515 | DBG("Video test pattern setup done\n"); | |
2516 | } | |
2517 | ||
2518 | static void msm_dsi_host_cmd_test_pattern_setup(struct msm_dsi_host *msm_host) | |
2519 | { | |
2520 | u32 reg; | |
2521 | ||
2522 | reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); | |
2523 | ||
2524 | /* initial value for test pattern */ | |
2525 | dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0, 0xff); | |
2526 | ||
2527 | reg |= DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL(CMD_MDP_MDSS_GENERAL_PATTERN); | |
2528 | ||
2529 | dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg); | |
2530 | /* draw checkered rectangle pattern */ | |
2531 | dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL2, | |
2532 | DSI_TPG_MAIN_CONTROL2_CMD_MDP0_CHECKERED_RECTANGLE_PATTERN); | |
2533 | ||
2534 | DBG("Cmd test pattern setup done\n"); | |
2535 | } | |
2536 | ||
2537 | void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host) | |
2538 | { | |
2539 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
2540 | bool is_video_mode = !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO); | |
2541 | u32 reg; | |
2542 | ||
2543 | if (is_video_mode) | |
2544 | msm_dsi_host_video_test_pattern_setup(msm_host); | |
2545 | else | |
2546 | msm_dsi_host_cmd_test_pattern_setup(msm_host); | |
2547 | ||
2548 | reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); | |
2549 | /* enable the test pattern generator */ | |
2550 | dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, (reg | DSI_TEST_PATTERN_GEN_CTRL_EN)); | |
2551 | ||
2552 | /* for command mode need to trigger one frame from tpg */ | |
2553 | if (!is_video_mode) | |
2554 | dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER, | |
2555 | DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER_SW_TRIGGER); | |
2556 | } | |
0f40ba48 | 2557 | |
4b2b1b36 | 2558 | struct drm_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host) |
0f40ba48 VK |
2559 | { |
2560 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
2561 | ||
2562 | return msm_host->dsc; | |
2563 | } |