Commit | Line | Data |
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caab277b | 1 | // SPDX-License-Identifier: GPL-2.0-only |
06c0dd96 | 2 | /* |
68cdbed9 | 3 | * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved. |
06c0dd96 RC |
4 | * Copyright (C) 2013 Red Hat |
5 | * Author: Rob Clark <robdclark@gmail.com> | |
06c0dd96 RC |
6 | */ |
7 | ||
ed851963 | 8 | #include <linux/sort.h> |
06c0dd96 | 9 | #include <drm/drm_mode.h> |
78f27b1c | 10 | #include <drm/drm_crtc.h> |
78f27b1c | 11 | #include <drm/drm_flip_work.h> |
fcd70cd3 | 12 | #include <drm/drm_probe_helper.h> |
78f27b1c MY |
13 | |
14 | #include "mdp5_kms.h" | |
06c0dd96 | 15 | |
e172d10a BG |
16 | #define CURSOR_WIDTH 64 |
17 | #define CURSOR_HEIGHT 64 | |
18 | ||
06c0dd96 RC |
19 | struct mdp5_crtc { |
20 | struct drm_crtc base; | |
06c0dd96 RC |
21 | int id; |
22 | bool enabled; | |
23 | ||
adfc0e63 | 24 | spinlock_t lm_lock; /* protect REG_MDP5_LM_* registers */ |
0deed25b | 25 | |
06c0dd96 RC |
26 | /* if there is a pending flip, these will be non-null: */ |
27 | struct drm_pending_vblank_event *event; | |
06c0dd96 | 28 | |
0a5c9aad HL |
29 | /* Bits have been flushed at the last commit, |
30 | * used to decide if a vsync has happened since last commit. | |
31 | */ | |
32 | u32 flushed_mask; | |
33 | ||
06c0dd96 RC |
34 | #define PENDING_CURSOR 0x1 |
35 | #define PENDING_FLIP 0x2 | |
36 | atomic_t pending; | |
37 | ||
e172d10a BG |
38 | /* for unref'ing cursor bo's after scanout completes: */ |
39 | struct drm_flip_work unref_cursor_work; | |
40 | ||
06c0dd96 RC |
41 | struct mdp_irq vblank; |
42 | struct mdp_irq err; | |
68cdbed9 HL |
43 | struct mdp_irq pp_done; |
44 | ||
45 | struct completion pp_completion; | |
46 | ||
aa649e87 AT |
47 | bool lm_cursor_enabled; |
48 | ||
e172d10a BG |
49 | struct { |
50 | /* protect REG_MDP5_LM_CURSOR* registers and cursor scanout_bo*/ | |
51 | spinlock_t lock; | |
52 | ||
53 | /* current cursor being scanned out: */ | |
54 | struct drm_gem_object *scanout_bo; | |
9d9ea7a9 | 55 | uint64_t iova; |
58560890 | 56 | uint32_t width, height; |
23f94551 | 57 | int x, y; |
e172d10a | 58 | } cursor; |
06c0dd96 RC |
59 | }; |
60 | #define to_mdp5_crtc(x) container_of(x, struct mdp5_crtc, base) | |
61 | ||
9d9ea7a9 RC |
62 | static void mdp5_crtc_restore_cursor(struct drm_crtc *crtc); |
63 | ||
06c0dd96 RC |
64 | static struct mdp5_kms *get_kms(struct drm_crtc *crtc) |
65 | { | |
66 | struct msm_drm_private *priv = crtc->dev->dev_private; | |
67 | return to_mdp5_kms(to_mdp_kms(priv->kms)); | |
68 | } | |
69 | ||
70 | static void request_pending(struct drm_crtc *crtc, uint32_t pending) | |
71 | { | |
72 | struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); | |
73 | ||
74 | atomic_or(pending, &mdp5_crtc->pending); | |
75 | mdp_irq_register(&get_kms(crtc)->base, &mdp5_crtc->vblank); | |
76 | } | |
77 | ||
68cdbed9 HL |
78 | static void request_pp_done_pending(struct drm_crtc *crtc) |
79 | { | |
80 | struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); | |
81 | reinit_completion(&mdp5_crtc->pp_completion); | |
82 | } | |
83 | ||
0a5c9aad | 84 | static u32 crtc_flush(struct drm_crtc *crtc, u32 flush_mask) |
0deed25b | 85 | { |
0ddc3a63 AT |
86 | struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); |
87 | struct mdp5_ctl *ctl = mdp5_cstate->ctl; | |
f316b25a | 88 | struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; |
f9cb8d8d RC |
89 | bool start = !mdp5_cstate->defer_start; |
90 | ||
91 | mdp5_cstate->defer_start = false; | |
0deed25b | 92 | |
cee26588 | 93 | DBG("%s: flush=%08x", crtc->name, flush_mask); |
f9cb8d8d RC |
94 | |
95 | return mdp5_ctl_commit(ctl, pipeline, flush_mask, start); | |
0deed25b SV |
96 | } |
97 | ||
98 | /* | |
99 | * flush updates, to make sure hw is updated to new scanout fb, | |
100 | * so that we can safely queue unref to current fb (ie. next | |
101 | * vblank we know hw is done w/ previous scanout_fb). | |
102 | */ | |
0a5c9aad | 103 | static u32 crtc_flush_all(struct drm_crtc *crtc) |
06c0dd96 | 104 | { |
0ddc3a63 | 105 | struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); |
b7621b2a | 106 | struct mdp5_hw_mixer *mixer, *r_mixer; |
a8cecf33 | 107 | struct drm_plane *plane; |
0deed25b SV |
108 | uint32_t flush_mask = 0; |
109 | ||
ba0312a6 | 110 | /* this should not happen: */ |
0ddc3a63 | 111 | if (WARN_ON(!mdp5_cstate->ctl)) |
0a5c9aad | 112 | return 0; |
06c0dd96 | 113 | |
93b02beb | 114 | drm_atomic_crtc_for_each_plane(plane, crtc) { |
a055cf3a RC |
115 | if (!plane->state->visible) |
116 | continue; | |
0deed25b | 117 | flush_mask |= mdp5_plane_get_flush(plane); |
06c0dd96 | 118 | } |
389b09a1 | 119 | |
0ddc3a63 | 120 | mixer = mdp5_cstate->pipeline.mixer; |
adfc0e63 | 121 | flush_mask |= mdp_ctl_flush_mask_lm(mixer->lm); |
a8cecf33 | 122 | |
b7621b2a AT |
123 | r_mixer = mdp5_cstate->pipeline.r_mixer; |
124 | if (r_mixer) | |
125 | flush_mask |= mdp_ctl_flush_mask_lm(r_mixer->lm); | |
126 | ||
0a5c9aad | 127 | return crtc_flush(crtc, flush_mask); |
06c0dd96 RC |
128 | } |
129 | ||
06c0dd96 RC |
130 | /* if file!=NULL, this is preclose potential cancel-flip path */ |
131 | static void complete_flip(struct drm_crtc *crtc, struct drm_file *file) | |
132 | { | |
0ddc3a63 | 133 | struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); |
f316b25a | 134 | struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; |
06c0dd96 | 135 | struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); |
0ddc3a63 | 136 | struct mdp5_ctl *ctl = mdp5_cstate->ctl; |
06c0dd96 RC |
137 | struct drm_device *dev = crtc->dev; |
138 | struct drm_pending_vblank_event *event; | |
a8cecf33 | 139 | unsigned long flags; |
06c0dd96 RC |
140 | |
141 | spin_lock_irqsave(&dev->event_lock, flags); | |
142 | event = mdp5_crtc->event; | |
143 | if (event) { | |
02efb359 DV |
144 | mdp5_crtc->event = NULL; |
145 | DBG("%s: send event: %p", crtc->name, event); | |
146 | drm_crtc_send_vblank_event(crtc, event); | |
06c0dd96 RC |
147 | } |
148 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
149 | ||
0ddc3a63 | 150 | if (ctl && !crtc->state->enable) { |
e5989ee1 | 151 | /* set STAGE_UNUSED for all layers */ |
b7621b2a | 152 | mdp5_ctl_blend(ctl, pipeline, NULL, NULL, 0, 0); |
0ddc3a63 AT |
153 | /* XXX: What to do here? */ |
154 | /* mdp5_crtc->ctl = NULL; */ | |
ba0312a6 | 155 | } |
06c0dd96 RC |
156 | } |
157 | ||
e172d10a BG |
158 | static void unref_cursor_worker(struct drm_flip_work *work, void *val) |
159 | { | |
160 | struct mdp5_crtc *mdp5_crtc = | |
161 | container_of(work, struct mdp5_crtc, unref_cursor_work); | |
162 | struct mdp5_kms *mdp5_kms = get_kms(&mdp5_crtc->base); | |
f59f62d5 | 163 | struct msm_kms *kms = &mdp5_kms->base.base; |
e172d10a | 164 | |
7ad0e8cf | 165 | msm_gem_unpin_iova(val, kms->aspace); |
dc9a9b32 | 166 | drm_gem_object_put_unlocked(val); |
e172d10a BG |
167 | } |
168 | ||
06c0dd96 RC |
169 | static void mdp5_crtc_destroy(struct drm_crtc *crtc) |
170 | { | |
171 | struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); | |
172 | ||
06c0dd96 | 173 | drm_crtc_cleanup(crtc); |
e172d10a | 174 | drm_flip_work_cleanup(&mdp5_crtc->unref_cursor_work); |
06c0dd96 RC |
175 | |
176 | kfree(mdp5_crtc); | |
177 | } | |
178 | ||
829200ac AT |
179 | static inline u32 mdp5_lm_use_fg_alpha_mask(enum mdp_mixer_stage_id stage) |
180 | { | |
181 | switch (stage) { | |
182 | case STAGE0: return MDP5_LM_BLEND_COLOR_OUT_STAGE0_FG_ALPHA; | |
183 | case STAGE1: return MDP5_LM_BLEND_COLOR_OUT_STAGE1_FG_ALPHA; | |
184 | case STAGE2: return MDP5_LM_BLEND_COLOR_OUT_STAGE2_FG_ALPHA; | |
185 | case STAGE3: return MDP5_LM_BLEND_COLOR_OUT_STAGE3_FG_ALPHA; | |
186 | case STAGE4: return MDP5_LM_BLEND_COLOR_OUT_STAGE4_FG_ALPHA; | |
187 | case STAGE5: return MDP5_LM_BLEND_COLOR_OUT_STAGE5_FG_ALPHA; | |
188 | case STAGE6: return MDP5_LM_BLEND_COLOR_OUT_STAGE6_FG_ALPHA; | |
189 | default: | |
190 | return 0; | |
191 | } | |
192 | } | |
193 | ||
b7621b2a AT |
194 | /* |
195 | * left/right pipe offsets for the stage array used in blend_setup() | |
196 | */ | |
197 | #define PIPE_LEFT 0 | |
198 | #define PIPE_RIGHT 1 | |
199 | ||
0deed25b SV |
200 | /* |
201 | * blend_setup() - blend all the planes of a CRTC | |
202 | * | |
12987781 | 203 | * If no base layer is available, border will be enabled as the base layer. |
204 | * Otherwise all layers will be blended based on their stage calculated | |
205 | * in mdp5_crtc_atomic_check. | |
0deed25b | 206 | */ |
06c0dd96 RC |
207 | static void blend_setup(struct drm_crtc *crtc) |
208 | { | |
209 | struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); | |
0ddc3a63 | 210 | struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); |
f316b25a | 211 | struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; |
06c0dd96 | 212 | struct mdp5_kms *mdp5_kms = get_kms(crtc); |
0deed25b SV |
213 | struct drm_plane *plane; |
214 | const struct mdp5_cfg_hw *hw_cfg; | |
12987781 | 215 | struct mdp5_plane_state *pstate, *pstates[STAGE_MAX + 1] = {NULL}; |
216 | const struct mdp_format *format; | |
f316b25a | 217 | struct mdp5_hw_mixer *mixer = pipeline->mixer; |
adfc0e63 | 218 | uint32_t lm = mixer->lm; |
b7621b2a AT |
219 | struct mdp5_hw_mixer *r_mixer = pipeline->r_mixer; |
220 | uint32_t r_lm = r_mixer ? r_mixer->lm : 0; | |
0ddc3a63 | 221 | struct mdp5_ctl *ctl = mdp5_cstate->ctl; |
12987781 | 222 | uint32_t blend_op, fg_alpha, bg_alpha, ctl_blend_flags = 0; |
0deed25b | 223 | unsigned long flags; |
d490c9cd VK |
224 | enum mdp5_pipe stage[STAGE_MAX + 1][MAX_PIPE_STAGE] = { { SSPP_NONE } }; |
225 | enum mdp5_pipe r_stage[STAGE_MAX + 1][MAX_PIPE_STAGE] = { { SSPP_NONE } }; | |
12987781 | 226 | int i, plane_cnt = 0; |
829200ac AT |
227 | bool bg_alpha_enabled = false; |
228 | u32 mixer_op_mode = 0; | |
ed78560d | 229 | u32 val; |
12987781 | 230 | #define blender(stage) ((stage) - STAGE0) |
06c0dd96 | 231 | |
42238da8 | 232 | hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); |
06c0dd96 | 233 | |
0deed25b SV |
234 | spin_lock_irqsave(&mdp5_crtc->lm_lock, flags); |
235 | ||
236 | /* ctl could be released already when we are shutting down: */ | |
0ddc3a63 AT |
237 | /* XXX: Can this happen now? */ |
238 | if (!ctl) | |
0deed25b SV |
239 | goto out; |
240 | ||
12987781 | 241 | /* Collect all plane information */ |
93b02beb | 242 | drm_atomic_crtc_for_each_plane(plane, crtc) { |
bf8dc0a0 AT |
243 | enum mdp5_pipe right_pipe; |
244 | ||
a055cf3a RC |
245 | if (!plane->state->visible) |
246 | continue; | |
247 | ||
12987781 | 248 | pstate = to_mdp5_plane_state(plane->state); |
249 | pstates[pstate->stage] = pstate; | |
b7621b2a AT |
250 | stage[pstate->stage][PIPE_LEFT] = mdp5_plane_pipe(plane); |
251 | /* | |
252 | * if we have a right mixer, stage the same pipe as we | |
253 | * have on the left mixer | |
254 | */ | |
255 | if (r_mixer) | |
256 | r_stage[pstate->stage][PIPE_LEFT] = | |
257 | mdp5_plane_pipe(plane); | |
bf8dc0a0 AT |
258 | /* |
259 | * if we have a right pipe (i.e, the plane comprises of 2 | |
260 | * hwpipes, then stage the right pipe on the right side of both | |
261 | * the layer mixers | |
262 | */ | |
263 | right_pipe = mdp5_plane_right_pipe(plane); | |
264 | if (right_pipe) { | |
265 | stage[pstate->stage][PIPE_RIGHT] = right_pipe; | |
266 | r_stage[pstate->stage][PIPE_RIGHT] = right_pipe; | |
267 | } | |
b7621b2a | 268 | |
12987781 | 269 | plane_cnt++; |
270 | } | |
06c0dd96 | 271 | |
1455adbd | 272 | if (!pstates[STAGE_BASE]) { |
12987781 | 273 | ctl_blend_flags |= MDP5_CTL_BLEND_OP_FLAG_BORDER_OUT; |
274 | DBG("Border Color is enabled"); | |
829200ac AT |
275 | } else if (plane_cnt) { |
276 | format = to_mdp_format(msm_framebuffer_format(pstates[STAGE_BASE]->base.fb)); | |
277 | ||
278 | if (format->alpha_enable) | |
279 | bg_alpha_enabled = true; | |
12987781 | 280 | } |
281 | ||
282 | /* The reset for blending */ | |
283 | for (i = STAGE0; i <= STAGE_MAX; i++) { | |
284 | if (!pstates[i]) | |
285 | continue; | |
286 | ||
287 | format = to_mdp_format( | |
288 | msm_framebuffer_format(pstates[i]->base.fb)); | |
289 | plane = pstates[i]->base.plane; | |
290 | blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) | | |
291 | MDP5_LM_BLEND_OP_MODE_BG_ALPHA(BG_CONST); | |
292 | fg_alpha = pstates[i]->alpha; | |
293 | bg_alpha = 0xFF - pstates[i]->alpha; | |
829200ac AT |
294 | |
295 | if (!format->alpha_enable && bg_alpha_enabled) | |
296 | mixer_op_mode = 0; | |
297 | else | |
298 | mixer_op_mode |= mdp5_lm_use_fg_alpha_mask(i); | |
299 | ||
12987781 | 300 | DBG("Stage %d fg_alpha %x bg_alpha %x", i, fg_alpha, bg_alpha); |
301 | ||
302 | if (format->alpha_enable && pstates[i]->premultiplied) { | |
303 | blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) | | |
304 | MDP5_LM_BLEND_OP_MODE_BG_ALPHA(FG_PIXEL); | |
305 | if (fg_alpha != 0xff) { | |
306 | bg_alpha = fg_alpha; | |
307 | blend_op |= | |
308 | MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA | | |
309 | MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA; | |
310 | } else { | |
311 | blend_op |= MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA; | |
312 | } | |
313 | } else if (format->alpha_enable) { | |
314 | blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_PIXEL) | | |
315 | MDP5_LM_BLEND_OP_MODE_BG_ALPHA(FG_PIXEL); | |
316 | if (fg_alpha != 0xff) { | |
317 | bg_alpha = fg_alpha; | |
318 | blend_op |= | |
319 | MDP5_LM_BLEND_OP_MODE_FG_MOD_ALPHA | | |
320 | MDP5_LM_BLEND_OP_MODE_FG_INV_MOD_ALPHA | | |
321 | MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA | | |
322 | MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA; | |
323 | } else { | |
324 | blend_op |= MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA; | |
325 | } | |
326 | } | |
0deed25b | 327 | |
12987781 | 328 | mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_OP_MODE(lm, |
329 | blender(i)), blend_op); | |
0deed25b | 330 | mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_FG_ALPHA(lm, |
12987781 | 331 | blender(i)), fg_alpha); |
0deed25b | 332 | mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_BG_ALPHA(lm, |
12987781 | 333 | blender(i)), bg_alpha); |
b7621b2a AT |
334 | if (r_mixer) { |
335 | mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_OP_MODE(r_lm, | |
336 | blender(i)), blend_op); | |
337 | mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_FG_ALPHA(r_lm, | |
338 | blender(i)), fg_alpha); | |
339 | mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_BG_ALPHA(r_lm, | |
340 | blender(i)), bg_alpha); | |
341 | } | |
0deed25b SV |
342 | } |
343 | ||
ed78560d AT |
344 | val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm)); |
345 | mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm), | |
346 | val | mixer_op_mode); | |
347 | if (r_mixer) { | |
348 | val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm)); | |
b7621b2a | 349 | mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm), |
ed78560d AT |
350 | val | mixer_op_mode); |
351 | } | |
829200ac | 352 | |
b7621b2a AT |
353 | mdp5_ctl_blend(ctl, pipeline, stage, r_stage, plane_cnt, |
354 | ctl_blend_flags); | |
0deed25b SV |
355 | out: |
356 | spin_unlock_irqrestore(&mdp5_crtc->lm_lock, flags); | |
06c0dd96 RC |
357 | } |
358 | ||
ed851963 | 359 | static void mdp5_crtc_mode_set_nofb(struct drm_crtc *crtc) |
06c0dd96 RC |
360 | { |
361 | struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); | |
0ddc3a63 | 362 | struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); |
06c0dd96 | 363 | struct mdp5_kms *mdp5_kms = get_kms(crtc); |
0ddc3a63 | 364 | struct mdp5_hw_mixer *mixer = mdp5_cstate->pipeline.mixer; |
b7621b2a | 365 | struct mdp5_hw_mixer *r_mixer = mdp5_cstate->pipeline.r_mixer; |
adfc0e63 | 366 | uint32_t lm = mixer->lm; |
ed78560d | 367 | u32 mixer_width, val; |
0deed25b | 368 | unsigned long flags; |
ed851963 RC |
369 | struct drm_display_mode *mode; |
370 | ||
371 | if (WARN_ON(!crtc->state)) | |
372 | return; | |
06c0dd96 | 373 | |
ed851963 | 374 | mode = &crtc->state->adjusted_mode; |
06c0dd96 | 375 | |
7510a9c6 | 376 | DBG("%s: set mode: " DRM_MODE_FMT, crtc->name, DRM_MODE_ARG(mode)); |
06c0dd96 | 377 | |
ed78560d AT |
378 | mixer_width = mode->hdisplay; |
379 | if (r_mixer) | |
380 | mixer_width /= 2; | |
381 | ||
0deed25b | 382 | spin_lock_irqsave(&mdp5_crtc->lm_lock, flags); |
adfc0e63 | 383 | mdp5_write(mdp5_kms, REG_MDP5_LM_OUT_SIZE(lm), |
ed78560d | 384 | MDP5_LM_OUT_SIZE_WIDTH(mixer_width) | |
06c0dd96 | 385 | MDP5_LM_OUT_SIZE_HEIGHT(mode->vdisplay)); |
ed78560d AT |
386 | |
387 | /* Assign mixer to LEFT side in source split mode */ | |
388 | val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm)); | |
389 | val &= ~MDP5_LM_BLEND_COLOR_OUT_SPLIT_LEFT_RIGHT; | |
390 | mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm), val); | |
391 | ||
392 | if (r_mixer) { | |
393 | u32 r_lm = r_mixer->lm; | |
394 | ||
395 | mdp5_write(mdp5_kms, REG_MDP5_LM_OUT_SIZE(r_lm), | |
396 | MDP5_LM_OUT_SIZE_WIDTH(mixer_width) | | |
b7621b2a | 397 | MDP5_LM_OUT_SIZE_HEIGHT(mode->vdisplay)); |
ed78560d AT |
398 | |
399 | /* Assign mixer to RIGHT side in source split mode */ | |
400 | val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm)); | |
401 | val |= MDP5_LM_BLEND_COLOR_OUT_SPLIT_LEFT_RIGHT; | |
402 | mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm), val); | |
403 | } | |
404 | ||
0deed25b | 405 | spin_unlock_irqrestore(&mdp5_crtc->lm_lock, flags); |
06c0dd96 RC |
406 | } |
407 | ||
64581714 LP |
408 | static void mdp5_crtc_atomic_disable(struct drm_crtc *crtc, |
409 | struct drm_crtc_state *old_state) | |
06c0dd96 RC |
410 | { |
411 | struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); | |
0ddc3a63 | 412 | struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); |
0b776d45 | 413 | struct mdp5_kms *mdp5_kms = get_kms(crtc); |
d68fe15b | 414 | struct device *dev = &mdp5_kms->pdev->dev; |
e765ea77 | 415 | unsigned long flags; |
0b776d45 | 416 | |
cee26588 | 417 | DBG("%s", crtc->name); |
0b776d45 RC |
418 | |
419 | if (WARN_ON(!mdp5_crtc->enabled)) | |
420 | return; | |
421 | ||
0033e1b5 RC |
422 | /* Disable/save vblank irq handling before power is disabled */ |
423 | drm_crtc_vblank_off(crtc); | |
424 | ||
0ddc3a63 | 425 | if (mdp5_cstate->cmd_mode) |
68cdbed9 HL |
426 | mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->pp_done); |
427 | ||
0b776d45 | 428 | mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->err); |
3c352b66 | 429 | pm_runtime_put_sync(dev); |
0b776d45 | 430 | |
e765ea77 SP |
431 | if (crtc->state->event && !crtc->state->active) { |
432 | WARN_ON(mdp5_crtc->event); | |
433 | spin_lock_irqsave(&mdp5_kms->dev->event_lock, flags); | |
434 | drm_crtc_send_vblank_event(crtc, crtc->state->event); | |
435 | crtc->state->event = NULL; | |
436 | spin_unlock_irqrestore(&mdp5_kms->dev->event_lock, flags); | |
437 | } | |
438 | ||
0b776d45 | 439 | mdp5_crtc->enabled = false; |
06c0dd96 RC |
440 | } |
441 | ||
0b20a0f8 LP |
442 | static void mdp5_crtc_atomic_enable(struct drm_crtc *crtc, |
443 | struct drm_crtc_state *old_state) | |
06c0dd96 | 444 | { |
ed851963 | 445 | struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); |
0ddc3a63 | 446 | struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); |
0b776d45 | 447 | struct mdp5_kms *mdp5_kms = get_kms(crtc); |
d68fe15b | 448 | struct device *dev = &mdp5_kms->pdev->dev; |
0b776d45 | 449 | |
cee26588 | 450 | DBG("%s", crtc->name); |
0b776d45 RC |
451 | |
452 | if (WARN_ON(mdp5_crtc->enabled)) | |
453 | return; | |
454 | ||
d68fe15b | 455 | pm_runtime_get_sync(dev); |
710e7a44 | 456 | |
aa649e87 AT |
457 | if (mdp5_crtc->lm_cursor_enabled) { |
458 | /* | |
459 | * Restore LM cursor state, as it might have been lost | |
460 | * with suspend: | |
461 | */ | |
462 | if (mdp5_crtc->cursor.iova) { | |
463 | unsigned long flags; | |
464 | ||
465 | spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags); | |
466 | mdp5_crtc_restore_cursor(crtc); | |
467 | spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags); | |
468 | ||
469 | mdp5_ctl_set_cursor(mdp5_cstate->ctl, | |
470 | &mdp5_cstate->pipeline, 0, true); | |
471 | } else { | |
472 | mdp5_ctl_set_cursor(mdp5_cstate->ctl, | |
473 | &mdp5_cstate->pipeline, 0, false); | |
474 | } | |
9d9ea7a9 RC |
475 | } |
476 | ||
0033e1b5 RC |
477 | /* Restore vblank irq handling after power is enabled */ |
478 | drm_crtc_vblank_on(crtc); | |
479 | ||
710e7a44 AT |
480 | mdp5_crtc_mode_set_nofb(crtc); |
481 | ||
0b776d45 RC |
482 | mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->err); |
483 | ||
0ddc3a63 | 484 | if (mdp5_cstate->cmd_mode) |
68cdbed9 HL |
485 | mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->pp_done); |
486 | ||
0b776d45 | 487 | mdp5_crtc->enabled = true; |
06c0dd96 RC |
488 | } |
489 | ||
894558ec | 490 | int mdp5_crtc_setup_pipeline(struct drm_crtc *crtc, |
8480adac AT |
491 | struct drm_crtc_state *new_crtc_state, |
492 | bool need_right_mixer) | |
894558ec AT |
493 | { |
494 | struct mdp5_crtc_state *mdp5_cstate = | |
495 | to_mdp5_crtc_state(new_crtc_state); | |
496 | struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; | |
bcb877b7 | 497 | struct mdp5_interface *intf; |
894558ec AT |
498 | bool new_mixer = false; |
499 | ||
500 | new_mixer = !pipeline->mixer; | |
501 | ||
8480adac AT |
502 | if ((need_right_mixer && !pipeline->r_mixer) || |
503 | (!need_right_mixer && pipeline->r_mixer)) | |
504 | new_mixer = true; | |
505 | ||
894558ec AT |
506 | if (new_mixer) { |
507 | struct mdp5_hw_mixer *old_mixer = pipeline->mixer; | |
8480adac AT |
508 | struct mdp5_hw_mixer *old_r_mixer = pipeline->r_mixer; |
509 | u32 caps; | |
510 | int ret; | |
511 | ||
512 | caps = MDP_LM_CAP_DISPLAY; | |
513 | if (need_right_mixer) | |
514 | caps |= MDP_LM_CAP_PAIR; | |
894558ec | 515 | |
8480adac AT |
516 | ret = mdp5_mixer_assign(new_crtc_state->state, crtc, caps, |
517 | &pipeline->mixer, need_right_mixer ? | |
518 | &pipeline->r_mixer : NULL); | |
519 | if (ret) | |
520 | return ret; | |
894558ec AT |
521 | |
522 | mdp5_mixer_release(new_crtc_state->state, old_mixer); | |
8480adac AT |
523 | if (old_r_mixer) { |
524 | mdp5_mixer_release(new_crtc_state->state, old_r_mixer); | |
525 | if (!need_right_mixer) | |
526 | pipeline->r_mixer = NULL; | |
527 | } | |
894558ec AT |
528 | } |
529 | ||
bcb877b7 AT |
530 | /* |
531 | * these should have been already set up in the encoder's atomic | |
532 | * check (called by drm_atomic_helper_check_modeset) | |
533 | */ | |
534 | intf = pipeline->intf; | |
535 | ||
536 | mdp5_cstate->err_irqmask = intf2err(intf->num); | |
537 | mdp5_cstate->vblank_irqmask = intf2vblank(pipeline->mixer, intf); | |
538 | ||
539 | if ((intf->type == INTF_DSI) && | |
540 | (intf->mode == MDP5_INTF_DSI_MODE_COMMAND)) { | |
541 | mdp5_cstate->pp_done_irqmask = lm2ppdone(pipeline->mixer); | |
542 | mdp5_cstate->cmd_mode = true; | |
543 | } else { | |
544 | mdp5_cstate->pp_done_irqmask = 0; | |
545 | mdp5_cstate->cmd_mode = false; | |
546 | } | |
547 | ||
894558ec AT |
548 | return 0; |
549 | } | |
550 | ||
ed851963 RC |
551 | struct plane_state { |
552 | struct drm_plane *plane; | |
553 | struct mdp5_plane_state *state; | |
554 | }; | |
555 | ||
556 | static int pstate_cmp(const void *a, const void *b) | |
06c0dd96 | 557 | { |
ed851963 RC |
558 | struct plane_state *pa = (struct plane_state *)a; |
559 | struct plane_state *pb = (struct plane_state *)b; | |
560 | return pa->state->zpos - pb->state->zpos; | |
06c0dd96 RC |
561 | } |
562 | ||
1455adbd RC |
563 | /* is there a helper for this? */ |
564 | static bool is_fullscreen(struct drm_crtc_state *cstate, | |
565 | struct drm_plane_state *pstate) | |
566 | { | |
567 | return (pstate->crtc_x <= 0) && (pstate->crtc_y <= 0) && | |
568 | ((pstate->crtc_x + pstate->crtc_w) >= cstate->mode.hdisplay) && | |
569 | ((pstate->crtc_y + pstate->crtc_h) >= cstate->mode.vdisplay); | |
570 | } | |
571 | ||
5c3ddb85 | 572 | static enum mdp_mixer_stage_id get_start_stage(struct drm_crtc *crtc, |
359ae862 AT |
573 | struct drm_crtc_state *new_crtc_state, |
574 | struct drm_plane_state *bpstate) | |
575 | { | |
576 | struct mdp5_crtc_state *mdp5_cstate = | |
577 | to_mdp5_crtc_state(new_crtc_state); | |
578 | ||
579 | /* | |
580 | * if we're in source split mode, it's mandatory to have | |
581 | * border out on the base stage | |
582 | */ | |
583 | if (mdp5_cstate->pipeline.r_mixer) | |
584 | return STAGE0; | |
585 | ||
586 | /* if the bottom-most layer is not fullscreen, we need to use | |
587 | * it for solid-color: | |
588 | */ | |
589 | if (!is_fullscreen(new_crtc_state, bpstate)) | |
590 | return STAGE0; | |
591 | ||
592 | return STAGE_BASE; | |
593 | } | |
594 | ||
ed851963 RC |
595 | static int mdp5_crtc_atomic_check(struct drm_crtc *crtc, |
596 | struct drm_crtc_state *state) | |
0deed25b | 597 | { |
ed851963 RC |
598 | struct mdp5_kms *mdp5_kms = get_kms(crtc); |
599 | struct drm_plane *plane; | |
600 | struct drm_device *dev = crtc->dev; | |
12987781 | 601 | struct plane_state pstates[STAGE_MAX + 1]; |
602 | const struct mdp5_cfg_hw *hw_cfg; | |
2f196b7c | 603 | const struct drm_plane_state *pstate; |
8480adac | 604 | const struct drm_display_mode *mode = &state->adjusted_mode; |
5798c8e0 | 605 | bool cursor_plane = false; |
8480adac | 606 | bool need_right_mixer = false; |
359ae862 | 607 | int cnt = 0, i; |
894558ec | 608 | int ret; |
359ae862 | 609 | enum mdp_mixer_stage_id start; |
0deed25b | 610 | |
cee26588 | 611 | DBG("%s: check", crtc->name); |
0deed25b | 612 | |
2f196b7c | 613 | drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) { |
a055cf3a RC |
614 | if (!pstate->visible) |
615 | continue; | |
616 | ||
ed851963 RC |
617 | pstates[cnt].plane = plane; |
618 | pstates[cnt].state = to_mdp5_plane_state(pstate); | |
619 | ||
8480adac AT |
620 | /* |
621 | * if any plane on this crtc uses 2 hwpipes, then we need | |
622 | * the crtc to have a right hwmixer. | |
623 | */ | |
624 | if (pstates[cnt].state->r_hwpipe) | |
625 | need_right_mixer = true; | |
ed851963 | 626 | cnt++; |
5798c8e0 AT |
627 | |
628 | if (plane->type == DRM_PLANE_TYPE_CURSOR) | |
629 | cursor_plane = true; | |
ed851963 RC |
630 | } |
631 | ||
359ae862 AT |
632 | /* bail out early if there aren't any planes */ |
633 | if (!cnt) | |
634 | return 0; | |
635 | ||
8480adac AT |
636 | hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); |
637 | ||
638 | /* | |
639 | * we need a right hwmixer if the mode's width is greater than a single | |
640 | * LM's max width | |
641 | */ | |
642 | if (mode->hdisplay > hw_cfg->lm.max_width) | |
643 | need_right_mixer = true; | |
644 | ||
645 | ret = mdp5_crtc_setup_pipeline(crtc, state, need_right_mixer); | |
894558ec | 646 | if (ret) { |
6a41da17 | 647 | DRM_DEV_ERROR(dev->dev, "couldn't assign mixers %d\n", ret); |
894558ec AT |
648 | return ret; |
649 | } | |
650 | ||
12987781 | 651 | /* assign a stage based on sorted zpos property */ |
ed851963 RC |
652 | sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL); |
653 | ||
5798c8e0 AT |
654 | /* trigger a warning if cursor isn't the highest zorder */ |
655 | WARN_ON(cursor_plane && | |
656 | (pstates[cnt - 1].plane->type != DRM_PLANE_TYPE_CURSOR)); | |
657 | ||
359ae862 AT |
658 | start = get_start_stage(crtc, state, &pstates[0].state->base); |
659 | ||
1455adbd RC |
660 | /* verify that there are not too many planes attached to crtc |
661 | * and that we don't have conflicting mixer stages: | |
662 | */ | |
359ae862 | 663 | if ((cnt + start - 1) >= hw_cfg->lm.nb_stages) { |
6a41da17 | 664 | DRM_DEV_ERROR(dev->dev, "too many planes! cnt=%d, start stage=%d\n", |
359ae862 | 665 | cnt, start); |
1455adbd RC |
666 | return -EINVAL; |
667 | } | |
668 | ||
ed851963 | 669 | for (i = 0; i < cnt; i++) { |
5798c8e0 AT |
670 | if (cursor_plane && (i == (cnt - 1))) |
671 | pstates[i].state->stage = hw_cfg->lm.nb_stages; | |
672 | else | |
359ae862 | 673 | pstates[i].state->stage = start + i; |
cee26588 | 674 | DBG("%s: assign pipe %s on stage=%d", crtc->name, |
4a0f012d | 675 | pstates[i].plane->name, |
ed851963 RC |
676 | pstates[i].state->stage); |
677 | } | |
678 | ||
679 | return 0; | |
0deed25b SV |
680 | } |
681 | ||
613d2b27 ML |
682 | static void mdp5_crtc_atomic_begin(struct drm_crtc *crtc, |
683 | struct drm_crtc_state *old_crtc_state) | |
ed851963 | 684 | { |
cee26588 | 685 | DBG("%s: begin", crtc->name); |
ed851963 | 686 | } |
0deed25b | 687 | |
613d2b27 ML |
688 | static void mdp5_crtc_atomic_flush(struct drm_crtc *crtc, |
689 | struct drm_crtc_state *old_crtc_state) | |
06c0dd96 RC |
690 | { |
691 | struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); | |
0ddc3a63 | 692 | struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); |
06c0dd96 | 693 | struct drm_device *dev = crtc->dev; |
06c0dd96 RC |
694 | unsigned long flags; |
695 | ||
cee26588 | 696 | DBG("%s: event: %p", crtc->name, crtc->state->event); |
06c0dd96 | 697 | |
ed851963 | 698 | WARN_ON(mdp5_crtc->event); |
06c0dd96 RC |
699 | |
700 | spin_lock_irqsave(&dev->event_lock, flags); | |
ed851963 | 701 | mdp5_crtc->event = crtc->state->event; |
78b32d49 | 702 | crtc->state->event = NULL; |
06c0dd96 RC |
703 | spin_unlock_irqrestore(&dev->event_lock, flags); |
704 | ||
ba0312a6 SV |
705 | /* |
706 | * If no CTL has been allocated in mdp5_crtc_atomic_check(), | |
707 | * it means we are trying to flush a CRTC whose state is disabled: | |
708 | * nothing else needs to be done. | |
709 | */ | |
0ddc3a63 AT |
710 | /* XXX: Can this happen now ? */ |
711 | if (unlikely(!mdp5_cstate->ctl)) | |
ba0312a6 SV |
712 | return; |
713 | ||
ed851963 | 714 | blend_setup(crtc); |
0a5c9aad | 715 | |
68cdbed9 HL |
716 | /* PP_DONE irq is only used by command mode for now. |
717 | * It is better to request pending before FLUSH and START trigger | |
718 | * to make sure no pp_done irq missed. | |
719 | * This is safe because no pp_done will happen before SW trigger | |
720 | * in command mode. | |
721 | */ | |
0ddc3a63 | 722 | if (mdp5_cstate->cmd_mode) |
68cdbed9 HL |
723 | request_pp_done_pending(crtc); |
724 | ||
0a5c9aad HL |
725 | mdp5_crtc->flushed_mask = crtc_flush_all(crtc); |
726 | ||
0ddc3a63 AT |
727 | /* XXX are we leaking out state here? */ |
728 | mdp5_crtc->vblank.irqmask = mdp5_cstate->vblank_irqmask; | |
729 | mdp5_crtc->err.irqmask = mdp5_cstate->err_irqmask; | |
730 | mdp5_crtc->pp_done.irqmask = mdp5_cstate->pp_done_irqmask; | |
731 | ||
ed851963 | 732 | request_pending(crtc, PENDING_FLIP); |
06c0dd96 RC |
733 | } |
734 | ||
58560890 RC |
735 | static void get_roi(struct drm_crtc *crtc, uint32_t *roi_w, uint32_t *roi_h) |
736 | { | |
737 | struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); | |
738 | uint32_t xres = crtc->mode.hdisplay; | |
739 | uint32_t yres = crtc->mode.vdisplay; | |
740 | ||
741 | /* | |
742 | * Cursor Region Of Interest (ROI) is a plane read from cursor | |
743 | * buffer to render. The ROI region is determined by the visibility of | |
744 | * the cursor point. In the default Cursor image the cursor point will | |
23f94551 | 745 | * be at the top left of the cursor image. |
58560890 | 746 | * |
23f94551 | 747 | * Without rotation: |
58560890 RC |
748 | * If the cursor point reaches the right (xres - x < cursor.width) or |
749 | * bottom (yres - y < cursor.height) boundary of the screen, then ROI | |
750 | * width and ROI height need to be evaluated to crop the cursor image | |
751 | * accordingly. | |
752 | * (xres-x) will be new cursor width when x > (xres - cursor.width) | |
753 | * (yres-y) will be new cursor height when y > (yres - cursor.height) | |
23f94551 CB |
754 | * |
755 | * With rotation: | |
756 | * We get negative x and/or y coordinates. | |
757 | * (cursor.width - abs(x)) will be new cursor width when x < 0 | |
758 | * (cursor.height - abs(y)) will be new cursor width when y < 0 | |
58560890 | 759 | */ |
23f94551 CB |
760 | if (mdp5_crtc->cursor.x >= 0) |
761 | *roi_w = min(mdp5_crtc->cursor.width, xres - | |
58560890 | 762 | mdp5_crtc->cursor.x); |
23f94551 CB |
763 | else |
764 | *roi_w = mdp5_crtc->cursor.width - abs(mdp5_crtc->cursor.x); | |
765 | if (mdp5_crtc->cursor.y >= 0) | |
766 | *roi_h = min(mdp5_crtc->cursor.height, yres - | |
58560890 | 767 | mdp5_crtc->cursor.y); |
23f94551 CB |
768 | else |
769 | *roi_h = mdp5_crtc->cursor.height - abs(mdp5_crtc->cursor.y); | |
58560890 RC |
770 | } |
771 | ||
9d9ea7a9 RC |
772 | static void mdp5_crtc_restore_cursor(struct drm_crtc *crtc) |
773 | { | |
24c478ea | 774 | const struct drm_format_info *info = drm_format_info(DRM_FORMAT_ARGB8888); |
9d9ea7a9 RC |
775 | struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); |
776 | struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); | |
777 | struct mdp5_kms *mdp5_kms = get_kms(crtc); | |
778 | const enum mdp5_cursor_alpha cur_alpha = CURSOR_ALPHA_PER_PIXEL; | |
779 | uint32_t blendcfg, stride; | |
23f94551 | 780 | uint32_t x, y, src_x, src_y, width, height; |
9d9ea7a9 RC |
781 | uint32_t roi_w, roi_h; |
782 | int lm; | |
783 | ||
784 | assert_spin_locked(&mdp5_crtc->cursor.lock); | |
785 | ||
786 | lm = mdp5_cstate->pipeline.mixer->lm; | |
787 | ||
788 | x = mdp5_crtc->cursor.x; | |
789 | y = mdp5_crtc->cursor.y; | |
790 | width = mdp5_crtc->cursor.width; | |
791 | height = mdp5_crtc->cursor.height; | |
792 | ||
b0f986b4 | 793 | stride = width * info->cpp[0]; |
9d9ea7a9 RC |
794 | |
795 | get_roi(crtc, &roi_w, &roi_h); | |
796 | ||
23f94551 CB |
797 | /* If cusror buffer overlaps due to rotation on the |
798 | * upper or left screen border the pixel offset inside | |
799 | * the cursor buffer of the ROI is the positive overlap | |
800 | * distance. | |
801 | */ | |
802 | if (mdp5_crtc->cursor.x < 0) { | |
803 | src_x = abs(mdp5_crtc->cursor.x); | |
804 | x = 0; | |
805 | } else { | |
806 | src_x = 0; | |
807 | } | |
808 | if (mdp5_crtc->cursor.y < 0) { | |
809 | src_y = abs(mdp5_crtc->cursor.y); | |
810 | y = 0; | |
811 | } else { | |
812 | src_y = 0; | |
813 | } | |
814 | DBG("%s: x=%d, y=%d roi_w=%d roi_h=%d src_x=%d src_y=%d", | |
815 | crtc->name, x, y, roi_w, roi_h, src_x, src_y); | |
816 | ||
9d9ea7a9 RC |
817 | mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_STRIDE(lm), stride); |
818 | mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_FORMAT(lm), | |
819 | MDP5_LM_CURSOR_FORMAT_FORMAT(CURSOR_FMT_ARGB8888)); | |
820 | mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_IMG_SIZE(lm), | |
821 | MDP5_LM_CURSOR_IMG_SIZE_SRC_H(height) | | |
822 | MDP5_LM_CURSOR_IMG_SIZE_SRC_W(width)); | |
823 | mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_SIZE(lm), | |
824 | MDP5_LM_CURSOR_SIZE_ROI_H(roi_h) | | |
825 | MDP5_LM_CURSOR_SIZE_ROI_W(roi_w)); | |
826 | mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_START_XY(lm), | |
827 | MDP5_LM_CURSOR_START_XY_Y_START(y) | | |
828 | MDP5_LM_CURSOR_START_XY_X_START(x)); | |
23f94551 CB |
829 | mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_XY(lm), |
830 | MDP5_LM_CURSOR_XY_SRC_Y(src_y) | | |
831 | MDP5_LM_CURSOR_XY_SRC_X(src_x)); | |
9d9ea7a9 RC |
832 | mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BASE_ADDR(lm), |
833 | mdp5_crtc->cursor.iova); | |
834 | ||
835 | blendcfg = MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_EN; | |
836 | blendcfg |= MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(cur_alpha); | |
837 | mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BLEND_CONFIG(lm), blendcfg); | |
838 | } | |
839 | ||
e172d10a BG |
840 | static int mdp5_crtc_cursor_set(struct drm_crtc *crtc, |
841 | struct drm_file *file, uint32_t handle, | |
842 | uint32_t width, uint32_t height) | |
843 | { | |
844 | struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); | |
0ddc3a63 | 845 | struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); |
f316b25a | 846 | struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; |
e172d10a BG |
847 | struct drm_device *dev = crtc->dev; |
848 | struct mdp5_kms *mdp5_kms = get_kms(crtc); | |
d68fe15b | 849 | struct platform_device *pdev = mdp5_kms->pdev; |
f59f62d5 | 850 | struct msm_kms *kms = &mdp5_kms->base.base; |
389b09a1 | 851 | struct drm_gem_object *cursor_bo, *old_bo = NULL; |
0ddc3a63 | 852 | struct mdp5_ctl *ctl; |
9d9ea7a9 | 853 | int ret; |
e172d10a | 854 | uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0); |
389b09a1 | 855 | bool cursor_enable = true; |
e172d10a BG |
856 | unsigned long flags; |
857 | ||
aa649e87 AT |
858 | if (!mdp5_crtc->lm_cursor_enabled) { |
859 | dev_warn(dev->dev, | |
860 | "cursor_set is deprecated with cursor planes\n"); | |
861 | return -EINVAL; | |
862 | } | |
863 | ||
e172d10a | 864 | if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) { |
6a41da17 | 865 | DRM_DEV_ERROR(dev->dev, "bad cursor size: %dx%d\n", width, height); |
e172d10a BG |
866 | return -EINVAL; |
867 | } | |
868 | ||
0ddc3a63 AT |
869 | ctl = mdp5_cstate->ctl; |
870 | if (!ctl) | |
e172d10a BG |
871 | return -EINVAL; |
872 | ||
b7621b2a AT |
873 | /* don't support LM cursors when we we have source split enabled */ |
874 | if (mdp5_cstate->pipeline.r_mixer) | |
875 | return -EINVAL; | |
876 | ||
e172d10a BG |
877 | if (!handle) { |
878 | DBG("Cursor off"); | |
389b09a1 | 879 | cursor_enable = false; |
9d9ea7a9 | 880 | mdp5_crtc->cursor.iova = 0; |
d68fe15b | 881 | pm_runtime_get_sync(&pdev->dev); |
389b09a1 | 882 | goto set_cursor; |
e172d10a BG |
883 | } |
884 | ||
a8ad0bd8 | 885 | cursor_bo = drm_gem_object_lookup(file, handle); |
e172d10a BG |
886 | if (!cursor_bo) |
887 | return -ENOENT; | |
888 | ||
9fe041f6 | 889 | ret = msm_gem_get_and_pin_iova(cursor_bo, kms->aspace, |
9d9ea7a9 | 890 | &mdp5_crtc->cursor.iova); |
e172d10a BG |
891 | if (ret) |
892 | return -EINVAL; | |
893 | ||
d68fe15b AT |
894 | pm_runtime_get_sync(&pdev->dev); |
895 | ||
e172d10a BG |
896 | spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags); |
897 | old_bo = mdp5_crtc->cursor.scanout_bo; | |
898 | ||
58560890 RC |
899 | mdp5_crtc->cursor.scanout_bo = cursor_bo; |
900 | mdp5_crtc->cursor.width = width; | |
901 | mdp5_crtc->cursor.height = height; | |
902 | ||
9d9ea7a9 | 903 | mdp5_crtc_restore_cursor(crtc); |
e172d10a | 904 | |
e172d10a BG |
905 | spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags); |
906 | ||
389b09a1 | 907 | set_cursor: |
f316b25a | 908 | ret = mdp5_ctl_set_cursor(ctl, pipeline, 0, cursor_enable); |
389b09a1 | 909 | if (ret) { |
6a41da17 | 910 | DRM_DEV_ERROR(dev->dev, "failed to %sable cursor: %d\n", |
389b09a1 | 911 | cursor_enable ? "en" : "dis", ret); |
e172d10a | 912 | goto end; |
389b09a1 | 913 | } |
e172d10a | 914 | |
e172d10a BG |
915 | crtc_flush(crtc, flush_mask); |
916 | ||
917 | end: | |
3c352b66 | 918 | pm_runtime_put_sync(&pdev->dev); |
e172d10a BG |
919 | if (old_bo) { |
920 | drm_flip_work_queue(&mdp5_crtc->unref_cursor_work, old_bo); | |
921 | /* enable vblank to complete cursor work: */ | |
922 | request_pending(crtc, PENDING_CURSOR); | |
923 | } | |
924 | return ret; | |
925 | } | |
926 | ||
927 | static int mdp5_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
928 | { | |
929 | struct mdp5_kms *mdp5_kms = get_kms(crtc); | |
930 | struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); | |
0ddc3a63 | 931 | struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); |
e172d10a | 932 | uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0); |
aa649e87 | 933 | struct drm_device *dev = crtc->dev; |
e172d10a BG |
934 | uint32_t roi_w; |
935 | uint32_t roi_h; | |
936 | unsigned long flags; | |
937 | ||
aa649e87 AT |
938 | if (!mdp5_crtc->lm_cursor_enabled) { |
939 | dev_warn(dev->dev, | |
940 | "cursor_move is deprecated with cursor planes\n"); | |
941 | return -EINVAL; | |
942 | } | |
943 | ||
b7621b2a AT |
944 | /* don't support LM cursors when we we have source split enabled */ |
945 | if (mdp5_cstate->pipeline.r_mixer) | |
946 | return -EINVAL; | |
947 | ||
ba0312a6 SV |
948 | /* In case the CRTC is disabled, just drop the cursor update */ |
949 | if (unlikely(!crtc->state->enable)) | |
950 | return 0; | |
951 | ||
23f94551 CB |
952 | /* accept negative x/y coordinates up to maximum cursor overlap */ |
953 | mdp5_crtc->cursor.x = x = max(x, -(int)mdp5_crtc->cursor.width); | |
954 | mdp5_crtc->cursor.y = y = max(y, -(int)mdp5_crtc->cursor.height); | |
e172d10a | 955 | |
58560890 | 956 | get_roi(crtc, &roi_w, &roi_h); |
e172d10a | 957 | |
d68fe15b | 958 | pm_runtime_get_sync(&mdp5_kms->pdev->dev); |
af1f5f12 | 959 | |
e172d10a | 960 | spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags); |
9d9ea7a9 | 961 | mdp5_crtc_restore_cursor(crtc); |
e172d10a BG |
962 | spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags); |
963 | ||
964 | crtc_flush(crtc, flush_mask); | |
965 | ||
3c352b66 | 966 | pm_runtime_put_sync(&mdp5_kms->pdev->dev); |
af1f5f12 | 967 | |
e172d10a BG |
968 | return 0; |
969 | } | |
970 | ||
c1e2a130 AT |
971 | static void |
972 | mdp5_crtc_atomic_print_state(struct drm_printer *p, | |
973 | const struct drm_crtc_state *state) | |
974 | { | |
975 | struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(state); | |
976 | struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; | |
b7621b2a | 977 | struct mdp5_kms *mdp5_kms = get_kms(state->crtc); |
c1e2a130 AT |
978 | |
979 | if (WARN_ON(!pipeline)) | |
980 | return; | |
981 | ||
1af81790 RC |
982 | if (mdp5_cstate->ctl) |
983 | drm_printf(p, "\tctl=%d\n", mdp5_ctl_get_ctl_id(mdp5_cstate->ctl)); | |
984 | ||
c1e2a130 AT |
985 | drm_printf(p, "\thwmixer=%s\n", pipeline->mixer ? |
986 | pipeline->mixer->name : "(null)"); | |
b7621b2a AT |
987 | |
988 | if (mdp5_kms->caps & MDP_CAP_SRC_SPLIT) | |
989 | drm_printf(p, "\tright hwmixer=%s\n", pipeline->r_mixer ? | |
990 | pipeline->r_mixer->name : "(null)"); | |
1af81790 RC |
991 | |
992 | drm_printf(p, "\tcmd_mode=%d\n", mdp5_cstate->cmd_mode); | |
c1e2a130 AT |
993 | } |
994 | ||
c1e2a130 AT |
995 | static struct drm_crtc_state * |
996 | mdp5_crtc_duplicate_state(struct drm_crtc *crtc) | |
997 | { | |
998 | struct mdp5_crtc_state *mdp5_cstate; | |
999 | ||
1000 | if (WARN_ON(!crtc->state)) | |
1001 | return NULL; | |
1002 | ||
1003 | mdp5_cstate = kmemdup(to_mdp5_crtc_state(crtc->state), | |
1004 | sizeof(*mdp5_cstate), GFP_KERNEL); | |
1005 | if (!mdp5_cstate) | |
1006 | return NULL; | |
1007 | ||
1008 | __drm_atomic_helper_crtc_duplicate_state(crtc, &mdp5_cstate->base); | |
1009 | ||
1010 | return &mdp5_cstate->base; | |
1011 | } | |
1012 | ||
1013 | static void mdp5_crtc_destroy_state(struct drm_crtc *crtc, struct drm_crtc_state *state) | |
1014 | { | |
1015 | struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(state); | |
1016 | ||
1017 | __drm_atomic_helper_crtc_destroy_state(state); | |
1018 | ||
1019 | kfree(mdp5_cstate); | |
1020 | } | |
1021 | ||
1cff7440 ML |
1022 | static void mdp5_crtc_reset(struct drm_crtc *crtc) |
1023 | { | |
1024 | struct mdp5_crtc_state *mdp5_cstate = | |
1025 | kzalloc(sizeof(*mdp5_cstate), GFP_KERNEL); | |
1026 | ||
1027 | if (crtc->state) | |
1028 | mdp5_crtc_destroy_state(crtc, crtc->state); | |
1029 | ||
1030 | __drm_atomic_helper_crtc_reset(crtc, &mdp5_cstate->base); | |
1031 | } | |
1032 | ||
06c0dd96 | 1033 | static const struct drm_crtc_funcs mdp5_crtc_funcs = { |
ed851963 | 1034 | .set_config = drm_atomic_helper_set_config, |
06c0dd96 | 1035 | .destroy = mdp5_crtc_destroy, |
ed851963 | 1036 | .page_flip = drm_atomic_helper_page_flip, |
c1e2a130 AT |
1037 | .reset = mdp5_crtc_reset, |
1038 | .atomic_duplicate_state = mdp5_crtc_duplicate_state, | |
1039 | .atomic_destroy_state = mdp5_crtc_destroy_state, | |
e172d10a BG |
1040 | .cursor_set = mdp5_crtc_cursor_set, |
1041 | .cursor_move = mdp5_crtc_cursor_move, | |
c1e2a130 | 1042 | .atomic_print_state = mdp5_crtc_atomic_print_state, |
06c0dd96 RC |
1043 | }; |
1044 | ||
1045 | static const struct drm_crtc_helper_funcs mdp5_crtc_helper_funcs = { | |
ed851963 | 1046 | .mode_set_nofb = mdp5_crtc_mode_set_nofb, |
ed851963 RC |
1047 | .atomic_check = mdp5_crtc_atomic_check, |
1048 | .atomic_begin = mdp5_crtc_atomic_begin, | |
1049 | .atomic_flush = mdp5_crtc_atomic_flush, | |
0b20a0f8 | 1050 | .atomic_enable = mdp5_crtc_atomic_enable, |
64581714 | 1051 | .atomic_disable = mdp5_crtc_atomic_disable, |
06c0dd96 RC |
1052 | }; |
1053 | ||
1054 | static void mdp5_crtc_vblank_irq(struct mdp_irq *irq, uint32_t irqstatus) | |
1055 | { | |
1056 | struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc, vblank); | |
1057 | struct drm_crtc *crtc = &mdp5_crtc->base; | |
e172d10a | 1058 | struct msm_drm_private *priv = crtc->dev->dev_private; |
06c0dd96 RC |
1059 | unsigned pending; |
1060 | ||
1061 | mdp_irq_unregister(&get_kms(crtc)->base, &mdp5_crtc->vblank); | |
1062 | ||
1063 | pending = atomic_xchg(&mdp5_crtc->pending, 0); | |
1064 | ||
1065 | if (pending & PENDING_FLIP) { | |
1066 | complete_flip(crtc, NULL); | |
06c0dd96 | 1067 | } |
e172d10a BG |
1068 | |
1069 | if (pending & PENDING_CURSOR) | |
1070 | drm_flip_work_commit(&mdp5_crtc->unref_cursor_work, priv->wq); | |
06c0dd96 RC |
1071 | } |
1072 | ||
1073 | static void mdp5_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus) | |
1074 | { | |
1075 | struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc, err); | |
0deed25b | 1076 | |
cee26588 | 1077 | DBG("%s: error: %08x", mdp5_crtc->base.name, irqstatus); |
06c0dd96 RC |
1078 | } |
1079 | ||
68cdbed9 HL |
1080 | static void mdp5_crtc_pp_done_irq(struct mdp_irq *irq, uint32_t irqstatus) |
1081 | { | |
1082 | struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc, | |
1083 | pp_done); | |
1084 | ||
1085 | complete(&mdp5_crtc->pp_completion); | |
1086 | } | |
1087 | ||
1088 | static void mdp5_crtc_wait_for_pp_done(struct drm_crtc *crtc) | |
1089 | { | |
1090 | struct drm_device *dev = crtc->dev; | |
1091 | struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); | |
0ddc3a63 | 1092 | struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); |
68cdbed9 HL |
1093 | int ret; |
1094 | ||
1095 | ret = wait_for_completion_timeout(&mdp5_crtc->pp_completion, | |
1096 | msecs_to_jiffies(50)); | |
1097 | if (ret == 0) | |
adfc0e63 | 1098 | dev_warn(dev->dev, "pp done time out, lm=%d\n", |
0ddc3a63 | 1099 | mdp5_cstate->pipeline.mixer->lm); |
68cdbed9 HL |
1100 | } |
1101 | ||
0a5c9aad HL |
1102 | static void mdp5_crtc_wait_for_flush_done(struct drm_crtc *crtc) |
1103 | { | |
1104 | struct drm_device *dev = crtc->dev; | |
1105 | struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); | |
0ddc3a63 AT |
1106 | struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); |
1107 | struct mdp5_ctl *ctl = mdp5_cstate->ctl; | |
0a5c9aad HL |
1108 | int ret; |
1109 | ||
1110 | /* Should not call this function if crtc is disabled. */ | |
0ddc3a63 | 1111 | if (!ctl) |
0a5c9aad HL |
1112 | return; |
1113 | ||
1114 | ret = drm_crtc_vblank_get(crtc); | |
1115 | if (ret) | |
1116 | return; | |
1117 | ||
1118 | ret = wait_event_timeout(dev->vblank[drm_crtc_index(crtc)].queue, | |
0ddc3a63 | 1119 | ((mdp5_ctl_get_commit_status(ctl) & |
0a5c9aad HL |
1120 | mdp5_crtc->flushed_mask) == 0), |
1121 | msecs_to_jiffies(50)); | |
1122 | if (ret <= 0) | |
1123 | dev_warn(dev->dev, "vblank time out, crtc=%d\n", mdp5_crtc->id); | |
1124 | ||
1125 | mdp5_crtc->flushed_mask = 0; | |
1126 | ||
1127 | drm_crtc_vblank_put(crtc); | |
1128 | } | |
1129 | ||
06c0dd96 RC |
1130 | uint32_t mdp5_crtc_vblank(struct drm_crtc *crtc) |
1131 | { | |
1132 | struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); | |
1133 | return mdp5_crtc->vblank.irqmask; | |
1134 | } | |
1135 | ||
f316b25a | 1136 | void mdp5_crtc_set_pipeline(struct drm_crtc *crtc) |
06c0dd96 | 1137 | { |
0ddc3a63 | 1138 | struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); |
06c0dd96 | 1139 | struct mdp5_kms *mdp5_kms = get_kms(crtc); |
0a5c9aad | 1140 | |
0ddc3a63 | 1141 | /* should this be done elsewhere ? */ |
8bc1fe92 | 1142 | mdp_irq_update(&mdp5_kms->base); |
06c0dd96 | 1143 | |
f316b25a | 1144 | mdp5_ctl_set_pipeline(mdp5_cstate->ctl, &mdp5_cstate->pipeline); |
0deed25b | 1145 | } |
06c0dd96 | 1146 | |
10967a06 AT |
1147 | struct mdp5_ctl *mdp5_crtc_get_ctl(struct drm_crtc *crtc) |
1148 | { | |
0ddc3a63 | 1149 | struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); |
10967a06 | 1150 | |
0ddc3a63 | 1151 | return mdp5_cstate->ctl; |
10967a06 AT |
1152 | } |
1153 | ||
adfc0e63 | 1154 | struct mdp5_hw_mixer *mdp5_crtc_get_mixer(struct drm_crtc *crtc) |
0deed25b | 1155 | { |
0ddc3a63 AT |
1156 | struct mdp5_crtc_state *mdp5_cstate; |
1157 | ||
1158 | if (WARN_ON(!crtc)) | |
1159 | return ERR_PTR(-EINVAL); | |
1160 | ||
1161 | mdp5_cstate = to_mdp5_crtc_state(crtc->state); | |
1162 | ||
1163 | return WARN_ON(!mdp5_cstate->pipeline.mixer) ? | |
1164 | ERR_PTR(-EINVAL) : mdp5_cstate->pipeline.mixer; | |
389b09a1 | 1165 | } |
0deed25b | 1166 | |
f316b25a AT |
1167 | struct mdp5_pipeline *mdp5_crtc_get_pipeline(struct drm_crtc *crtc) |
1168 | { | |
1169 | struct mdp5_crtc_state *mdp5_cstate; | |
1170 | ||
1171 | if (WARN_ON(!crtc)) | |
1172 | return ERR_PTR(-EINVAL); | |
1173 | ||
1174 | mdp5_cstate = to_mdp5_crtc_state(crtc->state); | |
1175 | ||
1176 | return &mdp5_cstate->pipeline; | |
1177 | } | |
1178 | ||
0a5c9aad HL |
1179 | void mdp5_crtc_wait_for_commit_done(struct drm_crtc *crtc) |
1180 | { | |
0ddc3a63 | 1181 | struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); |
68cdbed9 | 1182 | |
0ddc3a63 | 1183 | if (mdp5_cstate->cmd_mode) |
68cdbed9 HL |
1184 | mdp5_crtc_wait_for_pp_done(crtc); |
1185 | else | |
1186 | mdp5_crtc_wait_for_flush_done(crtc); | |
0a5c9aad HL |
1187 | } |
1188 | ||
06c0dd96 RC |
1189 | /* initialize crtc */ |
1190 | struct drm_crtc *mdp5_crtc_init(struct drm_device *dev, | |
5798c8e0 AT |
1191 | struct drm_plane *plane, |
1192 | struct drm_plane *cursor_plane, int id) | |
06c0dd96 RC |
1193 | { |
1194 | struct drm_crtc *crtc = NULL; | |
1195 | struct mdp5_crtc *mdp5_crtc; | |
06c0dd96 RC |
1196 | |
1197 | mdp5_crtc = kzalloc(sizeof(*mdp5_crtc), GFP_KERNEL); | |
d7f8db53 BB |
1198 | if (!mdp5_crtc) |
1199 | return ERR_PTR(-ENOMEM); | |
06c0dd96 RC |
1200 | |
1201 | crtc = &mdp5_crtc->base; | |
1202 | ||
06c0dd96 | 1203 | mdp5_crtc->id = id; |
0deed25b SV |
1204 | |
1205 | spin_lock_init(&mdp5_crtc->lm_lock); | |
e172d10a | 1206 | spin_lock_init(&mdp5_crtc->cursor.lock); |
68cdbed9 | 1207 | init_completion(&mdp5_crtc->pp_completion); |
06c0dd96 RC |
1208 | |
1209 | mdp5_crtc->vblank.irq = mdp5_crtc_vblank_irq; | |
1210 | mdp5_crtc->err.irq = mdp5_crtc_err_irq; | |
0ddc3a63 | 1211 | mdp5_crtc->pp_done.irq = mdp5_crtc_pp_done_irq; |
06c0dd96 | 1212 | |
aa649e87 AT |
1213 | mdp5_crtc->lm_cursor_enabled = cursor_plane ? false : true; |
1214 | ||
1215 | drm_crtc_init_with_planes(dev, crtc, plane, cursor_plane, | |
1216 | &mdp5_crtc_funcs, NULL); | |
e172d10a BG |
1217 | |
1218 | drm_flip_work_init(&mdp5_crtc->unref_cursor_work, | |
1219 | "unref cursor", unref_cursor_worker); | |
1220 | ||
06c0dd96 RC |
1221 | drm_crtc_helper_add(crtc, &mdp5_crtc_helper_funcs); |
1222 | ||
06c0dd96 | 1223 | return crtc; |
06c0dd96 | 1224 | } |