Commit | Line | Data |
---|---|---|
97fb5e8d | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
25fdd593 | 2 | /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. |
25fdd593 JS |
3 | */ |
4 | ||
5 | #ifndef _DPU_HW_MDSS_H | |
6 | #define _DPU_HW_MDSS_H | |
7 | ||
8 | #include <linux/kernel.h> | |
9 | #include <linux/err.h> | |
10 | ||
11 | #include "msm_drv.h" | |
12 | ||
13 | #define DPU_DBG_NAME "dpu" | |
14 | ||
15 | #define DPU_NONE 0 | |
16 | ||
17 | #ifndef DPU_CSC_MATRIX_COEFF_SIZE | |
18 | #define DPU_CSC_MATRIX_COEFF_SIZE 9 | |
19 | #endif | |
20 | ||
21 | #ifndef DPU_CSC_CLAMP_SIZE | |
22 | #define DPU_CSC_CLAMP_SIZE 6 | |
23 | #endif | |
24 | ||
25 | #ifndef DPU_CSC_BIAS_SIZE | |
26 | #define DPU_CSC_BIAS_SIZE 3 | |
27 | #endif | |
28 | ||
29 | #ifndef DPU_MAX_PLANES | |
30 | #define DPU_MAX_PLANES 4 | |
31 | #endif | |
32 | ||
33 | #define PIPES_PER_STAGE 2 | |
34 | #ifndef DPU_MAX_DE_CURVES | |
35 | #define DPU_MAX_DE_CURVES 3 | |
36 | #endif | |
37 | ||
38 | enum dpu_format_flags { | |
39 | DPU_FORMAT_FLAG_YUV_BIT, | |
40 | DPU_FORMAT_FLAG_DX_BIT, | |
41 | DPU_FORMAT_FLAG_COMPRESSED_BIT, | |
42 | DPU_FORMAT_FLAG_BIT_MAX, | |
43 | }; | |
44 | ||
45 | #define DPU_FORMAT_FLAG_YUV BIT(DPU_FORMAT_FLAG_YUV_BIT) | |
46 | #define DPU_FORMAT_FLAG_DX BIT(DPU_FORMAT_FLAG_DX_BIT) | |
47 | #define DPU_FORMAT_FLAG_COMPRESSED BIT(DPU_FORMAT_FLAG_COMPRESSED_BIT) | |
48 | #define DPU_FORMAT_IS_YUV(X) \ | |
49 | (test_bit(DPU_FORMAT_FLAG_YUV_BIT, (X)->flag)) | |
50 | #define DPU_FORMAT_IS_DX(X) \ | |
51 | (test_bit(DPU_FORMAT_FLAG_DX_BIT, (X)->flag)) | |
52 | #define DPU_FORMAT_IS_LINEAR(X) ((X)->fetch_mode == DPU_FETCH_LINEAR) | |
53 | #define DPU_FORMAT_IS_TILE(X) \ | |
54 | (((X)->fetch_mode == DPU_FETCH_UBWC) && \ | |
55 | !test_bit(DPU_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag)) | |
56 | #define DPU_FORMAT_IS_UBWC(X) \ | |
57 | (((X)->fetch_mode == DPU_FETCH_UBWC) && \ | |
58 | test_bit(DPU_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag)) | |
59 | ||
60 | #define DPU_BLEND_FG_ALPHA_FG_CONST (0 << 0) | |
61 | #define DPU_BLEND_FG_ALPHA_BG_CONST (1 << 0) | |
62 | #define DPU_BLEND_FG_ALPHA_FG_PIXEL (2 << 0) | |
63 | #define DPU_BLEND_FG_ALPHA_BG_PIXEL (3 << 0) | |
64 | #define DPU_BLEND_FG_INV_ALPHA (1 << 2) | |
65 | #define DPU_BLEND_FG_MOD_ALPHA (1 << 3) | |
66 | #define DPU_BLEND_FG_INV_MOD_ALPHA (1 << 4) | |
67 | #define DPU_BLEND_FG_TRANSP_EN (1 << 5) | |
68 | #define DPU_BLEND_BG_ALPHA_FG_CONST (0 << 8) | |
69 | #define DPU_BLEND_BG_ALPHA_BG_CONST (1 << 8) | |
70 | #define DPU_BLEND_BG_ALPHA_FG_PIXEL (2 << 8) | |
71 | #define DPU_BLEND_BG_ALPHA_BG_PIXEL (3 << 8) | |
72 | #define DPU_BLEND_BG_INV_ALPHA (1 << 10) | |
73 | #define DPU_BLEND_BG_MOD_ALPHA (1 << 11) | |
74 | #define DPU_BLEND_BG_INV_MOD_ALPHA (1 << 12) | |
75 | #define DPU_BLEND_BG_TRANSP_EN (1 << 13) | |
76 | ||
77 | #define DPU_VSYNC0_SOURCE_GPIO 0 | |
78 | #define DPU_VSYNC1_SOURCE_GPIO 1 | |
79 | #define DPU_VSYNC2_SOURCE_GPIO 2 | |
80 | #define DPU_VSYNC_SOURCE_INTF_0 3 | |
81 | #define DPU_VSYNC_SOURCE_INTF_1 4 | |
82 | #define DPU_VSYNC_SOURCE_INTF_2 5 | |
83 | #define DPU_VSYNC_SOURCE_INTF_3 6 | |
84 | #define DPU_VSYNC_SOURCE_WD_TIMER_4 11 | |
85 | #define DPU_VSYNC_SOURCE_WD_TIMER_3 12 | |
86 | #define DPU_VSYNC_SOURCE_WD_TIMER_2 13 | |
87 | #define DPU_VSYNC_SOURCE_WD_TIMER_1 14 | |
88 | #define DPU_VSYNC_SOURCE_WD_TIMER_0 15 | |
89 | ||
90 | enum dpu_hw_blk_type { | |
91 | DPU_HW_BLK_TOP = 0, | |
92 | DPU_HW_BLK_SSPP, | |
93 | DPU_HW_BLK_LM, | |
94 | DPU_HW_BLK_CTL, | |
25fdd593 JS |
95 | DPU_HW_BLK_PINGPONG, |
96 | DPU_HW_BLK_INTF, | |
97 | DPU_HW_BLK_WB, | |
98 | DPU_HW_BLK_MAX, | |
99 | }; | |
100 | ||
101 | enum dpu_mdp { | |
102 | MDP_TOP = 0x1, | |
103 | MDP_MAX, | |
104 | }; | |
105 | ||
106 | enum dpu_sspp { | |
107 | SSPP_NONE, | |
108 | SSPP_VIG0, | |
109 | SSPP_VIG1, | |
110 | SSPP_VIG2, | |
111 | SSPP_VIG3, | |
112 | SSPP_RGB0, | |
113 | SSPP_RGB1, | |
114 | SSPP_RGB2, | |
115 | SSPP_RGB3, | |
116 | SSPP_DMA0, | |
117 | SSPP_DMA1, | |
118 | SSPP_DMA2, | |
119 | SSPP_DMA3, | |
120 | SSPP_CURSOR0, | |
121 | SSPP_CURSOR1, | |
122 | SSPP_MAX | |
123 | }; | |
124 | ||
125 | enum dpu_sspp_type { | |
126 | SSPP_TYPE_VIG, | |
127 | SSPP_TYPE_RGB, | |
128 | SSPP_TYPE_DMA, | |
129 | SSPP_TYPE_CURSOR, | |
130 | SSPP_TYPE_MAX | |
131 | }; | |
132 | ||
133 | enum dpu_lm { | |
134 | LM_0 = 1, | |
135 | LM_1, | |
136 | LM_2, | |
137 | LM_3, | |
138 | LM_4, | |
139 | LM_5, | |
140 | LM_6, | |
141 | LM_MAX | |
142 | }; | |
143 | ||
144 | enum dpu_stage { | |
145 | DPU_STAGE_BASE = 0, | |
146 | DPU_STAGE_0, | |
147 | DPU_STAGE_1, | |
148 | DPU_STAGE_2, | |
149 | DPU_STAGE_3, | |
150 | DPU_STAGE_4, | |
151 | DPU_STAGE_5, | |
152 | DPU_STAGE_6, | |
153 | DPU_STAGE_7, | |
154 | DPU_STAGE_8, | |
155 | DPU_STAGE_9, | |
156 | DPU_STAGE_10, | |
157 | DPU_STAGE_MAX | |
158 | }; | |
159 | enum dpu_dspp { | |
160 | DSPP_0 = 1, | |
161 | DSPP_1, | |
162 | DSPP_2, | |
163 | DSPP_3, | |
164 | DSPP_MAX | |
165 | }; | |
166 | ||
25fdd593 JS |
167 | enum dpu_ctl { |
168 | CTL_0 = 1, | |
169 | CTL_1, | |
170 | CTL_2, | |
171 | CTL_3, | |
172 | CTL_4, | |
173 | CTL_MAX | |
174 | }; | |
175 | ||
25fdd593 JS |
176 | enum dpu_pingpong { |
177 | PINGPONG_0 = 1, | |
178 | PINGPONG_1, | |
179 | PINGPONG_2, | |
180 | PINGPONG_3, | |
181 | PINGPONG_4, | |
182 | PINGPONG_S0, | |
183 | PINGPONG_MAX | |
184 | }; | |
185 | ||
186 | enum dpu_intf { | |
187 | INTF_0 = 1, | |
188 | INTF_1, | |
189 | INTF_2, | |
190 | INTF_3, | |
191 | INTF_4, | |
192 | INTF_5, | |
193 | INTF_6, | |
194 | INTF_MAX | |
195 | }; | |
196 | ||
197 | enum dpu_intf_type { | |
198 | INTF_NONE = 0x0, | |
199 | INTF_DSI = 0x1, | |
200 | INTF_HDMI = 0x3, | |
201 | INTF_LCDC = 0x5, | |
202 | INTF_EDP = 0x9, | |
203 | INTF_DP = 0xa, | |
204 | INTF_TYPE_MAX, | |
205 | ||
206 | /* virtual interfaces */ | |
207 | INTF_WB = 0x100, | |
208 | }; | |
209 | ||
210 | enum dpu_intf_mode { | |
211 | INTF_MODE_NONE = 0, | |
212 | INTF_MODE_CMD, | |
213 | INTF_MODE_VIDEO, | |
214 | INTF_MODE_WB_BLOCK, | |
215 | INTF_MODE_WB_LINE, | |
216 | INTF_MODE_MAX | |
217 | }; | |
218 | ||
219 | enum dpu_wb { | |
220 | WB_0 = 1, | |
221 | WB_1, | |
222 | WB_2, | |
223 | WB_3, | |
224 | WB_MAX | |
225 | }; | |
226 | ||
25fdd593 JS |
227 | enum dpu_cwb { |
228 | CWB_0 = 0x1, | |
229 | CWB_1, | |
230 | CWB_2, | |
231 | CWB_3, | |
232 | CWB_MAX | |
233 | }; | |
234 | ||
235 | enum dpu_wd_timer { | |
236 | WD_TIMER_0 = 0x1, | |
237 | WD_TIMER_1, | |
238 | WD_TIMER_2, | |
239 | WD_TIMER_3, | |
240 | WD_TIMER_4, | |
241 | WD_TIMER_5, | |
242 | WD_TIMER_MAX | |
243 | }; | |
244 | ||
245 | enum dpu_vbif { | |
246 | VBIF_0, | |
247 | VBIF_1, | |
248 | VBIF_MAX, | |
249 | VBIF_RT = VBIF_0, | |
250 | VBIF_NRT = VBIF_1 | |
251 | }; | |
252 | ||
25fdd593 JS |
253 | /** |
254 | * DPU HW,Component order color map | |
255 | */ | |
256 | enum { | |
257 | C0_G_Y = 0, | |
258 | C1_B_Cb = 1, | |
259 | C2_R_Cr = 2, | |
260 | C3_ALPHA = 3 | |
261 | }; | |
262 | ||
263 | /** | |
264 | * enum dpu_plane_type - defines how the color component pixel packing | |
265 | * @DPU_PLANE_INTERLEAVED : Color components in single plane | |
266 | * @DPU_PLANE_PLANAR : Color component in separate planes | |
267 | * @DPU_PLANE_PSEUDO_PLANAR : Chroma components interleaved in separate plane | |
268 | */ | |
269 | enum dpu_plane_type { | |
270 | DPU_PLANE_INTERLEAVED, | |
271 | DPU_PLANE_PLANAR, | |
272 | DPU_PLANE_PSEUDO_PLANAR, | |
273 | }; | |
274 | ||
275 | /** | |
276 | * enum dpu_chroma_samp_type - chroma sub-samplng type | |
277 | * @DPU_CHROMA_RGB : No chroma subsampling | |
278 | * @DPU_CHROMA_H2V1 : Chroma pixels are horizontally subsampled | |
279 | * @DPU_CHROMA_H1V2 : Chroma pixels are vertically subsampled | |
280 | * @DPU_CHROMA_420 : 420 subsampling | |
281 | */ | |
282 | enum dpu_chroma_samp_type { | |
283 | DPU_CHROMA_RGB, | |
284 | DPU_CHROMA_H2V1, | |
285 | DPU_CHROMA_H1V2, | |
286 | DPU_CHROMA_420 | |
287 | }; | |
288 | ||
289 | /** | |
290 | * dpu_fetch_type - Defines How DPU HW fetches data | |
291 | * @DPU_FETCH_LINEAR : fetch is line by line | |
292 | * @DPU_FETCH_TILE : fetches data in Z order from a tile | |
293 | * @DPU_FETCH_UBWC : fetch and decompress data | |
294 | */ | |
295 | enum dpu_fetch_type { | |
296 | DPU_FETCH_LINEAR, | |
297 | DPU_FETCH_TILE, | |
298 | DPU_FETCH_UBWC | |
299 | }; | |
300 | ||
301 | /** | |
302 | * Value of enum chosen to fit the number of bits | |
303 | * expected by the HW programming. | |
304 | */ | |
305 | enum { | |
306 | COLOR_ALPHA_1BIT = 0, | |
307 | COLOR_ALPHA_4BIT = 1, | |
308 | COLOR_4BIT = 0, | |
309 | COLOR_5BIT = 1, /* No 5-bit Alpha */ | |
310 | COLOR_6BIT = 2, /* 6-Bit Alpha also = 2 */ | |
311 | COLOR_8BIT = 3, /* 8-Bit Alpha also = 3 */ | |
312 | }; | |
313 | ||
314 | /** | |
315 | * enum dpu_3d_blend_mode | |
316 | * Desribes how the 3d data is blended | |
317 | * @BLEND_3D_NONE : 3d blending not enabled | |
318 | * @BLEND_3D_FRAME_INT : Frame interleaving | |
319 | * @BLEND_3D_H_ROW_INT : Horizontal row interleaving | |
320 | * @BLEND_3D_V_ROW_INT : vertical row interleaving | |
321 | * @BLEND_3D_COL_INT : column interleaving | |
322 | * @BLEND_3D_MAX : | |
323 | */ | |
324 | enum dpu_3d_blend_mode { | |
325 | BLEND_3D_NONE = 0, | |
326 | BLEND_3D_FRAME_INT, | |
327 | BLEND_3D_H_ROW_INT, | |
328 | BLEND_3D_V_ROW_INT, | |
329 | BLEND_3D_COL_INT, | |
330 | BLEND_3D_MAX | |
331 | }; | |
332 | ||
333 | /** struct dpu_format - defines the format configuration which | |
334 | * allows DPU HW to correctly fetch and decode the format | |
335 | * @base: base msm_format struture containing fourcc code | |
336 | * @fetch_planes: how the color components are packed in pixel format | |
337 | * @element: element color ordering | |
338 | * @bits: element bit widths | |
339 | * @chroma_sample: chroma sub-samplng type | |
340 | * @unpack_align_msb: unpack aligned, 0 to LSB, 1 to MSB | |
341 | * @unpack_tight: 0 for loose, 1 for tight | |
342 | * @unpack_count: 0 = 1 component, 1 = 2 component | |
343 | * @bpp: bytes per pixel | |
344 | * @alpha_enable: whether the format has an alpha channel | |
345 | * @num_planes: number of planes (including meta data planes) | |
346 | * @fetch_mode: linear, tiled, or ubwc hw fetch behavior | |
25fdd593 JS |
347 | * @flag: usage bit flags |
348 | * @tile_width: format tile width | |
349 | * @tile_height: format tile height | |
350 | */ | |
351 | struct dpu_format { | |
352 | struct msm_format base; | |
353 | enum dpu_plane_type fetch_planes; | |
354 | u8 element[DPU_MAX_PLANES]; | |
355 | u8 bits[DPU_MAX_PLANES]; | |
356 | enum dpu_chroma_samp_type chroma_sample; | |
357 | u8 unpack_align_msb; | |
358 | u8 unpack_tight; | |
359 | u8 unpack_count; | |
360 | u8 bpp; | |
361 | u8 alpha_enable; | |
362 | u8 num_planes; | |
363 | enum dpu_fetch_type fetch_mode; | |
364 | DECLARE_BITMAP(flag, DPU_FORMAT_FLAG_BIT_MAX); | |
365 | u16 tile_width; | |
366 | u16 tile_height; | |
367 | }; | |
368 | #define to_dpu_format(x) container_of(x, struct dpu_format, base) | |
369 | ||
370 | /** | |
371 | * struct dpu_hw_fmt_layout - format information of the source pixel data | |
372 | * @format: pixel format parameters | |
373 | * @num_planes: number of planes (including meta data planes) | |
374 | * @width: image width | |
375 | * @height: image height | |
376 | * @total_size: total size in bytes | |
377 | * @plane_addr: address of each plane | |
378 | * @plane_size: length of each plane | |
379 | * @plane_pitch: pitch of each plane | |
380 | */ | |
381 | struct dpu_hw_fmt_layout { | |
382 | const struct dpu_format *format; | |
383 | uint32_t num_planes; | |
384 | uint32_t width; | |
385 | uint32_t height; | |
386 | uint32_t total_size; | |
387 | uint32_t plane_addr[DPU_MAX_PLANES]; | |
388 | uint32_t plane_size[DPU_MAX_PLANES]; | |
389 | uint32_t plane_pitch[DPU_MAX_PLANES]; | |
390 | }; | |
391 | ||
392 | struct dpu_csc_cfg { | |
393 | /* matrix coefficients in S15.16 format */ | |
394 | uint32_t csc_mv[DPU_CSC_MATRIX_COEFF_SIZE]; | |
395 | uint32_t csc_pre_bv[DPU_CSC_BIAS_SIZE]; | |
396 | uint32_t csc_post_bv[DPU_CSC_BIAS_SIZE]; | |
397 | uint32_t csc_pre_lv[DPU_CSC_CLAMP_SIZE]; | |
398 | uint32_t csc_post_lv[DPU_CSC_CLAMP_SIZE]; | |
399 | }; | |
400 | ||
401 | /** | |
402 | * struct dpu_mdss_color - mdss color description | |
403 | * color 0 : green | |
404 | * color 1 : blue | |
405 | * color 2 : red | |
406 | * color 3 : alpha | |
407 | */ | |
408 | struct dpu_mdss_color { | |
409 | u32 color_0; | |
410 | u32 color_1; | |
411 | u32 color_2; | |
412 | u32 color_3; | |
413 | }; | |
414 | ||
415 | /* | |
416 | * Define bit masks for h/w logging. | |
417 | */ | |
418 | #define DPU_DBG_MASK_NONE (1 << 0) | |
9816b226 JS |
419 | #define DPU_DBG_MASK_INTF (1 << 1) |
420 | #define DPU_DBG_MASK_LM (1 << 2) | |
421 | #define DPU_DBG_MASK_CTL (1 << 3) | |
422 | #define DPU_DBG_MASK_PINGPONG (1 << 4) | |
423 | #define DPU_DBG_MASK_SSPP (1 << 5) | |
424 | #define DPU_DBG_MASK_WB (1 << 6) | |
425 | #define DPU_DBG_MASK_TOP (1 << 7) | |
426 | #define DPU_DBG_MASK_VBIF (1 << 8) | |
427 | #define DPU_DBG_MASK_ROT (1 << 9) | |
25fdd593 JS |
428 | |
429 | #endif /* _DPU_HW_MDSS_H */ |