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7198e6b0 RC |
1 | /* |
2 | * Copyright (C) 2013 Red Hat | |
3 | * Author: Rob Clark <robdclark@gmail.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | #include "adreno_gpu.h" | |
19 | #include "msm_gem.h" | |
871d812a | 20 | #include "msm_mmu.h" |
7198e6b0 | 21 | |
7198e6b0 RC |
22 | #define RB_SIZE SZ_32K |
23 | #define RB_BLKSIZE 16 | |
24 | ||
25 | int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value) | |
26 | { | |
27 | struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); | |
28 | ||
29 | switch (param) { | |
30 | case MSM_PARAM_GPU_ID: | |
31 | *value = adreno_gpu->info->revn; | |
32 | return 0; | |
33 | case MSM_PARAM_GMEM_SIZE: | |
55459968 | 34 | *value = adreno_gpu->gmem; |
7198e6b0 | 35 | return 0; |
4e1cbaa3 RC |
36 | case MSM_PARAM_CHIP_ID: |
37 | *value = adreno_gpu->rev.patchid | | |
38 | (adreno_gpu->rev.minor << 8) | | |
39 | (adreno_gpu->rev.major << 16) | | |
40 | (adreno_gpu->rev.core << 24); | |
41 | return 0; | |
7198e6b0 RC |
42 | default: |
43 | DBG("%s: invalid param: %u", gpu->name, param); | |
44 | return -EINVAL; | |
45 | } | |
46 | } | |
47 | ||
48 | #define rbmemptr(adreno_gpu, member) \ | |
49 | ((adreno_gpu)->memptrs_iova + offsetof(struct adreno_rbmemptrs, member)) | |
50 | ||
51 | int adreno_hw_init(struct msm_gpu *gpu) | |
52 | { | |
53 | struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); | |
944fc36c | 54 | int ret; |
7198e6b0 RC |
55 | |
56 | DBG("%s", gpu->name); | |
57 | ||
a1ad3523 | 58 | ret = msm_gem_get_iova(gpu->rb->bo, gpu->id, &gpu->rb_iova); |
944fc36c RC |
59 | if (ret) { |
60 | gpu->rb_iova = 0; | |
61 | dev_err(gpu->dev->dev, "could not map ringbuffer: %d\n", ret); | |
62 | return ret; | |
63 | } | |
64 | ||
7198e6b0 RC |
65 | /* Setup REG_CP_RB_CNTL: */ |
66 | gpu_write(gpu, REG_AXXX_CP_RB_CNTL, | |
67 | /* size is log2(quad-words): */ | |
68 | AXXX_CP_RB_CNTL_BUFSZ(ilog2(gpu->rb->size / 8)) | | |
55459968 | 69 | AXXX_CP_RB_CNTL_BLKSZ(ilog2(RB_BLKSIZE / 8))); |
7198e6b0 RC |
70 | |
71 | /* Setup ringbuffer address: */ | |
72 | gpu_write(gpu, REG_AXXX_CP_RB_BASE, gpu->rb_iova); | |
73 | gpu_write(gpu, REG_AXXX_CP_RB_RPTR_ADDR, rbmemptr(adreno_gpu, rptr)); | |
74 | ||
75 | /* Setup scratch/timestamp: */ | |
76 | gpu_write(gpu, REG_AXXX_SCRATCH_ADDR, rbmemptr(adreno_gpu, fence)); | |
77 | ||
78 | gpu_write(gpu, REG_AXXX_SCRATCH_UMSK, 0x1); | |
79 | ||
80 | return 0; | |
81 | } | |
82 | ||
83 | static uint32_t get_wptr(struct msm_ringbuffer *ring) | |
84 | { | |
85 | return ring->cur - ring->start; | |
86 | } | |
87 | ||
88 | uint32_t adreno_last_fence(struct msm_gpu *gpu) | |
89 | { | |
90 | struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); | |
91 | return adreno_gpu->memptrs->fence; | |
92 | } | |
93 | ||
bd6f82d8 RC |
94 | void adreno_recover(struct msm_gpu *gpu) |
95 | { | |
96 | struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); | |
97 | struct drm_device *dev = gpu->dev; | |
98 | int ret; | |
99 | ||
100 | gpu->funcs->pm_suspend(gpu); | |
101 | ||
102 | /* reset ringbuffer: */ | |
103 | gpu->rb->cur = gpu->rb->start; | |
104 | ||
105 | /* reset completed fence seqno, just discard anything pending: */ | |
106 | adreno_gpu->memptrs->fence = gpu->submitted_fence; | |
26791c48 RC |
107 | adreno_gpu->memptrs->rptr = 0; |
108 | adreno_gpu->memptrs->wptr = 0; | |
bd6f82d8 RC |
109 | |
110 | gpu->funcs->pm_resume(gpu); | |
111 | ret = gpu->funcs->hw_init(gpu); | |
112 | if (ret) { | |
113 | dev_err(dev->dev, "gpu hw init failed: %d\n", ret); | |
114 | /* hmm, oh well? */ | |
115 | } | |
116 | } | |
117 | ||
7198e6b0 RC |
118 | int adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, |
119 | struct msm_file_private *ctx) | |
120 | { | |
121 | struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); | |
122 | struct msm_drm_private *priv = gpu->dev->dev_private; | |
123 | struct msm_ringbuffer *ring = gpu->rb; | |
124 | unsigned i, ibs = 0; | |
125 | ||
7198e6b0 RC |
126 | for (i = 0; i < submit->nr_cmds; i++) { |
127 | switch (submit->cmd[i].type) { | |
128 | case MSM_SUBMIT_CMD_IB_TARGET_BUF: | |
129 | /* ignore IB-targets */ | |
130 | break; | |
131 | case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: | |
132 | /* ignore if there has not been a ctx switch: */ | |
133 | if (priv->lastctx == ctx) | |
134 | break; | |
135 | case MSM_SUBMIT_CMD_BUF: | |
136 | OUT_PKT3(ring, CP_INDIRECT_BUFFER_PFD, 2); | |
137 | OUT_RING(ring, submit->cmd[i].iova); | |
138 | OUT_RING(ring, submit->cmd[i].size); | |
139 | ibs++; | |
140 | break; | |
141 | } | |
142 | } | |
143 | ||
144 | /* on a320, at least, we seem to need to pad things out to an | |
145 | * even number of qwords to avoid issue w/ CP hanging on wrap- | |
146 | * around: | |
147 | */ | |
148 | if (ibs % 2) | |
149 | OUT_PKT2(ring); | |
150 | ||
151 | OUT_PKT0(ring, REG_AXXX_CP_SCRATCH_REG2, 1); | |
152 | OUT_RING(ring, submit->fence); | |
153 | ||
154 | if (adreno_is_a3xx(adreno_gpu)) { | |
155 | /* Flush HLSQ lazy updates to make sure there is nothing | |
156 | * pending for indirect loads after the timestamp has | |
157 | * passed: | |
158 | */ | |
159 | OUT_PKT3(ring, CP_EVENT_WRITE, 1); | |
160 | OUT_RING(ring, HLSQ_FLUSH); | |
161 | ||
162 | OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1); | |
163 | OUT_RING(ring, 0x00000000); | |
164 | } | |
165 | ||
166 | OUT_PKT3(ring, CP_EVENT_WRITE, 3); | |
167 | OUT_RING(ring, CACHE_FLUSH_TS); | |
168 | OUT_RING(ring, rbmemptr(adreno_gpu, fence)); | |
169 | OUT_RING(ring, submit->fence); | |
170 | ||
171 | /* we could maybe be clever and only CP_COND_EXEC the interrupt: */ | |
172 | OUT_PKT3(ring, CP_INTERRUPT, 1); | |
173 | OUT_RING(ring, 0x80000000); | |
174 | ||
175 | #if 0 | |
176 | if (adreno_is_a3xx(adreno_gpu)) { | |
177 | /* Dummy set-constant to trigger context rollover */ | |
178 | OUT_PKT3(ring, CP_SET_CONSTANT, 2); | |
179 | OUT_RING(ring, CP_REG(REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG)); | |
180 | OUT_RING(ring, 0x00000000); | |
181 | } | |
182 | #endif | |
183 | ||
184 | gpu->funcs->flush(gpu); | |
185 | ||
186 | return 0; | |
187 | } | |
188 | ||
189 | void adreno_flush(struct msm_gpu *gpu) | |
190 | { | |
191 | uint32_t wptr = get_wptr(gpu->rb); | |
192 | ||
193 | /* ensure writes to ringbuffer have hit system memory: */ | |
194 | mb(); | |
195 | ||
196 | gpu_write(gpu, REG_AXXX_CP_RB_WPTR, wptr); | |
197 | } | |
198 | ||
199 | void adreno_idle(struct msm_gpu *gpu) | |
200 | { | |
201 | struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); | |
0963756f | 202 | uint32_t wptr = get_wptr(gpu->rb); |
7198e6b0 | 203 | |
0963756f RC |
204 | /* wait for CP to drain ringbuffer: */ |
205 | if (spin_until(adreno_gpu->memptrs->rptr == wptr)) | |
206 | DRM_ERROR("%s: timeout waiting to drain ringbuffer!\n", gpu->name); | |
7198e6b0 RC |
207 | |
208 | /* TODO maybe we need to reset GPU here to recover from hang? */ | |
209 | } | |
210 | ||
211 | #ifdef CONFIG_DEBUG_FS | |
212 | void adreno_show(struct msm_gpu *gpu, struct seq_file *m) | |
213 | { | |
214 | struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); | |
215 | ||
216 | seq_printf(m, "revision: %d (%d.%d.%d.%d)\n", | |
217 | adreno_gpu->info->revn, adreno_gpu->rev.core, | |
218 | adreno_gpu->rev.major, adreno_gpu->rev.minor, | |
219 | adreno_gpu->rev.patchid); | |
220 | ||
221 | seq_printf(m, "fence: %d/%d\n", adreno_gpu->memptrs->fence, | |
bd6f82d8 | 222 | gpu->submitted_fence); |
7198e6b0 RC |
223 | seq_printf(m, "rptr: %d\n", adreno_gpu->memptrs->rptr); |
224 | seq_printf(m, "wptr: %d\n", adreno_gpu->memptrs->wptr); | |
225 | seq_printf(m, "rb wptr: %d\n", get_wptr(gpu->rb)); | |
226 | } | |
227 | #endif | |
228 | ||
5b6ef08e RC |
229 | /* would be nice to not have to duplicate the _show() stuff with printk(): */ |
230 | void adreno_dump(struct msm_gpu *gpu) | |
231 | { | |
232 | struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); | |
233 | ||
234 | printk("revision: %d (%d.%d.%d.%d)\n", | |
235 | adreno_gpu->info->revn, adreno_gpu->rev.core, | |
236 | adreno_gpu->rev.major, adreno_gpu->rev.minor, | |
237 | adreno_gpu->rev.patchid); | |
238 | ||
239 | printk("fence: %d/%d\n", adreno_gpu->memptrs->fence, | |
240 | gpu->submitted_fence); | |
241 | printk("rptr: %d\n", adreno_gpu->memptrs->rptr); | |
242 | printk("wptr: %d\n", adreno_gpu->memptrs->wptr); | |
243 | printk("rb wptr: %d\n", get_wptr(gpu->rb)); | |
244 | ||
245 | } | |
246 | ||
0963756f | 247 | static uint32_t ring_freewords(struct msm_gpu *gpu) |
7198e6b0 RC |
248 | { |
249 | struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); | |
0963756f RC |
250 | uint32_t size = gpu->rb->size / 4; |
251 | uint32_t wptr = get_wptr(gpu->rb); | |
252 | uint32_t rptr = adreno_gpu->memptrs->rptr; | |
253 | return (rptr + (size - 1) - wptr) % size; | |
254 | } | |
255 | ||
256 | void adreno_wait_ring(struct msm_gpu *gpu, uint32_t ndwords) | |
257 | { | |
258 | if (spin_until(ring_freewords(gpu) >= ndwords)) | |
259 | DRM_ERROR("%s: timeout waiting for ringbuffer space\n", gpu->name); | |
7198e6b0 RC |
260 | } |
261 | ||
262 | static const char *iommu_ports[] = { | |
263 | "gfx3d_user", "gfx3d_priv", | |
264 | "gfx3d1_user", "gfx3d1_priv", | |
265 | }; | |
266 | ||
7198e6b0 | 267 | int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, |
3526e9fb | 268 | struct adreno_gpu *adreno_gpu, const struct adreno_gpu_funcs *funcs) |
7198e6b0 | 269 | { |
3526e9fb RC |
270 | struct adreno_platform_config *config = pdev->dev.platform_data; |
271 | struct msm_gpu *gpu = &adreno_gpu->base; | |
871d812a | 272 | struct msm_mmu *mmu; |
e2550b7a | 273 | int ret; |
7198e6b0 | 274 | |
3526e9fb RC |
275 | adreno_gpu->funcs = funcs; |
276 | adreno_gpu->info = adreno_info(config->rev); | |
277 | adreno_gpu->gmem = adreno_gpu->info->gmem; | |
278 | adreno_gpu->revn = adreno_gpu->info->revn; | |
279 | adreno_gpu->rev = config->rev; | |
280 | ||
281 | gpu->fast_rate = config->fast_rate; | |
282 | gpu->slow_rate = config->slow_rate; | |
283 | gpu->bus_freq = config->bus_freq; | |
284 | #ifdef CONFIG_MSM_BUS_SCALING | |
285 | gpu->bus_scale_table = config->bus_scale_table; | |
286 | #endif | |
287 | ||
288 | DBG("fast_rate=%u, slow_rate=%u, bus_freq=%u", | |
289 | gpu->fast_rate, gpu->slow_rate, gpu->bus_freq); | |
7198e6b0 | 290 | |
3526e9fb | 291 | ret = request_firmware(&adreno_gpu->pm4, adreno_gpu->info->pm4fw, drm->dev); |
7198e6b0 RC |
292 | if (ret) { |
293 | dev_err(drm->dev, "failed to load %s PM4 firmware: %d\n", | |
3526e9fb | 294 | adreno_gpu->info->pm4fw, ret); |
7198e6b0 RC |
295 | return ret; |
296 | } | |
297 | ||
3526e9fb | 298 | ret = request_firmware(&adreno_gpu->pfp, adreno_gpu->info->pfpfw, drm->dev); |
7198e6b0 RC |
299 | if (ret) { |
300 | dev_err(drm->dev, "failed to load %s PFP firmware: %d\n", | |
3526e9fb | 301 | adreno_gpu->info->pfpfw, ret); |
7198e6b0 RC |
302 | return ret; |
303 | } | |
304 | ||
3526e9fb RC |
305 | ret = msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base, |
306 | adreno_gpu->info->name, "kgsl_3d0_reg_memory", "kgsl_3d0_irq", | |
7198e6b0 RC |
307 | RB_SIZE); |
308 | if (ret) | |
309 | return ret; | |
310 | ||
3526e9fb | 311 | mmu = gpu->mmu; |
871d812a RC |
312 | if (mmu) { |
313 | ret = mmu->funcs->attach(mmu, iommu_ports, | |
314 | ARRAY_SIZE(iommu_ports)); | |
315 | if (ret) | |
316 | return ret; | |
317 | } | |
7198e6b0 | 318 | |
a1ad3523 | 319 | mutex_lock(&drm->struct_mutex); |
3526e9fb | 320 | adreno_gpu->memptrs_bo = msm_gem_new(drm, sizeof(*adreno_gpu->memptrs), |
7198e6b0 | 321 | MSM_BO_UNCACHED); |
a1ad3523 | 322 | mutex_unlock(&drm->struct_mutex); |
3526e9fb RC |
323 | if (IS_ERR(adreno_gpu->memptrs_bo)) { |
324 | ret = PTR_ERR(adreno_gpu->memptrs_bo); | |
325 | adreno_gpu->memptrs_bo = NULL; | |
7198e6b0 RC |
326 | dev_err(drm->dev, "could not allocate memptrs: %d\n", ret); |
327 | return ret; | |
328 | } | |
329 | ||
3526e9fb RC |
330 | adreno_gpu->memptrs = msm_gem_vaddr(adreno_gpu->memptrs_bo); |
331 | if (!adreno_gpu->memptrs) { | |
7198e6b0 RC |
332 | dev_err(drm->dev, "could not vmap memptrs\n"); |
333 | return -ENOMEM; | |
334 | } | |
335 | ||
3526e9fb RC |
336 | ret = msm_gem_get_iova(adreno_gpu->memptrs_bo, gpu->id, |
337 | &adreno_gpu->memptrs_iova); | |
7198e6b0 RC |
338 | if (ret) { |
339 | dev_err(drm->dev, "could not map memptrs: %d\n", ret); | |
340 | return ret; | |
341 | } | |
342 | ||
343 | return 0; | |
344 | } | |
345 | ||
346 | void adreno_gpu_cleanup(struct adreno_gpu *gpu) | |
347 | { | |
348 | if (gpu->memptrs_bo) { | |
349 | if (gpu->memptrs_iova) | |
350 | msm_gem_put_iova(gpu->memptrs_bo, gpu->base.id); | |
351 | drm_gem_object_unreference(gpu->memptrs_bo); | |
352 | } | |
353 | if (gpu->pm4) | |
354 | release_firmware(gpu->pm4); | |
355 | if (gpu->pfp) | |
356 | release_firmware(gpu->pfp); | |
357 | msm_gpu_cleanup(&gpu->base); | |
358 | } |