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1da177e4 LT |
1 | /* mga_dma.c -- DMA support for mga g200/g400 -*- linux-c -*- |
2 | * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com | |
3 | * | |
4 | * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. | |
5 | * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. | |
6 | * All Rights Reserved. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the "Software"), | |
10 | * to deal in the Software without restriction, including without limitation | |
11 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
12 | * and/or sell copies of the Software, and to permit persons to whom the | |
13 | * Software is furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the next | |
16 | * paragraph) shall be included in all copies or substantial portions of the | |
17 | * Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
20 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
21 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
22 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
23 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
24 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
25 | * DEALINGS IN THE SOFTWARE. | |
6795c985 DA |
26 | */ |
27 | ||
28 | /** | |
29 | * \file mga_dma.c | |
30 | * DMA support for MGA G200 / G400. | |
b5e89ed5 | 31 | * |
6795c985 DA |
32 | * \author Rickard E. (Rik) Faith <faith@valinux.com> |
33 | * \author Jeff Hartmann <jhartmann@valinux.com> | |
34 | * \author Keith Whitwell <keith@tungstengraphics.com> | |
35 | * \author Gareth Hughes <gareth@valinux.com> | |
1da177e4 LT |
36 | */ |
37 | ||
38 | #include "drmP.h" | |
39 | #include "drm.h" | |
6795c985 | 40 | #include "drm_sarea.h" |
1da177e4 LT |
41 | #include "mga_drm.h" |
42 | #include "mga_drv.h" | |
43 | ||
44 | #define MGA_DEFAULT_USEC_TIMEOUT 10000 | |
45 | #define MGA_FREELIST_DEBUG 0 | |
46 | ||
7ccf800e DA |
47 | #define MINIMAL_CLEANUP 0 |
48 | #define FULL_CLEANUP 1 | |
eddca551 | 49 | static int mga_do_cleanup_dma(struct drm_device *dev, int full_cleanup); |
1da177e4 LT |
50 | |
51 | /* ================================================================ | |
52 | * Engine control | |
53 | */ | |
54 | ||
b5e89ed5 | 55 | int mga_do_wait_for_idle(drm_mga_private_t * dev_priv) |
1da177e4 LT |
56 | { |
57 | u32 status = 0; | |
58 | int i; | |
b5e89ed5 | 59 | DRM_DEBUG("\n"); |
1da177e4 | 60 | |
b5e89ed5 DA |
61 | for (i = 0; i < dev_priv->usec_timeout; i++) { |
62 | status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK; | |
63 | if (status == MGA_ENDPRDMASTS) { | |
64 | MGA_WRITE8(MGA_CRTC_INDEX, 0); | |
1da177e4 LT |
65 | return 0; |
66 | } | |
b5e89ed5 | 67 | DRM_UDELAY(1); |
1da177e4 LT |
68 | } |
69 | ||
70 | #if MGA_DMA_DEBUG | |
b5e89ed5 DA |
71 | DRM_ERROR("failed!\n"); |
72 | DRM_INFO(" status=0x%08x\n", status); | |
1da177e4 | 73 | #endif |
20caafa6 | 74 | return -EBUSY; |
1da177e4 LT |
75 | } |
76 | ||
b5e89ed5 | 77 | static int mga_do_dma_reset(drm_mga_private_t * dev_priv) |
1da177e4 LT |
78 | { |
79 | drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; | |
80 | drm_mga_primary_buffer_t *primary = &dev_priv->prim; | |
81 | ||
b5e89ed5 | 82 | DRM_DEBUG("\n"); |
1da177e4 LT |
83 | |
84 | /* The primary DMA stream should look like new right about now. | |
85 | */ | |
86 | primary->tail = 0; | |
87 | primary->space = primary->size; | |
88 | primary->last_flush = 0; | |
89 | ||
90 | sarea_priv->last_wrap = 0; | |
91 | ||
92 | /* FIXME: Reset counters, buffer ages etc... | |
93 | */ | |
94 | ||
95 | /* FIXME: What else do we need to reinitialize? WARP stuff? | |
96 | */ | |
97 | ||
98 | return 0; | |
99 | } | |
100 | ||
101 | /* ================================================================ | |
102 | * Primary DMA stream | |
103 | */ | |
104 | ||
b5e89ed5 | 105 | void mga_do_dma_flush(drm_mga_private_t * dev_priv) |
1da177e4 LT |
106 | { |
107 | drm_mga_primary_buffer_t *primary = &dev_priv->prim; | |
108 | u32 head, tail; | |
109 | u32 status = 0; | |
110 | int i; | |
b5e89ed5 DA |
111 | DMA_LOCALS; |
112 | DRM_DEBUG("\n"); | |
113 | ||
114 | /* We need to wait so that we can do an safe flush */ | |
115 | for (i = 0; i < dev_priv->usec_timeout; i++) { | |
116 | status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK; | |
117 | if (status == MGA_ENDPRDMASTS) | |
118 | break; | |
119 | DRM_UDELAY(1); | |
1da177e4 LT |
120 | } |
121 | ||
b5e89ed5 DA |
122 | if (primary->tail == primary->last_flush) { |
123 | DRM_DEBUG(" bailing out...\n"); | |
1da177e4 LT |
124 | return; |
125 | } | |
126 | ||
127 | tail = primary->tail + dev_priv->primary->offset; | |
128 | ||
129 | /* We need to pad the stream between flushes, as the card | |
130 | * actually (partially?) reads the first of these commands. | |
131 | * See page 4-16 in the G400 manual, middle of the page or so. | |
132 | */ | |
b5e89ed5 | 133 | BEGIN_DMA(1); |
1da177e4 | 134 | |
b5e89ed5 DA |
135 | DMA_BLOCK(MGA_DMAPAD, 0x00000000, |
136 | MGA_DMAPAD, 0x00000000, | |
137 | MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000); | |
1da177e4 LT |
138 | |
139 | ADVANCE_DMA(); | |
140 | ||
141 | primary->last_flush = primary->tail; | |
142 | ||
b5e89ed5 | 143 | head = MGA_READ(MGA_PRIMADDRESS); |
1da177e4 | 144 | |
b5e89ed5 | 145 | if (head <= tail) { |
1da177e4 LT |
146 | primary->space = primary->size - primary->tail; |
147 | } else { | |
148 | primary->space = head - tail; | |
149 | } | |
150 | ||
b5e89ed5 DA |
151 | DRM_DEBUG(" head = 0x%06lx\n", head - dev_priv->primary->offset); |
152 | DRM_DEBUG(" tail = 0x%06lx\n", tail - dev_priv->primary->offset); | |
153 | DRM_DEBUG(" space = 0x%06x\n", primary->space); | |
1da177e4 LT |
154 | |
155 | mga_flush_write_combine(); | |
6795c985 | 156 | MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access); |
1da177e4 | 157 | |
b5e89ed5 | 158 | DRM_DEBUG("done.\n"); |
1da177e4 LT |
159 | } |
160 | ||
b5e89ed5 | 161 | void mga_do_dma_wrap_start(drm_mga_private_t * dev_priv) |
1da177e4 LT |
162 | { |
163 | drm_mga_primary_buffer_t *primary = &dev_priv->prim; | |
164 | u32 head, tail; | |
165 | DMA_LOCALS; | |
b5e89ed5 | 166 | DRM_DEBUG("\n"); |
1da177e4 LT |
167 | |
168 | BEGIN_DMA_WRAP(); | |
169 | ||
b5e89ed5 DA |
170 | DMA_BLOCK(MGA_DMAPAD, 0x00000000, |
171 | MGA_DMAPAD, 0x00000000, | |
172 | MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000); | |
1da177e4 LT |
173 | |
174 | ADVANCE_DMA(); | |
175 | ||
176 | tail = primary->tail + dev_priv->primary->offset; | |
177 | ||
178 | primary->tail = 0; | |
179 | primary->last_flush = 0; | |
180 | primary->last_wrap++; | |
181 | ||
b5e89ed5 | 182 | head = MGA_READ(MGA_PRIMADDRESS); |
1da177e4 | 183 | |
b5e89ed5 | 184 | if (head == dev_priv->primary->offset) { |
1da177e4 LT |
185 | primary->space = primary->size; |
186 | } else { | |
187 | primary->space = head - dev_priv->primary->offset; | |
188 | } | |
189 | ||
b5e89ed5 DA |
190 | DRM_DEBUG(" head = 0x%06lx\n", head - dev_priv->primary->offset); |
191 | DRM_DEBUG(" tail = 0x%06x\n", primary->tail); | |
192 | DRM_DEBUG(" wrap = %d\n", primary->last_wrap); | |
193 | DRM_DEBUG(" space = 0x%06x\n", primary->space); | |
1da177e4 LT |
194 | |
195 | mga_flush_write_combine(); | |
6795c985 | 196 | MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access); |
1da177e4 | 197 | |
b5e89ed5 DA |
198 | set_bit(0, &primary->wrapped); |
199 | DRM_DEBUG("done.\n"); | |
1da177e4 LT |
200 | } |
201 | ||
b5e89ed5 | 202 | void mga_do_dma_wrap_end(drm_mga_private_t * dev_priv) |
1da177e4 LT |
203 | { |
204 | drm_mga_primary_buffer_t *primary = &dev_priv->prim; | |
205 | drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; | |
206 | u32 head = dev_priv->primary->offset; | |
b5e89ed5 | 207 | DRM_DEBUG("\n"); |
1da177e4 LT |
208 | |
209 | sarea_priv->last_wrap++; | |
b5e89ed5 | 210 | DRM_DEBUG(" wrap = %d\n", sarea_priv->last_wrap); |
1da177e4 LT |
211 | |
212 | mga_flush_write_combine(); | |
b5e89ed5 | 213 | MGA_WRITE(MGA_PRIMADDRESS, head | MGA_DMA_GENERAL); |
1da177e4 | 214 | |
b5e89ed5 DA |
215 | clear_bit(0, &primary->wrapped); |
216 | DRM_DEBUG("done.\n"); | |
1da177e4 LT |
217 | } |
218 | ||
1da177e4 LT |
219 | /* ================================================================ |
220 | * Freelist management | |
221 | */ | |
222 | ||
223 | #define MGA_BUFFER_USED ~0 | |
224 | #define MGA_BUFFER_FREE 0 | |
225 | ||
226 | #if MGA_FREELIST_DEBUG | |
eddca551 | 227 | static void mga_freelist_print(struct drm_device * dev) |
1da177e4 LT |
228 | { |
229 | drm_mga_private_t *dev_priv = dev->dev_private; | |
230 | drm_mga_freelist_t *entry; | |
231 | ||
b5e89ed5 DA |
232 | DRM_INFO("\n"); |
233 | DRM_INFO("current dispatch: last=0x%x done=0x%x\n", | |
234 | dev_priv->sarea_priv->last_dispatch, | |
235 | (unsigned int)(MGA_READ(MGA_PRIMADDRESS) - | |
236 | dev_priv->primary->offset)); | |
237 | DRM_INFO("current freelist:\n"); | |
238 | ||
239 | for (entry = dev_priv->head->next; entry; entry = entry->next) { | |
240 | DRM_INFO(" %p idx=%2d age=0x%x 0x%06lx\n", | |
241 | entry, entry->buf->idx, entry->age.head, | |
242 | entry->age.head - dev_priv->primary->offset); | |
1da177e4 | 243 | } |
b5e89ed5 | 244 | DRM_INFO("\n"); |
1da177e4 LT |
245 | } |
246 | #endif | |
247 | ||
eddca551 | 248 | static int mga_freelist_init(struct drm_device * dev, drm_mga_private_t * dev_priv) |
1da177e4 | 249 | { |
cdd55a29 | 250 | struct drm_device_dma *dma = dev->dma; |
056219e2 | 251 | struct drm_buf *buf; |
1da177e4 LT |
252 | drm_mga_buf_priv_t *buf_priv; |
253 | drm_mga_freelist_t *entry; | |
254 | int i; | |
b5e89ed5 | 255 | DRM_DEBUG("count=%d\n", dma->buf_count); |
1da177e4 | 256 | |
b5e89ed5 DA |
257 | dev_priv->head = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER); |
258 | if (dev_priv->head == NULL) | |
20caafa6 | 259 | return -ENOMEM; |
1da177e4 | 260 | |
b5e89ed5 DA |
261 | memset(dev_priv->head, 0, sizeof(drm_mga_freelist_t)); |
262 | SET_AGE(&dev_priv->head->age, MGA_BUFFER_USED, 0); | |
1da177e4 | 263 | |
b5e89ed5 | 264 | for (i = 0; i < dma->buf_count; i++) { |
1da177e4 | 265 | buf = dma->buflist[i]; |
b5e89ed5 | 266 | buf_priv = buf->dev_private; |
1da177e4 | 267 | |
b5e89ed5 DA |
268 | entry = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER); |
269 | if (entry == NULL) | |
20caafa6 | 270 | return -ENOMEM; |
1da177e4 | 271 | |
b5e89ed5 | 272 | memset(entry, 0, sizeof(drm_mga_freelist_t)); |
1da177e4 LT |
273 | |
274 | entry->next = dev_priv->head->next; | |
275 | entry->prev = dev_priv->head; | |
b5e89ed5 | 276 | SET_AGE(&entry->age, MGA_BUFFER_FREE, 0); |
1da177e4 LT |
277 | entry->buf = buf; |
278 | ||
b5e89ed5 | 279 | if (dev_priv->head->next != NULL) |
1da177e4 | 280 | dev_priv->head->next->prev = entry; |
b5e89ed5 | 281 | if (entry->next == NULL) |
1da177e4 LT |
282 | dev_priv->tail = entry; |
283 | ||
284 | buf_priv->list_entry = entry; | |
285 | buf_priv->discard = 0; | |
286 | buf_priv->dispatched = 0; | |
287 | ||
288 | dev_priv->head->next = entry; | |
289 | } | |
290 | ||
291 | return 0; | |
292 | } | |
293 | ||
eddca551 | 294 | static void mga_freelist_cleanup(struct drm_device * dev) |
1da177e4 LT |
295 | { |
296 | drm_mga_private_t *dev_priv = dev->dev_private; | |
297 | drm_mga_freelist_t *entry; | |
298 | drm_mga_freelist_t *next; | |
b5e89ed5 | 299 | DRM_DEBUG("\n"); |
1da177e4 LT |
300 | |
301 | entry = dev_priv->head; | |
b5e89ed5 | 302 | while (entry) { |
1da177e4 | 303 | next = entry->next; |
b5e89ed5 | 304 | drm_free(entry, sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER); |
1da177e4 LT |
305 | entry = next; |
306 | } | |
307 | ||
308 | dev_priv->head = dev_priv->tail = NULL; | |
309 | } | |
310 | ||
311 | #if 0 | |
312 | /* FIXME: Still needed? | |
313 | */ | |
eddca551 | 314 | static void mga_freelist_reset(struct drm_device * dev) |
1da177e4 | 315 | { |
cdd55a29 | 316 | struct drm_device_dma *dma = dev->dma; |
056219e2 | 317 | struct drm_buf *buf; |
1da177e4 LT |
318 | drm_mga_buf_priv_t *buf_priv; |
319 | int i; | |
320 | ||
b5e89ed5 | 321 | for (i = 0; i < dma->buf_count; i++) { |
1da177e4 | 322 | buf = dma->buflist[i]; |
b5e89ed5 DA |
323 | buf_priv = buf->dev_private; |
324 | SET_AGE(&buf_priv->list_entry->age, MGA_BUFFER_FREE, 0); | |
1da177e4 LT |
325 | } |
326 | } | |
327 | #endif | |
328 | ||
056219e2 | 329 | static struct drm_buf *mga_freelist_get(struct drm_device * dev) |
1da177e4 LT |
330 | { |
331 | drm_mga_private_t *dev_priv = dev->dev_private; | |
332 | drm_mga_freelist_t *next; | |
333 | drm_mga_freelist_t *prev; | |
334 | drm_mga_freelist_t *tail = dev_priv->tail; | |
335 | u32 head, wrap; | |
b5e89ed5 | 336 | DRM_DEBUG("\n"); |
1da177e4 | 337 | |
b5e89ed5 | 338 | head = MGA_READ(MGA_PRIMADDRESS); |
1da177e4 LT |
339 | wrap = dev_priv->sarea_priv->last_wrap; |
340 | ||
b5e89ed5 DA |
341 | DRM_DEBUG(" tail=0x%06lx %d\n", |
342 | tail->age.head ? | |
343 | tail->age.head - dev_priv->primary->offset : 0, | |
344 | tail->age.wrap); | |
345 | DRM_DEBUG(" head=0x%06lx %d\n", | |
346 | head - dev_priv->primary->offset, wrap); | |
1da177e4 | 347 | |
b5e89ed5 | 348 | if (TEST_AGE(&tail->age, head, wrap)) { |
1da177e4 LT |
349 | prev = dev_priv->tail->prev; |
350 | next = dev_priv->tail; | |
351 | prev->next = NULL; | |
352 | next->prev = next->next = NULL; | |
353 | dev_priv->tail = prev; | |
b5e89ed5 | 354 | SET_AGE(&next->age, MGA_BUFFER_USED, 0); |
1da177e4 LT |
355 | return next->buf; |
356 | } | |
357 | ||
b5e89ed5 | 358 | DRM_DEBUG("returning NULL!\n"); |
1da177e4 LT |
359 | return NULL; |
360 | } | |
361 | ||
056219e2 | 362 | int mga_freelist_put(struct drm_device * dev, struct drm_buf * buf) |
1da177e4 LT |
363 | { |
364 | drm_mga_private_t *dev_priv = dev->dev_private; | |
365 | drm_mga_buf_priv_t *buf_priv = buf->dev_private; | |
366 | drm_mga_freelist_t *head, *entry, *prev; | |
367 | ||
b5e89ed5 DA |
368 | DRM_DEBUG("age=0x%06lx wrap=%d\n", |
369 | buf_priv->list_entry->age.head - | |
370 | dev_priv->primary->offset, buf_priv->list_entry->age.wrap); | |
1da177e4 LT |
371 | |
372 | entry = buf_priv->list_entry; | |
373 | head = dev_priv->head; | |
374 | ||
b5e89ed5 DA |
375 | if (buf_priv->list_entry->age.head == MGA_BUFFER_USED) { |
376 | SET_AGE(&entry->age, MGA_BUFFER_FREE, 0); | |
1da177e4 LT |
377 | prev = dev_priv->tail; |
378 | prev->next = entry; | |
379 | entry->prev = prev; | |
380 | entry->next = NULL; | |
381 | } else { | |
382 | prev = head->next; | |
383 | head->next = entry; | |
384 | prev->prev = entry; | |
385 | entry->prev = head; | |
386 | entry->next = prev; | |
387 | } | |
388 | ||
389 | return 0; | |
390 | } | |
391 | ||
1da177e4 LT |
392 | /* ================================================================ |
393 | * DMA initialization, cleanup | |
394 | */ | |
395 | ||
eddca551 | 396 | int mga_driver_load(struct drm_device * dev, unsigned long flags) |
6795c985 | 397 | { |
b5e89ed5 | 398 | drm_mga_private_t *dev_priv; |
52440211 | 399 | int ret; |
6795c985 DA |
400 | |
401 | dev_priv = drm_alloc(sizeof(drm_mga_private_t), DRM_MEM_DRIVER); | |
402 | if (!dev_priv) | |
20caafa6 | 403 | return -ENOMEM; |
6795c985 DA |
404 | |
405 | dev->dev_private = (void *)dev_priv; | |
406 | memset(dev_priv, 0, sizeof(drm_mga_private_t)); | |
407 | ||
408 | dev_priv->usec_timeout = MGA_DEFAULT_USEC_TIMEOUT; | |
409 | dev_priv->chipset = flags; | |
410 | ||
22eae947 DA |
411 | dev_priv->mmio_base = drm_get_resource_start(dev, 1); |
412 | dev_priv->mmio_size = drm_get_resource_len(dev, 1); | |
413 | ||
414 | dev->counters += 3; | |
415 | dev->types[6] = _DRM_STAT_IRQ; | |
416 | dev->types[7] = _DRM_STAT_PRIMARY; | |
417 | dev->types[8] = _DRM_STAT_SECONDARY; | |
418 | ||
52440211 KP |
419 | ret = drm_vblank_init(dev, 1); |
420 | ||
421 | if (ret) { | |
422 | (void) mga_driver_unload(dev); | |
423 | return ret; | |
424 | } | |
425 | ||
6795c985 DA |
426 | return 0; |
427 | } | |
428 | ||
908f9c48 | 429 | #if __OS_HAS_AGP |
6795c985 DA |
430 | /** |
431 | * Bootstrap the driver for AGP DMA. | |
b5e89ed5 | 432 | * |
6795c985 DA |
433 | * \todo |
434 | * Investigate whether there is any benifit to storing the WARP microcode in | |
435 | * AGP memory. If not, the microcode may as well always be put in PCI | |
436 | * memory. | |
437 | * | |
438 | * \todo | |
439 | * This routine needs to set dma_bs->agp_mode to the mode actually configured | |
440 | * in the hardware. Looking just at the Linux AGP driver code, I don't see | |
441 | * an easy way to determine this. | |
442 | * | |
443 | * \sa mga_do_dma_bootstrap, mga_do_pci_dma_bootstrap | |
444 | */ | |
eddca551 | 445 | static int mga_do_agp_dma_bootstrap(struct drm_device * dev, |
6795c985 DA |
446 | drm_mga_dma_bootstrap_t * dma_bs) |
447 | { | |
b5e89ed5 DA |
448 | drm_mga_private_t *const dev_priv = |
449 | (drm_mga_private_t *) dev->dev_private; | |
11909d64 | 450 | unsigned int warp_size = mga_warp_microcode_size(dev_priv); |
6795c985 | 451 | int err; |
b5e89ed5 | 452 | unsigned offset; |
6795c985 | 453 | const unsigned secondary_size = dma_bs->secondary_bin_count |
b5e89ed5 | 454 | * dma_bs->secondary_bin_size; |
6795c985 | 455 | const unsigned agp_size = (dma_bs->agp_size << 20); |
eddca551 DA |
456 | struct drm_buf_desc req; |
457 | struct drm_agp_mode mode; | |
458 | struct drm_agp_info info; | |
459 | struct drm_agp_buffer agp_req; | |
460 | struct drm_agp_binding bind_req; | |
6795c985 | 461 | |
6795c985 DA |
462 | /* Acquire AGP. */ |
463 | err = drm_agp_acquire(dev); | |
464 | if (err) { | |
7ccf800e | 465 | DRM_ERROR("Unable to acquire AGP: %d\n", err); |
6795c985 DA |
466 | return err; |
467 | } | |
468 | ||
469 | err = drm_agp_info(dev, &info); | |
470 | if (err) { | |
7ccf800e | 471 | DRM_ERROR("Unable to get AGP info: %d\n", err); |
6795c985 DA |
472 | return err; |
473 | } | |
474 | ||
475 | mode.mode = (info.mode & ~0x07) | dma_bs->agp_mode; | |
476 | err = drm_agp_enable(dev, mode); | |
477 | if (err) { | |
478 | DRM_ERROR("Unable to enable AGP (mode = 0x%lx)\n", mode.mode); | |
479 | return err; | |
480 | } | |
481 | ||
6795c985 DA |
482 | /* In addition to the usual AGP mode configuration, the G200 AGP cards |
483 | * need to have the AGP mode "manually" set. | |
484 | */ | |
485 | ||
486 | if (dev_priv->chipset == MGA_CARD_TYPE_G200) { | |
487 | if (mode.mode & 0x02) { | |
488 | MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_ENABLE); | |
b5e89ed5 | 489 | } else { |
6795c985 DA |
490 | MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_DISABLE); |
491 | } | |
492 | } | |
493 | ||
6795c985 | 494 | /* Allocate and bind AGP memory. */ |
7ccf800e DA |
495 | agp_req.size = agp_size; |
496 | agp_req.type = 0; | |
497 | err = drm_agp_alloc(dev, &agp_req); | |
498 | if (err) { | |
499 | dev_priv->agp_size = 0; | |
6795c985 DA |
500 | DRM_ERROR("Unable to allocate %uMB AGP memory\n", |
501 | dma_bs->agp_size); | |
7ccf800e | 502 | return err; |
6795c985 | 503 | } |
bc5f4523 | 504 | |
7ccf800e DA |
505 | dev_priv->agp_size = agp_size; |
506 | dev_priv->agp_handle = agp_req.handle; | |
b5e89ed5 | 507 | |
7ccf800e DA |
508 | bind_req.handle = agp_req.handle; |
509 | bind_req.offset = 0; | |
510 | err = drm_agp_bind(dev, &bind_req); | |
6795c985 | 511 | if (err) { |
7ccf800e | 512 | DRM_ERROR("Unable to bind AGP memory: %d\n", err); |
6795c985 DA |
513 | return err; |
514 | } | |
515 | ||
11909d64 DA |
516 | /* Make drm_addbufs happy by not trying to create a mapping for less |
517 | * than a page. | |
518 | */ | |
519 | if (warp_size < PAGE_SIZE) | |
520 | warp_size = PAGE_SIZE; | |
521 | ||
6795c985 | 522 | offset = 0; |
b5e89ed5 DA |
523 | err = drm_addmap(dev, offset, warp_size, |
524 | _DRM_AGP, _DRM_READ_ONLY, &dev_priv->warp); | |
6795c985 | 525 | if (err) { |
7ccf800e | 526 | DRM_ERROR("Unable to map WARP microcode: %d\n", err); |
6795c985 DA |
527 | return err; |
528 | } | |
529 | ||
530 | offset += warp_size; | |
b5e89ed5 DA |
531 | err = drm_addmap(dev, offset, dma_bs->primary_size, |
532 | _DRM_AGP, _DRM_READ_ONLY, &dev_priv->primary); | |
6795c985 | 533 | if (err) { |
7ccf800e | 534 | DRM_ERROR("Unable to map primary DMA region: %d\n", err); |
6795c985 DA |
535 | return err; |
536 | } | |
537 | ||
538 | offset += dma_bs->primary_size; | |
b5e89ed5 DA |
539 | err = drm_addmap(dev, offset, secondary_size, |
540 | _DRM_AGP, 0, &dev->agp_buffer_map); | |
6795c985 | 541 | if (err) { |
7ccf800e | 542 | DRM_ERROR("Unable to map secondary DMA region: %d\n", err); |
6795c985 DA |
543 | return err; |
544 | } | |
545 | ||
b5e89ed5 | 546 | (void)memset(&req, 0, sizeof(req)); |
6795c985 DA |
547 | req.count = dma_bs->secondary_bin_count; |
548 | req.size = dma_bs->secondary_bin_size; | |
549 | req.flags = _DRM_AGP_BUFFER; | |
550 | req.agp_start = offset; | |
551 | ||
b5e89ed5 | 552 | err = drm_addbufs_agp(dev, &req); |
6795c985 | 553 | if (err) { |
7ccf800e | 554 | DRM_ERROR("Unable to add secondary DMA buffers: %d\n", err); |
6795c985 DA |
555 | return err; |
556 | } | |
557 | ||
7ccf800e | 558 | { |
55910517 | 559 | struct drm_map_list *_entry; |
7ccf800e | 560 | unsigned long agp_token = 0; |
bc5f4523 | 561 | |
bd1b331f | 562 | list_for_each_entry(_entry, &dev->maplist, head) { |
7ccf800e DA |
563 | if (_entry->map == dev->agp_buffer_map) |
564 | agp_token = _entry->user_token; | |
565 | } | |
566 | if (!agp_token) | |
567 | return -EFAULT; | |
568 | ||
569 | dev->agp_buffer_token = agp_token; | |
570 | } | |
571 | ||
6795c985 | 572 | offset += secondary_size; |
b5e89ed5 DA |
573 | err = drm_addmap(dev, offset, agp_size - offset, |
574 | _DRM_AGP, 0, &dev_priv->agp_textures); | |
6795c985 | 575 | if (err) { |
7ccf800e | 576 | DRM_ERROR("Unable to map AGP texture region %d\n", err); |
6795c985 DA |
577 | return err; |
578 | } | |
579 | ||
580 | drm_core_ioremap(dev_priv->warp, dev); | |
581 | drm_core_ioremap(dev_priv->primary, dev); | |
582 | drm_core_ioremap(dev->agp_buffer_map, dev); | |
583 | ||
584 | if (!dev_priv->warp->handle || | |
585 | !dev_priv->primary->handle || !dev->agp_buffer_map->handle) { | |
586 | DRM_ERROR("failed to ioremap agp regions! (%p, %p, %p)\n", | |
587 | dev_priv->warp->handle, dev_priv->primary->handle, | |
588 | dev->agp_buffer_map->handle); | |
20caafa6 | 589 | return -ENOMEM; |
6795c985 DA |
590 | } |
591 | ||
592 | dev_priv->dma_access = MGA_PAGPXFER; | |
593 | dev_priv->wagp_enable = MGA_WAGP_ENABLE; | |
594 | ||
595 | DRM_INFO("Initialized card for AGP DMA.\n"); | |
596 | return 0; | |
597 | } | |
908f9c48 | 598 | #else |
eddca551 | 599 | static int mga_do_agp_dma_bootstrap(struct drm_device * dev, |
908f9c48 DA |
600 | drm_mga_dma_bootstrap_t * dma_bs) |
601 | { | |
602 | return -EINVAL; | |
603 | } | |
604 | #endif | |
6795c985 DA |
605 | |
606 | /** | |
607 | * Bootstrap the driver for PCI DMA. | |
b5e89ed5 | 608 | * |
6795c985 DA |
609 | * \todo |
610 | * The algorithm for decreasing the size of the primary DMA buffer could be | |
611 | * better. The size should be rounded up to the nearest page size, then | |
612 | * decrease the request size by a single page each pass through the loop. | |
613 | * | |
614 | * \todo | |
615 | * Determine whether the maximum address passed to drm_pci_alloc is correct. | |
616 | * The same goes for drm_addbufs_pci. | |
b5e89ed5 | 617 | * |
6795c985 DA |
618 | * \sa mga_do_dma_bootstrap, mga_do_agp_dma_bootstrap |
619 | */ | |
eddca551 | 620 | static int mga_do_pci_dma_bootstrap(struct drm_device * dev, |
6795c985 DA |
621 | drm_mga_dma_bootstrap_t * dma_bs) |
622 | { | |
b5e89ed5 DA |
623 | drm_mga_private_t *const dev_priv = |
624 | (drm_mga_private_t *) dev->dev_private; | |
11909d64 | 625 | unsigned int warp_size = mga_warp_microcode_size(dev_priv); |
6795c985 DA |
626 | unsigned int primary_size; |
627 | unsigned int bin_count; | |
628 | int err; | |
eddca551 | 629 | struct drm_buf_desc req; |
6795c985 | 630 | |
6795c985 DA |
631 | if (dev->dma == NULL) { |
632 | DRM_ERROR("dev->dma is NULL\n"); | |
20caafa6 | 633 | return -EFAULT; |
6795c985 DA |
634 | } |
635 | ||
11909d64 DA |
636 | /* Make drm_addbufs happy by not trying to create a mapping for less |
637 | * than a page. | |
638 | */ | |
639 | if (warp_size < PAGE_SIZE) | |
640 | warp_size = PAGE_SIZE; | |
641 | ||
6795c985 DA |
642 | /* The proper alignment is 0x100 for this mapping */ |
643 | err = drm_addmap(dev, 0, warp_size, _DRM_CONSISTENT, | |
644 | _DRM_READ_ONLY, &dev_priv->warp); | |
645 | if (err != 0) { | |
7ccf800e DA |
646 | DRM_ERROR("Unable to create mapping for WARP microcode: %d\n", |
647 | err); | |
6795c985 DA |
648 | return err; |
649 | } | |
650 | ||
651 | /* Other than the bottom two bits being used to encode other | |
652 | * information, there don't appear to be any restrictions on the | |
653 | * alignment of the primary or secondary DMA buffers. | |
654 | */ | |
655 | ||
b5e89ed5 DA |
656 | for (primary_size = dma_bs->primary_size; primary_size != 0; |
657 | primary_size >>= 1) { | |
6795c985 DA |
658 | /* The proper alignment for this mapping is 0x04 */ |
659 | err = drm_addmap(dev, 0, primary_size, _DRM_CONSISTENT, | |
660 | _DRM_READ_ONLY, &dev_priv->primary); | |
661 | if (!err) | |
662 | break; | |
663 | } | |
664 | ||
665 | if (err != 0) { | |
7ccf800e | 666 | DRM_ERROR("Unable to allocate primary DMA region: %d\n", err); |
20caafa6 | 667 | return -ENOMEM; |
6795c985 DA |
668 | } |
669 | ||
670 | if (dev_priv->primary->size != dma_bs->primary_size) { | |
671 | DRM_INFO("Primary DMA buffer size reduced from %u to %u.\n", | |
b5e89ed5 DA |
672 | dma_bs->primary_size, |
673 | (unsigned)dev_priv->primary->size); | |
6795c985 DA |
674 | dma_bs->primary_size = dev_priv->primary->size; |
675 | } | |
676 | ||
b5e89ed5 DA |
677 | for (bin_count = dma_bs->secondary_bin_count; bin_count > 0; |
678 | bin_count--) { | |
679 | (void)memset(&req, 0, sizeof(req)); | |
6795c985 DA |
680 | req.count = bin_count; |
681 | req.size = dma_bs->secondary_bin_size; | |
682 | ||
b5e89ed5 | 683 | err = drm_addbufs_pci(dev, &req); |
6795c985 DA |
684 | if (!err) { |
685 | break; | |
686 | } | |
687 | } | |
b5e89ed5 | 688 | |
6795c985 | 689 | if (bin_count == 0) { |
7ccf800e | 690 | DRM_ERROR("Unable to add secondary DMA buffers: %d\n", err); |
6795c985 DA |
691 | return err; |
692 | } | |
693 | ||
694 | if (bin_count != dma_bs->secondary_bin_count) { | |
695 | DRM_INFO("Secondary PCI DMA buffer bin count reduced from %u " | |
696 | "to %u.\n", dma_bs->secondary_bin_count, bin_count); | |
697 | ||
698 | dma_bs->secondary_bin_count = bin_count; | |
699 | } | |
700 | ||
701 | dev_priv->dma_access = 0; | |
702 | dev_priv->wagp_enable = 0; | |
703 | ||
704 | dma_bs->agp_mode = 0; | |
705 | ||
706 | DRM_INFO("Initialized card for PCI DMA.\n"); | |
707 | return 0; | |
708 | } | |
709 | ||
eddca551 | 710 | static int mga_do_dma_bootstrap(struct drm_device * dev, |
6795c985 DA |
711 | drm_mga_dma_bootstrap_t * dma_bs) |
712 | { | |
713 | const int is_agp = (dma_bs->agp_mode != 0) && drm_device_is_agp(dev); | |
714 | int err; | |
b5e89ed5 DA |
715 | drm_mga_private_t *const dev_priv = |
716 | (drm_mga_private_t *) dev->dev_private; | |
6795c985 DA |
717 | |
718 | dev_priv->used_new_dma_init = 1; | |
719 | ||
720 | /* The first steps are the same for both PCI and AGP based DMA. Map | |
721 | * the cards MMIO registers and map a status page. | |
722 | */ | |
b5e89ed5 DA |
723 | err = drm_addmap(dev, dev_priv->mmio_base, dev_priv->mmio_size, |
724 | _DRM_REGISTERS, _DRM_READ_ONLY, &dev_priv->mmio); | |
6795c985 | 725 | if (err) { |
7ccf800e | 726 | DRM_ERROR("Unable to map MMIO region: %d\n", err); |
6795c985 DA |
727 | return err; |
728 | } | |
729 | ||
b5e89ed5 DA |
730 | err = drm_addmap(dev, 0, SAREA_MAX, _DRM_SHM, |
731 | _DRM_READ_ONLY | _DRM_LOCKED | _DRM_KERNEL, | |
732 | &dev_priv->status); | |
6795c985 | 733 | if (err) { |
7ccf800e | 734 | DRM_ERROR("Unable to map status region: %d\n", err); |
6795c985 DA |
735 | return err; |
736 | } | |
737 | ||
6795c985 DA |
738 | /* The DMA initialization procedure is slightly different for PCI and |
739 | * AGP cards. AGP cards just allocate a large block of AGP memory and | |
740 | * carve off portions of it for internal uses. The remaining memory | |
741 | * is returned to user-mode to be used for AGP textures. | |
742 | */ | |
6795c985 DA |
743 | if (is_agp) { |
744 | err = mga_do_agp_dma_bootstrap(dev, dma_bs); | |
745 | } | |
b5e89ed5 | 746 | |
6795c985 DA |
747 | /* If we attempted to initialize the card for AGP DMA but failed, |
748 | * clean-up any mess that may have been created. | |
749 | */ | |
750 | ||
751 | if (err) { | |
7ccf800e | 752 | mga_do_cleanup_dma(dev, MINIMAL_CLEANUP); |
6795c985 DA |
753 | } |
754 | ||
6795c985 DA |
755 | /* Not only do we want to try and initialized PCI cards for PCI DMA, |
756 | * but we also try to initialized AGP cards that could not be | |
757 | * initialized for AGP DMA. This covers the case where we have an AGP | |
758 | * card in a system with an unsupported AGP chipset. In that case the | |
759 | * card will be detected as AGP, but we won't be able to allocate any | |
760 | * AGP memory, etc. | |
761 | */ | |
762 | ||
763 | if (!is_agp || err) { | |
764 | err = mga_do_pci_dma_bootstrap(dev, dma_bs); | |
765 | } | |
766 | ||
6795c985 DA |
767 | return err; |
768 | } | |
769 | ||
c153f45f EA |
770 | int mga_dma_bootstrap(struct drm_device *dev, void *data, |
771 | struct drm_file *file_priv) | |
6795c985 | 772 | { |
c153f45f | 773 | drm_mga_dma_bootstrap_t *bootstrap = data; |
6795c985 | 774 | int err; |
7ccf800e DA |
775 | static const int modes[] = { 0, 1, 2, 2, 4, 4, 4, 4 }; |
776 | const drm_mga_private_t *const dev_priv = | |
777 | (drm_mga_private_t *) dev->dev_private; | |
6795c985 | 778 | |
c153f45f | 779 | err = mga_do_dma_bootstrap(dev, bootstrap); |
7ccf800e DA |
780 | if (err) { |
781 | mga_do_cleanup_dma(dev, FULL_CLEANUP); | |
782 | return err; | |
783 | } | |
6795c985 | 784 | |
7ccf800e | 785 | if (dev_priv->agp_textures != NULL) { |
c153f45f EA |
786 | bootstrap->texture_handle = dev_priv->agp_textures->offset; |
787 | bootstrap->texture_size = dev_priv->agp_textures->size; | |
b5e89ed5 | 788 | } else { |
c153f45f EA |
789 | bootstrap->texture_handle = 0; |
790 | bootstrap->texture_size = 0; | |
6795c985 DA |
791 | } |
792 | ||
c153f45f | 793 | bootstrap->agp_mode = modes[bootstrap->agp_mode & 0x07]; |
7ccf800e | 794 | |
6795c985 DA |
795 | return err; |
796 | } | |
797 | ||
eddca551 | 798 | static int mga_do_init_dma(struct drm_device * dev, drm_mga_init_t * init) |
1da177e4 LT |
799 | { |
800 | drm_mga_private_t *dev_priv; | |
801 | int ret; | |
b5e89ed5 | 802 | DRM_DEBUG("\n"); |
1da177e4 | 803 | |
6795c985 | 804 | dev_priv = dev->dev_private; |
1da177e4 | 805 | |
6795c985 | 806 | if (init->sgram) { |
1da177e4 LT |
807 | dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_BLK; |
808 | } else { | |
809 | dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_RSTR; | |
810 | } | |
b5e89ed5 | 811 | dev_priv->maccess = init->maccess; |
1da177e4 | 812 | |
b5e89ed5 DA |
813 | dev_priv->fb_cpp = init->fb_cpp; |
814 | dev_priv->front_offset = init->front_offset; | |
815 | dev_priv->front_pitch = init->front_pitch; | |
816 | dev_priv->back_offset = init->back_offset; | |
817 | dev_priv->back_pitch = init->back_pitch; | |
1da177e4 | 818 | |
b5e89ed5 DA |
819 | dev_priv->depth_cpp = init->depth_cpp; |
820 | dev_priv->depth_offset = init->depth_offset; | |
821 | dev_priv->depth_pitch = init->depth_pitch; | |
1da177e4 LT |
822 | |
823 | /* FIXME: Need to support AGP textures... | |
824 | */ | |
825 | dev_priv->texture_offset = init->texture_offset[0]; | |
826 | dev_priv->texture_size = init->texture_size[0]; | |
827 | ||
da509d7a | 828 | dev_priv->sarea = drm_getsarea(dev); |
6795c985 DA |
829 | if (!dev_priv->sarea) { |
830 | DRM_ERROR("failed to find sarea!\n"); | |
20caafa6 | 831 | return -EINVAL; |
1da177e4 LT |
832 | } |
833 | ||
b5e89ed5 | 834 | if (!dev_priv->used_new_dma_init) { |
11909d64 DA |
835 | |
836 | dev_priv->dma_access = MGA_PAGPXFER; | |
837 | dev_priv->wagp_enable = MGA_WAGP_ENABLE; | |
838 | ||
6795c985 DA |
839 | dev_priv->status = drm_core_findmap(dev, init->status_offset); |
840 | if (!dev_priv->status) { | |
841 | DRM_ERROR("failed to find status page!\n"); | |
20caafa6 | 842 | return -EINVAL; |
6795c985 DA |
843 | } |
844 | dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset); | |
845 | if (!dev_priv->mmio) { | |
846 | DRM_ERROR("failed to find mmio region!\n"); | |
20caafa6 | 847 | return -EINVAL; |
6795c985 DA |
848 | } |
849 | dev_priv->warp = drm_core_findmap(dev, init->warp_offset); | |
850 | if (!dev_priv->warp) { | |
851 | DRM_ERROR("failed to find warp microcode region!\n"); | |
20caafa6 | 852 | return -EINVAL; |
6795c985 DA |
853 | } |
854 | dev_priv->primary = drm_core_findmap(dev, init->primary_offset); | |
855 | if (!dev_priv->primary) { | |
856 | DRM_ERROR("failed to find primary dma region!\n"); | |
20caafa6 | 857 | return -EINVAL; |
6795c985 | 858 | } |
d1f2b55a | 859 | dev->agp_buffer_token = init->buffers_offset; |
b5e89ed5 DA |
860 | dev->agp_buffer_map = |
861 | drm_core_findmap(dev, init->buffers_offset); | |
6795c985 DA |
862 | if (!dev->agp_buffer_map) { |
863 | DRM_ERROR("failed to find dma buffer region!\n"); | |
20caafa6 | 864 | return -EINVAL; |
6795c985 DA |
865 | } |
866 | ||
867 | drm_core_ioremap(dev_priv->warp, dev); | |
868 | drm_core_ioremap(dev_priv->primary, dev); | |
869 | drm_core_ioremap(dev->agp_buffer_map, dev); | |
1da177e4 LT |
870 | } |
871 | ||
872 | dev_priv->sarea_priv = | |
b5e89ed5 DA |
873 | (drm_mga_sarea_t *) ((u8 *) dev_priv->sarea->handle + |
874 | init->sarea_priv_offset); | |
1da177e4 | 875 | |
6795c985 DA |
876 | if (!dev_priv->warp->handle || |
877 | !dev_priv->primary->handle || | |
878 | ((dev_priv->dma_access != 0) && | |
879 | ((dev->agp_buffer_map == NULL) || | |
880 | (dev->agp_buffer_map->handle == NULL)))) { | |
881 | DRM_ERROR("failed to ioremap agp regions!\n"); | |
20caafa6 | 882 | return -ENOMEM; |
1da177e4 LT |
883 | } |
884 | ||
6795c985 DA |
885 | ret = mga_warp_install_microcode(dev_priv); |
886 | if (ret < 0) { | |
7ccf800e | 887 | DRM_ERROR("failed to install WARP ucode!: %d\n", ret); |
1da177e4 LT |
888 | return ret; |
889 | } | |
890 | ||
6795c985 DA |
891 | ret = mga_warp_init(dev_priv); |
892 | if (ret < 0) { | |
7ccf800e | 893 | DRM_ERROR("failed to init WARP engine!: %d\n", ret); |
1da177e4 LT |
894 | return ret; |
895 | } | |
896 | ||
b5e89ed5 | 897 | dev_priv->prim.status = (u32 *) dev_priv->status->handle; |
1da177e4 | 898 | |
b5e89ed5 | 899 | mga_do_wait_for_idle(dev_priv); |
1da177e4 LT |
900 | |
901 | /* Init the primary DMA registers. | |
902 | */ | |
b5e89ed5 | 903 | MGA_WRITE(MGA_PRIMADDRESS, dev_priv->primary->offset | MGA_DMA_GENERAL); |
1da177e4 | 904 | #if 0 |
b5e89ed5 DA |
905 | MGA_WRITE(MGA_PRIMPTR, virt_to_bus((void *)dev_priv->prim.status) | MGA_PRIMPTREN0 | /* Soft trap, SECEND, SETUPEND */ |
906 | MGA_PRIMPTREN1); /* DWGSYNC */ | |
1da177e4 LT |
907 | #endif |
908 | ||
b5e89ed5 DA |
909 | dev_priv->prim.start = (u8 *) dev_priv->primary->handle; |
910 | dev_priv->prim.end = ((u8 *) dev_priv->primary->handle | |
1da177e4 LT |
911 | + dev_priv->primary->size); |
912 | dev_priv->prim.size = dev_priv->primary->size; | |
913 | ||
914 | dev_priv->prim.tail = 0; | |
915 | dev_priv->prim.space = dev_priv->prim.size; | |
916 | dev_priv->prim.wrapped = 0; | |
917 | ||
918 | dev_priv->prim.last_flush = 0; | |
919 | dev_priv->prim.last_wrap = 0; | |
920 | ||
921 | dev_priv->prim.high_mark = 256 * DMA_BLOCK_SIZE; | |
922 | ||
923 | dev_priv->prim.status[0] = dev_priv->primary->offset; | |
924 | dev_priv->prim.status[1] = 0; | |
925 | ||
926 | dev_priv->sarea_priv->last_wrap = 0; | |
927 | dev_priv->sarea_priv->last_frame.head = 0; | |
928 | dev_priv->sarea_priv->last_frame.wrap = 0; | |
929 | ||
6795c985 DA |
930 | if (mga_freelist_init(dev, dev_priv) < 0) { |
931 | DRM_ERROR("could not initialize freelist\n"); | |
20caafa6 | 932 | return -ENOMEM; |
1da177e4 LT |
933 | } |
934 | ||
1da177e4 LT |
935 | return 0; |
936 | } | |
937 | ||
eddca551 | 938 | static int mga_do_cleanup_dma(struct drm_device *dev, int full_cleanup) |
1da177e4 | 939 | { |
6795c985 DA |
940 | int err = 0; |
941 | DRM_DEBUG("\n"); | |
1da177e4 LT |
942 | |
943 | /* Make sure interrupts are disabled here because the uninstall ioctl | |
944 | * may not have been called from userspace and after dev_private | |
945 | * is freed, it's too late. | |
946 | */ | |
b5e89ed5 DA |
947 | if (dev->irq_enabled) |
948 | drm_irq_uninstall(dev); | |
1da177e4 | 949 | |
b5e89ed5 | 950 | if (dev->dev_private) { |
1da177e4 LT |
951 | drm_mga_private_t *dev_priv = dev->dev_private; |
952 | ||
b5e89ed5 | 953 | if ((dev_priv->warp != NULL) |
11909d64 | 954 | && (dev_priv->warp->type != _DRM_CONSISTENT)) |
6795c985 DA |
955 | drm_core_ioremapfree(dev_priv->warp, dev); |
956 | ||
b5e89ed5 | 957 | if ((dev_priv->primary != NULL) |
6795c985 DA |
958 | && (dev_priv->primary->type != _DRM_CONSISTENT)) |
959 | drm_core_ioremapfree(dev_priv->primary, dev); | |
1da177e4 | 960 | |
6795c985 DA |
961 | if (dev->agp_buffer_map != NULL) |
962 | drm_core_ioremapfree(dev->agp_buffer_map, dev); | |
963 | ||
964 | if (dev_priv->used_new_dma_init) { | |
908f9c48 | 965 | #if __OS_HAS_AGP |
7ccf800e | 966 | if (dev_priv->agp_handle != 0) { |
eddca551 DA |
967 | struct drm_agp_binding unbind_req; |
968 | struct drm_agp_buffer free_req; | |
6795c985 | 969 | |
7ccf800e DA |
970 | unbind_req.handle = dev_priv->agp_handle; |
971 | drm_agp_unbind(dev, &unbind_req); | |
972 | ||
973 | free_req.handle = dev_priv->agp_handle; | |
974 | drm_agp_free(dev, &free_req); | |
bc5f4523 | 975 | |
7ccf800e DA |
976 | dev_priv->agp_textures = NULL; |
977 | dev_priv->agp_size = 0; | |
978 | dev_priv->agp_handle = 0; | |
6795c985 DA |
979 | } |
980 | ||
981 | if ((dev->agp != NULL) && dev->agp->acquired) { | |
982 | err = drm_agp_release(dev); | |
983 | } | |
908f9c48 | 984 | #endif |
1da177e4 LT |
985 | } |
986 | ||
6795c985 DA |
987 | dev_priv->warp = NULL; |
988 | dev_priv->primary = NULL; | |
6795c985 DA |
989 | dev_priv->sarea = NULL; |
990 | dev_priv->sarea_priv = NULL; | |
991 | dev->agp_buffer_map = NULL; | |
992 | ||
7ccf800e DA |
993 | if (full_cleanup) { |
994 | dev_priv->mmio = NULL; | |
995 | dev_priv->status = NULL; | |
996 | dev_priv->used_new_dma_init = 0; | |
997 | } | |
998 | ||
6795c985 DA |
999 | memset(&dev_priv->prim, 0, sizeof(dev_priv->prim)); |
1000 | dev_priv->warp_pipe = 0; | |
b5e89ed5 DA |
1001 | memset(dev_priv->warp_pipe_phys, 0, |
1002 | sizeof(dev_priv->warp_pipe_phys)); | |
6795c985 DA |
1003 | |
1004 | if (dev_priv->head != NULL) { | |
1005 | mga_freelist_cleanup(dev); | |
1006 | } | |
1da177e4 LT |
1007 | } |
1008 | ||
a96ca105 | 1009 | return err; |
1da177e4 LT |
1010 | } |
1011 | ||
c153f45f EA |
1012 | int mga_dma_init(struct drm_device *dev, void *data, |
1013 | struct drm_file *file_priv) | |
1da177e4 | 1014 | { |
c153f45f | 1015 | drm_mga_init_t *init = data; |
6795c985 | 1016 | int err; |
1da177e4 | 1017 | |
6c340eac | 1018 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 1019 | |
c153f45f | 1020 | switch (init->func) { |
1da177e4 | 1021 | case MGA_INIT_DMA: |
c153f45f | 1022 | err = mga_do_init_dma(dev, init); |
6795c985 | 1023 | if (err) { |
7ccf800e | 1024 | (void)mga_do_cleanup_dma(dev, FULL_CLEANUP); |
6795c985 DA |
1025 | } |
1026 | return err; | |
1da177e4 | 1027 | case MGA_CLEANUP_DMA: |
7ccf800e | 1028 | return mga_do_cleanup_dma(dev, FULL_CLEANUP); |
1da177e4 LT |
1029 | } |
1030 | ||
20caafa6 | 1031 | return -EINVAL; |
1da177e4 LT |
1032 | } |
1033 | ||
1da177e4 LT |
1034 | /* ================================================================ |
1035 | * Primary DMA stream management | |
1036 | */ | |
1037 | ||
c153f45f EA |
1038 | int mga_dma_flush(struct drm_device *dev, void *data, |
1039 | struct drm_file *file_priv) | |
1da177e4 | 1040 | { |
b5e89ed5 | 1041 | drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; |
c153f45f | 1042 | struct drm_lock *lock = data; |
1da177e4 | 1043 | |
6c340eac | 1044 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 1045 | |
b5e89ed5 | 1046 | DRM_DEBUG("%s%s%s\n", |
c153f45f EA |
1047 | (lock->flags & _DRM_LOCK_FLUSH) ? "flush, " : "", |
1048 | (lock->flags & _DRM_LOCK_FLUSH_ALL) ? "flush all, " : "", | |
1049 | (lock->flags & _DRM_LOCK_QUIESCENT) ? "idle, " : ""); | |
1da177e4 | 1050 | |
b5e89ed5 | 1051 | WRAP_WAIT_WITH_RETURN(dev_priv); |
1da177e4 | 1052 | |
c153f45f | 1053 | if (lock->flags & (_DRM_LOCK_FLUSH | _DRM_LOCK_FLUSH_ALL)) { |
b5e89ed5 | 1054 | mga_do_dma_flush(dev_priv); |
1da177e4 LT |
1055 | } |
1056 | ||
c153f45f | 1057 | if (lock->flags & _DRM_LOCK_QUIESCENT) { |
1da177e4 | 1058 | #if MGA_DMA_DEBUG |
b5e89ed5 DA |
1059 | int ret = mga_do_wait_for_idle(dev_priv); |
1060 | if (ret < 0) | |
3e684eae | 1061 | DRM_INFO("-EBUSY\n"); |
1da177e4 LT |
1062 | return ret; |
1063 | #else | |
b5e89ed5 | 1064 | return mga_do_wait_for_idle(dev_priv); |
1da177e4 LT |
1065 | #endif |
1066 | } else { | |
1067 | return 0; | |
1068 | } | |
1069 | } | |
1070 | ||
c153f45f EA |
1071 | int mga_dma_reset(struct drm_device *dev, void *data, |
1072 | struct drm_file *file_priv) | |
1da177e4 | 1073 | { |
b5e89ed5 | 1074 | drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; |
1da177e4 | 1075 | |
6c340eac | 1076 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 1077 | |
b5e89ed5 | 1078 | return mga_do_dma_reset(dev_priv); |
1da177e4 LT |
1079 | } |
1080 | ||
1da177e4 LT |
1081 | /* ================================================================ |
1082 | * DMA buffer management | |
1083 | */ | |
1084 | ||
6c340eac EA |
1085 | static int mga_dma_get_buffers(struct drm_device * dev, |
1086 | struct drm_file *file_priv, struct drm_dma * d) | |
1da177e4 | 1087 | { |
056219e2 | 1088 | struct drm_buf *buf; |
1da177e4 LT |
1089 | int i; |
1090 | ||
b5e89ed5 DA |
1091 | for (i = d->granted_count; i < d->request_count; i++) { |
1092 | buf = mga_freelist_get(dev); | |
1093 | if (!buf) | |
20caafa6 | 1094 | return -EAGAIN; |
1da177e4 | 1095 | |
6c340eac | 1096 | buf->file_priv = file_priv; |
1da177e4 | 1097 | |
b5e89ed5 DA |
1098 | if (DRM_COPY_TO_USER(&d->request_indices[i], |
1099 | &buf->idx, sizeof(buf->idx))) | |
20caafa6 | 1100 | return -EFAULT; |
b5e89ed5 DA |
1101 | if (DRM_COPY_TO_USER(&d->request_sizes[i], |
1102 | &buf->total, sizeof(buf->total))) | |
20caafa6 | 1103 | return -EFAULT; |
1da177e4 LT |
1104 | |
1105 | d->granted_count++; | |
1106 | } | |
1107 | return 0; | |
1108 | } | |
1109 | ||
c153f45f EA |
1110 | int mga_dma_buffers(struct drm_device *dev, void *data, |
1111 | struct drm_file *file_priv) | |
1da177e4 | 1112 | { |
cdd55a29 | 1113 | struct drm_device_dma *dma = dev->dma; |
b5e89ed5 | 1114 | drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; |
c153f45f | 1115 | struct drm_dma *d = data; |
1da177e4 LT |
1116 | int ret = 0; |
1117 | ||
6c340eac | 1118 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 1119 | |
1da177e4 LT |
1120 | /* Please don't send us buffers. |
1121 | */ | |
c153f45f | 1122 | if (d->send_count != 0) { |
b5e89ed5 | 1123 | DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", |
c153f45f | 1124 | DRM_CURRENTPID, d->send_count); |
20caafa6 | 1125 | return -EINVAL; |
1da177e4 LT |
1126 | } |
1127 | ||
1128 | /* We'll send you buffers. | |
1129 | */ | |
c153f45f | 1130 | if (d->request_count < 0 || d->request_count > dma->buf_count) { |
b5e89ed5 | 1131 | DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", |
c153f45f | 1132 | DRM_CURRENTPID, d->request_count, dma->buf_count); |
20caafa6 | 1133 | return -EINVAL; |
1da177e4 LT |
1134 | } |
1135 | ||
b5e89ed5 | 1136 | WRAP_TEST_WITH_RETURN(dev_priv); |
1da177e4 | 1137 | |
c153f45f | 1138 | d->granted_count = 0; |
1da177e4 | 1139 | |
c153f45f EA |
1140 | if (d->request_count) { |
1141 | ret = mga_dma_get_buffers(dev, file_priv, d); | |
1da177e4 LT |
1142 | } |
1143 | ||
1da177e4 LT |
1144 | return ret; |
1145 | } | |
1146 | ||
6795c985 DA |
1147 | /** |
1148 | * Called just before the module is unloaded. | |
1149 | */ | |
eddca551 | 1150 | int mga_driver_unload(struct drm_device * dev) |
6795c985 DA |
1151 | { |
1152 | drm_free(dev->dev_private, sizeof(drm_mga_private_t), DRM_MEM_DRIVER); | |
1153 | dev->dev_private = NULL; | |
1154 | ||
1155 | return 0; | |
1156 | } | |
1157 | ||
1158 | /** | |
1159 | * Called when the last opener of the device is closed. | |
1160 | */ | |
eddca551 | 1161 | void mga_driver_lastclose(struct drm_device * dev) |
1da177e4 | 1162 | { |
7ccf800e | 1163 | mga_do_cleanup_dma(dev, FULL_CLEANUP); |
1da177e4 LT |
1164 | } |
1165 | ||
eddca551 | 1166 | int mga_driver_dma_quiescent(struct drm_device * dev) |
1da177e4 LT |
1167 | { |
1168 | drm_mga_private_t *dev_priv = dev->dev_private; | |
b5e89ed5 | 1169 | return mga_do_wait_for_idle(dev_priv); |
1da177e4 | 1170 | } |