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1da177e4 LT |
1 | /* mga_dma.c -- DMA support for mga g200/g400 -*- linux-c -*- |
2 | * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com | |
3 | * | |
4 | * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. | |
5 | * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. | |
6 | * All Rights Reserved. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the "Software"), | |
10 | * to deal in the Software without restriction, including without limitation | |
11 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
12 | * and/or sell copies of the Software, and to permit persons to whom the | |
13 | * Software is furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the next | |
16 | * paragraph) shall be included in all copies or substantial portions of the | |
17 | * Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
20 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
21 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
22 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
23 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
24 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
25 | * DEALINGS IN THE SOFTWARE. | |
6795c985 DA |
26 | */ |
27 | ||
07687193 | 28 | /* |
6795c985 DA |
29 | * \file mga_dma.c |
30 | * DMA support for MGA G200 / G400. | |
b5e89ed5 | 31 | * |
6795c985 DA |
32 | * \author Rickard E. (Rik) Faith <faith@valinux.com> |
33 | * \author Jeff Hartmann <jhartmann@valinux.com> | |
34 | * \author Keith Whitwell <keith@tungstengraphics.com> | |
35 | * \author Gareth Hughes <gareth@valinux.com> | |
1da177e4 LT |
36 | */ |
37 | ||
91f85e8f SR |
38 | #include <linux/delay.h> |
39 | ||
1da177e4 LT |
40 | #include "mga_drv.h" |
41 | ||
42 | #define MGA_DEFAULT_USEC_TIMEOUT 10000 | |
43 | #define MGA_FREELIST_DEBUG 0 | |
44 | ||
7ccf800e DA |
45 | #define MINIMAL_CLEANUP 0 |
46 | #define FULL_CLEANUP 1 | |
eddca551 | 47 | static int mga_do_cleanup_dma(struct drm_device *dev, int full_cleanup); |
1da177e4 LT |
48 | |
49 | /* ================================================================ | |
50 | * Engine control | |
51 | */ | |
52 | ||
f2b2cb79 | 53 | int mga_do_wait_for_idle(drm_mga_private_t *dev_priv) |
1da177e4 LT |
54 | { |
55 | u32 status = 0; | |
56 | int i; | |
b5e89ed5 | 57 | DRM_DEBUG("\n"); |
1da177e4 | 58 | |
b5e89ed5 DA |
59 | for (i = 0; i < dev_priv->usec_timeout; i++) { |
60 | status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK; | |
61 | if (status == MGA_ENDPRDMASTS) { | |
62 | MGA_WRITE8(MGA_CRTC_INDEX, 0); | |
1da177e4 LT |
63 | return 0; |
64 | } | |
91f85e8f | 65 | udelay(1); |
1da177e4 LT |
66 | } |
67 | ||
68 | #if MGA_DMA_DEBUG | |
b5e89ed5 DA |
69 | DRM_ERROR("failed!\n"); |
70 | DRM_INFO(" status=0x%08x\n", status); | |
1da177e4 | 71 | #endif |
20caafa6 | 72 | return -EBUSY; |
1da177e4 LT |
73 | } |
74 | ||
f2b2cb79 | 75 | static int mga_do_dma_reset(drm_mga_private_t *dev_priv) |
1da177e4 LT |
76 | { |
77 | drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; | |
78 | drm_mga_primary_buffer_t *primary = &dev_priv->prim; | |
79 | ||
b5e89ed5 | 80 | DRM_DEBUG("\n"); |
1da177e4 LT |
81 | |
82 | /* The primary DMA stream should look like new right about now. | |
83 | */ | |
84 | primary->tail = 0; | |
85 | primary->space = primary->size; | |
86 | primary->last_flush = 0; | |
87 | ||
88 | sarea_priv->last_wrap = 0; | |
89 | ||
90 | /* FIXME: Reset counters, buffer ages etc... | |
91 | */ | |
92 | ||
93 | /* FIXME: What else do we need to reinitialize? WARP stuff? | |
94 | */ | |
95 | ||
96 | return 0; | |
97 | } | |
98 | ||
99 | /* ================================================================ | |
100 | * Primary DMA stream | |
101 | */ | |
102 | ||
f2b2cb79 | 103 | void mga_do_dma_flush(drm_mga_private_t *dev_priv) |
1da177e4 LT |
104 | { |
105 | drm_mga_primary_buffer_t *primary = &dev_priv->prim; | |
106 | u32 head, tail; | |
107 | u32 status = 0; | |
108 | int i; | |
b5e89ed5 DA |
109 | DMA_LOCALS; |
110 | DRM_DEBUG("\n"); | |
111 | ||
112 | /* We need to wait so that we can do an safe flush */ | |
113 | for (i = 0; i < dev_priv->usec_timeout; i++) { | |
114 | status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK; | |
115 | if (status == MGA_ENDPRDMASTS) | |
116 | break; | |
91f85e8f | 117 | udelay(1); |
1da177e4 LT |
118 | } |
119 | ||
b5e89ed5 DA |
120 | if (primary->tail == primary->last_flush) { |
121 | DRM_DEBUG(" bailing out...\n"); | |
1da177e4 LT |
122 | return; |
123 | } | |
124 | ||
125 | tail = primary->tail + dev_priv->primary->offset; | |
126 | ||
127 | /* We need to pad the stream between flushes, as the card | |
128 | * actually (partially?) reads the first of these commands. | |
129 | * See page 4-16 in the G400 manual, middle of the page or so. | |
130 | */ | |
b5e89ed5 | 131 | BEGIN_DMA(1); |
1da177e4 | 132 | |
b5e89ed5 DA |
133 | DMA_BLOCK(MGA_DMAPAD, 0x00000000, |
134 | MGA_DMAPAD, 0x00000000, | |
135 | MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000); | |
1da177e4 LT |
136 | |
137 | ADVANCE_DMA(); | |
138 | ||
139 | primary->last_flush = primary->tail; | |
140 | ||
b5e89ed5 | 141 | head = MGA_READ(MGA_PRIMADDRESS); |
1da177e4 | 142 | |
f2b2cb79 | 143 | if (head <= tail) |
1da177e4 | 144 | primary->space = primary->size - primary->tail; |
f2b2cb79 | 145 | else |
1da177e4 | 146 | primary->space = head - tail; |
1da177e4 | 147 | |
41c2e75e BH |
148 | DRM_DEBUG(" head = 0x%06lx\n", (unsigned long)(head - dev_priv->primary->offset)); |
149 | DRM_DEBUG(" tail = 0x%06lx\n", (unsigned long)(tail - dev_priv->primary->offset)); | |
b5e89ed5 | 150 | DRM_DEBUG(" space = 0x%06x\n", primary->space); |
1da177e4 LT |
151 | |
152 | mga_flush_write_combine(); | |
6795c985 | 153 | MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access); |
1da177e4 | 154 | |
b5e89ed5 | 155 | DRM_DEBUG("done.\n"); |
1da177e4 LT |
156 | } |
157 | ||
f2b2cb79 | 158 | void mga_do_dma_wrap_start(drm_mga_private_t *dev_priv) |
1da177e4 LT |
159 | { |
160 | drm_mga_primary_buffer_t *primary = &dev_priv->prim; | |
161 | u32 head, tail; | |
162 | DMA_LOCALS; | |
b5e89ed5 | 163 | DRM_DEBUG("\n"); |
1da177e4 LT |
164 | |
165 | BEGIN_DMA_WRAP(); | |
166 | ||
b5e89ed5 DA |
167 | DMA_BLOCK(MGA_DMAPAD, 0x00000000, |
168 | MGA_DMAPAD, 0x00000000, | |
169 | MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000); | |
1da177e4 LT |
170 | |
171 | ADVANCE_DMA(); | |
172 | ||
173 | tail = primary->tail + dev_priv->primary->offset; | |
174 | ||
175 | primary->tail = 0; | |
176 | primary->last_flush = 0; | |
177 | primary->last_wrap++; | |
178 | ||
b5e89ed5 | 179 | head = MGA_READ(MGA_PRIMADDRESS); |
1da177e4 | 180 | |
f2b2cb79 | 181 | if (head == dev_priv->primary->offset) |
1da177e4 | 182 | primary->space = primary->size; |
f2b2cb79 | 183 | else |
1da177e4 | 184 | primary->space = head - dev_priv->primary->offset; |
1da177e4 | 185 | |
41c2e75e | 186 | DRM_DEBUG(" head = 0x%06lx\n", (unsigned long)(head - dev_priv->primary->offset)); |
b5e89ed5 DA |
187 | DRM_DEBUG(" tail = 0x%06x\n", primary->tail); |
188 | DRM_DEBUG(" wrap = %d\n", primary->last_wrap); | |
189 | DRM_DEBUG(" space = 0x%06x\n", primary->space); | |
1da177e4 LT |
190 | |
191 | mga_flush_write_combine(); | |
6795c985 | 192 | MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access); |
1da177e4 | 193 | |
b5e89ed5 DA |
194 | set_bit(0, &primary->wrapped); |
195 | DRM_DEBUG("done.\n"); | |
1da177e4 LT |
196 | } |
197 | ||
f2b2cb79 | 198 | void mga_do_dma_wrap_end(drm_mga_private_t *dev_priv) |
1da177e4 LT |
199 | { |
200 | drm_mga_primary_buffer_t *primary = &dev_priv->prim; | |
201 | drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; | |
202 | u32 head = dev_priv->primary->offset; | |
b5e89ed5 | 203 | DRM_DEBUG("\n"); |
1da177e4 LT |
204 | |
205 | sarea_priv->last_wrap++; | |
b5e89ed5 | 206 | DRM_DEBUG(" wrap = %d\n", sarea_priv->last_wrap); |
1da177e4 LT |
207 | |
208 | mga_flush_write_combine(); | |
b5e89ed5 | 209 | MGA_WRITE(MGA_PRIMADDRESS, head | MGA_DMA_GENERAL); |
1da177e4 | 210 | |
b5e89ed5 DA |
211 | clear_bit(0, &primary->wrapped); |
212 | DRM_DEBUG("done.\n"); | |
1da177e4 LT |
213 | } |
214 | ||
1da177e4 LT |
215 | /* ================================================================ |
216 | * Freelist management | |
217 | */ | |
218 | ||
f2b2cb79 | 219 | #define MGA_BUFFER_USED (~0) |
1da177e4 LT |
220 | #define MGA_BUFFER_FREE 0 |
221 | ||
222 | #if MGA_FREELIST_DEBUG | |
f2b2cb79 | 223 | static void mga_freelist_print(struct drm_device *dev) |
1da177e4 LT |
224 | { |
225 | drm_mga_private_t *dev_priv = dev->dev_private; | |
226 | drm_mga_freelist_t *entry; | |
227 | ||
b5e89ed5 DA |
228 | DRM_INFO("\n"); |
229 | DRM_INFO("current dispatch: last=0x%x done=0x%x\n", | |
230 | dev_priv->sarea_priv->last_dispatch, | |
231 | (unsigned int)(MGA_READ(MGA_PRIMADDRESS) - | |
232 | dev_priv->primary->offset)); | |
233 | DRM_INFO("current freelist:\n"); | |
234 | ||
235 | for (entry = dev_priv->head->next; entry; entry = entry->next) { | |
236 | DRM_INFO(" %p idx=%2d age=0x%x 0x%06lx\n", | |
237 | entry, entry->buf->idx, entry->age.head, | |
41c2e75e | 238 | (unsigned long)(entry->age.head - dev_priv->primary->offset)); |
1da177e4 | 239 | } |
b5e89ed5 | 240 | DRM_INFO("\n"); |
1da177e4 LT |
241 | } |
242 | #endif | |
243 | ||
f2b2cb79 | 244 | static int mga_freelist_init(struct drm_device *dev, drm_mga_private_t *dev_priv) |
1da177e4 | 245 | { |
cdd55a29 | 246 | struct drm_device_dma *dma = dev->dma; |
056219e2 | 247 | struct drm_buf *buf; |
1da177e4 LT |
248 | drm_mga_buf_priv_t *buf_priv; |
249 | drm_mga_freelist_t *entry; | |
250 | int i; | |
b5e89ed5 | 251 | DRM_DEBUG("count=%d\n", dma->buf_count); |
1da177e4 | 252 | |
9a298b2a | 253 | dev_priv->head = kzalloc(sizeof(drm_mga_freelist_t), GFP_KERNEL); |
b5e89ed5 | 254 | if (dev_priv->head == NULL) |
20caafa6 | 255 | return -ENOMEM; |
1da177e4 | 256 | |
b5e89ed5 | 257 | SET_AGE(&dev_priv->head->age, MGA_BUFFER_USED, 0); |
1da177e4 | 258 | |
b5e89ed5 | 259 | for (i = 0; i < dma->buf_count; i++) { |
1da177e4 | 260 | buf = dma->buflist[i]; |
b5e89ed5 | 261 | buf_priv = buf->dev_private; |
1da177e4 | 262 | |
9a298b2a | 263 | entry = kzalloc(sizeof(drm_mga_freelist_t), GFP_KERNEL); |
b5e89ed5 | 264 | if (entry == NULL) |
20caafa6 | 265 | return -ENOMEM; |
1da177e4 | 266 | |
1da177e4 LT |
267 | entry->next = dev_priv->head->next; |
268 | entry->prev = dev_priv->head; | |
b5e89ed5 | 269 | SET_AGE(&entry->age, MGA_BUFFER_FREE, 0); |
1da177e4 LT |
270 | entry->buf = buf; |
271 | ||
b5e89ed5 | 272 | if (dev_priv->head->next != NULL) |
1da177e4 | 273 | dev_priv->head->next->prev = entry; |
b5e89ed5 | 274 | if (entry->next == NULL) |
1da177e4 LT |
275 | dev_priv->tail = entry; |
276 | ||
277 | buf_priv->list_entry = entry; | |
278 | buf_priv->discard = 0; | |
279 | buf_priv->dispatched = 0; | |
280 | ||
281 | dev_priv->head->next = entry; | |
282 | } | |
283 | ||
284 | return 0; | |
285 | } | |
286 | ||
f2b2cb79 | 287 | static void mga_freelist_cleanup(struct drm_device *dev) |
1da177e4 LT |
288 | { |
289 | drm_mga_private_t *dev_priv = dev->dev_private; | |
290 | drm_mga_freelist_t *entry; | |
291 | drm_mga_freelist_t *next; | |
b5e89ed5 | 292 | DRM_DEBUG("\n"); |
1da177e4 LT |
293 | |
294 | entry = dev_priv->head; | |
b5e89ed5 | 295 | while (entry) { |
1da177e4 | 296 | next = entry->next; |
9a298b2a | 297 | kfree(entry); |
1da177e4 LT |
298 | entry = next; |
299 | } | |
300 | ||
301 | dev_priv->head = dev_priv->tail = NULL; | |
302 | } | |
303 | ||
304 | #if 0 | |
305 | /* FIXME: Still needed? | |
306 | */ | |
f2b2cb79 | 307 | static void mga_freelist_reset(struct drm_device *dev) |
1da177e4 | 308 | { |
cdd55a29 | 309 | struct drm_device_dma *dma = dev->dma; |
056219e2 | 310 | struct drm_buf *buf; |
1da177e4 LT |
311 | drm_mga_buf_priv_t *buf_priv; |
312 | int i; | |
313 | ||
b5e89ed5 | 314 | for (i = 0; i < dma->buf_count; i++) { |
1da177e4 | 315 | buf = dma->buflist[i]; |
b5e89ed5 DA |
316 | buf_priv = buf->dev_private; |
317 | SET_AGE(&buf_priv->list_entry->age, MGA_BUFFER_FREE, 0); | |
1da177e4 LT |
318 | } |
319 | } | |
320 | #endif | |
321 | ||
056219e2 | 322 | static struct drm_buf *mga_freelist_get(struct drm_device * dev) |
1da177e4 LT |
323 | { |
324 | drm_mga_private_t *dev_priv = dev->dev_private; | |
325 | drm_mga_freelist_t *next; | |
326 | drm_mga_freelist_t *prev; | |
327 | drm_mga_freelist_t *tail = dev_priv->tail; | |
328 | u32 head, wrap; | |
b5e89ed5 | 329 | DRM_DEBUG("\n"); |
1da177e4 | 330 | |
b5e89ed5 | 331 | head = MGA_READ(MGA_PRIMADDRESS); |
1da177e4 LT |
332 | wrap = dev_priv->sarea_priv->last_wrap; |
333 | ||
b5e89ed5 DA |
334 | DRM_DEBUG(" tail=0x%06lx %d\n", |
335 | tail->age.head ? | |
41c2e75e | 336 | (unsigned long)(tail->age.head - dev_priv->primary->offset) : 0, |
b5e89ed5 DA |
337 | tail->age.wrap); |
338 | DRM_DEBUG(" head=0x%06lx %d\n", | |
41c2e75e | 339 | (unsigned long)(head - dev_priv->primary->offset), wrap); |
1da177e4 | 340 | |
b5e89ed5 | 341 | if (TEST_AGE(&tail->age, head, wrap)) { |
1da177e4 LT |
342 | prev = dev_priv->tail->prev; |
343 | next = dev_priv->tail; | |
344 | prev->next = NULL; | |
345 | next->prev = next->next = NULL; | |
346 | dev_priv->tail = prev; | |
b5e89ed5 | 347 | SET_AGE(&next->age, MGA_BUFFER_USED, 0); |
1da177e4 LT |
348 | return next->buf; |
349 | } | |
350 | ||
b5e89ed5 | 351 | DRM_DEBUG("returning NULL!\n"); |
1da177e4 LT |
352 | return NULL; |
353 | } | |
354 | ||
f2b2cb79 | 355 | int mga_freelist_put(struct drm_device *dev, struct drm_buf *buf) |
1da177e4 LT |
356 | { |
357 | drm_mga_private_t *dev_priv = dev->dev_private; | |
358 | drm_mga_buf_priv_t *buf_priv = buf->dev_private; | |
359 | drm_mga_freelist_t *head, *entry, *prev; | |
360 | ||
b5e89ed5 | 361 | DRM_DEBUG("age=0x%06lx wrap=%d\n", |
41c2e75e BH |
362 | (unsigned long)(buf_priv->list_entry->age.head - |
363 | dev_priv->primary->offset), | |
364 | buf_priv->list_entry->age.wrap); | |
1da177e4 LT |
365 | |
366 | entry = buf_priv->list_entry; | |
367 | head = dev_priv->head; | |
368 | ||
b5e89ed5 DA |
369 | if (buf_priv->list_entry->age.head == MGA_BUFFER_USED) { |
370 | SET_AGE(&entry->age, MGA_BUFFER_FREE, 0); | |
1da177e4 LT |
371 | prev = dev_priv->tail; |
372 | prev->next = entry; | |
373 | entry->prev = prev; | |
374 | entry->next = NULL; | |
375 | } else { | |
376 | prev = head->next; | |
377 | head->next = entry; | |
378 | prev->prev = entry; | |
379 | entry->prev = head; | |
380 | entry->next = prev; | |
381 | } | |
382 | ||
383 | return 0; | |
384 | } | |
385 | ||
1da177e4 LT |
386 | /* ================================================================ |
387 | * DMA initialization, cleanup | |
388 | */ | |
389 | ||
f2b2cb79 | 390 | int mga_driver_load(struct drm_device *dev, unsigned long flags) |
6795c985 | 391 | { |
b5e89ed5 | 392 | drm_mga_private_t *dev_priv; |
52440211 | 393 | int ret; |
6795c985 | 394 | |
858b2c1b DV |
395 | /* There are PCI versions of the G450. These cards have the |
396 | * same PCI ID as the AGP G450, but have an additional PCI-to-PCI | |
397 | * bridge chip. We detect these cards, which are not currently | |
398 | * supported by this driver, by looking at the device ID of the | |
399 | * bus the "card" is on. If vendor is 0x3388 (Hint Corp) and the | |
400 | * device is 0x0021 (HB6 Universal PCI-PCI bridge), we reject the | |
401 | * device. | |
402 | */ | |
403 | if ((dev->pdev->device == 0x0525) && dev->pdev->bus->self | |
404 | && (dev->pdev->bus->self->vendor == 0x3388) | |
405 | && (dev->pdev->bus->self->device == 0x0021) | |
406 | && dev->agp) { | |
407 | /* FIXME: This should be quirked in the pci core, but oh well | |
408 | * the hw probably stopped existing. */ | |
409 | arch_phys_wc_del(dev->agp->agp_mtrr); | |
410 | kfree(dev->agp); | |
411 | dev->agp = NULL; | |
412 | } | |
9a298b2a | 413 | dev_priv = kzalloc(sizeof(drm_mga_private_t), GFP_KERNEL); |
6795c985 | 414 | if (!dev_priv) |
20caafa6 | 415 | return -ENOMEM; |
6795c985 DA |
416 | |
417 | dev->dev_private = (void *)dev_priv; | |
6795c985 DA |
418 | |
419 | dev_priv->usec_timeout = MGA_DEFAULT_USEC_TIMEOUT; | |
420 | dev_priv->chipset = flags; | |
421 | ||
466e69b8 DA |
422 | pci_set_master(dev->pdev); |
423 | ||
01d73a69 JC |
424 | dev_priv->mmio_base = pci_resource_start(dev->pdev, 1); |
425 | dev_priv->mmio_size = pci_resource_len(dev->pdev, 1); | |
22eae947 | 426 | |
52440211 KP |
427 | ret = drm_vblank_init(dev, 1); |
428 | ||
429 | if (ret) { | |
430 | (void) mga_driver_unload(dev); | |
431 | return ret; | |
432 | } | |
433 | ||
6795c985 DA |
434 | return 0; |
435 | } | |
436 | ||
a7fb8a23 | 437 | #if IS_ENABLED(CONFIG_AGP) |
07687193 | 438 | /* |
6795c985 | 439 | * Bootstrap the driver for AGP DMA. |
b5e89ed5 | 440 | * |
6795c985 | 441 | * \todo |
25985edc | 442 | * Investigate whether there is any benefit to storing the WARP microcode in |
6795c985 DA |
443 | * AGP memory. If not, the microcode may as well always be put in PCI |
444 | * memory. | |
445 | * | |
446 | * \todo | |
447 | * This routine needs to set dma_bs->agp_mode to the mode actually configured | |
448 | * in the hardware. Looking just at the Linux AGP driver code, I don't see | |
449 | * an easy way to determine this. | |
450 | * | |
451 | * \sa mga_do_dma_bootstrap, mga_do_pci_dma_bootstrap | |
452 | */ | |
f2b2cb79 NK |
453 | static int mga_do_agp_dma_bootstrap(struct drm_device *dev, |
454 | drm_mga_dma_bootstrap_t *dma_bs) | |
6795c985 | 455 | { |
b5e89ed5 DA |
456 | drm_mga_private_t *const dev_priv = |
457 | (drm_mga_private_t *) dev->dev_private; | |
ece2be79 | 458 | unsigned int warp_size = MGA_WARP_UCODE_SIZE; |
6795c985 | 459 | int err; |
b5e89ed5 | 460 | unsigned offset; |
6795c985 | 461 | const unsigned secondary_size = dma_bs->secondary_bin_count |
b5e89ed5 | 462 | * dma_bs->secondary_bin_size; |
6795c985 | 463 | const unsigned agp_size = (dma_bs->agp_size << 20); |
eddca551 DA |
464 | struct drm_buf_desc req; |
465 | struct drm_agp_mode mode; | |
466 | struct drm_agp_info info; | |
467 | struct drm_agp_buffer agp_req; | |
468 | struct drm_agp_binding bind_req; | |
6795c985 | 469 | |
6795c985 DA |
470 | /* Acquire AGP. */ |
471 | err = drm_agp_acquire(dev); | |
472 | if (err) { | |
7ccf800e | 473 | DRM_ERROR("Unable to acquire AGP: %d\n", err); |
6795c985 DA |
474 | return err; |
475 | } | |
476 | ||
477 | err = drm_agp_info(dev, &info); | |
478 | if (err) { | |
7ccf800e | 479 | DRM_ERROR("Unable to get AGP info: %d\n", err); |
6795c985 DA |
480 | return err; |
481 | } | |
482 | ||
483 | mode.mode = (info.mode & ~0x07) | dma_bs->agp_mode; | |
484 | err = drm_agp_enable(dev, mode); | |
485 | if (err) { | |
486 | DRM_ERROR("Unable to enable AGP (mode = 0x%lx)\n", mode.mode); | |
487 | return err; | |
488 | } | |
489 | ||
6795c985 DA |
490 | /* In addition to the usual AGP mode configuration, the G200 AGP cards |
491 | * need to have the AGP mode "manually" set. | |
492 | */ | |
493 | ||
494 | if (dev_priv->chipset == MGA_CARD_TYPE_G200) { | |
f2b2cb79 | 495 | if (mode.mode & 0x02) |
6795c985 | 496 | MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_ENABLE); |
f2b2cb79 | 497 | else |
6795c985 | 498 | MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_DISABLE); |
6795c985 DA |
499 | } |
500 | ||
6795c985 | 501 | /* Allocate and bind AGP memory. */ |
7ccf800e DA |
502 | agp_req.size = agp_size; |
503 | agp_req.type = 0; | |
504 | err = drm_agp_alloc(dev, &agp_req); | |
505 | if (err) { | |
506 | dev_priv->agp_size = 0; | |
6795c985 DA |
507 | DRM_ERROR("Unable to allocate %uMB AGP memory\n", |
508 | dma_bs->agp_size); | |
7ccf800e | 509 | return err; |
6795c985 | 510 | } |
bc5f4523 | 511 | |
7ccf800e DA |
512 | dev_priv->agp_size = agp_size; |
513 | dev_priv->agp_handle = agp_req.handle; | |
b5e89ed5 | 514 | |
7ccf800e DA |
515 | bind_req.handle = agp_req.handle; |
516 | bind_req.offset = 0; | |
517 | err = drm_agp_bind(dev, &bind_req); | |
6795c985 | 518 | if (err) { |
7ccf800e | 519 | DRM_ERROR("Unable to bind AGP memory: %d\n", err); |
6795c985 DA |
520 | return err; |
521 | } | |
522 | ||
9fc5cde7 DH |
523 | /* Make drm_legacy_addbufs happy by not trying to create a mapping for |
524 | * less than a page. | |
11909d64 DA |
525 | */ |
526 | if (warp_size < PAGE_SIZE) | |
527 | warp_size = PAGE_SIZE; | |
528 | ||
6795c985 | 529 | offset = 0; |
9fc5cde7 DH |
530 | err = drm_legacy_addmap(dev, offset, warp_size, |
531 | _DRM_AGP, _DRM_READ_ONLY, &dev_priv->warp); | |
6795c985 | 532 | if (err) { |
7ccf800e | 533 | DRM_ERROR("Unable to map WARP microcode: %d\n", err); |
6795c985 DA |
534 | return err; |
535 | } | |
536 | ||
537 | offset += warp_size; | |
9fc5cde7 DH |
538 | err = drm_legacy_addmap(dev, offset, dma_bs->primary_size, |
539 | _DRM_AGP, _DRM_READ_ONLY, &dev_priv->primary); | |
6795c985 | 540 | if (err) { |
7ccf800e | 541 | DRM_ERROR("Unable to map primary DMA region: %d\n", err); |
6795c985 DA |
542 | return err; |
543 | } | |
544 | ||
545 | offset += dma_bs->primary_size; | |
9fc5cde7 DH |
546 | err = drm_legacy_addmap(dev, offset, secondary_size, |
547 | _DRM_AGP, 0, &dev->agp_buffer_map); | |
6795c985 | 548 | if (err) { |
7ccf800e | 549 | DRM_ERROR("Unable to map secondary DMA region: %d\n", err); |
6795c985 DA |
550 | return err; |
551 | } | |
552 | ||
b5e89ed5 | 553 | (void)memset(&req, 0, sizeof(req)); |
6795c985 DA |
554 | req.count = dma_bs->secondary_bin_count; |
555 | req.size = dma_bs->secondary_bin_size; | |
556 | req.flags = _DRM_AGP_BUFFER; | |
557 | req.agp_start = offset; | |
558 | ||
9fc5cde7 | 559 | err = drm_legacy_addbufs_agp(dev, &req); |
6795c985 | 560 | if (err) { |
7ccf800e | 561 | DRM_ERROR("Unable to add secondary DMA buffers: %d\n", err); |
6795c985 DA |
562 | return err; |
563 | } | |
564 | ||
7ccf800e | 565 | { |
55910517 | 566 | struct drm_map_list *_entry; |
7ccf800e | 567 | unsigned long agp_token = 0; |
bc5f4523 | 568 | |
bd1b331f | 569 | list_for_each_entry(_entry, &dev->maplist, head) { |
7ccf800e DA |
570 | if (_entry->map == dev->agp_buffer_map) |
571 | agp_token = _entry->user_token; | |
572 | } | |
573 | if (!agp_token) | |
574 | return -EFAULT; | |
575 | ||
576 | dev->agp_buffer_token = agp_token; | |
577 | } | |
578 | ||
6795c985 | 579 | offset += secondary_size; |
9fc5cde7 DH |
580 | err = drm_legacy_addmap(dev, offset, agp_size - offset, |
581 | _DRM_AGP, 0, &dev_priv->agp_textures); | |
6795c985 | 582 | if (err) { |
7ccf800e | 583 | DRM_ERROR("Unable to map AGP texture region %d\n", err); |
6795c985 DA |
584 | return err; |
585 | } | |
586 | ||
86c1fbd5 DV |
587 | drm_legacy_ioremap(dev_priv->warp, dev); |
588 | drm_legacy_ioremap(dev_priv->primary, dev); | |
589 | drm_legacy_ioremap(dev->agp_buffer_map, dev); | |
6795c985 DA |
590 | |
591 | if (!dev_priv->warp->handle || | |
592 | !dev_priv->primary->handle || !dev->agp_buffer_map->handle) { | |
593 | DRM_ERROR("failed to ioremap agp regions! (%p, %p, %p)\n", | |
594 | dev_priv->warp->handle, dev_priv->primary->handle, | |
595 | dev->agp_buffer_map->handle); | |
20caafa6 | 596 | return -ENOMEM; |
6795c985 DA |
597 | } |
598 | ||
599 | dev_priv->dma_access = MGA_PAGPXFER; | |
600 | dev_priv->wagp_enable = MGA_WAGP_ENABLE; | |
601 | ||
602 | DRM_INFO("Initialized card for AGP DMA.\n"); | |
603 | return 0; | |
604 | } | |
908f9c48 | 605 | #else |
f2b2cb79 NK |
606 | static int mga_do_agp_dma_bootstrap(struct drm_device *dev, |
607 | drm_mga_dma_bootstrap_t *dma_bs) | |
908f9c48 DA |
608 | { |
609 | return -EINVAL; | |
610 | } | |
611 | #endif | |
6795c985 | 612 | |
07687193 | 613 | /* |
6795c985 | 614 | * Bootstrap the driver for PCI DMA. |
b5e89ed5 | 615 | * |
6795c985 DA |
616 | * \todo |
617 | * The algorithm for decreasing the size of the primary DMA buffer could be | |
618 | * better. The size should be rounded up to the nearest page size, then | |
619 | * decrease the request size by a single page each pass through the loop. | |
620 | * | |
621 | * \todo | |
622 | * Determine whether the maximum address passed to drm_pci_alloc is correct. | |
9fc5cde7 | 623 | * The same goes for drm_legacy_addbufs_pci. |
b5e89ed5 | 624 | * |
6795c985 DA |
625 | * \sa mga_do_dma_bootstrap, mga_do_agp_dma_bootstrap |
626 | */ | |
f2b2cb79 NK |
627 | static int mga_do_pci_dma_bootstrap(struct drm_device *dev, |
628 | drm_mga_dma_bootstrap_t *dma_bs) | |
6795c985 | 629 | { |
b5e89ed5 DA |
630 | drm_mga_private_t *const dev_priv = |
631 | (drm_mga_private_t *) dev->dev_private; | |
ece2be79 | 632 | unsigned int warp_size = MGA_WARP_UCODE_SIZE; |
6795c985 DA |
633 | unsigned int primary_size; |
634 | unsigned int bin_count; | |
635 | int err; | |
eddca551 | 636 | struct drm_buf_desc req; |
6795c985 | 637 | |
6795c985 DA |
638 | if (dev->dma == NULL) { |
639 | DRM_ERROR("dev->dma is NULL\n"); | |
20caafa6 | 640 | return -EFAULT; |
6795c985 DA |
641 | } |
642 | ||
9fc5cde7 DH |
643 | /* Make drm_legacy_addbufs happy by not trying to create a mapping for |
644 | * less than a page. | |
11909d64 DA |
645 | */ |
646 | if (warp_size < PAGE_SIZE) | |
647 | warp_size = PAGE_SIZE; | |
648 | ||
6795c985 | 649 | /* The proper alignment is 0x100 for this mapping */ |
9fc5cde7 DH |
650 | err = drm_legacy_addmap(dev, 0, warp_size, _DRM_CONSISTENT, |
651 | _DRM_READ_ONLY, &dev_priv->warp); | |
6795c985 | 652 | if (err != 0) { |
7ccf800e DA |
653 | DRM_ERROR("Unable to create mapping for WARP microcode: %d\n", |
654 | err); | |
6795c985 DA |
655 | return err; |
656 | } | |
657 | ||
658 | /* Other than the bottom two bits being used to encode other | |
659 | * information, there don't appear to be any restrictions on the | |
660 | * alignment of the primary or secondary DMA buffers. | |
661 | */ | |
662 | ||
b5e89ed5 DA |
663 | for (primary_size = dma_bs->primary_size; primary_size != 0; |
664 | primary_size >>= 1) { | |
6795c985 | 665 | /* The proper alignment for this mapping is 0x04 */ |
9fc5cde7 DH |
666 | err = drm_legacy_addmap(dev, 0, primary_size, _DRM_CONSISTENT, |
667 | _DRM_READ_ONLY, &dev_priv->primary); | |
6795c985 DA |
668 | if (!err) |
669 | break; | |
670 | } | |
671 | ||
672 | if (err != 0) { | |
7ccf800e | 673 | DRM_ERROR("Unable to allocate primary DMA region: %d\n", err); |
20caafa6 | 674 | return -ENOMEM; |
6795c985 DA |
675 | } |
676 | ||
677 | if (dev_priv->primary->size != dma_bs->primary_size) { | |
678 | DRM_INFO("Primary DMA buffer size reduced from %u to %u.\n", | |
b5e89ed5 DA |
679 | dma_bs->primary_size, |
680 | (unsigned)dev_priv->primary->size); | |
6795c985 DA |
681 | dma_bs->primary_size = dev_priv->primary->size; |
682 | } | |
683 | ||
b5e89ed5 DA |
684 | for (bin_count = dma_bs->secondary_bin_count; bin_count > 0; |
685 | bin_count--) { | |
686 | (void)memset(&req, 0, sizeof(req)); | |
6795c985 DA |
687 | req.count = bin_count; |
688 | req.size = dma_bs->secondary_bin_size; | |
689 | ||
9fc5cde7 | 690 | err = drm_legacy_addbufs_pci(dev, &req); |
f2b2cb79 | 691 | if (!err) |
6795c985 | 692 | break; |
6795c985 | 693 | } |
b5e89ed5 | 694 | |
6795c985 | 695 | if (bin_count == 0) { |
7ccf800e | 696 | DRM_ERROR("Unable to add secondary DMA buffers: %d\n", err); |
6795c985 DA |
697 | return err; |
698 | } | |
699 | ||
700 | if (bin_count != dma_bs->secondary_bin_count) { | |
701 | DRM_INFO("Secondary PCI DMA buffer bin count reduced from %u " | |
702 | "to %u.\n", dma_bs->secondary_bin_count, bin_count); | |
703 | ||
704 | dma_bs->secondary_bin_count = bin_count; | |
705 | } | |
706 | ||
707 | dev_priv->dma_access = 0; | |
708 | dev_priv->wagp_enable = 0; | |
709 | ||
710 | dma_bs->agp_mode = 0; | |
711 | ||
712 | DRM_INFO("Initialized card for PCI DMA.\n"); | |
713 | return 0; | |
714 | } | |
715 | ||
f2b2cb79 NK |
716 | static int mga_do_dma_bootstrap(struct drm_device *dev, |
717 | drm_mga_dma_bootstrap_t *dma_bs) | |
6795c985 | 718 | { |
858b2c1b | 719 | const int is_agp = (dma_bs->agp_mode != 0) && dev->agp; |
6795c985 | 720 | int err; |
b5e89ed5 DA |
721 | drm_mga_private_t *const dev_priv = |
722 | (drm_mga_private_t *) dev->dev_private; | |
6795c985 DA |
723 | |
724 | dev_priv->used_new_dma_init = 1; | |
725 | ||
726 | /* The first steps are the same for both PCI and AGP based DMA. Map | |
727 | * the cards MMIO registers and map a status page. | |
728 | */ | |
9fc5cde7 DH |
729 | err = drm_legacy_addmap(dev, dev_priv->mmio_base, dev_priv->mmio_size, |
730 | _DRM_REGISTERS, _DRM_READ_ONLY, | |
731 | &dev_priv->mmio); | |
6795c985 | 732 | if (err) { |
7ccf800e | 733 | DRM_ERROR("Unable to map MMIO region: %d\n", err); |
6795c985 DA |
734 | return err; |
735 | } | |
736 | ||
9fc5cde7 DH |
737 | err = drm_legacy_addmap(dev, 0, SAREA_MAX, _DRM_SHM, |
738 | _DRM_READ_ONLY | _DRM_LOCKED | _DRM_KERNEL, | |
b5e89ed5 | 739 | &dev_priv->status); |
6795c985 | 740 | if (err) { |
7ccf800e | 741 | DRM_ERROR("Unable to map status region: %d\n", err); |
6795c985 DA |
742 | return err; |
743 | } | |
744 | ||
6795c985 DA |
745 | /* The DMA initialization procedure is slightly different for PCI and |
746 | * AGP cards. AGP cards just allocate a large block of AGP memory and | |
747 | * carve off portions of it for internal uses. The remaining memory | |
748 | * is returned to user-mode to be used for AGP textures. | |
749 | */ | |
f2b2cb79 | 750 | if (is_agp) |
6795c985 | 751 | err = mga_do_agp_dma_bootstrap(dev, dma_bs); |
b5e89ed5 | 752 | |
6795c985 DA |
753 | /* If we attempted to initialize the card for AGP DMA but failed, |
754 | * clean-up any mess that may have been created. | |
755 | */ | |
756 | ||
f2b2cb79 | 757 | if (err) |
7ccf800e | 758 | mga_do_cleanup_dma(dev, MINIMAL_CLEANUP); |
6795c985 | 759 | |
6795c985 DA |
760 | /* Not only do we want to try and initialized PCI cards for PCI DMA, |
761 | * but we also try to initialized AGP cards that could not be | |
762 | * initialized for AGP DMA. This covers the case where we have an AGP | |
763 | * card in a system with an unsupported AGP chipset. In that case the | |
764 | * card will be detected as AGP, but we won't be able to allocate any | |
765 | * AGP memory, etc. | |
766 | */ | |
767 | ||
f2b2cb79 | 768 | if (!is_agp || err) |
6795c985 | 769 | err = mga_do_pci_dma_bootstrap(dev, dma_bs); |
6795c985 | 770 | |
6795c985 DA |
771 | return err; |
772 | } | |
773 | ||
c153f45f EA |
774 | int mga_dma_bootstrap(struct drm_device *dev, void *data, |
775 | struct drm_file *file_priv) | |
6795c985 | 776 | { |
c153f45f | 777 | drm_mga_dma_bootstrap_t *bootstrap = data; |
6795c985 | 778 | int err; |
7ccf800e DA |
779 | static const int modes[] = { 0, 1, 2, 2, 4, 4, 4, 4 }; |
780 | const drm_mga_private_t *const dev_priv = | |
781 | (drm_mga_private_t *) dev->dev_private; | |
6795c985 | 782 | |
c153f45f | 783 | err = mga_do_dma_bootstrap(dev, bootstrap); |
7ccf800e DA |
784 | if (err) { |
785 | mga_do_cleanup_dma(dev, FULL_CLEANUP); | |
786 | return err; | |
787 | } | |
6795c985 | 788 | |
7ccf800e | 789 | if (dev_priv->agp_textures != NULL) { |
c153f45f EA |
790 | bootstrap->texture_handle = dev_priv->agp_textures->offset; |
791 | bootstrap->texture_size = dev_priv->agp_textures->size; | |
b5e89ed5 | 792 | } else { |
c153f45f EA |
793 | bootstrap->texture_handle = 0; |
794 | bootstrap->texture_size = 0; | |
6795c985 DA |
795 | } |
796 | ||
c153f45f | 797 | bootstrap->agp_mode = modes[bootstrap->agp_mode & 0x07]; |
7ccf800e | 798 | |
6795c985 DA |
799 | return err; |
800 | } | |
801 | ||
f2b2cb79 | 802 | static int mga_do_init_dma(struct drm_device *dev, drm_mga_init_t *init) |
1da177e4 LT |
803 | { |
804 | drm_mga_private_t *dev_priv; | |
805 | int ret; | |
b5e89ed5 | 806 | DRM_DEBUG("\n"); |
1da177e4 | 807 | |
6795c985 | 808 | dev_priv = dev->dev_private; |
1da177e4 | 809 | |
f2b2cb79 | 810 | if (init->sgram) |
1da177e4 | 811 | dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_BLK; |
f2b2cb79 | 812 | else |
1da177e4 | 813 | dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_RSTR; |
b5e89ed5 | 814 | dev_priv->maccess = init->maccess; |
1da177e4 | 815 | |
b5e89ed5 DA |
816 | dev_priv->fb_cpp = init->fb_cpp; |
817 | dev_priv->front_offset = init->front_offset; | |
818 | dev_priv->front_pitch = init->front_pitch; | |
819 | dev_priv->back_offset = init->back_offset; | |
820 | dev_priv->back_pitch = init->back_pitch; | |
1da177e4 | 821 | |
b5e89ed5 DA |
822 | dev_priv->depth_cpp = init->depth_cpp; |
823 | dev_priv->depth_offset = init->depth_offset; | |
824 | dev_priv->depth_pitch = init->depth_pitch; | |
1da177e4 LT |
825 | |
826 | /* FIXME: Need to support AGP textures... | |
827 | */ | |
828 | dev_priv->texture_offset = init->texture_offset[0]; | |
829 | dev_priv->texture_size = init->texture_size[0]; | |
830 | ||
9fc5cde7 | 831 | dev_priv->sarea = drm_legacy_getsarea(dev); |
6795c985 DA |
832 | if (!dev_priv->sarea) { |
833 | DRM_ERROR("failed to find sarea!\n"); | |
20caafa6 | 834 | return -EINVAL; |
1da177e4 LT |
835 | } |
836 | ||
b5e89ed5 | 837 | if (!dev_priv->used_new_dma_init) { |
11909d64 DA |
838 | |
839 | dev_priv->dma_access = MGA_PAGPXFER; | |
840 | dev_priv->wagp_enable = MGA_WAGP_ENABLE; | |
841 | ||
86c1fbd5 | 842 | dev_priv->status = drm_legacy_findmap(dev, init->status_offset); |
6795c985 DA |
843 | if (!dev_priv->status) { |
844 | DRM_ERROR("failed to find status page!\n"); | |
20caafa6 | 845 | return -EINVAL; |
6795c985 | 846 | } |
86c1fbd5 | 847 | dev_priv->mmio = drm_legacy_findmap(dev, init->mmio_offset); |
6795c985 DA |
848 | if (!dev_priv->mmio) { |
849 | DRM_ERROR("failed to find mmio region!\n"); | |
20caafa6 | 850 | return -EINVAL; |
6795c985 | 851 | } |
86c1fbd5 | 852 | dev_priv->warp = drm_legacy_findmap(dev, init->warp_offset); |
6795c985 DA |
853 | if (!dev_priv->warp) { |
854 | DRM_ERROR("failed to find warp microcode region!\n"); | |
20caafa6 | 855 | return -EINVAL; |
6795c985 | 856 | } |
86c1fbd5 | 857 | dev_priv->primary = drm_legacy_findmap(dev, init->primary_offset); |
6795c985 DA |
858 | if (!dev_priv->primary) { |
859 | DRM_ERROR("failed to find primary dma region!\n"); | |
20caafa6 | 860 | return -EINVAL; |
6795c985 | 861 | } |
d1f2b55a | 862 | dev->agp_buffer_token = init->buffers_offset; |
b5e89ed5 | 863 | dev->agp_buffer_map = |
86c1fbd5 | 864 | drm_legacy_findmap(dev, init->buffers_offset); |
6795c985 DA |
865 | if (!dev->agp_buffer_map) { |
866 | DRM_ERROR("failed to find dma buffer region!\n"); | |
20caafa6 | 867 | return -EINVAL; |
6795c985 DA |
868 | } |
869 | ||
86c1fbd5 DV |
870 | drm_legacy_ioremap(dev_priv->warp, dev); |
871 | drm_legacy_ioremap(dev_priv->primary, dev); | |
872 | drm_legacy_ioremap(dev->agp_buffer_map, dev); | |
1da177e4 LT |
873 | } |
874 | ||
875 | dev_priv->sarea_priv = | |
b5e89ed5 DA |
876 | (drm_mga_sarea_t *) ((u8 *) dev_priv->sarea->handle + |
877 | init->sarea_priv_offset); | |
1da177e4 | 878 | |
6795c985 DA |
879 | if (!dev_priv->warp->handle || |
880 | !dev_priv->primary->handle || | |
881 | ((dev_priv->dma_access != 0) && | |
882 | ((dev->agp_buffer_map == NULL) || | |
883 | (dev->agp_buffer_map->handle == NULL)))) { | |
884 | DRM_ERROR("failed to ioremap agp regions!\n"); | |
20caafa6 | 885 | return -ENOMEM; |
1da177e4 LT |
886 | } |
887 | ||
6795c985 DA |
888 | ret = mga_warp_install_microcode(dev_priv); |
889 | if (ret < 0) { | |
7ccf800e | 890 | DRM_ERROR("failed to install WARP ucode!: %d\n", ret); |
1da177e4 LT |
891 | return ret; |
892 | } | |
893 | ||
6795c985 DA |
894 | ret = mga_warp_init(dev_priv); |
895 | if (ret < 0) { | |
7ccf800e | 896 | DRM_ERROR("failed to init WARP engine!: %d\n", ret); |
1da177e4 LT |
897 | return ret; |
898 | } | |
899 | ||
b5e89ed5 | 900 | dev_priv->prim.status = (u32 *) dev_priv->status->handle; |
1da177e4 | 901 | |
b5e89ed5 | 902 | mga_do_wait_for_idle(dev_priv); |
1da177e4 LT |
903 | |
904 | /* Init the primary DMA registers. | |
905 | */ | |
b5e89ed5 | 906 | MGA_WRITE(MGA_PRIMADDRESS, dev_priv->primary->offset | MGA_DMA_GENERAL); |
1da177e4 | 907 | #if 0 |
b5e89ed5 DA |
908 | MGA_WRITE(MGA_PRIMPTR, virt_to_bus((void *)dev_priv->prim.status) | MGA_PRIMPTREN0 | /* Soft trap, SECEND, SETUPEND */ |
909 | MGA_PRIMPTREN1); /* DWGSYNC */ | |
1da177e4 LT |
910 | #endif |
911 | ||
b5e89ed5 DA |
912 | dev_priv->prim.start = (u8 *) dev_priv->primary->handle; |
913 | dev_priv->prim.end = ((u8 *) dev_priv->primary->handle | |
1da177e4 LT |
914 | + dev_priv->primary->size); |
915 | dev_priv->prim.size = dev_priv->primary->size; | |
916 | ||
917 | dev_priv->prim.tail = 0; | |
918 | dev_priv->prim.space = dev_priv->prim.size; | |
919 | dev_priv->prim.wrapped = 0; | |
920 | ||
921 | dev_priv->prim.last_flush = 0; | |
922 | dev_priv->prim.last_wrap = 0; | |
923 | ||
924 | dev_priv->prim.high_mark = 256 * DMA_BLOCK_SIZE; | |
925 | ||
926 | dev_priv->prim.status[0] = dev_priv->primary->offset; | |
927 | dev_priv->prim.status[1] = 0; | |
928 | ||
929 | dev_priv->sarea_priv->last_wrap = 0; | |
930 | dev_priv->sarea_priv->last_frame.head = 0; | |
931 | dev_priv->sarea_priv->last_frame.wrap = 0; | |
932 | ||
6795c985 DA |
933 | if (mga_freelist_init(dev, dev_priv) < 0) { |
934 | DRM_ERROR("could not initialize freelist\n"); | |
20caafa6 | 935 | return -ENOMEM; |
1da177e4 LT |
936 | } |
937 | ||
1da177e4 LT |
938 | return 0; |
939 | } | |
940 | ||
eddca551 | 941 | static int mga_do_cleanup_dma(struct drm_device *dev, int full_cleanup) |
1da177e4 | 942 | { |
6795c985 DA |
943 | int err = 0; |
944 | DRM_DEBUG("\n"); | |
1da177e4 LT |
945 | |
946 | /* Make sure interrupts are disabled here because the uninstall ioctl | |
947 | * may not have been called from userspace and after dev_private | |
948 | * is freed, it's too late. | |
949 | */ | |
b5e89ed5 DA |
950 | if (dev->irq_enabled) |
951 | drm_irq_uninstall(dev); | |
1da177e4 | 952 | |
b5e89ed5 | 953 | if (dev->dev_private) { |
1da177e4 LT |
954 | drm_mga_private_t *dev_priv = dev->dev_private; |
955 | ||
b5e89ed5 | 956 | if ((dev_priv->warp != NULL) |
11909d64 | 957 | && (dev_priv->warp->type != _DRM_CONSISTENT)) |
86c1fbd5 | 958 | drm_legacy_ioremapfree(dev_priv->warp, dev); |
6795c985 | 959 | |
b5e89ed5 | 960 | if ((dev_priv->primary != NULL) |
6795c985 | 961 | && (dev_priv->primary->type != _DRM_CONSISTENT)) |
86c1fbd5 | 962 | drm_legacy_ioremapfree(dev_priv->primary, dev); |
1da177e4 | 963 | |
6795c985 | 964 | if (dev->agp_buffer_map != NULL) |
86c1fbd5 | 965 | drm_legacy_ioremapfree(dev->agp_buffer_map, dev); |
6795c985 DA |
966 | |
967 | if (dev_priv->used_new_dma_init) { | |
a7fb8a23 | 968 | #if IS_ENABLED(CONFIG_AGP) |
7ccf800e | 969 | if (dev_priv->agp_handle != 0) { |
eddca551 DA |
970 | struct drm_agp_binding unbind_req; |
971 | struct drm_agp_buffer free_req; | |
6795c985 | 972 | |
7ccf800e DA |
973 | unbind_req.handle = dev_priv->agp_handle; |
974 | drm_agp_unbind(dev, &unbind_req); | |
975 | ||
976 | free_req.handle = dev_priv->agp_handle; | |
977 | drm_agp_free(dev, &free_req); | |
bc5f4523 | 978 | |
7ccf800e DA |
979 | dev_priv->agp_textures = NULL; |
980 | dev_priv->agp_size = 0; | |
981 | dev_priv->agp_handle = 0; | |
6795c985 DA |
982 | } |
983 | ||
f2b2cb79 | 984 | if ((dev->agp != NULL) && dev->agp->acquired) |
6795c985 | 985 | err = drm_agp_release(dev); |
908f9c48 | 986 | #endif |
1da177e4 LT |
987 | } |
988 | ||
6795c985 DA |
989 | dev_priv->warp = NULL; |
990 | dev_priv->primary = NULL; | |
6795c985 DA |
991 | dev_priv->sarea = NULL; |
992 | dev_priv->sarea_priv = NULL; | |
993 | dev->agp_buffer_map = NULL; | |
994 | ||
7ccf800e DA |
995 | if (full_cleanup) { |
996 | dev_priv->mmio = NULL; | |
997 | dev_priv->status = NULL; | |
998 | dev_priv->used_new_dma_init = 0; | |
999 | } | |
1000 | ||
6795c985 DA |
1001 | memset(&dev_priv->prim, 0, sizeof(dev_priv->prim)); |
1002 | dev_priv->warp_pipe = 0; | |
b5e89ed5 DA |
1003 | memset(dev_priv->warp_pipe_phys, 0, |
1004 | sizeof(dev_priv->warp_pipe_phys)); | |
6795c985 | 1005 | |
f2b2cb79 | 1006 | if (dev_priv->head != NULL) |
6795c985 | 1007 | mga_freelist_cleanup(dev); |
1da177e4 LT |
1008 | } |
1009 | ||
a96ca105 | 1010 | return err; |
1da177e4 LT |
1011 | } |
1012 | ||
c153f45f EA |
1013 | int mga_dma_init(struct drm_device *dev, void *data, |
1014 | struct drm_file *file_priv) | |
1da177e4 | 1015 | { |
c153f45f | 1016 | drm_mga_init_t *init = data; |
6795c985 | 1017 | int err; |
1da177e4 | 1018 | |
6c340eac | 1019 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 1020 | |
c153f45f | 1021 | switch (init->func) { |
1da177e4 | 1022 | case MGA_INIT_DMA: |
c153f45f | 1023 | err = mga_do_init_dma(dev, init); |
f2b2cb79 | 1024 | if (err) |
7ccf800e | 1025 | (void)mga_do_cleanup_dma(dev, FULL_CLEANUP); |
6795c985 | 1026 | return err; |
1da177e4 | 1027 | case MGA_CLEANUP_DMA: |
7ccf800e | 1028 | return mga_do_cleanup_dma(dev, FULL_CLEANUP); |
1da177e4 LT |
1029 | } |
1030 | ||
20caafa6 | 1031 | return -EINVAL; |
1da177e4 LT |
1032 | } |
1033 | ||
1da177e4 LT |
1034 | /* ================================================================ |
1035 | * Primary DMA stream management | |
1036 | */ | |
1037 | ||
c153f45f EA |
1038 | int mga_dma_flush(struct drm_device *dev, void *data, |
1039 | struct drm_file *file_priv) | |
1da177e4 | 1040 | { |
b5e89ed5 | 1041 | drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; |
c153f45f | 1042 | struct drm_lock *lock = data; |
1da177e4 | 1043 | |
6c340eac | 1044 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 1045 | |
b5e89ed5 | 1046 | DRM_DEBUG("%s%s%s\n", |
c153f45f EA |
1047 | (lock->flags & _DRM_LOCK_FLUSH) ? "flush, " : "", |
1048 | (lock->flags & _DRM_LOCK_FLUSH_ALL) ? "flush all, " : "", | |
1049 | (lock->flags & _DRM_LOCK_QUIESCENT) ? "idle, " : ""); | |
1da177e4 | 1050 | |
b5e89ed5 | 1051 | WRAP_WAIT_WITH_RETURN(dev_priv); |
1da177e4 | 1052 | |
f2b2cb79 | 1053 | if (lock->flags & (_DRM_LOCK_FLUSH | _DRM_LOCK_FLUSH_ALL)) |
b5e89ed5 | 1054 | mga_do_dma_flush(dev_priv); |
1da177e4 | 1055 | |
c153f45f | 1056 | if (lock->flags & _DRM_LOCK_QUIESCENT) { |
1da177e4 | 1057 | #if MGA_DMA_DEBUG |
b5e89ed5 DA |
1058 | int ret = mga_do_wait_for_idle(dev_priv); |
1059 | if (ret < 0) | |
3e684eae | 1060 | DRM_INFO("-EBUSY\n"); |
1da177e4 LT |
1061 | return ret; |
1062 | #else | |
b5e89ed5 | 1063 | return mga_do_wait_for_idle(dev_priv); |
1da177e4 LT |
1064 | #endif |
1065 | } else { | |
1066 | return 0; | |
1067 | } | |
1068 | } | |
1069 | ||
c153f45f EA |
1070 | int mga_dma_reset(struct drm_device *dev, void *data, |
1071 | struct drm_file *file_priv) | |
1da177e4 | 1072 | { |
b5e89ed5 | 1073 | drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; |
1da177e4 | 1074 | |
6c340eac | 1075 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 1076 | |
b5e89ed5 | 1077 | return mga_do_dma_reset(dev_priv); |
1da177e4 LT |
1078 | } |
1079 | ||
1da177e4 LT |
1080 | /* ================================================================ |
1081 | * DMA buffer management | |
1082 | */ | |
1083 | ||
f2b2cb79 NK |
1084 | static int mga_dma_get_buffers(struct drm_device *dev, |
1085 | struct drm_file *file_priv, struct drm_dma *d) | |
1da177e4 | 1086 | { |
056219e2 | 1087 | struct drm_buf *buf; |
1da177e4 LT |
1088 | int i; |
1089 | ||
b5e89ed5 DA |
1090 | for (i = d->granted_count; i < d->request_count; i++) { |
1091 | buf = mga_freelist_get(dev); | |
1092 | if (!buf) | |
20caafa6 | 1093 | return -EAGAIN; |
1da177e4 | 1094 | |
6c340eac | 1095 | buf->file_priv = file_priv; |
1da177e4 | 1096 | |
1d6ac185 | 1097 | if (copy_to_user(&d->request_indices[i], |
b5e89ed5 | 1098 | &buf->idx, sizeof(buf->idx))) |
20caafa6 | 1099 | return -EFAULT; |
1d6ac185 | 1100 | if (copy_to_user(&d->request_sizes[i], |
b5e89ed5 | 1101 | &buf->total, sizeof(buf->total))) |
20caafa6 | 1102 | return -EFAULT; |
1da177e4 LT |
1103 | |
1104 | d->granted_count++; | |
1105 | } | |
1106 | return 0; | |
1107 | } | |
1108 | ||
c153f45f EA |
1109 | int mga_dma_buffers(struct drm_device *dev, void *data, |
1110 | struct drm_file *file_priv) | |
1da177e4 | 1111 | { |
cdd55a29 | 1112 | struct drm_device_dma *dma = dev->dma; |
b5e89ed5 | 1113 | drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; |
c153f45f | 1114 | struct drm_dma *d = data; |
1da177e4 LT |
1115 | int ret = 0; |
1116 | ||
6c340eac | 1117 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 1118 | |
1da177e4 LT |
1119 | /* Please don't send us buffers. |
1120 | */ | |
c153f45f | 1121 | if (d->send_count != 0) { |
b5e89ed5 | 1122 | DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", |
91f85e8f | 1123 | task_pid_nr(current), d->send_count); |
20caafa6 | 1124 | return -EINVAL; |
1da177e4 LT |
1125 | } |
1126 | ||
1127 | /* We'll send you buffers. | |
1128 | */ | |
c153f45f | 1129 | if (d->request_count < 0 || d->request_count > dma->buf_count) { |
b5e89ed5 | 1130 | DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", |
91f85e8f SR |
1131 | task_pid_nr(current), d->request_count, |
1132 | dma->buf_count); | |
20caafa6 | 1133 | return -EINVAL; |
1da177e4 LT |
1134 | } |
1135 | ||
b5e89ed5 | 1136 | WRAP_TEST_WITH_RETURN(dev_priv); |
1da177e4 | 1137 | |
c153f45f | 1138 | d->granted_count = 0; |
1da177e4 | 1139 | |
f2b2cb79 | 1140 | if (d->request_count) |
c153f45f | 1141 | ret = mga_dma_get_buffers(dev, file_priv, d); |
1da177e4 | 1142 | |
1da177e4 LT |
1143 | return ret; |
1144 | } | |
1145 | ||
07687193 | 1146 | /* |
6795c985 DA |
1147 | * Called just before the module is unloaded. |
1148 | */ | |
11b3c20b | 1149 | void mga_driver_unload(struct drm_device *dev) |
6795c985 | 1150 | { |
9a298b2a | 1151 | kfree(dev->dev_private); |
6795c985 | 1152 | dev->dev_private = NULL; |
6795c985 DA |
1153 | } |
1154 | ||
07687193 | 1155 | /* |
6795c985 DA |
1156 | * Called when the last opener of the device is closed. |
1157 | */ | |
f2b2cb79 | 1158 | void mga_driver_lastclose(struct drm_device *dev) |
1da177e4 | 1159 | { |
7ccf800e | 1160 | mga_do_cleanup_dma(dev, FULL_CLEANUP); |
1da177e4 LT |
1161 | } |
1162 | ||
f2b2cb79 | 1163 | int mga_driver_dma_quiescent(struct drm_device *dev) |
1da177e4 LT |
1164 | { |
1165 | drm_mga_private_t *dev_priv = dev->dev_private; | |
b5e89ed5 | 1166 | return mga_do_wait_for_idle(dev_priv); |
1da177e4 | 1167 | } |