Merge tag 'pci-v6.16-fixes-3' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
[linux-block.git] / drivers / gpu / drm / meson / meson_drv.c
CommitLineData
1ccea77e 1// SPDX-License-Identifier: GPL-2.0-or-later
bbbe775e
NA
2/*
3 * Copyright (C) 2016 BayLibre, SAS
4 * Author: Neil Armstrong <narmstrong@baylibre.com>
5 * Copyright (C) 2014 Endless Mobile
6 *
bbbe775e
NA
7 * Written by:
8 * Jasper St. Pierre <jstpierre@mecheye.net>
9 */
10
736db966 11#include <linux/aperture.h>
a41e82e6 12#include <linux/component.h>
66620f48 13#include <linux/module.h>
bbbe775e 14#include <linux/of_graph.h>
8976eeee 15#include <linux/sys_soc.h>
66620f48
SR
16#include <linux/platform_device.h>
17#include <linux/soc/amlogic/meson-canvas.h>
bbbe775e 18
b86711c6 19#include <drm/clients/drm_client_setup.h>
bbbe775e 20#include <drm/drm_atomic_helper.h>
66620f48 21#include <drm/drm_drv.h>
8a9d46f4 22#include <drm/drm_fbdev_dma.h>
4a83c26a 23#include <drm/drm_gem_dma_helper.h>
24ef8157 24#include <drm/drm_gem_framebuffer_helper.h>
66620f48 25#include <drm/drm_modeset_helper_vtables.h>
a9b19b0d 26#include <drm/drm_module.h>
fcd70cd3 27#include <drm/drm_probe_helper.h>
66620f48 28#include <drm/drm_vblank.h>
bbbe775e 29
66620f48 30#include "meson_crtc.h"
bbbe775e 31#include "meson_drv.h"
f9a23481 32#include "meson_overlay.h"
66620f48 33#include "meson_plane.h"
d1b5e41e 34#include "meson_osd_afbcd.h"
66620f48 35#include "meson_registers.h"
72317eaa 36#include "meson_encoder_cvbs.h"
e67f6037 37#include "meson_encoder_hdmi.h"
42dcf15f 38#include "meson_encoder_dsi.h"
bbbe775e 39#include "meson_viu.h"
66620f48 40#include "meson_vpp.h"
d1b5e41e 41#include "meson_rdma.h"
bbbe775e
NA
42
43#define DRIVER_NAME "meson"
44#define DRIVER_DESC "Amlogic Meson DRM driver"
45
2021d5b7
NA
46/**
47 * DOC: Video Processing Unit
bbbe775e
NA
48 *
49 * VPU Handles the Global Video Processing, it includes management of the
50 * clocks gates, blocks reset lines and power domains.
51 *
52 * What is missing :
2021d5b7 53 *
bbbe775e
NA
54 * - Full reset of entire video processing HW blocks
55 * - Scaling and setup of the VPU clock
56 * - Bus clock gates
57 * - Powering up video processing HW blocks
58 * - Powering Up HDMI controller and PHY
59 */
60
bbbe775e 61static const struct drm_mode_config_funcs meson_mode_config_funcs = {
bbbe775e
NA
62 .atomic_check = drm_atomic_helper_check,
63 .atomic_commit = drm_atomic_helper_commit,
24ef8157 64 .fb_create = drm_gem_fb_create,
bbbe775e
NA
65};
66
ce0210c1
NA
67static const struct drm_mode_config_helper_funcs meson_mode_config_helpers = {
68 .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
69};
70
bbbe775e
NA
71static irqreturn_t meson_irq(int irq, void *arg)
72{
73 struct drm_device *dev = arg;
74 struct meson_drm *priv = dev->dev_private;
75
76 (void)readl_relaxed(priv->io_base + _REG(VENC_INTFLAG));
77
78 meson_crtc_irq(priv);
79
80 return IRQ_HANDLED;
81}
82
852ce728
NA
83static int meson_dumb_create(struct drm_file *file, struct drm_device *dev,
84 struct drm_mode_create_dumb *args)
85{
86 /*
87 * We need 64bytes aligned stride, and PAGE aligned size
88 */
89 args->pitch = ALIGN(DIV_ROUND_UP(args->width * args->bpp, 8), SZ_64);
90 args->size = PAGE_ALIGN(args->pitch * args->height);
91
4a83c26a 92 return drm_gem_dma_dumb_create_internal(file, dev, args);
852ce728
NA
93}
94
4a83c26a 95DEFINE_DRM_GEM_DMA_FOPS(fops);
bbbe775e 96
70a59dd8 97static const struct drm_driver meson_driver = {
0424fdaf 98 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
bbbe775e 99
4a83c26a
DK
100 /* DMA Ops */
101 DRM_GEM_DMA_DRIVER_OPS_WITH_DUMB_CREATE(meson_dumb_create),
57a03512 102 DRM_FBDEV_DMA_DRIVER_OPS,
bbbe775e
NA
103
104 /* Misc */
105 .fops = &fops,
106 .name = DRIVER_NAME,
107 .desc = DRIVER_DESC,
bbbe775e
NA
108 .major = 1,
109 .minor = 0,
110};
111
112static bool meson_vpu_has_available_connectors(struct device *dev)
113{
114 struct device_node *ep, *remote;
115
116 /* Parses each endpoint and check if remote exists */
117 for_each_endpoint_of_node(dev->of_node, ep) {
118 /* If the endpoint node exists, consider it enabled */
119 remote = of_graph_get_remote_port(ep);
91b3c8db
LH
120 if (remote) {
121 of_node_put(remote);
122 of_node_put(ep);
bbbe775e 123 return true;
91b3c8db 124 }
bbbe775e
NA
125 }
126
127 return false;
128}
129
0bcbddb7 130static const struct regmap_config meson_regmap_config = {
bbbe775e
NA
131 .reg_bits = 32,
132 .val_bits = 32,
133 .reg_stride = 4,
134 .max_register = 0x1000,
135};
136
09762525
NA
137static void meson_vpu_init(struct meson_drm *priv)
138{
bfb86819
JM
139 u32 value;
140
141 /*
142 * Slave dc0 and dc5 connected to master port 1.
143 * By default other slaves are connected to master port 0.
144 */
145 value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1) |
146 VPU_RDARB_SLAVE_TO_MASTER_PORT(5, 1);
147 writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C1));
148
149 /* Slave dc0 connected to master port 1 */
150 value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1);
151 writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C2));
152
153 /* Slave dc4 and dc7 connected to master port 1 */
154 value = VPU_RDARB_SLAVE_TO_MASTER_PORT(4, 1) |
155 VPU_RDARB_SLAVE_TO_MASTER_PORT(7, 1);
156 writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L2C1));
157
158 /* Slave dc1 connected to master port 1 */
159 value = VPU_RDARB_SLAVE_TO_MASTER_PORT(1, 1);
160 writel_relaxed(value, priv->io_base + _REG(VPU_WRARB_MODE_L2C1));
09762525
NA
161}
162
8976eeee
NA
163struct meson_drm_soc_attr {
164 struct meson_drm_soc_limits limits;
165 const struct soc_device_attribute *attrs;
166};
167
168static const struct meson_drm_soc_attr meson_drm_soc_attrs[] = {
169 /* S805X/S805Y HDMI PLL won't lock for HDMI PHY freq > 1,65GHz */
170 {
171 .limits = {
10175601 172 .max_hdmi_phy_freq = 1650000000,
8976eeee
NA
173 },
174 .attrs = (const struct soc_device_attribute []) {
175 { .soc_id = "GXL (S805*)", },
f6e68388 176 { /* sentinel */ }
8976eeee
NA
177 }
178 },
179};
180
8604889f 181static int meson_drv_bind_master(struct device *dev, bool has_components)
bbbe775e 182{
a41e82e6 183 struct platform_device *pdev = to_platform_device(dev);
d1b5e41e 184 const struct meson_drm_match_data *match;
bbbe775e
NA
185 struct meson_drm *priv;
186 struct drm_device *drm;
187 struct resource *res;
188 void __iomem *regs;
8976eeee 189 int ret, i;
bbbe775e
NA
190
191 /* Checks if an output connector is available */
192 if (!meson_vpu_has_available_connectors(dev)) {
193 dev_err(dev, "No output connector available\n");
194 return -ENODEV;
195 }
196
d1b5e41e
NA
197 match = of_device_get_match_data(dev);
198 if (!match)
199 return -ENODEV;
200
bbbe775e
NA
201 drm = drm_dev_alloc(&meson_driver, dev);
202 if (IS_ERR(drm))
203 return PTR_ERR(drm);
204
205 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
206 if (!priv) {
207 ret = -ENOMEM;
208 goto free_drm;
209 }
210 drm->dev_private = priv;
211 priv->drm = drm;
212 priv->dev = dev;
d1b5e41e
NA
213 priv->compat = match->compat;
214 priv->afbcd.ops = match->afbcd_ops;
528a25d0 215
d4cb82aa 216 regs = devm_platform_ioremap_resource_byname(pdev, "vpu");
2c18107b
CJ
217 if (IS_ERR(regs)) {
218 ret = PTR_ERR(regs);
219 goto free_drm;
220 }
bbbe775e
NA
221
222 priv->io_base = regs;
223
224 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hhi");
01a9e949
CJ
225 if (!res) {
226 ret = -EINVAL;
227 goto free_drm;
228 }
bbbe775e
NA
229 /* Simply ioremap since it may be a shared register zone */
230 regs = devm_ioremap(dev, res->start, resource_size(res));
2c18107b
CJ
231 if (!regs) {
232 ret = -EADDRNOTAVAIL;
233 goto free_drm;
234 }
bbbe775e
NA
235
236 priv->hhi = devm_regmap_init_mmio(dev, regs,
237 &meson_regmap_config);
238 if (IS_ERR(priv->hhi)) {
239 dev_err(&pdev->dev, "Couldn't create the HHI regmap\n");
2c18107b
CJ
240 ret = PTR_ERR(priv->hhi);
241 goto free_drm;
bbbe775e
NA
242 }
243
66cae477 244 priv->canvas = meson_canvas_get(dev);
2bf6b5b0
MJ
245 if (IS_ERR(priv->canvas)) {
246 ret = PTR_ERR(priv->canvas);
247 goto free_drm;
248 }
249
250 ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_osd1);
251 if (ret)
252 goto free_drm;
253 ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_0);
a695949b
YZ
254 if (ret)
255 goto free_canvas_osd1;
2bf6b5b0 256 ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_1);
a695949b
YZ
257 if (ret)
258 goto free_canvas_vd1_0;
2bf6b5b0 259 ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_2);
a695949b
YZ
260 if (ret)
261 goto free_canvas_vd1_1;
bbbe775e
NA
262
263 priv->vsync_irq = platform_get_irq(pdev, 0);
264
e770f6bf
CJ
265 ret = drm_vblank_init(drm, 1);
266 if (ret)
a695949b 267 goto free_canvas_vd1_2;
e770f6bf 268
8976eeee
NA
269 /* Assign limits per soc revision/package */
270 for (i = 0 ; i < ARRAY_SIZE(meson_drm_soc_attrs) ; ++i) {
271 if (soc_device_match(meson_drm_soc_attrs[i].attrs)) {
272 priv->limits = &meson_drm_soc_attrs[i].limits;
273 break;
274 }
275 }
276
6848c291
TZ
277 /*
278 * Remove early framebuffers (ie. simplefb). The framebuffer can be
279 * located anywhere in RAM
280 */
736db966 281 ret = aperture_remove_all_conflicting_devices(meson_driver.name);
6848c291 282 if (ret)
a695949b 283 goto free_canvas_vd1_2;
e3de0aa6 284
bd9ff7b5
DV
285 ret = drmm_mode_config_init(drm);
286 if (ret)
a695949b 287 goto free_canvas_vd1_2;
a41e82e6
NA
288 drm->mode_config.max_width = 3840;
289 drm->mode_config.max_height = 2160;
290 drm->mode_config.funcs = &meson_mode_config_funcs;
ce0210c1 291 drm->mode_config.helper_private = &meson_mode_config_helpers;
a41e82e6
NA
292
293 /* Hardware Initialization */
294
09762525 295 meson_vpu_init(priv);
a41e82e6
NA
296 meson_venc_init(priv);
297 meson_vpp_init(priv);
298 meson_viu_init(priv);
d1b5e41e
NA
299 if (priv->afbcd.ops) {
300 ret = priv->afbcd.ops->init(priv);
301 if (ret)
a695949b 302 goto free_canvas_vd1_2;
d1b5e41e 303 }
bbbe775e
NA
304
305 /* Encoder Initialization */
306
1a9e51be 307 ret = meson_encoder_cvbs_probe(priv);
bbbe775e 308 if (ret)
fa747d75 309 goto exit_afbcd;
bbbe775e 310
8604889f 311 if (has_components) {
6a044642 312 ret = component_bind_all(dev, drm);
8604889f
NA
313 if (ret) {
314 dev_err(drm->dev, "Couldn't bind all components\n");
6a044642
NA
315 /* Do not try to unbind */
316 has_components = false;
fa747d75 317 goto exit_afbcd;
8604889f 318 }
a41e82e6 319 }
bbbe775e 320
1a9e51be 321 ret = meson_encoder_hdmi_probe(priv);
e67f6037 322 if (ret)
6a044642 323 goto exit_afbcd;
e67f6037 324
42dcf15f 325 if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
1a9e51be 326 ret = meson_encoder_dsi_probe(priv);
42dcf15f
NA
327 if (ret)
328 goto exit_afbcd;
329 }
330
bbbe775e
NA
331 ret = meson_plane_create(priv);
332 if (ret)
6a044642 333 goto exit_afbcd;
bbbe775e 334
f9a23481
NA
335 ret = meson_overlay_create(priv);
336 if (ret)
6a044642 337 goto exit_afbcd;
f9a23481 338
bbbe775e
NA
339 ret = meson_crtc_create(priv);
340 if (ret)
6a044642 341 goto exit_afbcd;
bbbe775e 342
65a96965 343 ret = request_irq(priv->vsync_irq, meson_irq, 0, drm->driver->name, drm);
bbbe775e 344 if (ret)
6a044642 345 goto exit_afbcd;
bbbe775e
NA
346
347 drm_mode_config_reset(drm);
bbbe775e 348
bbbe775e
NA
349 drm_kms_helper_poll_init(drm);
350
351 platform_set_drvdata(pdev, priv);
352
353 ret = drm_dev_register(drm, 0);
354 if (ret)
2d8f9289 355 goto uninstall_irq;
bbbe775e 356
57a03512 357 drm_client_setup(drm, NULL);
efbb9df9 358
bbbe775e
NA
359 return 0;
360
2d8f9289 361uninstall_irq:
65a96965 362 free_irq(priv->vsync_irq, drm);
fa747d75
MB
363exit_afbcd:
364 if (priv->afbcd.ops)
365 priv->afbcd.ops->exit(priv);
a695949b
YZ
366free_canvas_vd1_2:
367 meson_canvas_free(priv->canvas, priv->canvas_id_vd1_2);
368free_canvas_vd1_1:
369 meson_canvas_free(priv->canvas, priv->canvas_id_vd1_1);
370free_canvas_vd1_0:
371 meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0);
372free_canvas_osd1:
373 meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
bbbe775e 374free_drm:
dcacf651 375 drm_dev_put(drm);
bbbe775e 376
42dcf15f 377 meson_encoder_dsi_remove(priv);
6a044642
NA
378 meson_encoder_hdmi_remove(priv);
379 meson_encoder_cvbs_remove(priv);
380
381 if (has_components)
382 component_unbind_all(dev, drm);
383
bbbe775e
NA
384 return ret;
385}
386
8604889f
NA
387static int meson_drv_bind(struct device *dev)
388{
389 return meson_drv_bind_master(dev, true);
390}
391
a41e82e6 392static void meson_drv_unbind(struct device *dev)
bbbe775e 393{
776e7867
JPB
394 struct meson_drm *priv = dev_get_drvdata(dev);
395 struct drm_device *drm = priv->drm;
66cae477 396
f9a23481 397 if (priv->canvas) {
66cae477 398 meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
f9a23481
NA
399 meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0);
400 meson_canvas_free(priv->canvas, priv->canvas_id_vd1_1);
401 meson_canvas_free(priv->canvas, priv->canvas_id_vd1_2);
402 }
bbbe775e
NA
403
404 drm_dev_unregister(drm);
405 drm_kms_helper_poll_fini(drm);
e78ad18b 406 drm_atomic_helper_shutdown(drm);
65a96965 407 free_irq(priv->vsync_irq, drm);
dcacf651 408 drm_dev_put(drm);
09847723 409
42dcf15f 410 meson_encoder_dsi_remove(priv);
09847723
AL
411 meson_encoder_hdmi_remove(priv);
412 meson_encoder_cvbs_remove(priv);
413
31c51998 414 component_unbind_all(dev, drm);
fa62ee25 415
04b8a5d9
MB
416 if (priv->afbcd.ops)
417 priv->afbcd.ops->exit(priv);
bbbe775e
NA
418}
419
a41e82e6
NA
420static const struct component_master_ops meson_drv_master_ops = {
421 .bind = meson_drv_bind,
422 .unbind = meson_drv_unbind,
423};
424
cf3d4e53
NA
425static int __maybe_unused meson_drv_pm_suspend(struct device *dev)
426{
427 struct meson_drm *priv = dev_get_drvdata(dev);
428
429 if (!priv)
430 return 0;
431
432 return drm_mode_config_helper_suspend(priv->drm);
433}
434
435static int __maybe_unused meson_drv_pm_resume(struct device *dev)
436{
437 struct meson_drm *priv = dev_get_drvdata(dev);
438
439 if (!priv)
440 return 0;
441
442 meson_vpu_init(priv);
443 meson_venc_init(priv);
444 meson_vpp_init(priv);
445 meson_viu_init(priv);
d1b5e41e
NA
446 if (priv->afbcd.ops)
447 priv->afbcd.ops->init(priv);
cf3d4e53 448
c54a8f1f 449 return drm_mode_config_helper_resume(priv->drm);
cf3d4e53
NA
450}
451
fa0c16ca
AL
452static void meson_drv_shutdown(struct platform_device *pdev)
453{
454 struct meson_drm *priv = dev_get_drvdata(&pdev->dev);
fa0c16ca 455
7cfc4ea7
NA
456 if (!priv)
457 return;
458
459 drm_kms_helper_poll_fini(priv->drm);
460 drm_atomic_helper_shutdown(priv->drm);
fa0c16ca
AL
461}
462
44e16166
NA
463/*
464 * Only devices to use as components
465 * TOFIX: get rid of components when we can finally
466 * get meson_dx_hdmi to stop using the meson_drm
467 * private structure for HHI registers.
468 */
469static const struct of_device_id components_dev_match[] = {
470 { .compatible = "amlogic,meson-gxbb-dw-hdmi" },
471 { .compatible = "amlogic,meson-gxl-dw-hdmi" },
472 { .compatible = "amlogic,meson-gxm-dw-hdmi" },
473 { .compatible = "amlogic,meson-g12a-dw-hdmi" },
d235a7c4
NA
474 {}
475};
476
a41e82e6
NA
477static int meson_drv_probe(struct platform_device *pdev)
478{
479 struct component_match *match = NULL;
480 struct device_node *np = pdev->dev.of_node;
481 struct device_node *ep, *remote;
482 int count = 0;
483
484 for_each_endpoint_of_node(np, ep) {
485 remote = of_graph_get_remote_port_parent(ep);
f672b93e
JL
486 if (!remote || !of_device_is_available(remote)) {
487 of_node_put(remote);
a41e82e6 488 continue;
f672b93e 489 }
a41e82e6 490
44e16166
NA
491 if (of_match_node(components_dev_match, remote)) {
492 component_match_add(&pdev->dev, &match, component_compare_of, remote);
d235a7c4 493
44e16166
NA
494 dev_dbg(&pdev->dev, "parent %pOF remote match add %pOF parent %s\n",
495 np, remote, dev_name(&pdev->dev));
496 }
d235a7c4 497
f672b93e 498 of_node_put(remote);
d235a7c4
NA
499
500 ++count;
a41e82e6
NA
501 }
502
8604889f
NA
503 if (count && !match)
504 return meson_drv_bind_master(&pdev->dev, false);
505
a41e82e6
NA
506 /* If some endpoints were found, initialize the nodes */
507 if (count) {
508 dev_info(&pdev->dev, "Queued %d outputs on vpu\n", count);
509
510 return component_master_add_with_match(&pdev->dev,
511 &meson_drv_master_ops,
512 match);
513 }
514
515 /* If no output endpoints were available, simply bail out */
516 return 0;
517};
518
38ca2d93 519static void meson_drv_remove(struct platform_device *pdev)
8616f2a0
AL
520{
521 component_master_del(&pdev->dev, &meson_drv_master_ops);
8616f2a0
AL
522}
523
d1b5e41e
NA
524static struct meson_drm_match_data meson_drm_gxbb_data = {
525 .compat = VPU_COMPATIBLE_GXBB,
526};
527
528static struct meson_drm_match_data meson_drm_gxl_data = {
529 .compat = VPU_COMPATIBLE_GXL,
530};
531
532static struct meson_drm_match_data meson_drm_gxm_data = {
533 .compat = VPU_COMPATIBLE_GXM,
534 .afbcd_ops = &meson_afbcd_gxm_ops,
535};
536
537static struct meson_drm_match_data meson_drm_g12a_data = {
538 .compat = VPU_COMPATIBLE_G12A,
539 .afbcd_ops = &meson_afbcd_g12a_ops,
540};
541
bbbe775e 542static const struct of_device_id dt_match[] = {
528a25d0 543 { .compatible = "amlogic,meson-gxbb-vpu",
d1b5e41e 544 .data = (void *)&meson_drm_gxbb_data },
528a25d0 545 { .compatible = "amlogic,meson-gxl-vpu",
d1b5e41e 546 .data = (void *)&meson_drm_gxl_data },
528a25d0 547 { .compatible = "amlogic,meson-gxm-vpu",
d1b5e41e 548 .data = (void *)&meson_drm_gxm_data },
528a25d0 549 { .compatible = "amlogic,meson-g12a-vpu",
d1b5e41e 550 .data = (void *)&meson_drm_g12a_data },
bbbe775e
NA
551 {}
552};
553MODULE_DEVICE_TABLE(of, dt_match);
554
cf3d4e53
NA
555static const struct dev_pm_ops meson_drv_pm_ops = {
556 SET_SYSTEM_SLEEP_PM_OPS(meson_drv_pm_suspend, meson_drv_pm_resume)
557};
558
bbbe775e
NA
559static struct platform_driver meson_drm_platform_driver = {
560 .probe = meson_drv_probe,
e70140ba 561 .remove = meson_drv_remove,
fa0c16ca 562 .shutdown = meson_drv_shutdown,
bbbe775e 563 .driver = {
8aaacbc0 564 .name = "meson-drm",
bbbe775e 565 .of_match_table = dt_match,
cf3d4e53 566 .pm = &meson_drv_pm_ops,
bbbe775e
NA
567 },
568};
569
a9b19b0d 570drm_module_platform_driver(meson_drm_platform_driver);
bbbe775e
NA
571
572MODULE_AUTHOR("Jasper St. Pierre <jstpierre@mecheye.net>");
573MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
574MODULE_DESCRIPTION(DRIVER_DESC);
575MODULE_LICENSE("GPL");