Merge tag 'for-linux-6.12-ofs1' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6-block.git] / drivers / gpu / drm / meson / meson_drv.c
CommitLineData
1ccea77e 1// SPDX-License-Identifier: GPL-2.0-or-later
bbbe775e
NA
2/*
3 * Copyright (C) 2016 BayLibre, SAS
4 * Author: Neil Armstrong <narmstrong@baylibre.com>
5 * Copyright (C) 2014 Endless Mobile
6 *
bbbe775e
NA
7 * Written by:
8 * Jasper St. Pierre <jstpierre@mecheye.net>
9 */
10
a41e82e6 11#include <linux/component.h>
66620f48 12#include <linux/module.h>
bbbe775e 13#include <linux/of_graph.h>
8976eeee 14#include <linux/sys_soc.h>
66620f48
SR
15#include <linux/platform_device.h>
16#include <linux/soc/amlogic/meson-canvas.h>
bbbe775e 17
6848c291 18#include <drm/drm_aperture.h>
bbbe775e 19#include <drm/drm_atomic_helper.h>
66620f48 20#include <drm/drm_drv.h>
8a9d46f4 21#include <drm/drm_fbdev_dma.h>
4a83c26a 22#include <drm/drm_gem_dma_helper.h>
24ef8157 23#include <drm/drm_gem_framebuffer_helper.h>
66620f48 24#include <drm/drm_modeset_helper_vtables.h>
a9b19b0d 25#include <drm/drm_module.h>
fcd70cd3 26#include <drm/drm_probe_helper.h>
66620f48 27#include <drm/drm_vblank.h>
bbbe775e 28
66620f48 29#include "meson_crtc.h"
bbbe775e 30#include "meson_drv.h"
f9a23481 31#include "meson_overlay.h"
66620f48 32#include "meson_plane.h"
d1b5e41e 33#include "meson_osd_afbcd.h"
66620f48 34#include "meson_registers.h"
72317eaa 35#include "meson_encoder_cvbs.h"
e67f6037 36#include "meson_encoder_hdmi.h"
42dcf15f 37#include "meson_encoder_dsi.h"
bbbe775e 38#include "meson_viu.h"
66620f48 39#include "meson_vpp.h"
d1b5e41e 40#include "meson_rdma.h"
bbbe775e
NA
41
42#define DRIVER_NAME "meson"
43#define DRIVER_DESC "Amlogic Meson DRM driver"
44
2021d5b7
NA
45/**
46 * DOC: Video Processing Unit
bbbe775e
NA
47 *
48 * VPU Handles the Global Video Processing, it includes management of the
49 * clocks gates, blocks reset lines and power domains.
50 *
51 * What is missing :
2021d5b7 52 *
bbbe775e
NA
53 * - Full reset of entire video processing HW blocks
54 * - Scaling and setup of the VPU clock
55 * - Bus clock gates
56 * - Powering up video processing HW blocks
57 * - Powering Up HDMI controller and PHY
58 */
59
bbbe775e 60static const struct drm_mode_config_funcs meson_mode_config_funcs = {
bbbe775e
NA
61 .atomic_check = drm_atomic_helper_check,
62 .atomic_commit = drm_atomic_helper_commit,
24ef8157 63 .fb_create = drm_gem_fb_create,
bbbe775e
NA
64};
65
ce0210c1
NA
66static const struct drm_mode_config_helper_funcs meson_mode_config_helpers = {
67 .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
68};
69
bbbe775e
NA
70static irqreturn_t meson_irq(int irq, void *arg)
71{
72 struct drm_device *dev = arg;
73 struct meson_drm *priv = dev->dev_private;
74
75 (void)readl_relaxed(priv->io_base + _REG(VENC_INTFLAG));
76
77 meson_crtc_irq(priv);
78
79 return IRQ_HANDLED;
80}
81
852ce728
NA
82static int meson_dumb_create(struct drm_file *file, struct drm_device *dev,
83 struct drm_mode_create_dumb *args)
84{
85 /*
86 * We need 64bytes aligned stride, and PAGE aligned size
87 */
88 args->pitch = ALIGN(DIV_ROUND_UP(args->width * args->bpp, 8), SZ_64);
89 args->size = PAGE_ALIGN(args->pitch * args->height);
90
4a83c26a 91 return drm_gem_dma_dumb_create_internal(file, dev, args);
852ce728
NA
92}
93
4a83c26a 94DEFINE_DRM_GEM_DMA_FOPS(fops);
bbbe775e 95
70a59dd8 96static const struct drm_driver meson_driver = {
0424fdaf 97 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
bbbe775e 98
4a83c26a
DK
99 /* DMA Ops */
100 DRM_GEM_DMA_DRIVER_OPS_WITH_DUMB_CREATE(meson_dumb_create),
bbbe775e
NA
101
102 /* Misc */
103 .fops = &fops,
104 .name = DRIVER_NAME,
105 .desc = DRIVER_DESC,
106 .date = "20161109",
107 .major = 1,
108 .minor = 0,
109};
110
111static bool meson_vpu_has_available_connectors(struct device *dev)
112{
113 struct device_node *ep, *remote;
114
115 /* Parses each endpoint and check if remote exists */
116 for_each_endpoint_of_node(dev->of_node, ep) {
117 /* If the endpoint node exists, consider it enabled */
118 remote = of_graph_get_remote_port(ep);
91b3c8db
LH
119 if (remote) {
120 of_node_put(remote);
121 of_node_put(ep);
bbbe775e 122 return true;
91b3c8db 123 }
bbbe775e
NA
124 }
125
126 return false;
127}
128
129static struct regmap_config meson_regmap_config = {
130 .reg_bits = 32,
131 .val_bits = 32,
132 .reg_stride = 4,
133 .max_register = 0x1000,
134};
135
09762525
NA
136static void meson_vpu_init(struct meson_drm *priv)
137{
bfb86819
JM
138 u32 value;
139
140 /*
141 * Slave dc0 and dc5 connected to master port 1.
142 * By default other slaves are connected to master port 0.
143 */
144 value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1) |
145 VPU_RDARB_SLAVE_TO_MASTER_PORT(5, 1);
146 writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C1));
147
148 /* Slave dc0 connected to master port 1 */
149 value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1);
150 writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C2));
151
152 /* Slave dc4 and dc7 connected to master port 1 */
153 value = VPU_RDARB_SLAVE_TO_MASTER_PORT(4, 1) |
154 VPU_RDARB_SLAVE_TO_MASTER_PORT(7, 1);
155 writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L2C1));
156
157 /* Slave dc1 connected to master port 1 */
158 value = VPU_RDARB_SLAVE_TO_MASTER_PORT(1, 1);
159 writel_relaxed(value, priv->io_base + _REG(VPU_WRARB_MODE_L2C1));
09762525
NA
160}
161
8976eeee
NA
162struct meson_drm_soc_attr {
163 struct meson_drm_soc_limits limits;
164 const struct soc_device_attribute *attrs;
165};
166
167static const struct meson_drm_soc_attr meson_drm_soc_attrs[] = {
168 /* S805X/S805Y HDMI PLL won't lock for HDMI PHY freq > 1,65GHz */
169 {
170 .limits = {
171 .max_hdmi_phy_freq = 1650000,
172 },
173 .attrs = (const struct soc_device_attribute []) {
174 { .soc_id = "GXL (S805*)", },
f6e68388 175 { /* sentinel */ }
8976eeee
NA
176 }
177 },
178};
179
8604889f 180static int meson_drv_bind_master(struct device *dev, bool has_components)
bbbe775e 181{
a41e82e6 182 struct platform_device *pdev = to_platform_device(dev);
d1b5e41e 183 const struct meson_drm_match_data *match;
bbbe775e
NA
184 struct meson_drm *priv;
185 struct drm_device *drm;
186 struct resource *res;
187 void __iomem *regs;
8976eeee 188 int ret, i;
bbbe775e
NA
189
190 /* Checks if an output connector is available */
191 if (!meson_vpu_has_available_connectors(dev)) {
192 dev_err(dev, "No output connector available\n");
193 return -ENODEV;
194 }
195
d1b5e41e
NA
196 match = of_device_get_match_data(dev);
197 if (!match)
198 return -ENODEV;
199
bbbe775e
NA
200 drm = drm_dev_alloc(&meson_driver, dev);
201 if (IS_ERR(drm))
202 return PTR_ERR(drm);
203
204 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
205 if (!priv) {
206 ret = -ENOMEM;
207 goto free_drm;
208 }
209 drm->dev_private = priv;
210 priv->drm = drm;
211 priv->dev = dev;
d1b5e41e
NA
212 priv->compat = match->compat;
213 priv->afbcd.ops = match->afbcd_ops;
528a25d0 214
d4cb82aa 215 regs = devm_platform_ioremap_resource_byname(pdev, "vpu");
2c18107b
CJ
216 if (IS_ERR(regs)) {
217 ret = PTR_ERR(regs);
218 goto free_drm;
219 }
bbbe775e
NA
220
221 priv->io_base = regs;
222
223 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hhi");
01a9e949
CJ
224 if (!res) {
225 ret = -EINVAL;
226 goto free_drm;
227 }
bbbe775e
NA
228 /* Simply ioremap since it may be a shared register zone */
229 regs = devm_ioremap(dev, res->start, resource_size(res));
2c18107b
CJ
230 if (!regs) {
231 ret = -EADDRNOTAVAIL;
232 goto free_drm;
233 }
bbbe775e
NA
234
235 priv->hhi = devm_regmap_init_mmio(dev, regs,
236 &meson_regmap_config);
237 if (IS_ERR(priv->hhi)) {
238 dev_err(&pdev->dev, "Couldn't create the HHI regmap\n");
2c18107b
CJ
239 ret = PTR_ERR(priv->hhi);
240 goto free_drm;
bbbe775e
NA
241 }
242
66cae477 243 priv->canvas = meson_canvas_get(dev);
2bf6b5b0
MJ
244 if (IS_ERR(priv->canvas)) {
245 ret = PTR_ERR(priv->canvas);
246 goto free_drm;
247 }
248
249 ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_osd1);
250 if (ret)
251 goto free_drm;
252 ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_0);
a695949b
YZ
253 if (ret)
254 goto free_canvas_osd1;
2bf6b5b0 255 ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_1);
a695949b
YZ
256 if (ret)
257 goto free_canvas_vd1_0;
2bf6b5b0 258 ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_2);
a695949b
YZ
259 if (ret)
260 goto free_canvas_vd1_1;
bbbe775e
NA
261
262 priv->vsync_irq = platform_get_irq(pdev, 0);
263
e770f6bf
CJ
264 ret = drm_vblank_init(drm, 1);
265 if (ret)
a695949b 266 goto free_canvas_vd1_2;
e770f6bf 267
8976eeee
NA
268 /* Assign limits per soc revision/package */
269 for (i = 0 ; i < ARRAY_SIZE(meson_drm_soc_attrs) ; ++i) {
270 if (soc_device_match(meson_drm_soc_attrs[i].attrs)) {
271 priv->limits = &meson_drm_soc_attrs[i].limits;
272 break;
273 }
274 }
275
6848c291
TZ
276 /*
277 * Remove early framebuffers (ie. simplefb). The framebuffer can be
278 * located anywhere in RAM
279 */
62aeaeaa 280 ret = drm_aperture_remove_framebuffers(&meson_driver);
6848c291 281 if (ret)
a695949b 282 goto free_canvas_vd1_2;
e3de0aa6 283
bd9ff7b5
DV
284 ret = drmm_mode_config_init(drm);
285 if (ret)
a695949b 286 goto free_canvas_vd1_2;
a41e82e6
NA
287 drm->mode_config.max_width = 3840;
288 drm->mode_config.max_height = 2160;
289 drm->mode_config.funcs = &meson_mode_config_funcs;
ce0210c1 290 drm->mode_config.helper_private = &meson_mode_config_helpers;
a41e82e6
NA
291
292 /* Hardware Initialization */
293
09762525 294 meson_vpu_init(priv);
a41e82e6
NA
295 meson_venc_init(priv);
296 meson_vpp_init(priv);
297 meson_viu_init(priv);
d1b5e41e
NA
298 if (priv->afbcd.ops) {
299 ret = priv->afbcd.ops->init(priv);
300 if (ret)
a695949b 301 goto free_canvas_vd1_2;
d1b5e41e 302 }
bbbe775e
NA
303
304 /* Encoder Initialization */
305
1a9e51be 306 ret = meson_encoder_cvbs_probe(priv);
bbbe775e 307 if (ret)
fa747d75 308 goto exit_afbcd;
bbbe775e 309
8604889f 310 if (has_components) {
6a044642 311 ret = component_bind_all(dev, drm);
8604889f
NA
312 if (ret) {
313 dev_err(drm->dev, "Couldn't bind all components\n");
6a044642
NA
314 /* Do not try to unbind */
315 has_components = false;
fa747d75 316 goto exit_afbcd;
8604889f 317 }
a41e82e6 318 }
bbbe775e 319
1a9e51be 320 ret = meson_encoder_hdmi_probe(priv);
e67f6037 321 if (ret)
6a044642 322 goto exit_afbcd;
e67f6037 323
42dcf15f 324 if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
1a9e51be 325 ret = meson_encoder_dsi_probe(priv);
42dcf15f
NA
326 if (ret)
327 goto exit_afbcd;
328 }
329
bbbe775e
NA
330 ret = meson_plane_create(priv);
331 if (ret)
6a044642 332 goto exit_afbcd;
bbbe775e 333
f9a23481
NA
334 ret = meson_overlay_create(priv);
335 if (ret)
6a044642 336 goto exit_afbcd;
f9a23481 337
bbbe775e
NA
338 ret = meson_crtc_create(priv);
339 if (ret)
6a044642 340 goto exit_afbcd;
bbbe775e 341
65a96965 342 ret = request_irq(priv->vsync_irq, meson_irq, 0, drm->driver->name, drm);
bbbe775e 343 if (ret)
6a044642 344 goto exit_afbcd;
bbbe775e
NA
345
346 drm_mode_config_reset(drm);
bbbe775e 347
bbbe775e
NA
348 drm_kms_helper_poll_init(drm);
349
350 platform_set_drvdata(pdev, priv);
351
352 ret = drm_dev_register(drm, 0);
353 if (ret)
2d8f9289 354 goto uninstall_irq;
bbbe775e 355
8a9d46f4 356 drm_fbdev_dma_setup(drm, 32);
efbb9df9 357
bbbe775e
NA
358 return 0;
359
2d8f9289 360uninstall_irq:
65a96965 361 free_irq(priv->vsync_irq, drm);
fa747d75
MB
362exit_afbcd:
363 if (priv->afbcd.ops)
364 priv->afbcd.ops->exit(priv);
a695949b
YZ
365free_canvas_vd1_2:
366 meson_canvas_free(priv->canvas, priv->canvas_id_vd1_2);
367free_canvas_vd1_1:
368 meson_canvas_free(priv->canvas, priv->canvas_id_vd1_1);
369free_canvas_vd1_0:
370 meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0);
371free_canvas_osd1:
372 meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
bbbe775e 373free_drm:
dcacf651 374 drm_dev_put(drm);
bbbe775e 375
42dcf15f 376 meson_encoder_dsi_remove(priv);
6a044642
NA
377 meson_encoder_hdmi_remove(priv);
378 meson_encoder_cvbs_remove(priv);
379
380 if (has_components)
381 component_unbind_all(dev, drm);
382
bbbe775e
NA
383 return ret;
384}
385
8604889f
NA
386static int meson_drv_bind(struct device *dev)
387{
388 return meson_drv_bind_master(dev, true);
389}
390
a41e82e6 391static void meson_drv_unbind(struct device *dev)
bbbe775e 392{
776e7867
JPB
393 struct meson_drm *priv = dev_get_drvdata(dev);
394 struct drm_device *drm = priv->drm;
66cae477 395
f9a23481 396 if (priv->canvas) {
66cae477 397 meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
f9a23481
NA
398 meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0);
399 meson_canvas_free(priv->canvas, priv->canvas_id_vd1_1);
400 meson_canvas_free(priv->canvas, priv->canvas_id_vd1_2);
401 }
bbbe775e
NA
402
403 drm_dev_unregister(drm);
404 drm_kms_helper_poll_fini(drm);
e78ad18b 405 drm_atomic_helper_shutdown(drm);
65a96965 406 free_irq(priv->vsync_irq, drm);
dcacf651 407 drm_dev_put(drm);
09847723 408
42dcf15f 409 meson_encoder_dsi_remove(priv);
09847723
AL
410 meson_encoder_hdmi_remove(priv);
411 meson_encoder_cvbs_remove(priv);
412
31c51998 413 component_unbind_all(dev, drm);
fa62ee25 414
04b8a5d9
MB
415 if (priv->afbcd.ops)
416 priv->afbcd.ops->exit(priv);
bbbe775e
NA
417}
418
a41e82e6
NA
419static const struct component_master_ops meson_drv_master_ops = {
420 .bind = meson_drv_bind,
421 .unbind = meson_drv_unbind,
422};
423
cf3d4e53
NA
424static int __maybe_unused meson_drv_pm_suspend(struct device *dev)
425{
426 struct meson_drm *priv = dev_get_drvdata(dev);
427
428 if (!priv)
429 return 0;
430
431 return drm_mode_config_helper_suspend(priv->drm);
432}
433
434static int __maybe_unused meson_drv_pm_resume(struct device *dev)
435{
436 struct meson_drm *priv = dev_get_drvdata(dev);
437
438 if (!priv)
439 return 0;
440
441 meson_vpu_init(priv);
442 meson_venc_init(priv);
443 meson_vpp_init(priv);
444 meson_viu_init(priv);
d1b5e41e
NA
445 if (priv->afbcd.ops)
446 priv->afbcd.ops->init(priv);
cf3d4e53 447
c54a8f1f 448 return drm_mode_config_helper_resume(priv->drm);
cf3d4e53
NA
449}
450
fa0c16ca
AL
451static void meson_drv_shutdown(struct platform_device *pdev)
452{
453 struct meson_drm *priv = dev_get_drvdata(&pdev->dev);
fa0c16ca 454
7cfc4ea7
NA
455 if (!priv)
456 return;
457
458 drm_kms_helper_poll_fini(priv->drm);
459 drm_atomic_helper_shutdown(priv->drm);
fa0c16ca
AL
460}
461
44e16166
NA
462/*
463 * Only devices to use as components
464 * TOFIX: get rid of components when we can finally
465 * get meson_dx_hdmi to stop using the meson_drm
466 * private structure for HHI registers.
467 */
468static const struct of_device_id components_dev_match[] = {
469 { .compatible = "amlogic,meson-gxbb-dw-hdmi" },
470 { .compatible = "amlogic,meson-gxl-dw-hdmi" },
471 { .compatible = "amlogic,meson-gxm-dw-hdmi" },
472 { .compatible = "amlogic,meson-g12a-dw-hdmi" },
d235a7c4
NA
473 {}
474};
475
a41e82e6
NA
476static int meson_drv_probe(struct platform_device *pdev)
477{
478 struct component_match *match = NULL;
479 struct device_node *np = pdev->dev.of_node;
480 struct device_node *ep, *remote;
481 int count = 0;
482
483 for_each_endpoint_of_node(np, ep) {
484 remote = of_graph_get_remote_port_parent(ep);
f672b93e
JL
485 if (!remote || !of_device_is_available(remote)) {
486 of_node_put(remote);
a41e82e6 487 continue;
f672b93e 488 }
a41e82e6 489
44e16166
NA
490 if (of_match_node(components_dev_match, remote)) {
491 component_match_add(&pdev->dev, &match, component_compare_of, remote);
d235a7c4 492
44e16166
NA
493 dev_dbg(&pdev->dev, "parent %pOF remote match add %pOF parent %s\n",
494 np, remote, dev_name(&pdev->dev));
495 }
d235a7c4 496
f672b93e 497 of_node_put(remote);
d235a7c4
NA
498
499 ++count;
a41e82e6
NA
500 }
501
8604889f
NA
502 if (count && !match)
503 return meson_drv_bind_master(&pdev->dev, false);
504
a41e82e6
NA
505 /* If some endpoints were found, initialize the nodes */
506 if (count) {
507 dev_info(&pdev->dev, "Queued %d outputs on vpu\n", count);
508
509 return component_master_add_with_match(&pdev->dev,
510 &meson_drv_master_ops,
511 match);
512 }
513
514 /* If no output endpoints were available, simply bail out */
515 return 0;
516};
517
38ca2d93 518static void meson_drv_remove(struct platform_device *pdev)
8616f2a0
AL
519{
520 component_master_del(&pdev->dev, &meson_drv_master_ops);
8616f2a0
AL
521}
522
d1b5e41e
NA
523static struct meson_drm_match_data meson_drm_gxbb_data = {
524 .compat = VPU_COMPATIBLE_GXBB,
525};
526
527static struct meson_drm_match_data meson_drm_gxl_data = {
528 .compat = VPU_COMPATIBLE_GXL,
529};
530
531static struct meson_drm_match_data meson_drm_gxm_data = {
532 .compat = VPU_COMPATIBLE_GXM,
533 .afbcd_ops = &meson_afbcd_gxm_ops,
534};
535
536static struct meson_drm_match_data meson_drm_g12a_data = {
537 .compat = VPU_COMPATIBLE_G12A,
538 .afbcd_ops = &meson_afbcd_g12a_ops,
539};
540
bbbe775e 541static const struct of_device_id dt_match[] = {
528a25d0 542 { .compatible = "amlogic,meson-gxbb-vpu",
d1b5e41e 543 .data = (void *)&meson_drm_gxbb_data },
528a25d0 544 { .compatible = "amlogic,meson-gxl-vpu",
d1b5e41e 545 .data = (void *)&meson_drm_gxl_data },
528a25d0 546 { .compatible = "amlogic,meson-gxm-vpu",
d1b5e41e 547 .data = (void *)&meson_drm_gxm_data },
528a25d0 548 { .compatible = "amlogic,meson-g12a-vpu",
d1b5e41e 549 .data = (void *)&meson_drm_g12a_data },
bbbe775e
NA
550 {}
551};
552MODULE_DEVICE_TABLE(of, dt_match);
553
cf3d4e53
NA
554static const struct dev_pm_ops meson_drv_pm_ops = {
555 SET_SYSTEM_SLEEP_PM_OPS(meson_drv_pm_suspend, meson_drv_pm_resume)
556};
557
bbbe775e
NA
558static struct platform_driver meson_drm_platform_driver = {
559 .probe = meson_drv_probe,
38ca2d93 560 .remove_new = meson_drv_remove,
fa0c16ca 561 .shutdown = meson_drv_shutdown,
bbbe775e 562 .driver = {
8aaacbc0 563 .name = "meson-drm",
bbbe775e 564 .of_match_table = dt_match,
cf3d4e53 565 .pm = &meson_drv_pm_ops,
bbbe775e
NA
566 },
567};
568
a9b19b0d 569drm_module_platform_driver(meson_drm_platform_driver);
bbbe775e
NA
570
571MODULE_AUTHOR("Jasper St. Pierre <jstpierre@mecheye.net>");
572MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
573MODULE_DESCRIPTION(DRIVER_DESC);
574MODULE_LICENSE("GPL");