Commit | Line | Data |
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2e54c14e CH |
1 | /* |
2 | * Copyright (c) 2015 MediaTek Inc. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
13 | ||
14 | #include <drm/drmP.h> | |
15 | #include <drm/drm_atomic_helper.h> | |
2e54c14e CH |
16 | #include <drm/drm_mipi_dsi.h> |
17 | #include <drm/drm_panel.h> | |
ebc94461 | 18 | #include <drm/drm_of.h> |
fcd70cd3 | 19 | #include <drm/drm_probe_helper.h> |
2e54c14e CH |
20 | #include <linux/clk.h> |
21 | #include <linux/component.h> | |
f752413e | 22 | #include <linux/iopoll.h> |
dd5080a5 | 23 | #include <linux/irq.h> |
2e54c14e CH |
24 | #include <linux/of.h> |
25 | #include <linux/of_platform.h> | |
2e54c14e CH |
26 | #include <linux/phy/phy.h> |
27 | #include <linux/platform_device.h> | |
21898816 | 28 | #include <video/mipi_display.h> |
2e54c14e CH |
29 | #include <video/videomode.h> |
30 | ||
31 | #include "mtk_drm_ddp_comp.h" | |
32 | ||
2e54c14e CH |
33 | #define DSI_START 0x00 |
34 | ||
dd5080a5 | 35 | #define DSI_INTEN 0x08 |
36 | ||
37 | #define DSI_INTSTA 0x0c | |
38 | #define LPRX_RD_RDY_INT_FLAG BIT(0) | |
39 | #define CMD_DONE_INT_FLAG BIT(1) | |
40 | #define TE_RDY_INT_FLAG BIT(2) | |
41 | #define VM_DONE_INT_FLAG BIT(3) | |
42 | #define EXT_TE_RDY_INT_FLAG BIT(4) | |
43 | #define DSI_BUSY BIT(31) | |
44 | ||
2e54c14e CH |
45 | #define DSI_CON_CTRL 0x10 |
46 | #define DSI_RESET BIT(0) | |
47 | #define DSI_EN BIT(1) | |
48 | ||
49 | #define DSI_MODE_CTRL 0x14 | |
50 | #define MODE (3) | |
51 | #define CMD_MODE 0 | |
52 | #define SYNC_PULSE_MODE 1 | |
53 | #define SYNC_EVENT_MODE 2 | |
54 | #define BURST_MODE 3 | |
55 | #define FRM_MODE BIT(16) | |
56 | #define MIX_MODE BIT(17) | |
57 | ||
58 | #define DSI_TXRX_CTRL 0x18 | |
80a5cfd6 | 59 | #define VC_NUM BIT(1) |
2e54c14e CH |
60 | #define LANE_NUM (0xf << 2) |
61 | #define DIS_EOT BIT(6) | |
62 | #define NULL_EN BIT(7) | |
63 | #define TE_FREERUN BIT(8) | |
64 | #define EXT_TE_EN BIT(9) | |
65 | #define EXT_TE_EDGE BIT(10) | |
66 | #define MAX_RTN_SIZE (0xf << 12) | |
67 | #define HSTX_CKLP_EN BIT(16) | |
68 | ||
69 | #define DSI_PSCTRL 0x1c | |
70 | #define DSI_PS_WC 0x3fff | |
71 | #define DSI_PS_SEL (3 << 16) | |
72 | #define PACKED_PS_16BIT_RGB565 (0 << 16) | |
73 | #define LOOSELY_PS_18BIT_RGB666 (1 << 16) | |
74 | #define PACKED_PS_18BIT_RGB666 (2 << 16) | |
75 | #define PACKED_PS_24BIT_RGB888 (3 << 16) | |
76 | ||
77 | #define DSI_VSA_NL 0x20 | |
78 | #define DSI_VBP_NL 0x24 | |
79 | #define DSI_VFP_NL 0x28 | |
80 | #define DSI_VACT_NL 0x2C | |
81 | #define DSI_HSA_WC 0x50 | |
82 | #define DSI_HBP_WC 0x54 | |
83 | #define DSI_HFP_WC 0x58 | |
84 | ||
21898816 | 85 | #define DSI_CMDQ_SIZE 0x60 |
86 | #define CMDQ_SIZE 0x3f | |
87 | ||
2e54c14e CH |
88 | #define DSI_HSTX_CKL_WC 0x64 |
89 | ||
21898816 | 90 | #define DSI_RX_DATA0 0x74 |
91 | #define DSI_RX_DATA1 0x78 | |
92 | #define DSI_RX_DATA2 0x7c | |
93 | #define DSI_RX_DATA3 0x80 | |
94 | ||
dd5080a5 | 95 | #define DSI_RACK 0x84 |
96 | #define RACK BIT(0) | |
97 | ||
2e54c14e CH |
98 | #define DSI_PHY_LCCON 0x104 |
99 | #define LC_HS_TX_EN BIT(0) | |
100 | #define LC_ULPM_EN BIT(1) | |
101 | #define LC_WAKEUP_EN BIT(2) | |
102 | ||
103 | #define DSI_PHY_LD0CON 0x108 | |
104 | #define LD0_HS_TX_EN BIT(0) | |
105 | #define LD0_ULPM_EN BIT(1) | |
106 | #define LD0_WAKEUP_EN BIT(2) | |
107 | ||
108 | #define DSI_PHY_TIMECON0 0x110 | |
109 | #define LPX (0xff << 0) | |
f6c87239 | 110 | #define HS_PREP (0xff << 8) |
2e54c14e CH |
111 | #define HS_ZERO (0xff << 16) |
112 | #define HS_TRAIL (0xff << 24) | |
113 | ||
114 | #define DSI_PHY_TIMECON1 0x114 | |
115 | #define TA_GO (0xff << 0) | |
116 | #define TA_SURE (0xff << 8) | |
117 | #define TA_GET (0xff << 16) | |
118 | #define DA_HS_EXIT (0xff << 24) | |
119 | ||
120 | #define DSI_PHY_TIMECON2 0x118 | |
121 | #define CONT_DET (0xff << 0) | |
122 | #define CLK_ZERO (0xff << 16) | |
123 | #define CLK_TRAIL (0xff << 24) | |
124 | ||
125 | #define DSI_PHY_TIMECON3 0x11c | |
f6c87239 | 126 | #define CLK_HS_PREP (0xff << 0) |
2e54c14e CH |
127 | #define CLK_HS_POST (0xff << 8) |
128 | #define CLK_HS_EXIT (0xff << 16) | |
129 | ||
0707632b | 130 | #define DSI_VM_CMD_CON 0x130 |
131 | #define VM_CMD_EN BIT(0) | |
132 | #define TS_VFP_EN BIT(5) | |
133 | ||
21898816 | 134 | #define DSI_CMDQ0 0x180 |
135 | #define CONFIG (0xff << 0) | |
136 | #define SHORT_PACKET 0 | |
137 | #define LONG_PACKET 2 | |
138 | #define BTA BIT(2) | |
139 | #define DATA_ID (0xff << 8) | |
140 | #define DATA_0 (0xff << 16) | |
141 | #define DATA_1 (0xff << 24) | |
142 | ||
f6c87239 JS |
143 | #define T_LPX 5 |
144 | #define T_HS_PREP 6 | |
145 | #define T_HS_TRAIL 8 | |
146 | #define T_HS_EXIT 7 | |
147 | #define T_HS_ZERO 10 | |
148 | ||
2e54c14e CH |
149 | #define NS_TO_CYCLE(n, c) ((n) / (c) + (((n) % (c)) ? 1 : 0)) |
150 | ||
21898816 | 151 | #define MTK_DSI_HOST_IS_READ(type) \ |
152 | ((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \ | |
153 | (type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \ | |
154 | (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \ | |
155 | (type == MIPI_DSI_DCS_READ)) | |
156 | ||
2e54c14e CH |
157 | struct phy; |
158 | ||
159 | struct mtk_dsi { | |
160 | struct mtk_ddp_comp ddp_comp; | |
161 | struct device *dev; | |
162 | struct mipi_dsi_host host; | |
163 | struct drm_encoder encoder; | |
164 | struct drm_connector conn; | |
165 | struct drm_panel *panel; | |
166 | struct drm_bridge *bridge; | |
167 | struct phy *phy; | |
168 | ||
169 | void __iomem *regs; | |
170 | ||
171 | struct clk *engine_clk; | |
172 | struct clk *digital_clk; | |
173 | struct clk *hs_clk; | |
174 | ||
175 | u32 data_rate; | |
176 | ||
177 | unsigned long mode_flags; | |
178 | enum mipi_dsi_pixel_format format; | |
179 | unsigned int lanes; | |
180 | struct videomode vm; | |
181 | int refcount; | |
182 | bool enabled; | |
dd5080a5 | 183 | u32 irq_data; |
184 | wait_queue_head_t irq_wait_queue; | |
2e54c14e CH |
185 | }; |
186 | ||
187 | static inline struct mtk_dsi *encoder_to_dsi(struct drm_encoder *e) | |
188 | { | |
189 | return container_of(e, struct mtk_dsi, encoder); | |
190 | } | |
191 | ||
192 | static inline struct mtk_dsi *connector_to_dsi(struct drm_connector *c) | |
193 | { | |
194 | return container_of(c, struct mtk_dsi, conn); | |
195 | } | |
196 | ||
197 | static inline struct mtk_dsi *host_to_dsi(struct mipi_dsi_host *h) | |
198 | { | |
199 | return container_of(h, struct mtk_dsi, host); | |
200 | } | |
201 | ||
202 | static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data) | |
203 | { | |
204 | u32 temp = readl(dsi->regs + offset); | |
205 | ||
206 | writel((temp & ~mask) | (data & mask), dsi->regs + offset); | |
207 | } | |
208 | ||
80a5cfd6 | 209 | static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi) |
2e54c14e CH |
210 | { |
211 | u32 timcon0, timcon1, timcon2, timcon3; | |
f6c87239 | 212 | u32 ui, cycle_time; |
2e54c14e CH |
213 | |
214 | ui = 1000 / dsi->data_rate + 0x01; | |
215 | cycle_time = 8000 / dsi->data_rate + 0x01; | |
2e54c14e | 216 | |
f6c87239 JS |
217 | timcon0 = T_LPX | T_HS_PREP << 8 | T_HS_ZERO << 16 | T_HS_TRAIL << 24; |
218 | timcon1 = 4 * T_LPX | (3 * T_LPX / 2) << 8 | 5 * T_LPX << 16 | | |
219 | T_HS_EXIT << 24; | |
2e54c14e CH |
220 | timcon2 = ((NS_TO_CYCLE(0x64, cycle_time) + 0xa) << 24) | |
221 | (NS_TO_CYCLE(0x150, cycle_time) << 16); | |
f6c87239 JS |
222 | timcon3 = NS_TO_CYCLE(0x40, cycle_time) | (2 * T_LPX) << 16 | |
223 | NS_TO_CYCLE(80 + 52 * ui, cycle_time) << 8; | |
2e54c14e CH |
224 | |
225 | writel(timcon0, dsi->regs + DSI_PHY_TIMECON0); | |
226 | writel(timcon1, dsi->regs + DSI_PHY_TIMECON1); | |
227 | writel(timcon2, dsi->regs + DSI_PHY_TIMECON2); | |
228 | writel(timcon3, dsi->regs + DSI_PHY_TIMECON3); | |
229 | } | |
230 | ||
231 | static void mtk_dsi_enable(struct mtk_dsi *dsi) | |
232 | { | |
233 | mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, DSI_EN); | |
234 | } | |
235 | ||
236 | static void mtk_dsi_disable(struct mtk_dsi *dsi) | |
237 | { | |
238 | mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, 0); | |
239 | } | |
240 | ||
80a5cfd6 | 241 | static void mtk_dsi_reset_engine(struct mtk_dsi *dsi) |
2e54c14e CH |
242 | { |
243 | mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, DSI_RESET); | |
244 | mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, 0); | |
245 | } | |
246 | ||
80a5cfd6 | 247 | static void mtk_dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi) |
2e54c14e CH |
248 | { |
249 | mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0); | |
250 | mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0); | |
251 | } | |
252 | ||
80a5cfd6 | 253 | static void mtk_dsi_clk_ulp_mode_leave(struct mtk_dsi *dsi) |
2e54c14e CH |
254 | { |
255 | mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0); | |
256 | mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, LC_WAKEUP_EN); | |
257 | mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, 0); | |
258 | } | |
259 | ||
80a5cfd6 | 260 | static void mtk_dsi_lane0_ulp_mode_enter(struct mtk_dsi *dsi) |
2e54c14e CH |
261 | { |
262 | mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_HS_TX_EN, 0); | |
263 | mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0); | |
264 | } | |
265 | ||
80a5cfd6 | 266 | static void mtk_dsi_lane0_ulp_mode_leave(struct mtk_dsi *dsi) |
2e54c14e CH |
267 | { |
268 | mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0); | |
269 | mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, LD0_WAKEUP_EN); | |
270 | mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, 0); | |
271 | } | |
272 | ||
80a5cfd6 | 273 | static bool mtk_dsi_clk_hs_state(struct mtk_dsi *dsi) |
2e54c14e CH |
274 | { |
275 | u32 tmp_reg1; | |
276 | ||
277 | tmp_reg1 = readl(dsi->regs + DSI_PHY_LCCON); | |
278 | return ((tmp_reg1 & LC_HS_TX_EN) == 1) ? true : false; | |
279 | } | |
280 | ||
80a5cfd6 | 281 | static void mtk_dsi_clk_hs_mode(struct mtk_dsi *dsi, bool enter) |
2e54c14e | 282 | { |
80a5cfd6 | 283 | if (enter && !mtk_dsi_clk_hs_state(dsi)) |
2e54c14e | 284 | mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, LC_HS_TX_EN); |
80a5cfd6 | 285 | else if (!enter && mtk_dsi_clk_hs_state(dsi)) |
2e54c14e CH |
286 | mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0); |
287 | } | |
288 | ||
80a5cfd6 | 289 | static void mtk_dsi_set_mode(struct mtk_dsi *dsi) |
2e54c14e CH |
290 | { |
291 | u32 vid_mode = CMD_MODE; | |
292 | ||
293 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { | |
0707632b | 294 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) |
2e54c14e | 295 | vid_mode = BURST_MODE; |
0707632b | 296 | else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) |
297 | vid_mode = SYNC_PULSE_MODE; | |
298 | else | |
299 | vid_mode = SYNC_EVENT_MODE; | |
2e54c14e CH |
300 | } |
301 | ||
302 | writel(vid_mode, dsi->regs + DSI_MODE_CTRL); | |
303 | } | |
304 | ||
0707632b | 305 | static void mtk_dsi_set_vm_cmd(struct mtk_dsi *dsi) |
306 | { | |
307 | mtk_dsi_mask(dsi, DSI_VM_CMD_CON, VM_CMD_EN, VM_CMD_EN); | |
308 | mtk_dsi_mask(dsi, DSI_VM_CMD_CON, TS_VFP_EN, TS_VFP_EN); | |
309 | } | |
310 | ||
80a5cfd6 | 311 | static void mtk_dsi_ps_control_vact(struct mtk_dsi *dsi) |
2e54c14e CH |
312 | { |
313 | struct videomode *vm = &dsi->vm; | |
314 | u32 dsi_buf_bpp, ps_wc; | |
315 | u32 ps_bpp_mode; | |
316 | ||
317 | if (dsi->format == MIPI_DSI_FMT_RGB565) | |
318 | dsi_buf_bpp = 2; | |
319 | else | |
320 | dsi_buf_bpp = 3; | |
321 | ||
322 | ps_wc = vm->hactive * dsi_buf_bpp; | |
323 | ps_bpp_mode = ps_wc; | |
324 | ||
325 | switch (dsi->format) { | |
326 | case MIPI_DSI_FMT_RGB888: | |
327 | ps_bpp_mode |= PACKED_PS_24BIT_RGB888; | |
328 | break; | |
329 | case MIPI_DSI_FMT_RGB666: | |
330 | ps_bpp_mode |= PACKED_PS_18BIT_RGB666; | |
331 | break; | |
332 | case MIPI_DSI_FMT_RGB666_PACKED: | |
333 | ps_bpp_mode |= LOOSELY_PS_18BIT_RGB666; | |
334 | break; | |
335 | case MIPI_DSI_FMT_RGB565: | |
336 | ps_bpp_mode |= PACKED_PS_16BIT_RGB565; | |
337 | break; | |
338 | } | |
339 | ||
340 | writel(vm->vactive, dsi->regs + DSI_VACT_NL); | |
341 | writel(ps_bpp_mode, dsi->regs + DSI_PSCTRL); | |
342 | writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC); | |
343 | } | |
344 | ||
80a5cfd6 | 345 | static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi) |
2e54c14e CH |
346 | { |
347 | u32 tmp_reg; | |
348 | ||
349 | switch (dsi->lanes) { | |
350 | case 1: | |
351 | tmp_reg = 1 << 2; | |
352 | break; | |
353 | case 2: | |
354 | tmp_reg = 3 << 2; | |
355 | break; | |
356 | case 3: | |
357 | tmp_reg = 7 << 2; | |
358 | break; | |
359 | case 4: | |
360 | tmp_reg = 0xf << 2; | |
361 | break; | |
362 | default: | |
363 | tmp_reg = 0xf << 2; | |
364 | break; | |
365 | } | |
366 | ||
2d52bfba | 367 | tmp_reg |= (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6; |
368 | tmp_reg |= (dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3; | |
369 | ||
2e54c14e CH |
370 | writel(tmp_reg, dsi->regs + DSI_TXRX_CTRL); |
371 | } | |
372 | ||
80a5cfd6 | 373 | static void mtk_dsi_ps_control(struct mtk_dsi *dsi) |
2e54c14e | 374 | { |
80a5cfd6 | 375 | u32 dsi_tmp_buf_bpp; |
2e54c14e CH |
376 | u32 tmp_reg; |
377 | ||
378 | switch (dsi->format) { | |
379 | case MIPI_DSI_FMT_RGB888: | |
380 | tmp_reg = PACKED_PS_24BIT_RGB888; | |
381 | dsi_tmp_buf_bpp = 3; | |
382 | break; | |
383 | case MIPI_DSI_FMT_RGB666: | |
384 | tmp_reg = LOOSELY_PS_18BIT_RGB666; | |
385 | dsi_tmp_buf_bpp = 3; | |
386 | break; | |
387 | case MIPI_DSI_FMT_RGB666_PACKED: | |
388 | tmp_reg = PACKED_PS_18BIT_RGB666; | |
389 | dsi_tmp_buf_bpp = 3; | |
390 | break; | |
391 | case MIPI_DSI_FMT_RGB565: | |
392 | tmp_reg = PACKED_PS_16BIT_RGB565; | |
393 | dsi_tmp_buf_bpp = 2; | |
394 | break; | |
395 | default: | |
396 | tmp_reg = PACKED_PS_24BIT_RGB888; | |
397 | dsi_tmp_buf_bpp = 3; | |
398 | break; | |
399 | } | |
400 | ||
401 | tmp_reg += dsi->vm.hactive * dsi_tmp_buf_bpp & DSI_PS_WC; | |
402 | writel(tmp_reg, dsi->regs + DSI_PSCTRL); | |
403 | } | |
404 | ||
80a5cfd6 | 405 | static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi) |
2e54c14e | 406 | { |
80a5cfd6 | 407 | u32 horizontal_sync_active_byte; |
408 | u32 horizontal_backporch_byte; | |
409 | u32 horizontal_frontporch_byte; | |
410 | u32 dsi_tmp_buf_bpp; | |
2e54c14e CH |
411 | |
412 | struct videomode *vm = &dsi->vm; | |
413 | ||
414 | if (dsi->format == MIPI_DSI_FMT_RGB565) | |
415 | dsi_tmp_buf_bpp = 2; | |
416 | else | |
417 | dsi_tmp_buf_bpp = 3; | |
418 | ||
419 | writel(vm->vsync_len, dsi->regs + DSI_VSA_NL); | |
420 | writel(vm->vback_porch, dsi->regs + DSI_VBP_NL); | |
421 | writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL); | |
422 | writel(vm->vactive, dsi->regs + DSI_VACT_NL); | |
423 | ||
424 | horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10); | |
425 | ||
426 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) | |
427 | horizontal_backporch_byte = | |
428 | (vm->hback_porch * dsi_tmp_buf_bpp - 10); | |
429 | else | |
430 | horizontal_backporch_byte = ((vm->hback_porch + vm->hsync_len) * | |
431 | dsi_tmp_buf_bpp - 10); | |
432 | ||
433 | horizontal_frontporch_byte = (vm->hfront_porch * dsi_tmp_buf_bpp - 12); | |
434 | ||
435 | writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC); | |
436 | writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC); | |
437 | writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC); | |
438 | ||
80a5cfd6 | 439 | mtk_dsi_ps_control(dsi); |
2e54c14e CH |
440 | } |
441 | ||
442 | static void mtk_dsi_start(struct mtk_dsi *dsi) | |
443 | { | |
444 | writel(0, dsi->regs + DSI_START); | |
445 | writel(1, dsi->regs + DSI_START); | |
446 | } | |
447 | ||
0707632b | 448 | static void mtk_dsi_stop(struct mtk_dsi *dsi) |
449 | { | |
450 | writel(0, dsi->regs + DSI_START); | |
451 | } | |
452 | ||
453 | static void mtk_dsi_set_cmd_mode(struct mtk_dsi *dsi) | |
454 | { | |
455 | writel(CMD_MODE, dsi->regs + DSI_MODE_CTRL); | |
456 | } | |
457 | ||
dd5080a5 | 458 | static void mtk_dsi_set_interrupt_enable(struct mtk_dsi *dsi) |
459 | { | |
460 | u32 inten = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG; | |
461 | ||
462 | writel(inten, dsi->regs + DSI_INTEN); | |
463 | } | |
464 | ||
465 | static void mtk_dsi_irq_data_set(struct mtk_dsi *dsi, u32 irq_bit) | |
466 | { | |
467 | dsi->irq_data |= irq_bit; | |
468 | } | |
469 | ||
21898816 | 470 | static void mtk_dsi_irq_data_clear(struct mtk_dsi *dsi, u32 irq_bit) |
dd5080a5 | 471 | { |
472 | dsi->irq_data &= ~irq_bit; | |
473 | } | |
474 | ||
21898816 | 475 | static s32 mtk_dsi_wait_for_irq_done(struct mtk_dsi *dsi, u32 irq_flag, |
dd5080a5 | 476 | unsigned int timeout) |
477 | { | |
478 | s32 ret = 0; | |
479 | unsigned long jiffies = msecs_to_jiffies(timeout); | |
480 | ||
481 | ret = wait_event_interruptible_timeout(dsi->irq_wait_queue, | |
482 | dsi->irq_data & irq_flag, | |
483 | jiffies); | |
484 | if (ret == 0) { | |
485 | DRM_WARN("Wait DSI IRQ(0x%08x) Timeout\n", irq_flag); | |
486 | ||
487 | mtk_dsi_enable(dsi); | |
488 | mtk_dsi_reset_engine(dsi); | |
489 | } | |
490 | ||
491 | return ret; | |
492 | } | |
493 | ||
494 | static irqreturn_t mtk_dsi_irq(int irq, void *dev_id) | |
495 | { | |
496 | struct mtk_dsi *dsi = dev_id; | |
497 | u32 status, tmp; | |
498 | u32 flag = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG; | |
499 | ||
500 | status = readl(dsi->regs + DSI_INTSTA) & flag; | |
501 | ||
502 | if (status) { | |
503 | do { | |
504 | mtk_dsi_mask(dsi, DSI_RACK, RACK, RACK); | |
505 | tmp = readl(dsi->regs + DSI_INTSTA); | |
506 | } while (tmp & DSI_BUSY); | |
507 | ||
508 | mtk_dsi_mask(dsi, DSI_INTSTA, status, 0); | |
509 | mtk_dsi_irq_data_set(dsi, status); | |
510 | wake_up_interruptible(&dsi->irq_wait_queue); | |
511 | } | |
512 | ||
513 | return IRQ_HANDLED; | |
514 | } | |
515 | ||
0707632b | 516 | static s32 mtk_dsi_switch_to_cmd_mode(struct mtk_dsi *dsi, u8 irq_flag, u32 t) |
517 | { | |
518 | mtk_dsi_irq_data_clear(dsi, irq_flag); | |
519 | mtk_dsi_set_cmd_mode(dsi); | |
520 | ||
521 | if (!mtk_dsi_wait_for_irq_done(dsi, irq_flag, t)) { | |
522 | DRM_ERROR("failed to switch cmd mode\n"); | |
523 | return -ETIME; | |
524 | } else { | |
525 | return 0; | |
526 | } | |
527 | } | |
528 | ||
529 | static int mtk_dsi_poweron(struct mtk_dsi *dsi) | |
530 | { | |
531 | struct device *dev = dsi->dev; | |
532 | int ret; | |
533 | u64 pixel_clock, total_bits; | |
534 | u32 htotal, htotal_bits, bit_per_pixel, overhead_cycles, overhead_bits; | |
535 | ||
536 | if (++dsi->refcount != 1) | |
537 | return 0; | |
538 | ||
539 | switch (dsi->format) { | |
540 | case MIPI_DSI_FMT_RGB565: | |
541 | bit_per_pixel = 16; | |
542 | break; | |
543 | case MIPI_DSI_FMT_RGB666_PACKED: | |
544 | bit_per_pixel = 18; | |
545 | break; | |
546 | case MIPI_DSI_FMT_RGB666: | |
547 | case MIPI_DSI_FMT_RGB888: | |
548 | default: | |
549 | bit_per_pixel = 24; | |
550 | break; | |
551 | } | |
552 | ||
553 | /** | |
0707632b | 554 | * htotal_time = htotal * byte_per_pixel / num_lanes |
555 | * overhead_time = lpx + hs_prepare + hs_zero + hs_trail + hs_exit | |
556 | * mipi_ratio = (htotal_time + overhead_time) / htotal_time | |
557 | * data_rate = pixel_clock * bit_per_pixel * mipi_ratio / num_lanes; | |
558 | */ | |
72ac6969 | 559 | pixel_clock = dsi->vm.pixelclock; |
0707632b | 560 | htotal = dsi->vm.hactive + dsi->vm.hback_porch + dsi->vm.hfront_porch + |
561 | dsi->vm.hsync_len; | |
562 | htotal_bits = htotal * bit_per_pixel; | |
563 | ||
564 | overhead_cycles = T_LPX + T_HS_PREP + T_HS_ZERO + T_HS_TRAIL + | |
565 | T_HS_EXIT; | |
566 | overhead_bits = overhead_cycles * dsi->lanes * 8; | |
567 | total_bits = htotal_bits + overhead_bits; | |
568 | ||
569 | dsi->data_rate = DIV_ROUND_UP_ULL(pixel_clock * total_bits, | |
570 | htotal * dsi->lanes); | |
571 | ||
572 | ret = clk_set_rate(dsi->hs_clk, dsi->data_rate); | |
573 | if (ret < 0) { | |
574 | dev_err(dev, "Failed to set data rate: %d\n", ret); | |
575 | goto err_refcount; | |
576 | } | |
577 | ||
578 | phy_power_on(dsi->phy); | |
579 | ||
580 | ret = clk_prepare_enable(dsi->engine_clk); | |
581 | if (ret < 0) { | |
582 | dev_err(dev, "Failed to enable engine clock: %d\n", ret); | |
583 | goto err_phy_power_off; | |
584 | } | |
585 | ||
586 | ret = clk_prepare_enable(dsi->digital_clk); | |
587 | if (ret < 0) { | |
588 | dev_err(dev, "Failed to enable digital clock: %d\n", ret); | |
589 | goto err_disable_engine_clk; | |
590 | } | |
591 | ||
592 | mtk_dsi_enable(dsi); | |
593 | mtk_dsi_reset_engine(dsi); | |
594 | mtk_dsi_phy_timconfig(dsi); | |
595 | ||
596 | mtk_dsi_rxtx_control(dsi); | |
597 | mtk_dsi_ps_control_vact(dsi); | |
598 | mtk_dsi_set_vm_cmd(dsi); | |
599 | mtk_dsi_config_vdo_timing(dsi); | |
600 | mtk_dsi_set_interrupt_enable(dsi); | |
601 | ||
602 | mtk_dsi_clk_ulp_mode_leave(dsi); | |
603 | mtk_dsi_lane0_ulp_mode_leave(dsi); | |
604 | mtk_dsi_clk_hs_mode(dsi, 0); | |
605 | ||
606 | if (dsi->panel) { | |
607 | if (drm_panel_prepare(dsi->panel)) { | |
608 | DRM_ERROR("failed to prepare the panel\n"); | |
609 | goto err_disable_digital_clk; | |
610 | } | |
611 | } | |
612 | ||
613 | return 0; | |
614 | err_disable_digital_clk: | |
615 | clk_disable_unprepare(dsi->digital_clk); | |
616 | err_disable_engine_clk: | |
617 | clk_disable_unprepare(dsi->engine_clk); | |
618 | err_phy_power_off: | |
619 | phy_power_off(dsi->phy); | |
620 | err_refcount: | |
621 | dsi->refcount--; | |
622 | return ret; | |
623 | } | |
624 | ||
2e54c14e CH |
625 | static void mtk_dsi_poweroff(struct mtk_dsi *dsi) |
626 | { | |
627 | if (WARN_ON(dsi->refcount == 0)) | |
628 | return; | |
629 | ||
630 | if (--dsi->refcount != 0) | |
631 | return; | |
632 | ||
0707632b | 633 | if (!mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, 500)) { |
634 | if (dsi->panel) { | |
635 | if (drm_panel_unprepare(dsi->panel)) { | |
636 | DRM_ERROR("failed to unprepare the panel\n"); | |
637 | return; | |
638 | } | |
639 | } | |
640 | } | |
641 | ||
642 | mtk_dsi_reset_engine(dsi); | |
80a5cfd6 | 643 | mtk_dsi_lane0_ulp_mode_enter(dsi); |
644 | mtk_dsi_clk_ulp_mode_enter(dsi); | |
2e54c14e CH |
645 | |
646 | mtk_dsi_disable(dsi); | |
647 | ||
648 | clk_disable_unprepare(dsi->engine_clk); | |
649 | clk_disable_unprepare(dsi->digital_clk); | |
650 | ||
651 | phy_power_off(dsi->phy); | |
652 | } | |
653 | ||
654 | static void mtk_output_dsi_enable(struct mtk_dsi *dsi) | |
655 | { | |
656 | int ret; | |
657 | ||
658 | if (dsi->enabled) | |
659 | return; | |
660 | ||
2e54c14e CH |
661 | ret = mtk_dsi_poweron(dsi); |
662 | if (ret < 0) { | |
663 | DRM_ERROR("failed to power on dsi\n"); | |
664 | return; | |
665 | } | |
666 | ||
80a5cfd6 | 667 | mtk_dsi_set_mode(dsi); |
668 | mtk_dsi_clk_hs_mode(dsi, 1); | |
2e54c14e CH |
669 | |
670 | mtk_dsi_start(dsi); | |
671 | ||
0707632b | 672 | if (dsi->panel) { |
673 | if (drm_panel_enable(dsi->panel)) { | |
674 | DRM_ERROR("failed to enable the panel\n"); | |
675 | goto err_dsi_power_off; | |
676 | } | |
677 | } | |
678 | ||
2e54c14e | 679 | dsi->enabled = true; |
0707632b | 680 | |
681 | return; | |
682 | err_dsi_power_off: | |
683 | mtk_dsi_stop(dsi); | |
684 | mtk_dsi_poweroff(dsi); | |
2e54c14e CH |
685 | } |
686 | ||
687 | static void mtk_output_dsi_disable(struct mtk_dsi *dsi) | |
688 | { | |
689 | if (!dsi->enabled) | |
690 | return; | |
691 | ||
692 | if (dsi->panel) { | |
693 | if (drm_panel_disable(dsi->panel)) { | |
694 | DRM_ERROR("failed to disable the panel\n"); | |
695 | return; | |
696 | } | |
697 | } | |
698 | ||
0707632b | 699 | mtk_dsi_stop(dsi); |
2e54c14e CH |
700 | mtk_dsi_poweroff(dsi); |
701 | ||
702 | dsi->enabled = false; | |
703 | } | |
704 | ||
705 | static void mtk_dsi_encoder_destroy(struct drm_encoder *encoder) | |
706 | { | |
707 | drm_encoder_cleanup(encoder); | |
708 | } | |
709 | ||
710 | static const struct drm_encoder_funcs mtk_dsi_encoder_funcs = { | |
711 | .destroy = mtk_dsi_encoder_destroy, | |
712 | }; | |
713 | ||
714 | static bool mtk_dsi_encoder_mode_fixup(struct drm_encoder *encoder, | |
715 | const struct drm_display_mode *mode, | |
716 | struct drm_display_mode *adjusted_mode) | |
717 | { | |
718 | return true; | |
719 | } | |
720 | ||
721 | static void mtk_dsi_encoder_mode_set(struct drm_encoder *encoder, | |
722 | struct drm_display_mode *mode, | |
723 | struct drm_display_mode *adjusted) | |
724 | { | |
725 | struct mtk_dsi *dsi = encoder_to_dsi(encoder); | |
726 | ||
72ac6969 | 727 | drm_display_mode_to_videomode(adjusted, &dsi->vm); |
2e54c14e CH |
728 | } |
729 | ||
730 | static void mtk_dsi_encoder_disable(struct drm_encoder *encoder) | |
731 | { | |
732 | struct mtk_dsi *dsi = encoder_to_dsi(encoder); | |
733 | ||
734 | mtk_output_dsi_disable(dsi); | |
735 | } | |
736 | ||
737 | static void mtk_dsi_encoder_enable(struct drm_encoder *encoder) | |
738 | { | |
739 | struct mtk_dsi *dsi = encoder_to_dsi(encoder); | |
740 | ||
741 | mtk_output_dsi_enable(dsi); | |
742 | } | |
743 | ||
2e54c14e CH |
744 | static int mtk_dsi_connector_get_modes(struct drm_connector *connector) |
745 | { | |
746 | struct mtk_dsi *dsi = connector_to_dsi(connector); | |
747 | ||
748 | return drm_panel_get_modes(dsi->panel); | |
749 | } | |
750 | ||
2e54c14e CH |
751 | static const struct drm_encoder_helper_funcs mtk_dsi_encoder_helper_funcs = { |
752 | .mode_fixup = mtk_dsi_encoder_mode_fixup, | |
753 | .mode_set = mtk_dsi_encoder_mode_set, | |
754 | .disable = mtk_dsi_encoder_disable, | |
755 | .enable = mtk_dsi_encoder_enable, | |
756 | }; | |
757 | ||
758 | static const struct drm_connector_funcs mtk_dsi_connector_funcs = { | |
2e54c14e CH |
759 | .fill_modes = drm_helper_probe_single_connector_modes, |
760 | .destroy = drm_connector_cleanup, | |
761 | .reset = drm_atomic_helper_connector_reset, | |
762 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, | |
763 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, | |
764 | }; | |
765 | ||
766 | static const struct drm_connector_helper_funcs | |
767 | mtk_dsi_connector_helper_funcs = { | |
768 | .get_modes = mtk_dsi_connector_get_modes, | |
2e54c14e CH |
769 | }; |
770 | ||
2e54c14e CH |
771 | static int mtk_dsi_create_connector(struct drm_device *drm, struct mtk_dsi *dsi) |
772 | { | |
773 | int ret; | |
774 | ||
775 | ret = drm_connector_init(drm, &dsi->conn, &mtk_dsi_connector_funcs, | |
776 | DRM_MODE_CONNECTOR_DSI); | |
777 | if (ret) { | |
778 | DRM_ERROR("Failed to connector init to drm\n"); | |
779 | return ret; | |
780 | } | |
781 | ||
782 | drm_connector_helper_add(&dsi->conn, &mtk_dsi_connector_helper_funcs); | |
783 | ||
784 | dsi->conn.dpms = DRM_MODE_DPMS_OFF; | |
cde4c44d | 785 | drm_connector_attach_encoder(&dsi->conn, &dsi->encoder); |
2e54c14e CH |
786 | |
787 | if (dsi->panel) { | |
788 | ret = drm_panel_attach(dsi->panel, &dsi->conn); | |
789 | if (ret) { | |
790 | DRM_ERROR("Failed to attach panel to drm\n"); | |
791 | goto err_connector_cleanup; | |
792 | } | |
793 | } | |
794 | ||
795 | return 0; | |
796 | ||
797 | err_connector_cleanup: | |
798 | drm_connector_cleanup(&dsi->conn); | |
799 | return ret; | |
800 | } | |
801 | ||
802 | static int mtk_dsi_create_conn_enc(struct drm_device *drm, struct mtk_dsi *dsi) | |
803 | { | |
804 | int ret; | |
805 | ||
806 | ret = drm_encoder_init(drm, &dsi->encoder, &mtk_dsi_encoder_funcs, | |
807 | DRM_MODE_ENCODER_DSI, NULL); | |
808 | if (ret) { | |
809 | DRM_ERROR("Failed to encoder init to drm\n"); | |
810 | return ret; | |
811 | } | |
812 | drm_encoder_helper_add(&dsi->encoder, &mtk_dsi_encoder_helper_funcs); | |
813 | ||
814 | /* | |
815 | * Currently display data paths are statically assigned to a crtc each. | |
816 | * crtc 0 is OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 | |
817 | */ | |
818 | dsi->encoder.possible_crtcs = 1; | |
819 | ||
820 | /* If there's a bridge, attach to it and let it create the connector */ | |
a0071bc4 NB |
821 | if (dsi->bridge) { |
822 | ret = drm_bridge_attach(&dsi->encoder, dsi->bridge, NULL); | |
823 | if (ret) { | |
824 | DRM_ERROR("Failed to attach bridge to drm\n"); | |
825 | goto err_encoder_cleanup; | |
826 | } | |
827 | } else { | |
2e54c14e CH |
828 | /* Otherwise create our own connector and attach to a panel */ |
829 | ret = mtk_dsi_create_connector(drm, dsi); | |
830 | if (ret) | |
831 | goto err_encoder_cleanup; | |
832 | } | |
833 | ||
834 | return 0; | |
835 | ||
836 | err_encoder_cleanup: | |
837 | drm_encoder_cleanup(&dsi->encoder); | |
838 | return ret; | |
839 | } | |
840 | ||
841 | static void mtk_dsi_destroy_conn_enc(struct mtk_dsi *dsi) | |
842 | { | |
843 | drm_encoder_cleanup(&dsi->encoder); | |
844 | /* Skip connector cleanup if creation was delegated to the bridge */ | |
2ea9f317 | 845 | if (dsi->conn.dev) |
2e54c14e | 846 | drm_connector_cleanup(&dsi->conn); |
2e54c14e CH |
847 | } |
848 | ||
849 | static void mtk_dsi_ddp_start(struct mtk_ddp_comp *comp) | |
850 | { | |
851 | struct mtk_dsi *dsi = container_of(comp, struct mtk_dsi, ddp_comp); | |
852 | ||
853 | mtk_dsi_poweron(dsi); | |
854 | } | |
855 | ||
856 | static void mtk_dsi_ddp_stop(struct mtk_ddp_comp *comp) | |
857 | { | |
858 | struct mtk_dsi *dsi = container_of(comp, struct mtk_dsi, ddp_comp); | |
859 | ||
860 | mtk_dsi_poweroff(dsi); | |
861 | } | |
862 | ||
863 | static const struct mtk_ddp_comp_funcs mtk_dsi_funcs = { | |
864 | .start = mtk_dsi_ddp_start, | |
865 | .stop = mtk_dsi_ddp_stop, | |
866 | }; | |
867 | ||
868 | static int mtk_dsi_host_attach(struct mipi_dsi_host *host, | |
869 | struct mipi_dsi_device *device) | |
870 | { | |
871 | struct mtk_dsi *dsi = host_to_dsi(host); | |
872 | ||
873 | dsi->lanes = device->lanes; | |
874 | dsi->format = device->format; | |
875 | dsi->mode_flags = device->mode_flags; | |
876 | ||
877 | if (dsi->conn.dev) | |
878 | drm_helper_hpd_irq_event(dsi->conn.dev); | |
879 | ||
880 | return 0; | |
881 | } | |
882 | ||
883 | static int mtk_dsi_host_detach(struct mipi_dsi_host *host, | |
884 | struct mipi_dsi_device *device) | |
885 | { | |
886 | struct mtk_dsi *dsi = host_to_dsi(host); | |
887 | ||
888 | if (dsi->conn.dev) | |
889 | drm_helper_hpd_irq_event(dsi->conn.dev); | |
890 | ||
891 | return 0; | |
892 | } | |
893 | ||
21898816 | 894 | static void mtk_dsi_wait_for_idle(struct mtk_dsi *dsi) |
895 | { | |
f752413e DC |
896 | int ret; |
897 | u32 val; | |
21898816 | 898 | |
f752413e DC |
899 | ret = readl_poll_timeout(dsi->regs + DSI_INTSTA, val, !(val & DSI_BUSY), |
900 | 4, 2000000); | |
901 | if (ret) { | |
21898816 | 902 | DRM_WARN("polling dsi wait not busy timeout!\n"); |
903 | ||
904 | mtk_dsi_enable(dsi); | |
905 | mtk_dsi_reset_engine(dsi); | |
906 | } | |
907 | } | |
908 | ||
909 | static u32 mtk_dsi_recv_cnt(u8 type, u8 *read_data) | |
910 | { | |
911 | switch (type) { | |
912 | case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: | |
913 | case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: | |
914 | return 1; | |
915 | case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: | |
916 | case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: | |
917 | return 2; | |
918 | case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE: | |
919 | case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE: | |
920 | return read_data[1] + read_data[2] * 16; | |
921 | case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: | |
922 | DRM_INFO("type is 0x02, try again\n"); | |
923 | break; | |
924 | default: | |
afd89636 | 925 | DRM_INFO("type(0x%x) not recognized\n", type); |
21898816 | 926 | break; |
927 | } | |
928 | ||
929 | return 0; | |
930 | } | |
931 | ||
932 | static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct mipi_dsi_msg *msg) | |
933 | { | |
934 | const char *tx_buf = msg->tx_buf; | |
935 | u8 config, cmdq_size, cmdq_off, type = msg->type; | |
936 | u32 reg_val, cmdq_mask, i; | |
937 | ||
938 | if (MTK_DSI_HOST_IS_READ(type)) | |
939 | config = BTA; | |
940 | else | |
941 | config = (msg->tx_len > 2) ? LONG_PACKET : SHORT_PACKET; | |
942 | ||
943 | if (msg->tx_len > 2) { | |
944 | cmdq_size = 1 + (msg->tx_len + 3) / 4; | |
945 | cmdq_off = 4; | |
946 | cmdq_mask = CONFIG | DATA_ID | DATA_0 | DATA_1; | |
947 | reg_val = (msg->tx_len << 16) | (type << 8) | config; | |
948 | } else { | |
949 | cmdq_size = 1; | |
950 | cmdq_off = 2; | |
951 | cmdq_mask = CONFIG | DATA_ID; | |
952 | reg_val = (type << 8) | config; | |
953 | } | |
954 | ||
955 | for (i = 0; i < msg->tx_len; i++) | |
956 | writeb(tx_buf[i], dsi->regs + DSI_CMDQ0 + cmdq_off + i); | |
957 | ||
958 | mtk_dsi_mask(dsi, DSI_CMDQ0, cmdq_mask, reg_val); | |
959 | mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size); | |
960 | } | |
961 | ||
962 | static ssize_t mtk_dsi_host_send_cmd(struct mtk_dsi *dsi, | |
963 | const struct mipi_dsi_msg *msg, u8 flag) | |
964 | { | |
965 | mtk_dsi_wait_for_idle(dsi); | |
966 | mtk_dsi_irq_data_clear(dsi, flag); | |
967 | mtk_dsi_cmdq(dsi, msg); | |
968 | mtk_dsi_start(dsi); | |
969 | ||
970 | if (!mtk_dsi_wait_for_irq_done(dsi, flag, 2000)) | |
971 | return -ETIME; | |
972 | else | |
973 | return 0; | |
974 | } | |
975 | ||
976 | static ssize_t mtk_dsi_host_transfer(struct mipi_dsi_host *host, | |
977 | const struct mipi_dsi_msg *msg) | |
978 | { | |
979 | struct mtk_dsi *dsi = host_to_dsi(host); | |
980 | u32 recv_cnt, i; | |
981 | u8 read_data[16]; | |
982 | void *src_addr; | |
983 | u8 irq_flag = CMD_DONE_INT_FLAG; | |
984 | ||
985 | if (readl(dsi->regs + DSI_MODE_CTRL) & MODE) { | |
986 | DRM_ERROR("dsi engine is not command mode\n"); | |
987 | return -EINVAL; | |
988 | } | |
989 | ||
990 | if (MTK_DSI_HOST_IS_READ(msg->type)) | |
991 | irq_flag |= LPRX_RD_RDY_INT_FLAG; | |
992 | ||
993 | if (mtk_dsi_host_send_cmd(dsi, msg, irq_flag) < 0) | |
994 | return -ETIME; | |
995 | ||
996 | if (!MTK_DSI_HOST_IS_READ(msg->type)) | |
997 | return 0; | |
998 | ||
999 | if (!msg->rx_buf) { | |
1000 | DRM_ERROR("dsi receive buffer size may be NULL\n"); | |
1001 | return -EINVAL; | |
1002 | } | |
1003 | ||
1004 | for (i = 0; i < 16; i++) | |
1005 | *(read_data + i) = readb(dsi->regs + DSI_RX_DATA0 + i); | |
1006 | ||
1007 | recv_cnt = mtk_dsi_recv_cnt(read_data[0], read_data); | |
1008 | ||
1009 | if (recv_cnt > 2) | |
1010 | src_addr = &read_data[4]; | |
1011 | else | |
1012 | src_addr = &read_data[1]; | |
1013 | ||
1014 | if (recv_cnt > 10) | |
1015 | recv_cnt = 10; | |
1016 | ||
1017 | if (recv_cnt > msg->rx_len) | |
1018 | recv_cnt = msg->rx_len; | |
1019 | ||
1020 | if (recv_cnt) | |
1021 | memcpy(msg->rx_buf, src_addr, recv_cnt); | |
1022 | ||
1023 | DRM_INFO("dsi get %d byte data from the panel address(0x%x)\n", | |
1024 | recv_cnt, *((u8 *)(msg->tx_buf))); | |
1025 | ||
1026 | return recv_cnt; | |
1027 | } | |
1028 | ||
2e54c14e CH |
1029 | static const struct mipi_dsi_host_ops mtk_dsi_ops = { |
1030 | .attach = mtk_dsi_host_attach, | |
1031 | .detach = mtk_dsi_host_detach, | |
21898816 | 1032 | .transfer = mtk_dsi_host_transfer, |
2e54c14e CH |
1033 | }; |
1034 | ||
1035 | static int mtk_dsi_bind(struct device *dev, struct device *master, void *data) | |
1036 | { | |
1037 | int ret; | |
1038 | struct drm_device *drm = data; | |
1039 | struct mtk_dsi *dsi = dev_get_drvdata(dev); | |
1040 | ||
1041 | ret = mtk_ddp_comp_register(drm, &dsi->ddp_comp); | |
1042 | if (ret < 0) { | |
4bf99144 RH |
1043 | dev_err(dev, "Failed to register component %pOF: %d\n", |
1044 | dev->of_node, ret); | |
2e54c14e CH |
1045 | return ret; |
1046 | } | |
1047 | ||
1048 | ret = mipi_dsi_host_register(&dsi->host); | |
1049 | if (ret < 0) { | |
1050 | dev_err(dev, "failed to register DSI host: %d\n", ret); | |
1051 | goto err_ddp_comp_unregister; | |
1052 | } | |
1053 | ||
1054 | ret = mtk_dsi_create_conn_enc(drm, dsi); | |
1055 | if (ret) { | |
1056 | DRM_ERROR("Encoder create failed with %d\n", ret); | |
1057 | goto err_unregister; | |
1058 | } | |
1059 | ||
1060 | return 0; | |
1061 | ||
1062 | err_unregister: | |
1063 | mipi_dsi_host_unregister(&dsi->host); | |
1064 | err_ddp_comp_unregister: | |
1065 | mtk_ddp_comp_unregister(drm, &dsi->ddp_comp); | |
1066 | return ret; | |
1067 | } | |
1068 | ||
1069 | static void mtk_dsi_unbind(struct device *dev, struct device *master, | |
1070 | void *data) | |
1071 | { | |
1072 | struct drm_device *drm = data; | |
1073 | struct mtk_dsi *dsi = dev_get_drvdata(dev); | |
1074 | ||
1075 | mtk_dsi_destroy_conn_enc(dsi); | |
1076 | mipi_dsi_host_unregister(&dsi->host); | |
1077 | mtk_ddp_comp_unregister(drm, &dsi->ddp_comp); | |
1078 | } | |
1079 | ||
1080 | static const struct component_ops mtk_dsi_component_ops = { | |
1081 | .bind = mtk_dsi_bind, | |
1082 | .unbind = mtk_dsi_unbind, | |
1083 | }; | |
1084 | ||
1085 | static int mtk_dsi_probe(struct platform_device *pdev) | |
1086 | { | |
1087 | struct mtk_dsi *dsi; | |
1088 | struct device *dev = &pdev->dev; | |
2e54c14e | 1089 | struct resource *regs; |
dd5080a5 | 1090 | int irq_num; |
2e54c14e CH |
1091 | int comp_id; |
1092 | int ret; | |
1093 | ||
1094 | dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); | |
1095 | if (!dsi) | |
1096 | return -ENOMEM; | |
1097 | ||
1098 | dsi->host.ops = &mtk_dsi_ops; | |
1099 | dsi->host.dev = dev; | |
1100 | ||
ebc94461 RH |
1101 | ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0, |
1102 | &dsi->panel, &dsi->bridge); | |
1103 | if (ret) | |
1104 | return ret; | |
2e54c14e CH |
1105 | |
1106 | dsi->engine_clk = devm_clk_get(dev, "engine"); | |
1107 | if (IS_ERR(dsi->engine_clk)) { | |
1108 | ret = PTR_ERR(dsi->engine_clk); | |
1109 | dev_err(dev, "Failed to get engine clock: %d\n", ret); | |
1110 | return ret; | |
1111 | } | |
1112 | ||
1113 | dsi->digital_clk = devm_clk_get(dev, "digital"); | |
1114 | if (IS_ERR(dsi->digital_clk)) { | |
1115 | ret = PTR_ERR(dsi->digital_clk); | |
1116 | dev_err(dev, "Failed to get digital clock: %d\n", ret); | |
1117 | return ret; | |
1118 | } | |
1119 | ||
1120 | dsi->hs_clk = devm_clk_get(dev, "hs"); | |
1121 | if (IS_ERR(dsi->hs_clk)) { | |
1122 | ret = PTR_ERR(dsi->hs_clk); | |
1123 | dev_err(dev, "Failed to get hs clock: %d\n", ret); | |
1124 | return ret; | |
1125 | } | |
1126 | ||
1127 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1128 | dsi->regs = devm_ioremap_resource(dev, regs); | |
1129 | if (IS_ERR(dsi->regs)) { | |
1130 | ret = PTR_ERR(dsi->regs); | |
1131 | dev_err(dev, "Failed to ioremap memory: %d\n", ret); | |
1132 | return ret; | |
1133 | } | |
1134 | ||
1135 | dsi->phy = devm_phy_get(dev, "dphy"); | |
1136 | if (IS_ERR(dsi->phy)) { | |
1137 | ret = PTR_ERR(dsi->phy); | |
1138 | dev_err(dev, "Failed to get MIPI-DPHY: %d\n", ret); | |
1139 | return ret; | |
1140 | } | |
1141 | ||
1142 | comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DSI); | |
1143 | if (comp_id < 0) { | |
1144 | dev_err(dev, "Failed to identify by alias: %d\n", comp_id); | |
1145 | return comp_id; | |
1146 | } | |
1147 | ||
1148 | ret = mtk_ddp_comp_init(dev, dev->of_node, &dsi->ddp_comp, comp_id, | |
1149 | &mtk_dsi_funcs); | |
1150 | if (ret) { | |
1151 | dev_err(dev, "Failed to initialize component: %d\n", ret); | |
1152 | return ret; | |
1153 | } | |
1154 | ||
dd5080a5 | 1155 | irq_num = platform_get_irq(pdev, 0); |
1156 | if (irq_num < 0) { | |
1157 | dev_err(&pdev->dev, "failed to request dsi irq resource\n"); | |
1158 | return -EPROBE_DEFER; | |
1159 | } | |
1160 | ||
1161 | irq_set_status_flags(irq_num, IRQ_TYPE_LEVEL_LOW); | |
1162 | ret = devm_request_irq(&pdev->dev, irq_num, mtk_dsi_irq, | |
1163 | IRQF_TRIGGER_LOW, dev_name(&pdev->dev), dsi); | |
1164 | if (ret) { | |
1165 | dev_err(&pdev->dev, "failed to request mediatek dsi irq\n"); | |
1166 | return -EPROBE_DEFER; | |
1167 | } | |
1168 | ||
1169 | init_waitqueue_head(&dsi->irq_wait_queue); | |
1170 | ||
2e54c14e CH |
1171 | platform_set_drvdata(pdev, dsi); |
1172 | ||
1173 | return component_add(&pdev->dev, &mtk_dsi_component_ops); | |
1174 | } | |
1175 | ||
1176 | static int mtk_dsi_remove(struct platform_device *pdev) | |
1177 | { | |
1178 | struct mtk_dsi *dsi = platform_get_drvdata(pdev); | |
1179 | ||
1180 | mtk_output_dsi_disable(dsi); | |
1181 | component_del(&pdev->dev, &mtk_dsi_component_ops); | |
1182 | ||
1183 | return 0; | |
1184 | } | |
1185 | ||
1186 | static const struct of_device_id mtk_dsi_of_match[] = { | |
84a5ead1 | 1187 | { .compatible = "mediatek,mt2701-dsi" }, |
2e54c14e CH |
1188 | { .compatible = "mediatek,mt8173-dsi" }, |
1189 | { }, | |
1190 | }; | |
1191 | ||
1192 | struct platform_driver mtk_dsi_driver = { | |
1193 | .probe = mtk_dsi_probe, | |
1194 | .remove = mtk_dsi_remove, | |
1195 | .driver = { | |
1196 | .name = "mtk-dsi", | |
1197 | .of_match_table = mtk_dsi_of_match, | |
1198 | }, | |
1199 | }; |