Commit | Line | Data |
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1802d0be | 1 | // SPDX-License-Identifier: GPL-2.0-only |
2e54c14e CH |
2 | /* |
3 | * Copyright (c) 2015 MediaTek Inc. | |
2e54c14e CH |
4 | */ |
5 | ||
2e54c14e CH |
6 | #include <linux/clk.h> |
7 | #include <linux/component.h> | |
f752413e | 8 | #include <linux/iopoll.h> |
dd5080a5 | 9 | #include <linux/irq.h> |
2e54c14e CH |
10 | #include <linux/of.h> |
11 | #include <linux/of_platform.h> | |
2e54c14e CH |
12 | #include <linux/phy/phy.h> |
13 | #include <linux/platform_device.h> | |
9aef5867 | 14 | |
21898816 | 15 | #include <video/mipi_display.h> |
2e54c14e CH |
16 | #include <video/videomode.h> |
17 | ||
9aef5867 | 18 | #include <drm/drm_atomic_helper.h> |
ee68c743 | 19 | #include <drm/drm_bridge.h> |
a9d9fea7 | 20 | #include <drm/drm_bridge_connector.h> |
9aef5867 SR |
21 | #include <drm/drm_mipi_dsi.h> |
22 | #include <drm/drm_of.h> | |
23 | #include <drm/drm_panel.h> | |
24 | #include <drm/drm_print.h> | |
25 | #include <drm/drm_probe_helper.h> | |
b534c4f5 | 26 | #include <drm/drm_simple_kms_helper.h> |
9aef5867 | 27 | |
2e54c14e CH |
28 | #include "mtk_drm_ddp_comp.h" |
29 | ||
2e54c14e CH |
30 | #define DSI_START 0x00 |
31 | ||
dd5080a5 | 32 | #define DSI_INTEN 0x08 |
33 | ||
34 | #define DSI_INTSTA 0x0c | |
35 | #define LPRX_RD_RDY_INT_FLAG BIT(0) | |
36 | #define CMD_DONE_INT_FLAG BIT(1) | |
37 | #define TE_RDY_INT_FLAG BIT(2) | |
38 | #define VM_DONE_INT_FLAG BIT(3) | |
39 | #define EXT_TE_RDY_INT_FLAG BIT(4) | |
40 | #define DSI_BUSY BIT(31) | |
41 | ||
2e54c14e CH |
42 | #define DSI_CON_CTRL 0x10 |
43 | #define DSI_RESET BIT(0) | |
44 | #define DSI_EN BIT(1) | |
75374fc2 | 45 | #define DPHY_RESET BIT(2) |
2e54c14e CH |
46 | |
47 | #define DSI_MODE_CTRL 0x14 | |
48 | #define MODE (3) | |
49 | #define CMD_MODE 0 | |
50 | #define SYNC_PULSE_MODE 1 | |
51 | #define SYNC_EVENT_MODE 2 | |
52 | #define BURST_MODE 3 | |
53 | #define FRM_MODE BIT(16) | |
54 | #define MIX_MODE BIT(17) | |
55 | ||
56 | #define DSI_TXRX_CTRL 0x18 | |
80a5cfd6 | 57 | #define VC_NUM BIT(1) |
2e54c14e CH |
58 | #define LANE_NUM (0xf << 2) |
59 | #define DIS_EOT BIT(6) | |
60 | #define NULL_EN BIT(7) | |
61 | #define TE_FREERUN BIT(8) | |
62 | #define EXT_TE_EN BIT(9) | |
63 | #define EXT_TE_EDGE BIT(10) | |
64 | #define MAX_RTN_SIZE (0xf << 12) | |
65 | #define HSTX_CKLP_EN BIT(16) | |
66 | ||
67 | #define DSI_PSCTRL 0x1c | |
68 | #define DSI_PS_WC 0x3fff | |
69 | #define DSI_PS_SEL (3 << 16) | |
70 | #define PACKED_PS_16BIT_RGB565 (0 << 16) | |
71 | #define LOOSELY_PS_18BIT_RGB666 (1 << 16) | |
72 | #define PACKED_PS_18BIT_RGB666 (2 << 16) | |
73 | #define PACKED_PS_24BIT_RGB888 (3 << 16) | |
74 | ||
75 | #define DSI_VSA_NL 0x20 | |
76 | #define DSI_VBP_NL 0x24 | |
77 | #define DSI_VFP_NL 0x28 | |
78 | #define DSI_VACT_NL 0x2C | |
7bf54afe | 79 | #define DSI_SIZE_CON 0x38 |
2e54c14e CH |
80 | #define DSI_HSA_WC 0x50 |
81 | #define DSI_HBP_WC 0x54 | |
82 | #define DSI_HFP_WC 0x58 | |
83 | ||
21898816 | 84 | #define DSI_CMDQ_SIZE 0x60 |
85 | #define CMDQ_SIZE 0x3f | |
86 | ||
2e54c14e CH |
87 | #define DSI_HSTX_CKL_WC 0x64 |
88 | ||
21898816 | 89 | #define DSI_RX_DATA0 0x74 |
90 | #define DSI_RX_DATA1 0x78 | |
91 | #define DSI_RX_DATA2 0x7c | |
92 | #define DSI_RX_DATA3 0x80 | |
93 | ||
dd5080a5 | 94 | #define DSI_RACK 0x84 |
95 | #define RACK BIT(0) | |
96 | ||
2e54c14e CH |
97 | #define DSI_PHY_LCCON 0x104 |
98 | #define LC_HS_TX_EN BIT(0) | |
99 | #define LC_ULPM_EN BIT(1) | |
100 | #define LC_WAKEUP_EN BIT(2) | |
101 | ||
102 | #define DSI_PHY_LD0CON 0x108 | |
103 | #define LD0_HS_TX_EN BIT(0) | |
104 | #define LD0_ULPM_EN BIT(1) | |
105 | #define LD0_WAKEUP_EN BIT(2) | |
106 | ||
107 | #define DSI_PHY_TIMECON0 0x110 | |
108 | #define LPX (0xff << 0) | |
f6c87239 | 109 | #define HS_PREP (0xff << 8) |
2e54c14e CH |
110 | #define HS_ZERO (0xff << 16) |
111 | #define HS_TRAIL (0xff << 24) | |
112 | ||
113 | #define DSI_PHY_TIMECON1 0x114 | |
114 | #define TA_GO (0xff << 0) | |
115 | #define TA_SURE (0xff << 8) | |
116 | #define TA_GET (0xff << 16) | |
117 | #define DA_HS_EXIT (0xff << 24) | |
118 | ||
119 | #define DSI_PHY_TIMECON2 0x118 | |
120 | #define CONT_DET (0xff << 0) | |
121 | #define CLK_ZERO (0xff << 16) | |
122 | #define CLK_TRAIL (0xff << 24) | |
123 | ||
124 | #define DSI_PHY_TIMECON3 0x11c | |
f6c87239 | 125 | #define CLK_HS_PREP (0xff << 0) |
2e54c14e CH |
126 | #define CLK_HS_POST (0xff << 8) |
127 | #define CLK_HS_EXIT (0xff << 16) | |
128 | ||
0707632b | 129 | #define DSI_VM_CMD_CON 0x130 |
130 | #define VM_CMD_EN BIT(0) | |
131 | #define TS_VFP_EN BIT(5) | |
132 | ||
3c6bd94d JS |
133 | #define DSI_SHADOW_DEBUG 0x190U |
134 | #define FORCE_COMMIT BIT(0) | |
135 | #define BYPASS_SHADOW BIT(1) | |
136 | ||
21898816 | 137 | #define CONFIG (0xff << 0) |
138 | #define SHORT_PACKET 0 | |
139 | #define LONG_PACKET 2 | |
140 | #define BTA BIT(2) | |
141 | #define DATA_ID (0xff << 8) | |
142 | #define DATA_0 (0xff << 16) | |
143 | #define DATA_1 (0xff << 24) | |
144 | ||
2e54c14e CH |
145 | #define NS_TO_CYCLE(n, c) ((n) / (c) + (((n) % (c)) ? 1 : 0)) |
146 | ||
21898816 | 147 | #define MTK_DSI_HOST_IS_READ(type) \ |
148 | ((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \ | |
149 | (type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \ | |
150 | (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \ | |
151 | (type == MIPI_DSI_DCS_READ)) | |
152 | ||
7a5bc4e2 JS |
153 | struct mtk_phy_timing { |
154 | u32 lpx; | |
155 | u32 da_hs_prepare; | |
156 | u32 da_hs_zero; | |
157 | u32 da_hs_trail; | |
158 | ||
159 | u32 ta_go; | |
160 | u32 ta_sure; | |
161 | u32 ta_get; | |
162 | u32 da_hs_exit; | |
163 | ||
164 | u32 clk_hs_zero; | |
165 | u32 clk_hs_trail; | |
166 | ||
167 | u32 clk_hs_prepare; | |
168 | u32 clk_hs_post; | |
169 | u32 clk_hs_exit; | |
170 | }; | |
171 | ||
2e54c14e CH |
172 | struct phy; |
173 | ||
bb6bc298 JS |
174 | struct mtk_dsi_driver_data { |
175 | const u32 reg_cmdq_off; | |
3c6bd94d | 176 | bool has_shadow_ctl; |
7bf54afe | 177 | bool has_size_ctl; |
bb6bc298 JS |
178 | }; |
179 | ||
2e54c14e CH |
180 | struct mtk_dsi { |
181 | struct mtk_ddp_comp ddp_comp; | |
182 | struct device *dev; | |
183 | struct mipi_dsi_host host; | |
184 | struct drm_encoder encoder; | |
71e780f1 | 185 | struct drm_bridge bridge; |
68a9e11b | 186 | struct drm_bridge *next_bridge; |
a9d9fea7 | 187 | struct drm_connector *connector; |
2e54c14e CH |
188 | struct phy *phy; |
189 | ||
190 | void __iomem *regs; | |
191 | ||
192 | struct clk *engine_clk; | |
193 | struct clk *digital_clk; | |
194 | struct clk *hs_clk; | |
195 | ||
196 | u32 data_rate; | |
197 | ||
198 | unsigned long mode_flags; | |
199 | enum mipi_dsi_pixel_format format; | |
200 | unsigned int lanes; | |
201 | struct videomode vm; | |
7a5bc4e2 | 202 | struct mtk_phy_timing phy_timing; |
2e54c14e CH |
203 | int refcount; |
204 | bool enabled; | |
dd5080a5 | 205 | u32 irq_data; |
206 | wait_queue_head_t irq_wait_queue; | |
bb6bc298 | 207 | const struct mtk_dsi_driver_data *driver_data; |
2e54c14e CH |
208 | }; |
209 | ||
71e780f1 | 210 | static inline struct mtk_dsi *bridge_to_dsi(struct drm_bridge *b) |
2e54c14e | 211 | { |
71e780f1 | 212 | return container_of(b, struct mtk_dsi, bridge); |
2e54c14e CH |
213 | } |
214 | ||
2e54c14e CH |
215 | static inline struct mtk_dsi *host_to_dsi(struct mipi_dsi_host *h) |
216 | { | |
217 | return container_of(h, struct mtk_dsi, host); | |
218 | } | |
219 | ||
220 | static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data) | |
221 | { | |
222 | u32 temp = readl(dsi->regs + offset); | |
223 | ||
224 | writel((temp & ~mask) | (data & mask), dsi->regs + offset); | |
225 | } | |
226 | ||
80a5cfd6 | 227 | static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi) |
2e54c14e CH |
228 | { |
229 | u32 timcon0, timcon1, timcon2, timcon3; | |
e18e0f6b | 230 | u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, 1000000); |
7a5bc4e2 JS |
231 | struct mtk_phy_timing *timing = &dsi->phy_timing; |
232 | ||
e18e0f6b JS |
233 | timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1; |
234 | timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000; | |
235 | timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 + 1 - | |
236 | timing->da_hs_prepare; | |
237 | timing->da_hs_trail = timing->da_hs_prepare + 1; | |
2e54c14e | 238 | |
e18e0f6b JS |
239 | timing->ta_go = 4 * timing->lpx - 2; |
240 | timing->ta_sure = timing->lpx + 2; | |
241 | timing->ta_get = 4 * timing->lpx; | |
242 | timing->da_hs_exit = 2 * timing->lpx + 1; | |
2e54c14e | 243 | |
e18e0f6b JS |
244 | timing->clk_hs_prepare = 70 * data_rate_mhz / (8 * 1000); |
245 | timing->clk_hs_post = timing->clk_hs_prepare + 8; | |
246 | timing->clk_hs_trail = timing->clk_hs_prepare; | |
247 | timing->clk_hs_zero = timing->clk_hs_trail * 4; | |
248 | timing->clk_hs_exit = 2 * timing->clk_hs_trail; | |
7a5bc4e2 JS |
249 | |
250 | timcon0 = timing->lpx | timing->da_hs_prepare << 8 | | |
251 | timing->da_hs_zero << 16 | timing->da_hs_trail << 24; | |
252 | timcon1 = timing->ta_go | timing->ta_sure << 8 | | |
253 | timing->ta_get << 16 | timing->da_hs_exit << 24; | |
254 | timcon2 = 1 << 8 | timing->clk_hs_zero << 16 | | |
255 | timing->clk_hs_trail << 24; | |
256 | timcon3 = timing->clk_hs_prepare | timing->clk_hs_post << 8 | | |
257 | timing->clk_hs_exit << 16; | |
2e54c14e CH |
258 | |
259 | writel(timcon0, dsi->regs + DSI_PHY_TIMECON0); | |
260 | writel(timcon1, dsi->regs + DSI_PHY_TIMECON1); | |
261 | writel(timcon2, dsi->regs + DSI_PHY_TIMECON2); | |
262 | writel(timcon3, dsi->regs + DSI_PHY_TIMECON3); | |
263 | } | |
264 | ||
265 | static void mtk_dsi_enable(struct mtk_dsi *dsi) | |
266 | { | |
267 | mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, DSI_EN); | |
268 | } | |
269 | ||
270 | static void mtk_dsi_disable(struct mtk_dsi *dsi) | |
271 | { | |
272 | mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, 0); | |
273 | } | |
274 | ||
80a5cfd6 | 275 | static void mtk_dsi_reset_engine(struct mtk_dsi *dsi) |
2e54c14e CH |
276 | { |
277 | mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, DSI_RESET); | |
278 | mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, 0); | |
279 | } | |
280 | ||
75374fc2 JS |
281 | static void mtk_dsi_reset_dphy(struct mtk_dsi *dsi) |
282 | { | |
283 | mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, DPHY_RESET); | |
284 | mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, 0); | |
285 | } | |
286 | ||
80a5cfd6 | 287 | static void mtk_dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi) |
2e54c14e CH |
288 | { |
289 | mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0); | |
290 | mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0); | |
291 | } | |
292 | ||
80a5cfd6 | 293 | static void mtk_dsi_clk_ulp_mode_leave(struct mtk_dsi *dsi) |
2e54c14e CH |
294 | { |
295 | mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0); | |
296 | mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, LC_WAKEUP_EN); | |
297 | mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, 0); | |
298 | } | |
299 | ||
80a5cfd6 | 300 | static void mtk_dsi_lane0_ulp_mode_enter(struct mtk_dsi *dsi) |
2e54c14e CH |
301 | { |
302 | mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_HS_TX_EN, 0); | |
303 | mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0); | |
304 | } | |
305 | ||
80a5cfd6 | 306 | static void mtk_dsi_lane0_ulp_mode_leave(struct mtk_dsi *dsi) |
2e54c14e CH |
307 | { |
308 | mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0); | |
309 | mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, LD0_WAKEUP_EN); | |
310 | mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, 0); | |
311 | } | |
312 | ||
80a5cfd6 | 313 | static bool mtk_dsi_clk_hs_state(struct mtk_dsi *dsi) |
2e54c14e | 314 | { |
e9052927 | 315 | return readl(dsi->regs + DSI_PHY_LCCON) & LC_HS_TX_EN; |
2e54c14e CH |
316 | } |
317 | ||
80a5cfd6 | 318 | static void mtk_dsi_clk_hs_mode(struct mtk_dsi *dsi, bool enter) |
2e54c14e | 319 | { |
80a5cfd6 | 320 | if (enter && !mtk_dsi_clk_hs_state(dsi)) |
2e54c14e | 321 | mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, LC_HS_TX_EN); |
80a5cfd6 | 322 | else if (!enter && mtk_dsi_clk_hs_state(dsi)) |
2e54c14e CH |
323 | mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0); |
324 | } | |
325 | ||
80a5cfd6 | 326 | static void mtk_dsi_set_mode(struct mtk_dsi *dsi) |
2e54c14e CH |
327 | { |
328 | u32 vid_mode = CMD_MODE; | |
329 | ||
330 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { | |
0707632b | 331 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) |
2e54c14e | 332 | vid_mode = BURST_MODE; |
0707632b | 333 | else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) |
334 | vid_mode = SYNC_PULSE_MODE; | |
335 | else | |
336 | vid_mode = SYNC_EVENT_MODE; | |
2e54c14e CH |
337 | } |
338 | ||
339 | writel(vid_mode, dsi->regs + DSI_MODE_CTRL); | |
340 | } | |
341 | ||
0707632b | 342 | static void mtk_dsi_set_vm_cmd(struct mtk_dsi *dsi) |
343 | { | |
344 | mtk_dsi_mask(dsi, DSI_VM_CMD_CON, VM_CMD_EN, VM_CMD_EN); | |
345 | mtk_dsi_mask(dsi, DSI_VM_CMD_CON, TS_VFP_EN, TS_VFP_EN); | |
346 | } | |
347 | ||
80a5cfd6 | 348 | static void mtk_dsi_ps_control_vact(struct mtk_dsi *dsi) |
2e54c14e CH |
349 | { |
350 | struct videomode *vm = &dsi->vm; | |
351 | u32 dsi_buf_bpp, ps_wc; | |
352 | u32 ps_bpp_mode; | |
353 | ||
354 | if (dsi->format == MIPI_DSI_FMT_RGB565) | |
355 | dsi_buf_bpp = 2; | |
356 | else | |
357 | dsi_buf_bpp = 3; | |
358 | ||
359 | ps_wc = vm->hactive * dsi_buf_bpp; | |
360 | ps_bpp_mode = ps_wc; | |
361 | ||
362 | switch (dsi->format) { | |
363 | case MIPI_DSI_FMT_RGB888: | |
364 | ps_bpp_mode |= PACKED_PS_24BIT_RGB888; | |
365 | break; | |
366 | case MIPI_DSI_FMT_RGB666: | |
367 | ps_bpp_mode |= PACKED_PS_18BIT_RGB666; | |
368 | break; | |
369 | case MIPI_DSI_FMT_RGB666_PACKED: | |
370 | ps_bpp_mode |= LOOSELY_PS_18BIT_RGB666; | |
371 | break; | |
372 | case MIPI_DSI_FMT_RGB565: | |
373 | ps_bpp_mode |= PACKED_PS_16BIT_RGB565; | |
374 | break; | |
375 | } | |
376 | ||
377 | writel(vm->vactive, dsi->regs + DSI_VACT_NL); | |
378 | writel(ps_bpp_mode, dsi->regs + DSI_PSCTRL); | |
379 | writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC); | |
380 | } | |
381 | ||
80a5cfd6 | 382 | static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi) |
2e54c14e CH |
383 | { |
384 | u32 tmp_reg; | |
385 | ||
386 | switch (dsi->lanes) { | |
387 | case 1: | |
388 | tmp_reg = 1 << 2; | |
389 | break; | |
390 | case 2: | |
391 | tmp_reg = 3 << 2; | |
392 | break; | |
393 | case 3: | |
394 | tmp_reg = 7 << 2; | |
395 | break; | |
396 | case 4: | |
397 | tmp_reg = 0xf << 2; | |
398 | break; | |
399 | default: | |
400 | tmp_reg = 0xf << 2; | |
401 | break; | |
402 | } | |
403 | ||
2d52bfba | 404 | tmp_reg |= (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6; |
405 | tmp_reg |= (dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3; | |
406 | ||
2e54c14e CH |
407 | writel(tmp_reg, dsi->regs + DSI_TXRX_CTRL); |
408 | } | |
409 | ||
80a5cfd6 | 410 | static void mtk_dsi_ps_control(struct mtk_dsi *dsi) |
2e54c14e | 411 | { |
80a5cfd6 | 412 | u32 dsi_tmp_buf_bpp; |
2e54c14e CH |
413 | u32 tmp_reg; |
414 | ||
415 | switch (dsi->format) { | |
416 | case MIPI_DSI_FMT_RGB888: | |
417 | tmp_reg = PACKED_PS_24BIT_RGB888; | |
418 | dsi_tmp_buf_bpp = 3; | |
419 | break; | |
420 | case MIPI_DSI_FMT_RGB666: | |
421 | tmp_reg = LOOSELY_PS_18BIT_RGB666; | |
422 | dsi_tmp_buf_bpp = 3; | |
423 | break; | |
424 | case MIPI_DSI_FMT_RGB666_PACKED: | |
425 | tmp_reg = PACKED_PS_18BIT_RGB666; | |
426 | dsi_tmp_buf_bpp = 3; | |
427 | break; | |
428 | case MIPI_DSI_FMT_RGB565: | |
429 | tmp_reg = PACKED_PS_16BIT_RGB565; | |
430 | dsi_tmp_buf_bpp = 2; | |
431 | break; | |
432 | default: | |
433 | tmp_reg = PACKED_PS_24BIT_RGB888; | |
434 | dsi_tmp_buf_bpp = 3; | |
435 | break; | |
436 | } | |
437 | ||
438 | tmp_reg += dsi->vm.hactive * dsi_tmp_buf_bpp & DSI_PS_WC; | |
439 | writel(tmp_reg, dsi->regs + DSI_PSCTRL); | |
440 | } | |
441 | ||
80a5cfd6 | 442 | static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi) |
2e54c14e | 443 | { |
80a5cfd6 | 444 | u32 horizontal_sync_active_byte; |
445 | u32 horizontal_backporch_byte; | |
446 | u32 horizontal_frontporch_byte; | |
487778f8 CH |
447 | u32 horizontal_front_back_byte; |
448 | u32 data_phy_cycles_byte; | |
7a5bc4e2 | 449 | u32 dsi_tmp_buf_bpp, data_phy_cycles; |
487778f8 | 450 | u32 delta; |
7a5bc4e2 | 451 | struct mtk_phy_timing *timing = &dsi->phy_timing; |
2e54c14e CH |
452 | |
453 | struct videomode *vm = &dsi->vm; | |
454 | ||
455 | if (dsi->format == MIPI_DSI_FMT_RGB565) | |
456 | dsi_tmp_buf_bpp = 2; | |
457 | else | |
458 | dsi_tmp_buf_bpp = 3; | |
459 | ||
460 | writel(vm->vsync_len, dsi->regs + DSI_VSA_NL); | |
461 | writel(vm->vback_porch, dsi->regs + DSI_VBP_NL); | |
462 | writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL); | |
463 | writel(vm->vactive, dsi->regs + DSI_VACT_NL); | |
464 | ||
7bf54afe JS |
465 | if (dsi->driver_data->has_size_ctl) |
466 | writel(vm->vactive << 16 | vm->hactive, | |
467 | dsi->regs + DSI_SIZE_CON); | |
468 | ||
2e54c14e CH |
469 | horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10); |
470 | ||
471 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) | |
487778f8 | 472 | horizontal_backporch_byte = vm->hback_porch * dsi_tmp_buf_bpp - 10; |
2e54c14e | 473 | else |
35bf948f | 474 | horizontal_backporch_byte = (vm->hback_porch + vm->hsync_len) * |
487778f8 | 475 | dsi_tmp_buf_bpp - 10; |
2e54c14e | 476 | |
7a5bc4e2 | 477 | data_phy_cycles = timing->lpx + timing->da_hs_prepare + |
487778f8 CH |
478 | timing->da_hs_zero + timing->da_hs_exit + 3; |
479 | ||
480 | delta = dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST ? 18 : 12; | |
481 | ||
482 | horizontal_frontporch_byte = vm->hfront_porch * dsi_tmp_buf_bpp; | |
483 | horizontal_front_back_byte = horizontal_frontporch_byte + horizontal_backporch_byte; | |
484 | data_phy_cycles_byte = data_phy_cycles * dsi->lanes + delta; | |
485 | ||
486 | if (horizontal_front_back_byte > data_phy_cycles_byte) { | |
487 | horizontal_frontporch_byte -= data_phy_cycles_byte * | |
488 | horizontal_frontporch_byte / | |
489 | horizontal_front_back_byte; | |
490 | ||
491 | horizontal_backporch_byte -= data_phy_cycles_byte * | |
492 | horizontal_backporch_byte / | |
493 | horizontal_front_back_byte; | |
7a5bc4e2 | 494 | } else { |
487778f8 | 495 | DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n"); |
7a5bc4e2 | 496 | } |
2e54c14e CH |
497 | |
498 | writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC); | |
499 | writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC); | |
500 | writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC); | |
501 | ||
80a5cfd6 | 502 | mtk_dsi_ps_control(dsi); |
2e54c14e CH |
503 | } |
504 | ||
505 | static void mtk_dsi_start(struct mtk_dsi *dsi) | |
506 | { | |
507 | writel(0, dsi->regs + DSI_START); | |
508 | writel(1, dsi->regs + DSI_START); | |
509 | } | |
510 | ||
0707632b | 511 | static void mtk_dsi_stop(struct mtk_dsi *dsi) |
512 | { | |
513 | writel(0, dsi->regs + DSI_START); | |
514 | } | |
515 | ||
516 | static void mtk_dsi_set_cmd_mode(struct mtk_dsi *dsi) | |
517 | { | |
518 | writel(CMD_MODE, dsi->regs + DSI_MODE_CTRL); | |
519 | } | |
520 | ||
dd5080a5 | 521 | static void mtk_dsi_set_interrupt_enable(struct mtk_dsi *dsi) |
522 | { | |
523 | u32 inten = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG; | |
524 | ||
525 | writel(inten, dsi->regs + DSI_INTEN); | |
526 | } | |
527 | ||
528 | static void mtk_dsi_irq_data_set(struct mtk_dsi *dsi, u32 irq_bit) | |
529 | { | |
530 | dsi->irq_data |= irq_bit; | |
531 | } | |
532 | ||
21898816 | 533 | static void mtk_dsi_irq_data_clear(struct mtk_dsi *dsi, u32 irq_bit) |
dd5080a5 | 534 | { |
535 | dsi->irq_data &= ~irq_bit; | |
536 | } | |
537 | ||
21898816 | 538 | static s32 mtk_dsi_wait_for_irq_done(struct mtk_dsi *dsi, u32 irq_flag, |
dd5080a5 | 539 | unsigned int timeout) |
540 | { | |
541 | s32 ret = 0; | |
542 | unsigned long jiffies = msecs_to_jiffies(timeout); | |
543 | ||
544 | ret = wait_event_interruptible_timeout(dsi->irq_wait_queue, | |
545 | dsi->irq_data & irq_flag, | |
546 | jiffies); | |
547 | if (ret == 0) { | |
548 | DRM_WARN("Wait DSI IRQ(0x%08x) Timeout\n", irq_flag); | |
549 | ||
550 | mtk_dsi_enable(dsi); | |
551 | mtk_dsi_reset_engine(dsi); | |
552 | } | |
553 | ||
554 | return ret; | |
555 | } | |
556 | ||
557 | static irqreturn_t mtk_dsi_irq(int irq, void *dev_id) | |
558 | { | |
559 | struct mtk_dsi *dsi = dev_id; | |
560 | u32 status, tmp; | |
561 | u32 flag = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG; | |
562 | ||
563 | status = readl(dsi->regs + DSI_INTSTA) & flag; | |
564 | ||
565 | if (status) { | |
566 | do { | |
567 | mtk_dsi_mask(dsi, DSI_RACK, RACK, RACK); | |
568 | tmp = readl(dsi->regs + DSI_INTSTA); | |
569 | } while (tmp & DSI_BUSY); | |
570 | ||
571 | mtk_dsi_mask(dsi, DSI_INTSTA, status, 0); | |
572 | mtk_dsi_irq_data_set(dsi, status); | |
573 | wake_up_interruptible(&dsi->irq_wait_queue); | |
574 | } | |
575 | ||
576 | return IRQ_HANDLED; | |
577 | } | |
578 | ||
0707632b | 579 | static s32 mtk_dsi_switch_to_cmd_mode(struct mtk_dsi *dsi, u8 irq_flag, u32 t) |
580 | { | |
581 | mtk_dsi_irq_data_clear(dsi, irq_flag); | |
582 | mtk_dsi_set_cmd_mode(dsi); | |
583 | ||
584 | if (!mtk_dsi_wait_for_irq_done(dsi, irq_flag, t)) { | |
585 | DRM_ERROR("failed to switch cmd mode\n"); | |
586 | return -ETIME; | |
587 | } else { | |
588 | return 0; | |
589 | } | |
590 | } | |
591 | ||
592 | static int mtk_dsi_poweron(struct mtk_dsi *dsi) | |
593 | { | |
b3218e74 | 594 | struct device *dev = dsi->host.dev; |
0707632b | 595 | int ret; |
7a5bc4e2 | 596 | u32 bit_per_pixel; |
0707632b | 597 | |
598 | if (++dsi->refcount != 1) | |
599 | return 0; | |
600 | ||
601 | switch (dsi->format) { | |
602 | case MIPI_DSI_FMT_RGB565: | |
603 | bit_per_pixel = 16; | |
604 | break; | |
605 | case MIPI_DSI_FMT_RGB666_PACKED: | |
606 | bit_per_pixel = 18; | |
607 | break; | |
608 | case MIPI_DSI_FMT_RGB666: | |
609 | case MIPI_DSI_FMT_RGB888: | |
610 | default: | |
611 | bit_per_pixel = 24; | |
612 | break; | |
613 | } | |
614 | ||
7a5bc4e2 JS |
615 | dsi->data_rate = DIV_ROUND_UP_ULL(dsi->vm.pixelclock * bit_per_pixel, |
616 | dsi->lanes); | |
0707632b | 617 | |
618 | ret = clk_set_rate(dsi->hs_clk, dsi->data_rate); | |
619 | if (ret < 0) { | |
620 | dev_err(dev, "Failed to set data rate: %d\n", ret); | |
621 | goto err_refcount; | |
622 | } | |
623 | ||
624 | phy_power_on(dsi->phy); | |
625 | ||
626 | ret = clk_prepare_enable(dsi->engine_clk); | |
627 | if (ret < 0) { | |
628 | dev_err(dev, "Failed to enable engine clock: %d\n", ret); | |
629 | goto err_phy_power_off; | |
630 | } | |
631 | ||
632 | ret = clk_prepare_enable(dsi->digital_clk); | |
633 | if (ret < 0) { | |
634 | dev_err(dev, "Failed to enable digital clock: %d\n", ret); | |
635 | goto err_disable_engine_clk; | |
636 | } | |
637 | ||
638 | mtk_dsi_enable(dsi); | |
3c6bd94d JS |
639 | |
640 | if (dsi->driver_data->has_shadow_ctl) | |
641 | writel(FORCE_COMMIT | BYPASS_SHADOW, | |
642 | dsi->regs + DSI_SHADOW_DEBUG); | |
643 | ||
0707632b | 644 | mtk_dsi_reset_engine(dsi); |
645 | mtk_dsi_phy_timconfig(dsi); | |
646 | ||
647 | mtk_dsi_rxtx_control(dsi); | |
75374fc2 JS |
648 | usleep_range(30, 100); |
649 | mtk_dsi_reset_dphy(dsi); | |
0707632b | 650 | mtk_dsi_ps_control_vact(dsi); |
651 | mtk_dsi_set_vm_cmd(dsi); | |
652 | mtk_dsi_config_vdo_timing(dsi); | |
653 | mtk_dsi_set_interrupt_enable(dsi); | |
654 | ||
655 | mtk_dsi_clk_ulp_mode_leave(dsi); | |
656 | mtk_dsi_lane0_ulp_mode_leave(dsi); | |
657 | mtk_dsi_clk_hs_mode(dsi, 0); | |
658 | ||
0707632b | 659 | return 0; |
0707632b | 660 | err_disable_engine_clk: |
661 | clk_disable_unprepare(dsi->engine_clk); | |
662 | err_phy_power_off: | |
663 | phy_power_off(dsi->phy); | |
664 | err_refcount: | |
665 | dsi->refcount--; | |
666 | return ret; | |
667 | } | |
668 | ||
2e54c14e CH |
669 | static void mtk_dsi_poweroff(struct mtk_dsi *dsi) |
670 | { | |
671 | if (WARN_ON(dsi->refcount == 0)) | |
672 | return; | |
673 | ||
674 | if (--dsi->refcount != 0) | |
675 | return; | |
676 | ||
2458d9d6 HYW |
677 | /* |
678 | * mtk_dsi_stop() and mtk_dsi_start() is asymmetric, since | |
679 | * mtk_dsi_stop() should be called after mtk_drm_crtc_atomic_disable(), | |
680 | * which needs irq for vblank, and mtk_dsi_stop() will disable irq. | |
681 | * mtk_dsi_start() needs to be called in mtk_output_dsi_enable(), | |
682 | * after dsi is fully set. | |
683 | */ | |
684 | mtk_dsi_stop(dsi); | |
685 | ||
2dd8075d | 686 | mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, 500); |
0707632b | 687 | mtk_dsi_reset_engine(dsi); |
80a5cfd6 | 688 | mtk_dsi_lane0_ulp_mode_enter(dsi); |
689 | mtk_dsi_clk_ulp_mode_enter(dsi); | |
2e54c14e CH |
690 | |
691 | mtk_dsi_disable(dsi); | |
692 | ||
693 | clk_disable_unprepare(dsi->engine_clk); | |
694 | clk_disable_unprepare(dsi->digital_clk); | |
695 | ||
696 | phy_power_off(dsi->phy); | |
697 | } | |
698 | ||
699 | static void mtk_output_dsi_enable(struct mtk_dsi *dsi) | |
700 | { | |
701 | int ret; | |
702 | ||
703 | if (dsi->enabled) | |
704 | return; | |
705 | ||
2e54c14e CH |
706 | ret = mtk_dsi_poweron(dsi); |
707 | if (ret < 0) { | |
708 | DRM_ERROR("failed to power on dsi\n"); | |
709 | return; | |
710 | } | |
711 | ||
80a5cfd6 | 712 | mtk_dsi_set_mode(dsi); |
713 | mtk_dsi_clk_hs_mode(dsi, 1); | |
2e54c14e CH |
714 | |
715 | mtk_dsi_start(dsi); | |
716 | ||
717 | dsi->enabled = true; | |
718 | } | |
719 | ||
720 | static void mtk_output_dsi_disable(struct mtk_dsi *dsi) | |
721 | { | |
722 | if (!dsi->enabled) | |
723 | return; | |
724 | ||
2e54c14e CH |
725 | mtk_dsi_poweroff(dsi); |
726 | ||
727 | dsi->enabled = false; | |
728 | } | |
729 | ||
71e780f1 EBS |
730 | static int mtk_dsi_bridge_attach(struct drm_bridge *bridge, |
731 | enum drm_bridge_attach_flags flags) | |
732 | { | |
733 | struct mtk_dsi *dsi = bridge_to_dsi(bridge); | |
734 | ||
2dd8075d EBS |
735 | /* Attach the panel or bridge to the dsi bridge */ |
736 | return drm_bridge_attach(bridge->encoder, dsi->next_bridge, | |
737 | &dsi->bridge, flags); | |
71e780f1 EBS |
738 | } |
739 | ||
740 | static void mtk_dsi_bridge_mode_set(struct drm_bridge *bridge, | |
741 | const struct drm_display_mode *mode, | |
742 | const struct drm_display_mode *adjusted) | |
743 | { | |
744 | struct mtk_dsi *dsi = bridge_to_dsi(bridge); | |
2e54c14e | 745 | |
72ac6969 | 746 | drm_display_mode_to_videomode(adjusted, &dsi->vm); |
2e54c14e CH |
747 | } |
748 | ||
71e780f1 | 749 | static void mtk_dsi_bridge_disable(struct drm_bridge *bridge) |
2e54c14e | 750 | { |
71e780f1 | 751 | struct mtk_dsi *dsi = bridge_to_dsi(bridge); |
2e54c14e CH |
752 | |
753 | mtk_output_dsi_disable(dsi); | |
754 | } | |
755 | ||
71e780f1 | 756 | static void mtk_dsi_bridge_enable(struct drm_bridge *bridge) |
2e54c14e | 757 | { |
71e780f1 | 758 | struct mtk_dsi *dsi = bridge_to_dsi(bridge); |
2e54c14e CH |
759 | |
760 | mtk_output_dsi_enable(dsi); | |
761 | } | |
762 | ||
71e780f1 EBS |
763 | static const struct drm_bridge_funcs mtk_dsi_bridge_funcs = { |
764 | .attach = mtk_dsi_bridge_attach, | |
71e780f1 EBS |
765 | .disable = mtk_dsi_bridge_disable, |
766 | .enable = mtk_dsi_bridge_enable, | |
767 | .mode_set = mtk_dsi_bridge_mode_set, | |
2e54c14e CH |
768 | }; |
769 | ||
2e54c14e CH |
770 | static void mtk_dsi_ddp_start(struct mtk_ddp_comp *comp) |
771 | { | |
772 | struct mtk_dsi *dsi = container_of(comp, struct mtk_dsi, ddp_comp); | |
773 | ||
774 | mtk_dsi_poweron(dsi); | |
775 | } | |
776 | ||
777 | static void mtk_dsi_ddp_stop(struct mtk_ddp_comp *comp) | |
778 | { | |
779 | struct mtk_dsi *dsi = container_of(comp, struct mtk_dsi, ddp_comp); | |
780 | ||
781 | mtk_dsi_poweroff(dsi); | |
782 | } | |
783 | ||
784 | static const struct mtk_ddp_comp_funcs mtk_dsi_funcs = { | |
785 | .start = mtk_dsi_ddp_start, | |
786 | .stop = mtk_dsi_ddp_stop, | |
787 | }; | |
788 | ||
789 | static int mtk_dsi_host_attach(struct mipi_dsi_host *host, | |
790 | struct mipi_dsi_device *device) | |
791 | { | |
792 | struct mtk_dsi *dsi = host_to_dsi(host); | |
793 | ||
794 | dsi->lanes = device->lanes; | |
795 | dsi->format = device->format; | |
796 | dsi->mode_flags = device->mode_flags; | |
797 | ||
2e54c14e CH |
798 | return 0; |
799 | } | |
800 | ||
21898816 | 801 | static void mtk_dsi_wait_for_idle(struct mtk_dsi *dsi) |
802 | { | |
f752413e DC |
803 | int ret; |
804 | u32 val; | |
21898816 | 805 | |
f752413e DC |
806 | ret = readl_poll_timeout(dsi->regs + DSI_INTSTA, val, !(val & DSI_BUSY), |
807 | 4, 2000000); | |
808 | if (ret) { | |
21898816 | 809 | DRM_WARN("polling dsi wait not busy timeout!\n"); |
810 | ||
811 | mtk_dsi_enable(dsi); | |
812 | mtk_dsi_reset_engine(dsi); | |
813 | } | |
814 | } | |
815 | ||
816 | static u32 mtk_dsi_recv_cnt(u8 type, u8 *read_data) | |
817 | { | |
818 | switch (type) { | |
819 | case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: | |
820 | case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: | |
821 | return 1; | |
822 | case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: | |
823 | case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: | |
824 | return 2; | |
825 | case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE: | |
826 | case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE: | |
827 | return read_data[1] + read_data[2] * 16; | |
828 | case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: | |
829 | DRM_INFO("type is 0x02, try again\n"); | |
830 | break; | |
831 | default: | |
afd89636 | 832 | DRM_INFO("type(0x%x) not recognized\n", type); |
21898816 | 833 | break; |
834 | } | |
835 | ||
836 | return 0; | |
837 | } | |
838 | ||
839 | static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct mipi_dsi_msg *msg) | |
840 | { | |
841 | const char *tx_buf = msg->tx_buf; | |
842 | u8 config, cmdq_size, cmdq_off, type = msg->type; | |
843 | u32 reg_val, cmdq_mask, i; | |
bb6bc298 | 844 | u32 reg_cmdq_off = dsi->driver_data->reg_cmdq_off; |
21898816 | 845 | |
846 | if (MTK_DSI_HOST_IS_READ(type)) | |
847 | config = BTA; | |
848 | else | |
849 | config = (msg->tx_len > 2) ? LONG_PACKET : SHORT_PACKET; | |
850 | ||
851 | if (msg->tx_len > 2) { | |
852 | cmdq_size = 1 + (msg->tx_len + 3) / 4; | |
853 | cmdq_off = 4; | |
854 | cmdq_mask = CONFIG | DATA_ID | DATA_0 | DATA_1; | |
855 | reg_val = (msg->tx_len << 16) | (type << 8) | config; | |
856 | } else { | |
857 | cmdq_size = 1; | |
858 | cmdq_off = 2; | |
859 | cmdq_mask = CONFIG | DATA_ID; | |
860 | reg_val = (type << 8) | config; | |
861 | } | |
862 | ||
863 | for (i = 0; i < msg->tx_len; i++) | |
89d0e3f8 JS |
864 | mtk_dsi_mask(dsi, (reg_cmdq_off + cmdq_off + i) & (~0x3U), |
865 | (0xffUL << (((i + cmdq_off) & 3U) * 8U)), | |
866 | tx_buf[i] << (((i + cmdq_off) & 3U) * 8U)); | |
21898816 | 867 | |
bb6bc298 | 868 | mtk_dsi_mask(dsi, reg_cmdq_off, cmdq_mask, reg_val); |
21898816 | 869 | mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size); |
870 | } | |
871 | ||
872 | static ssize_t mtk_dsi_host_send_cmd(struct mtk_dsi *dsi, | |
873 | const struct mipi_dsi_msg *msg, u8 flag) | |
874 | { | |
875 | mtk_dsi_wait_for_idle(dsi); | |
876 | mtk_dsi_irq_data_clear(dsi, flag); | |
877 | mtk_dsi_cmdq(dsi, msg); | |
878 | mtk_dsi_start(dsi); | |
879 | ||
880 | if (!mtk_dsi_wait_for_irq_done(dsi, flag, 2000)) | |
881 | return -ETIME; | |
882 | else | |
883 | return 0; | |
884 | } | |
885 | ||
886 | static ssize_t mtk_dsi_host_transfer(struct mipi_dsi_host *host, | |
887 | const struct mipi_dsi_msg *msg) | |
888 | { | |
889 | struct mtk_dsi *dsi = host_to_dsi(host); | |
890 | u32 recv_cnt, i; | |
891 | u8 read_data[16]; | |
892 | void *src_addr; | |
893 | u8 irq_flag = CMD_DONE_INT_FLAG; | |
894 | ||
895 | if (readl(dsi->regs + DSI_MODE_CTRL) & MODE) { | |
896 | DRM_ERROR("dsi engine is not command mode\n"); | |
897 | return -EINVAL; | |
898 | } | |
899 | ||
900 | if (MTK_DSI_HOST_IS_READ(msg->type)) | |
901 | irq_flag |= LPRX_RD_RDY_INT_FLAG; | |
902 | ||
903 | if (mtk_dsi_host_send_cmd(dsi, msg, irq_flag) < 0) | |
904 | return -ETIME; | |
905 | ||
906 | if (!MTK_DSI_HOST_IS_READ(msg->type)) | |
907 | return 0; | |
908 | ||
909 | if (!msg->rx_buf) { | |
910 | DRM_ERROR("dsi receive buffer size may be NULL\n"); | |
911 | return -EINVAL; | |
912 | } | |
913 | ||
914 | for (i = 0; i < 16; i++) | |
915 | *(read_data + i) = readb(dsi->regs + DSI_RX_DATA0 + i); | |
916 | ||
917 | recv_cnt = mtk_dsi_recv_cnt(read_data[0], read_data); | |
918 | ||
919 | if (recv_cnt > 2) | |
920 | src_addr = &read_data[4]; | |
921 | else | |
922 | src_addr = &read_data[1]; | |
923 | ||
924 | if (recv_cnt > 10) | |
925 | recv_cnt = 10; | |
926 | ||
927 | if (recv_cnt > msg->rx_len) | |
928 | recv_cnt = msg->rx_len; | |
929 | ||
930 | if (recv_cnt) | |
931 | memcpy(msg->rx_buf, src_addr, recv_cnt); | |
932 | ||
933 | DRM_INFO("dsi get %d byte data from the panel address(0x%x)\n", | |
934 | recv_cnt, *((u8 *)(msg->tx_buf))); | |
935 | ||
936 | return recv_cnt; | |
937 | } | |
938 | ||
2e54c14e CH |
939 | static const struct mipi_dsi_host_ops mtk_dsi_ops = { |
940 | .attach = mtk_dsi_host_attach, | |
21898816 | 941 | .transfer = mtk_dsi_host_transfer, |
2e54c14e CH |
942 | }; |
943 | ||
71e780f1 EBS |
944 | static int mtk_dsi_encoder_init(struct drm_device *drm, struct mtk_dsi *dsi) |
945 | { | |
946 | int ret; | |
947 | ||
45880ff0 EBS |
948 | ret = drm_simple_encoder_init(drm, &dsi->encoder, |
949 | DRM_MODE_ENCODER_DSI); | |
71e780f1 EBS |
950 | if (ret) { |
951 | DRM_ERROR("Failed to encoder init to drm\n"); | |
952 | return ret; | |
953 | } | |
954 | ||
5aa8e764 | 955 | dsi->encoder.possible_crtcs = mtk_drm_find_possible_crtc_by_comp(drm, dsi->ddp_comp); |
71e780f1 | 956 | |
a9d9fea7 EBS |
957 | ret = drm_bridge_attach(&dsi->encoder, &dsi->bridge, NULL, |
958 | DRM_BRIDGE_ATTACH_NO_CONNECTOR); | |
71e780f1 EBS |
959 | if (ret) |
960 | goto err_cleanup_encoder; | |
961 | ||
a9d9fea7 EBS |
962 | dsi->connector = drm_bridge_connector_init(drm, &dsi->encoder); |
963 | if (IS_ERR(dsi->connector)) { | |
964 | DRM_ERROR("Unable to create bridge connector\n"); | |
965 | ret = PTR_ERR(dsi->connector); | |
966 | goto err_cleanup_encoder; | |
967 | } | |
968 | drm_connector_attach_encoder(dsi->connector, &dsi->encoder); | |
969 | ||
71e780f1 EBS |
970 | return 0; |
971 | ||
972 | err_cleanup_encoder: | |
973 | drm_encoder_cleanup(&dsi->encoder); | |
974 | return ret; | |
975 | } | |
976 | ||
2e54c14e CH |
977 | static int mtk_dsi_bind(struct device *dev, struct device *master, void *data) |
978 | { | |
979 | int ret; | |
980 | struct drm_device *drm = data; | |
981 | struct mtk_dsi *dsi = dev_get_drvdata(dev); | |
982 | ||
983 | ret = mtk_ddp_comp_register(drm, &dsi->ddp_comp); | |
984 | if (ret < 0) { | |
4bf99144 RH |
985 | dev_err(dev, "Failed to register component %pOF: %d\n", |
986 | dev->of_node, ret); | |
2e54c14e CH |
987 | return ret; |
988 | } | |
989 | ||
71e780f1 EBS |
990 | ret = mtk_dsi_encoder_init(drm, dsi); |
991 | if (ret) | |
2e54c14e | 992 | goto err_unregister; |
2e54c14e CH |
993 | |
994 | return 0; | |
995 | ||
996 | err_unregister: | |
2e54c14e CH |
997 | mtk_ddp_comp_unregister(drm, &dsi->ddp_comp); |
998 | return ret; | |
999 | } | |
1000 | ||
1001 | static void mtk_dsi_unbind(struct device *dev, struct device *master, | |
1002 | void *data) | |
1003 | { | |
1004 | struct drm_device *drm = data; | |
1005 | struct mtk_dsi *dsi = dev_get_drvdata(dev); | |
1006 | ||
71e780f1 | 1007 | drm_encoder_cleanup(&dsi->encoder); |
2e54c14e CH |
1008 | mtk_ddp_comp_unregister(drm, &dsi->ddp_comp); |
1009 | } | |
1010 | ||
1011 | static const struct component_ops mtk_dsi_component_ops = { | |
1012 | .bind = mtk_dsi_bind, | |
1013 | .unbind = mtk_dsi_unbind, | |
1014 | }; | |
1015 | ||
1016 | static int mtk_dsi_probe(struct platform_device *pdev) | |
1017 | { | |
1018 | struct mtk_dsi *dsi; | |
1019 | struct device *dev = &pdev->dev; | |
2dd8075d | 1020 | struct drm_panel *panel; |
2e54c14e | 1021 | struct resource *regs; |
dd5080a5 | 1022 | int irq_num; |
2e54c14e CH |
1023 | int comp_id; |
1024 | int ret; | |
1025 | ||
1026 | dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); | |
1027 | if (!dsi) | |
1028 | return -ENOMEM; | |
1029 | ||
1030 | dsi->host.ops = &mtk_dsi_ops; | |
1031 | dsi->host.dev = dev; | |
b3218e74 JS |
1032 | ret = mipi_dsi_host_register(&dsi->host); |
1033 | if (ret < 0) { | |
1034 | dev_err(dev, "failed to register DSI host: %d\n", ret); | |
1035 | return ret; | |
1036 | } | |
2e54c14e | 1037 | |
ebc94461 | 1038 | ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0, |
2dd8075d | 1039 | &panel, &dsi->next_bridge); |
ebc94461 | 1040 | if (ret) |
b3218e74 | 1041 | goto err_unregister_host; |
2e54c14e | 1042 | |
2dd8075d EBS |
1043 | if (panel) { |
1044 | dsi->next_bridge = devm_drm_panel_bridge_add(dev, panel); | |
1045 | if (IS_ERR(dsi->next_bridge)) { | |
1046 | ret = PTR_ERR(dsi->next_bridge); | |
1047 | goto err_unregister_host; | |
1048 | } | |
1049 | } | |
1050 | ||
bb6bc298 | 1051 | dsi->driver_data = of_device_get_match_data(dev); |
2e54c14e CH |
1052 | |
1053 | dsi->engine_clk = devm_clk_get(dev, "engine"); | |
1054 | if (IS_ERR(dsi->engine_clk)) { | |
1055 | ret = PTR_ERR(dsi->engine_clk); | |
af19d645 MB |
1056 | |
1057 | if (ret != -EPROBE_DEFER) | |
1058 | dev_err(dev, "Failed to get engine clock: %d\n", ret); | |
b3218e74 | 1059 | goto err_unregister_host; |
2e54c14e CH |
1060 | } |
1061 | ||
1062 | dsi->digital_clk = devm_clk_get(dev, "digital"); | |
1063 | if (IS_ERR(dsi->digital_clk)) { | |
1064 | ret = PTR_ERR(dsi->digital_clk); | |
af19d645 MB |
1065 | |
1066 | if (ret != -EPROBE_DEFER) | |
1067 | dev_err(dev, "Failed to get digital clock: %d\n", ret); | |
b3218e74 | 1068 | goto err_unregister_host; |
2e54c14e CH |
1069 | } |
1070 | ||
1071 | dsi->hs_clk = devm_clk_get(dev, "hs"); | |
1072 | if (IS_ERR(dsi->hs_clk)) { | |
1073 | ret = PTR_ERR(dsi->hs_clk); | |
1074 | dev_err(dev, "Failed to get hs clock: %d\n", ret); | |
b3218e74 | 1075 | goto err_unregister_host; |
2e54c14e CH |
1076 | } |
1077 | ||
1078 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1079 | dsi->regs = devm_ioremap_resource(dev, regs); | |
1080 | if (IS_ERR(dsi->regs)) { | |
1081 | ret = PTR_ERR(dsi->regs); | |
1082 | dev_err(dev, "Failed to ioremap memory: %d\n", ret); | |
b3218e74 | 1083 | goto err_unregister_host; |
2e54c14e CH |
1084 | } |
1085 | ||
1086 | dsi->phy = devm_phy_get(dev, "dphy"); | |
1087 | if (IS_ERR(dsi->phy)) { | |
1088 | ret = PTR_ERR(dsi->phy); | |
1089 | dev_err(dev, "Failed to get MIPI-DPHY: %d\n", ret); | |
b3218e74 | 1090 | goto err_unregister_host; |
2e54c14e CH |
1091 | } |
1092 | ||
1093 | comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DSI); | |
1094 | if (comp_id < 0) { | |
1095 | dev_err(dev, "Failed to identify by alias: %d\n", comp_id); | |
b3218e74 JS |
1096 | ret = comp_id; |
1097 | goto err_unregister_host; | |
2e54c14e CH |
1098 | } |
1099 | ||
1100 | ret = mtk_ddp_comp_init(dev, dev->of_node, &dsi->ddp_comp, comp_id, | |
1101 | &mtk_dsi_funcs); | |
1102 | if (ret) { | |
1103 | dev_err(dev, "Failed to initialize component: %d\n", ret); | |
b3218e74 | 1104 | goto err_unregister_host; |
2e54c14e CH |
1105 | } |
1106 | ||
dd5080a5 | 1107 | irq_num = platform_get_irq(pdev, 0); |
1108 | if (irq_num < 0) { | |
b3218e74 JS |
1109 | dev_err(&pdev->dev, "failed to get dsi irq_num: %d\n", irq_num); |
1110 | ret = irq_num; | |
1111 | goto err_unregister_host; | |
dd5080a5 | 1112 | } |
1113 | ||
1114 | irq_set_status_flags(irq_num, IRQ_TYPE_LEVEL_LOW); | |
1115 | ret = devm_request_irq(&pdev->dev, irq_num, mtk_dsi_irq, | |
1116 | IRQF_TRIGGER_LOW, dev_name(&pdev->dev), dsi); | |
1117 | if (ret) { | |
1118 | dev_err(&pdev->dev, "failed to request mediatek dsi irq\n"); | |
b3218e74 | 1119 | goto err_unregister_host; |
dd5080a5 | 1120 | } |
1121 | ||
1122 | init_waitqueue_head(&dsi->irq_wait_queue); | |
1123 | ||
2e54c14e CH |
1124 | platform_set_drvdata(pdev, dsi); |
1125 | ||
71e780f1 EBS |
1126 | dsi->bridge.funcs = &mtk_dsi_bridge_funcs; |
1127 | dsi->bridge.of_node = dev->of_node; | |
1128 | dsi->bridge.type = DRM_MODE_CONNECTOR_DSI; | |
1129 | ||
1130 | drm_bridge_add(&dsi->bridge); | |
1131 | ||
b3218e74 JS |
1132 | ret = component_add(&pdev->dev, &mtk_dsi_component_ops); |
1133 | if (ret) { | |
1134 | dev_err(&pdev->dev, "failed to add component: %d\n", ret); | |
1135 | goto err_unregister_host; | |
1136 | } | |
1137 | ||
1138 | return 0; | |
1139 | ||
1140 | err_unregister_host: | |
1141 | mipi_dsi_host_unregister(&dsi->host); | |
1142 | return ret; | |
2e54c14e CH |
1143 | } |
1144 | ||
1145 | static int mtk_dsi_remove(struct platform_device *pdev) | |
1146 | { | |
1147 | struct mtk_dsi *dsi = platform_get_drvdata(pdev); | |
1148 | ||
1149 | mtk_output_dsi_disable(dsi); | |
71e780f1 | 1150 | drm_bridge_remove(&dsi->bridge); |
2e54c14e | 1151 | component_del(&pdev->dev, &mtk_dsi_component_ops); |
b3218e74 | 1152 | mipi_dsi_host_unregister(&dsi->host); |
2e54c14e CH |
1153 | |
1154 | return 0; | |
1155 | } | |
1156 | ||
bb6bc298 JS |
1157 | static const struct mtk_dsi_driver_data mt8173_dsi_driver_data = { |
1158 | .reg_cmdq_off = 0x200, | |
1159 | }; | |
1160 | ||
1161 | static const struct mtk_dsi_driver_data mt2701_dsi_driver_data = { | |
1162 | .reg_cmdq_off = 0x180, | |
1163 | }; | |
1164 | ||
e249e3e8 JS |
1165 | static const struct mtk_dsi_driver_data mt8183_dsi_driver_data = { |
1166 | .reg_cmdq_off = 0x200, | |
1167 | .has_shadow_ctl = true, | |
1168 | .has_size_ctl = true, | |
1169 | }; | |
1170 | ||
2e54c14e | 1171 | static const struct of_device_id mtk_dsi_of_match[] = { |
bb6bc298 JS |
1172 | { .compatible = "mediatek,mt2701-dsi", |
1173 | .data = &mt2701_dsi_driver_data }, | |
1174 | { .compatible = "mediatek,mt8173-dsi", | |
1175 | .data = &mt8173_dsi_driver_data }, | |
e249e3e8 JS |
1176 | { .compatible = "mediatek,mt8183-dsi", |
1177 | .data = &mt8183_dsi_driver_data }, | |
2e54c14e CH |
1178 | { }, |
1179 | }; | |
1180 | ||
1181 | struct platform_driver mtk_dsi_driver = { | |
1182 | .probe = mtk_dsi_probe, | |
1183 | .remove = mtk_dsi_remove, | |
1184 | .driver = { | |
1185 | .name = "mtk-dsi", | |
1186 | .of_match_table = mtk_dsi_of_match, | |
1187 | }, | |
1188 | }; |