Commit | Line | Data |
---|---|---|
b8d181e4 PZ |
1 | /* |
2 | * i.MX IPUv3 DP Overlay Planes | |
3 | * | |
4 | * Copyright (C) 2013 Philipp Zabel, Pengutronix | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | */ | |
15 | ||
16 | #include <drm/drmP.h> | |
17 | #include <drm/drm_fb_cma_helper.h> | |
18 | #include <drm/drm_gem_cma_helper.h> | |
19 | ||
39b9004d | 20 | #include "video/imx-ipu-v3.h" |
b8d181e4 PZ |
21 | #include "ipuv3-plane.h" |
22 | ||
23 | #define to_ipu_plane(x) container_of(x, struct ipu_plane, base) | |
24 | ||
25 | static const uint32_t ipu_plane_formats[] = { | |
c639a1cf | 26 | DRM_FORMAT_ARGB1555, |
b8d181e4 | 27 | DRM_FORMAT_XRGB1555, |
c639a1cf | 28 | DRM_FORMAT_ABGR1555, |
b8d181e4 | 29 | DRM_FORMAT_XBGR1555, |
c639a1cf PZ |
30 | DRM_FORMAT_RGBA5551, |
31 | DRM_FORMAT_BGRA5551, | |
cb166a30 | 32 | DRM_FORMAT_ARGB4444, |
b8d181e4 PZ |
33 | DRM_FORMAT_ARGB8888, |
34 | DRM_FORMAT_XRGB8888, | |
35 | DRM_FORMAT_ABGR8888, | |
36 | DRM_FORMAT_XBGR8888, | |
59d6b718 PZ |
37 | DRM_FORMAT_RGBA8888, |
38 | DRM_FORMAT_RGBX8888, | |
39 | DRM_FORMAT_BGRA8888, | |
40 | DRM_FORMAT_BGRA8888, | |
7932131f PZ |
41 | DRM_FORMAT_UYVY, |
42 | DRM_FORMAT_VYUY, | |
b8d181e4 PZ |
43 | DRM_FORMAT_YUYV, |
44 | DRM_FORMAT_YVYU, | |
45 | DRM_FORMAT_YUV420, | |
46 | DRM_FORMAT_YVU420, | |
33bee520 | 47 | DRM_FORMAT_RGB565, |
b8d181e4 PZ |
48 | }; |
49 | ||
50 | int ipu_plane_irq(struct ipu_plane *ipu_plane) | |
51 | { | |
52 | return ipu_idmac_channel_irq(ipu_plane->ipu, ipu_plane->ipu_ch, | |
53 | IPU_IRQ_EOF); | |
54 | } | |
55 | ||
56 | static int calc_vref(struct drm_display_mode *mode) | |
57 | { | |
58 | unsigned long htotal, vtotal; | |
59 | ||
60 | htotal = mode->htotal; | |
61 | vtotal = mode->vtotal; | |
62 | ||
63 | if (!htotal || !vtotal) | |
64 | return 60; | |
65 | ||
66 | return DIV_ROUND_UP(mode->clock * 1000, vtotal * htotal); | |
67 | } | |
68 | ||
69 | static inline int calc_bandwidth(int width, int height, unsigned int vref) | |
70 | { | |
71 | return width * height * vref; | |
72 | } | |
73 | ||
74 | int ipu_plane_set_base(struct ipu_plane *ipu_plane, struct drm_framebuffer *fb, | |
75 | int x, int y) | |
76 | { | |
67ca6b60 PZ |
77 | struct drm_gem_cma_object *cma_obj[3]; |
78 | unsigned long eba, ubo, vbo; | |
79 | int active, i; | |
80 | ||
81 | for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) { | |
82 | cma_obj[i] = drm_fb_cma_get_gem_obj(fb, i); | |
83 | if (!cma_obj[i]) { | |
84 | DRM_DEBUG_KMS("plane %d entry is null.\n", i); | |
85 | return -EFAULT; | |
86 | } | |
b8d181e4 PZ |
87 | } |
88 | ||
67ca6b60 | 89 | eba = cma_obj[0]->paddr + fb->offsets[0] + |
bc2b067a | 90 | fb->pitches[0] * y + (fb->bits_per_pixel >> 3) * x; |
356f9524 | 91 | |
67ca6b60 PZ |
92 | if (eba & 0x7) { |
93 | DRM_DEBUG_KMS("base address must be a multiple of 8.\n"); | |
94 | return -EINVAL; | |
95 | } | |
96 | ||
97 | if (fb->pitches[0] < 1 || fb->pitches[0] > 16384) { | |
98 | DRM_DEBUG_KMS("pitches out of range.\n"); | |
99 | return -EINVAL; | |
100 | } | |
101 | ||
102 | if (ipu_plane->enabled && fb->pitches[0] != ipu_plane->stride[0]) { | |
103 | DRM_DEBUG_KMS("pitches must not change while plane is enabled.\n"); | |
104 | return -EINVAL; | |
105 | } | |
106 | ||
107 | ipu_plane->stride[0] = fb->pitches[0]; | |
108 | ||
109 | switch (fb->pixel_format) { | |
110 | case DRM_FORMAT_YUV420: | |
111 | case DRM_FORMAT_YVU420: | |
112 | /* | |
113 | * Multiplanar formats have to meet the following restrictions: | |
114 | * - The (up to) three plane addresses are EBA, EBA+UBO, EBA+VBO | |
115 | * - EBA, UBO and VBO are a multiple of 8 | |
116 | * - UBO and VBO are unsigned and not larger than 0xfffff8 | |
117 | * - Only EBA may be changed while scanout is active | |
118 | * - The strides of U and V planes must be identical. | |
119 | */ | |
120 | ubo = cma_obj[1]->paddr + fb->offsets[1] + | |
121 | fb->pitches[1] * y / 2 + x / 2 - eba; | |
122 | vbo = cma_obj[2]->paddr + fb->offsets[2] + | |
123 | fb->pitches[2] * y / 2 + x / 2 - eba; | |
124 | ||
125 | if ((ubo & 0x7) || (vbo & 0x7)) { | |
126 | DRM_DEBUG_KMS("U/V buffer offsets must be a multiple of 8.\n"); | |
127 | return -EINVAL; | |
128 | } | |
129 | ||
130 | if ((ubo > 0xfffff8) || (vbo > 0xfffff8)) { | |
131 | DRM_DEBUG_KMS("U/V buffer offsets must be positive and not larger than 0xfffff8.\n"); | |
132 | return -EINVAL; | |
133 | } | |
134 | ||
135 | if (ipu_plane->enabled && ((ipu_plane->u_offset != ubo) || | |
136 | (ipu_plane->v_offset != vbo))) { | |
137 | DRM_DEBUG_KMS("U/V buffer offsets must not change while plane is enabled.\n"); | |
138 | return -EINVAL; | |
139 | } | |
140 | ||
141 | if (fb->pitches[1] != fb->pitches[2]) { | |
142 | DRM_DEBUG_KMS("U/V pitches must be identical.\n"); | |
143 | return -EINVAL; | |
144 | } | |
145 | ||
146 | if (fb->pitches[1] < 1 || fb->pitches[1] > 16384) { | |
147 | DRM_DEBUG_KMS("U/V pitches out of range.\n"); | |
148 | return -EINVAL; | |
149 | } | |
150 | ||
151 | if (ipu_plane->enabled && | |
152 | (ipu_plane->stride[1] != fb->pitches[1])) { | |
153 | DRM_DEBUG_KMS("U/V pitches must not change while plane is enabled.\n"); | |
154 | return -EINVAL; | |
155 | } | |
156 | ||
157 | ipu_plane->u_offset = ubo; | |
158 | ipu_plane->v_offset = vbo; | |
159 | ipu_plane->stride[1] = fb->pitches[1]; | |
160 | ||
161 | dev_dbg(ipu_plane->base.dev->dev, | |
162 | "phys = %pad %pad %pad, x = %d, y = %d", | |
163 | &cma_obj[0]->paddr, &cma_obj[1]->paddr, | |
164 | &cma_obj[2]->paddr, x, y); | |
165 | break; | |
166 | default: | |
167 | dev_dbg(ipu_plane->base.dev->dev, "phys = %pad, x = %d, y = %d", | |
168 | &cma_obj[0]->paddr, x, y); | |
169 | break; | |
170 | } | |
171 | ||
356f9524 PZ |
172 | if (ipu_plane->enabled) { |
173 | active = ipu_idmac_get_current_buffer(ipu_plane->ipu_ch); | |
174 | ipu_cpmem_set_buffer(ipu_plane->ipu_ch, !active, eba); | |
175 | ipu_idmac_select_buffer(ipu_plane->ipu_ch, !active); | |
176 | } else { | |
177 | ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 0, eba); | |
178 | ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 1, eba); | |
179 | } | |
b8d181e4 | 180 | |
32f71106 LS |
181 | /* cache offsets for subsequent pageflips */ |
182 | ipu_plane->x = x; | |
183 | ipu_plane->y = y; | |
184 | ||
b8d181e4 PZ |
185 | return 0; |
186 | } | |
187 | ||
188 | int ipu_plane_mode_set(struct ipu_plane *ipu_plane, struct drm_crtc *crtc, | |
189 | struct drm_display_mode *mode, | |
190 | struct drm_framebuffer *fb, int crtc_x, int crtc_y, | |
191 | unsigned int crtc_w, unsigned int crtc_h, | |
192 | uint32_t src_x, uint32_t src_y, | |
dd7fa6d8 | 193 | uint32_t src_w, uint32_t src_h, bool interlaced) |
b8d181e4 | 194 | { |
b8d181e4 PZ |
195 | struct device *dev = ipu_plane->base.dev->dev; |
196 | int ret; | |
197 | ||
198 | /* no scaling */ | |
199 | if (src_w != crtc_w || src_h != crtc_h) | |
200 | return -EINVAL; | |
201 | ||
202 | /* clip to crtc bounds */ | |
203 | if (crtc_x < 0) { | |
204 | if (-crtc_x > crtc_w) | |
205 | return -EINVAL; | |
206 | src_x += -crtc_x; | |
207 | src_w -= -crtc_x; | |
208 | crtc_w -= -crtc_x; | |
209 | crtc_x = 0; | |
210 | } | |
211 | if (crtc_y < 0) { | |
212 | if (-crtc_y > crtc_h) | |
213 | return -EINVAL; | |
214 | src_y += -crtc_y; | |
215 | src_h -= -crtc_y; | |
216 | crtc_h -= -crtc_y; | |
217 | crtc_y = 0; | |
218 | } | |
219 | if (crtc_x + crtc_w > mode->hdisplay) { | |
220 | if (crtc_x > mode->hdisplay) | |
221 | return -EINVAL; | |
222 | crtc_w = mode->hdisplay - crtc_x; | |
223 | src_w = crtc_w; | |
224 | } | |
225 | if (crtc_y + crtc_h > mode->vdisplay) { | |
226 | if (crtc_y > mode->vdisplay) | |
227 | return -EINVAL; | |
228 | crtc_h = mode->vdisplay - crtc_y; | |
229 | src_h = crtc_h; | |
230 | } | |
231 | /* full plane minimum width is 13 pixels */ | |
232 | if (crtc_w < 13 && (ipu_plane->dp_flow != IPU_DP_FLOW_SYNC_FG)) | |
233 | return -EINVAL; | |
234 | if (crtc_h < 2) | |
235 | return -EINVAL; | |
236 | ||
9a666030 PZ |
237 | /* |
238 | * since we cannot touch active IDMAC channels, we do not support | |
239 | * resizing the enabled plane or changing its format | |
240 | */ | |
241 | if (ipu_plane->enabled) { | |
242 | if (src_w != ipu_plane->w || src_h != ipu_plane->h || | |
243 | fb->pixel_format != ipu_plane->base.fb->pixel_format) | |
244 | return -EINVAL; | |
245 | ||
246 | return ipu_plane_set_base(ipu_plane, fb, src_x, src_y); | |
247 | } | |
248 | ||
b8d181e4 PZ |
249 | switch (ipu_plane->dp_flow) { |
250 | case IPU_DP_FLOW_SYNC_BG: | |
251 | ret = ipu_dp_setup_channel(ipu_plane->dp, | |
252 | IPUV3_COLORSPACE_RGB, | |
253 | IPUV3_COLORSPACE_RGB); | |
254 | if (ret) { | |
255 | dev_err(dev, | |
256 | "initializing display processor failed with %d\n", | |
257 | ret); | |
258 | return ret; | |
259 | } | |
e6245fc7 | 260 | ipu_dp_set_global_alpha(ipu_plane->dp, true, 0, true); |
b8d181e4 PZ |
261 | break; |
262 | case IPU_DP_FLOW_SYNC_FG: | |
263 | ipu_dp_setup_channel(ipu_plane->dp, | |
264 | ipu_drm_fourcc_to_colorspace(fb->pixel_format), | |
265 | IPUV3_COLORSPACE_UNKNOWN); | |
266 | ipu_dp_set_window_pos(ipu_plane->dp, crtc_x, crtc_y); | |
e6245fc7 PZ |
267 | /* Enable local alpha on partial plane */ |
268 | switch (fb->pixel_format) { | |
c639a1cf PZ |
269 | case DRM_FORMAT_ARGB1555: |
270 | case DRM_FORMAT_ABGR1555: | |
271 | case DRM_FORMAT_RGBA5551: | |
272 | case DRM_FORMAT_BGRA5551: | |
cb166a30 | 273 | case DRM_FORMAT_ARGB4444: |
e6245fc7 PZ |
274 | case DRM_FORMAT_ARGB8888: |
275 | case DRM_FORMAT_ABGR8888: | |
59d6b718 PZ |
276 | case DRM_FORMAT_RGBA8888: |
277 | case DRM_FORMAT_BGRA8888: | |
e6245fc7 PZ |
278 | ipu_dp_set_global_alpha(ipu_plane->dp, false, 0, false); |
279 | break; | |
280 | default: | |
281 | break; | |
282 | } | |
b8d181e4 PZ |
283 | } |
284 | ||
b8d181e4 PZ |
285 | ret = ipu_dmfc_alloc_bandwidth(ipu_plane->dmfc, |
286 | calc_bandwidth(crtc_w, crtc_h, | |
287 | calc_vref(mode)), 64); | |
288 | if (ret) { | |
289 | dev_err(dev, "allocating dmfc bandwidth failed with %d\n", ret); | |
290 | return ret; | |
291 | } | |
292 | ||
6bcaf0c5 LY |
293 | ipu_dmfc_config_wait4eot(ipu_plane->dmfc, crtc_w); |
294 | ||
2eb671c4 SL |
295 | ipu_cpmem_zero(ipu_plane->ipu_ch); |
296 | ipu_cpmem_set_resolution(ipu_plane->ipu_ch, src_w, src_h); | |
297 | ret = ipu_cpmem_set_fmt(ipu_plane->ipu_ch, fb->pixel_format); | |
b8d181e4 PZ |
298 | if (ret < 0) { |
299 | dev_err(dev, "unsupported pixel format 0x%08x\n", | |
300 | fb->pixel_format); | |
301 | return ret; | |
302 | } | |
303 | ipu_cpmem_set_high_priority(ipu_plane->ipu_ch); | |
356f9524 | 304 | ipu_idmac_set_double_buffer(ipu_plane->ipu_ch, 1); |
7cd9bebe | 305 | ipu_cpmem_set_stride(ipu_plane->ipu_ch, fb->pitches[0]); |
b8d181e4 PZ |
306 | |
307 | ret = ipu_plane_set_base(ipu_plane, fb, src_x, src_y); | |
308 | if (ret < 0) | |
309 | return ret; | |
dd7fa6d8 PZ |
310 | if (interlaced) |
311 | ipu_cpmem_interlaced_scan(ipu_plane->ipu_ch, fb->pitches[0]); | |
b8d181e4 | 312 | |
6ac217ee PZ |
313 | if (fb->pixel_format == DRM_FORMAT_YUV420) { |
314 | ipu_cpmem_set_yuv_planar_full(ipu_plane->ipu_ch, | |
315 | ipu_plane->stride[1], | |
316 | ipu_plane->u_offset, | |
317 | ipu_plane->v_offset); | |
318 | } else if (fb->pixel_format == DRM_FORMAT_YVU420) { | |
319 | ipu_cpmem_set_yuv_planar_full(ipu_plane->ipu_ch, | |
320 | ipu_plane->stride[1], | |
321 | ipu_plane->v_offset, | |
322 | ipu_plane->u_offset); | |
323 | } | |
324 | ||
9a666030 PZ |
325 | ipu_plane->w = src_w; |
326 | ipu_plane->h = src_h; | |
327 | ||
b8d181e4 PZ |
328 | return 0; |
329 | } | |
330 | ||
331 | void ipu_plane_put_resources(struct ipu_plane *ipu_plane) | |
332 | { | |
333 | if (!IS_ERR_OR_NULL(ipu_plane->dp)) | |
334 | ipu_dp_put(ipu_plane->dp); | |
335 | if (!IS_ERR_OR_NULL(ipu_plane->dmfc)) | |
336 | ipu_dmfc_put(ipu_plane->dmfc); | |
337 | if (!IS_ERR_OR_NULL(ipu_plane->ipu_ch)) | |
338 | ipu_idmac_put(ipu_plane->ipu_ch); | |
339 | } | |
340 | ||
341 | int ipu_plane_get_resources(struct ipu_plane *ipu_plane) | |
342 | { | |
343 | int ret; | |
344 | ||
345 | ipu_plane->ipu_ch = ipu_idmac_get(ipu_plane->ipu, ipu_plane->dma); | |
346 | if (IS_ERR(ipu_plane->ipu_ch)) { | |
347 | ret = PTR_ERR(ipu_plane->ipu_ch); | |
348 | DRM_ERROR("failed to get idmac channel: %d\n", ret); | |
349 | return ret; | |
350 | } | |
351 | ||
352 | ipu_plane->dmfc = ipu_dmfc_get(ipu_plane->ipu, ipu_plane->dma); | |
353 | if (IS_ERR(ipu_plane->dmfc)) { | |
354 | ret = PTR_ERR(ipu_plane->dmfc); | |
355 | DRM_ERROR("failed to get dmfc: ret %d\n", ret); | |
356 | goto err_out; | |
357 | } | |
358 | ||
359 | if (ipu_plane->dp_flow >= 0) { | |
360 | ipu_plane->dp = ipu_dp_get(ipu_plane->ipu, ipu_plane->dp_flow); | |
361 | if (IS_ERR(ipu_plane->dp)) { | |
362 | ret = PTR_ERR(ipu_plane->dp); | |
363 | DRM_ERROR("failed to get dp flow: %d\n", ret); | |
364 | goto err_out; | |
365 | } | |
366 | } | |
367 | ||
368 | return 0; | |
369 | err_out: | |
370 | ipu_plane_put_resources(ipu_plane); | |
371 | ||
372 | return ret; | |
373 | } | |
374 | ||
375 | void ipu_plane_enable(struct ipu_plane *ipu_plane) | |
376 | { | |
285bbb01 PZ |
377 | if (ipu_plane->dp) |
378 | ipu_dp_enable(ipu_plane->ipu); | |
b8d181e4 PZ |
379 | ipu_dmfc_enable_channel(ipu_plane->dmfc); |
380 | ipu_idmac_enable_channel(ipu_plane->ipu_ch); | |
381 | if (ipu_plane->dp) | |
382 | ipu_dp_enable_channel(ipu_plane->dp); | |
383 | ||
384 | ipu_plane->enabled = true; | |
385 | } | |
386 | ||
387 | void ipu_plane_disable(struct ipu_plane *ipu_plane) | |
388 | { | |
389 | ipu_plane->enabled = false; | |
390 | ||
391 | ipu_idmac_wait_busy(ipu_plane->ipu_ch, 50); | |
392 | ||
393 | if (ipu_plane->dp) | |
394 | ipu_dp_disable_channel(ipu_plane->dp); | |
395 | ipu_idmac_disable_channel(ipu_plane->ipu_ch); | |
396 | ipu_dmfc_disable_channel(ipu_plane->dmfc); | |
285bbb01 PZ |
397 | if (ipu_plane->dp) |
398 | ipu_dp_disable(ipu_plane->ipu); | |
b8d181e4 PZ |
399 | } |
400 | ||
b8d181e4 PZ |
401 | /* |
402 | * drm_plane API | |
403 | */ | |
404 | ||
405 | static int ipu_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, | |
406 | struct drm_framebuffer *fb, int crtc_x, int crtc_y, | |
407 | unsigned int crtc_w, unsigned int crtc_h, | |
408 | uint32_t src_x, uint32_t src_y, | |
409 | uint32_t src_w, uint32_t src_h) | |
410 | { | |
411 | struct ipu_plane *ipu_plane = to_ipu_plane(plane); | |
412 | int ret = 0; | |
413 | ||
414 | DRM_DEBUG_KMS("plane - %p\n", plane); | |
415 | ||
416 | if (!ipu_plane->enabled) | |
417 | ret = ipu_plane_get_resources(ipu_plane); | |
418 | if (ret < 0) | |
419 | return ret; | |
420 | ||
421 | ret = ipu_plane_mode_set(ipu_plane, crtc, &crtc->hwmode, fb, | |
422 | crtc_x, crtc_y, crtc_w, crtc_h, | |
dd7fa6d8 PZ |
423 | src_x >> 16, src_y >> 16, src_w >> 16, src_h >> 16, |
424 | false); | |
b8d181e4 PZ |
425 | if (ret < 0) { |
426 | ipu_plane_put_resources(ipu_plane); | |
427 | return ret; | |
428 | } | |
429 | ||
430 | if (crtc != plane->crtc) | |
beec8ec0 | 431 | dev_dbg(plane->dev->dev, "crtc change: %p -> %p\n", |
b8d181e4 | 432 | plane->crtc, crtc); |
b8d181e4 | 433 | |
b46355f0 SG |
434 | if (!ipu_plane->enabled) |
435 | ipu_plane_enable(ipu_plane); | |
b8d181e4 PZ |
436 | |
437 | return 0; | |
438 | } | |
439 | ||
440 | static int ipu_disable_plane(struct drm_plane *plane) | |
441 | { | |
442 | struct ipu_plane *ipu_plane = to_ipu_plane(plane); | |
443 | ||
444 | DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__); | |
445 | ||
b46355f0 SG |
446 | if (ipu_plane->enabled) |
447 | ipu_plane_disable(ipu_plane); | |
b8d181e4 PZ |
448 | |
449 | ipu_plane_put_resources(ipu_plane); | |
450 | ||
451 | return 0; | |
452 | } | |
453 | ||
454 | static void ipu_plane_destroy(struct drm_plane *plane) | |
455 | { | |
456 | struct ipu_plane *ipu_plane = to_ipu_plane(plane); | |
457 | ||
458 | DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__); | |
459 | ||
460 | ipu_disable_plane(plane); | |
461 | drm_plane_cleanup(plane); | |
462 | kfree(ipu_plane); | |
463 | } | |
464 | ||
8b3ce873 | 465 | static const struct drm_plane_funcs ipu_plane_funcs = { |
b8d181e4 PZ |
466 | .update_plane = ipu_update_plane, |
467 | .disable_plane = ipu_disable_plane, | |
468 | .destroy = ipu_plane_destroy, | |
469 | }; | |
470 | ||
471 | struct ipu_plane *ipu_plane_init(struct drm_device *dev, struct ipu_soc *ipu, | |
472 | int dma, int dp, unsigned int possible_crtcs, | |
43895599 | 473 | enum drm_plane_type type) |
b8d181e4 PZ |
474 | { |
475 | struct ipu_plane *ipu_plane; | |
476 | int ret; | |
477 | ||
478 | DRM_DEBUG_KMS("channel %d, dp flow %d, possible_crtcs=0x%x\n", | |
479 | dma, dp, possible_crtcs); | |
480 | ||
481 | ipu_plane = kzalloc(sizeof(*ipu_plane), GFP_KERNEL); | |
482 | if (!ipu_plane) { | |
483 | DRM_ERROR("failed to allocate plane\n"); | |
484 | return ERR_PTR(-ENOMEM); | |
485 | } | |
486 | ||
487 | ipu_plane->ipu = ipu; | |
488 | ipu_plane->dma = dma; | |
489 | ipu_plane->dp_flow = dp; | |
490 | ||
43895599 PZ |
491 | ret = drm_universal_plane_init(dev, &ipu_plane->base, possible_crtcs, |
492 | &ipu_plane_funcs, ipu_plane_formats, | |
b0b3b795 VS |
493 | ARRAY_SIZE(ipu_plane_formats), type, |
494 | NULL); | |
b8d181e4 PZ |
495 | if (ret) { |
496 | DRM_ERROR("failed to initialize plane\n"); | |
497 | kfree(ipu_plane); | |
498 | return ERR_PTR(ret); | |
499 | } | |
500 | ||
501 | return ipu_plane; | |
502 | } |