[linux-2.6-block.git] / drivers / gpu / drm / imx / ipuv3-crtc.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * i.MX IPUv3 Graphics driver
 *
 * Copyright (C) 2011 Sascha Hauer, Pengutronix
 */
#include <linux/clk.h>
#include <linux/component.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/export.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <drm/drmP.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_fb_cma_helper.h>
#include <drm/drm_gem_cma_helper.h>
#include <drm/drm_probe_helper.h>

#include <video/imx-ipu-v3.h>
#include "imx-drm.h"
#include "ipuv3-plane.h"

#define DRIVER_DESC		"i.MX IPUv3 Graphics"

struct ipu_crtc {
	struct device		*dev;
	struct drm_crtc		base;

	/* plane[0] is the full plane, plane[1] is the partial plane */
	struct ipu_plane	*plane[2];

	struct ipu_dc		*dc;
	struct ipu_di		*di;
	int			irq;
	struct drm_pending_vblank_event *event;
};

static inline struct ipu_crtc *to_ipu_crtc(struct drm_crtc *crtc)
{
	return container_of(crtc, struct ipu_crtc, base);
}

static void ipu_crtc_atomic_enable(struct drm_crtc *crtc,
				   struct drm_crtc_state *old_state)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);

	ipu_prg_enable(ipu);
	ipu_dc_enable(ipu);
	ipu_dc_enable_channel(ipu_crtc->dc);
	ipu_di_enable(ipu_crtc->di);
}

static void ipu_crtc_disable_planes(struct ipu_crtc *ipu_crtc,
				    struct drm_crtc_state *old_crtc_state)
{
	bool disable_partial = false;
	bool disable_full = false;
	struct drm_plane *plane;

	drm_atomic_crtc_state_for_each_plane(plane, old_crtc_state) {
		if (plane == &ipu_crtc->plane[0]->base)
			disable_full = true;
		if (&ipu_crtc->plane[1] && plane == &ipu_crtc->plane[1]->base)
			disable_partial = true;
	}

	if (disable_partial)
		ipu_plane_disable(ipu_crtc->plane[1], true);
	if (disable_full)
		ipu_plane_disable(ipu_crtc->plane[0], false);
}

static void ipu_crtc_atomic_disable(struct drm_crtc *crtc,
				    struct drm_crtc_state *old_crtc_state)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);

	ipu_dc_disable_channel(ipu_crtc->dc);
	ipu_di_disable(ipu_crtc->di);
	/*
	 * Planes must be disabled before DC clock is removed, as otherwise the
	 * attached IDMACs will be left in undefined state, possibly hanging
	 * the IPU or even system.
	 */
	ipu_crtc_disable_planes(ipu_crtc, old_crtc_state);
	ipu_dc_disable(ipu);
	ipu_prg_disable(ipu);

	spin_lock_irq(&crtc->dev->event_lock);
	if (crtc->state->event) {
		drm_crtc_send_vblank_event(crtc, crtc->state->event);
		crtc->state->event = NULL;
	}
	spin_unlock_irq(&crtc->dev->event_lock);

	drm_crtc_vblank_off(crtc);
}

static void imx_drm_crtc_reset(struct drm_crtc *crtc)
{
	struct imx_crtc_state *state;

	if (crtc->state) {
		if (crtc->state->mode_blob)
			drm_property_blob_put(crtc->state->mode_blob);

		state = to_imx_crtc_state(crtc->state);
		memset(state, 0, sizeof(*state));
	} else {
		state = kzalloc(sizeof(*state), GFP_KERNEL);
		if (!state)
			return;
		crtc->state = &state->base;
	}

	state->base.crtc = crtc;
}

static struct drm_crtc_state *imx_drm_crtc_duplicate_state(struct drm_crtc *crtc)
{
	struct imx_crtc_state *state;

	state = kzalloc(sizeof(*state), GFP_KERNEL);
	if (!state)
		return NULL;

	__drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);

	WARN_ON(state->base.crtc != crtc);
	state->base.crtc = crtc;

	return &state->base;
}

static void imx_drm_crtc_destroy_state(struct drm_crtc *crtc,
				       struct drm_crtc_state *state)
{
	__drm_atomic_helper_crtc_destroy_state(state);
	kfree(to_imx_crtc_state(state));
}

static int ipu_enable_vblank(struct drm_crtc *crtc)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);

	enable_irq(ipu_crtc->irq);

	return 0;
}

static void ipu_disable_vblank(struct drm_crtc *crtc)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);

	disable_irq_nosync(ipu_crtc->irq);
}

static const struct drm_crtc_funcs ipu_crtc_funcs = {
	.set_config = drm_atomic_helper_set_config,
	.destroy = drm_crtc_cleanup,
	.page_flip = drm_atomic_helper_page_flip,
	.reset = imx_drm_crtc_reset,
	.atomic_duplicate_state = imx_drm_crtc_duplicate_state,
	.atomic_destroy_state = imx_drm_crtc_destroy_state,
	.enable_vblank = ipu_enable_vblank,
	.disable_vblank = ipu_disable_vblank,
};

static irqreturn_t ipu_irq_handler(int irq, void *dev_id)
{
	struct ipu_crtc *ipu_crtc = dev_id;
	struct drm_crtc *crtc = &ipu_crtc->base;
	unsigned long flags;
	int i;

	drm_crtc_handle_vblank(crtc);

	if (ipu_crtc->event) {
		for (i = 0; i < ARRAY_SIZE(ipu_crtc->plane); i++) {
			struct ipu_plane *plane = ipu_crtc->plane[i];

			if (!plane)
				continue;

			if (ipu_plane_atomic_update_pending(&plane->base))
				break;
		}

		if (i == ARRAY_SIZE(ipu_crtc->plane)) {
			spin_lock_irqsave(&crtc->dev->event_lock, flags);
			drm_crtc_send_vblank_event(crtc, ipu_crtc->event);
			ipu_crtc->event = NULL;
			drm_crtc_vblank_put(crtc);
			spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
		}
	}

	return IRQ_HANDLED;
}

static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc,
				  const struct drm_display_mode *mode,
				  struct drm_display_mode *adjusted_mode)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	struct videomode vm;
	int ret;

	drm_display_mode_to_videomode(adjusted_mode, &vm);

	ret = ipu_di_adjust_videomode(ipu_crtc->di, &vm);
	if (ret)
		return false;

	if ((vm.vsync_len == 0) || (vm.hsync_len == 0))
		return false;

	drm_display_mode_from_videomode(&vm, adjusted_mode);

	return true;
}

static int ipu_crtc_atomic_check(struct drm_crtc *crtc,
				 struct drm_crtc_state *state)
{
	u32 primary_plane_mask = drm_plane_mask(crtc->primary);

	if (state->active && (primary_plane_mask & state->plane_mask) == 0)
		return -EINVAL;

	return 0;
}

static void ipu_crtc_atomic_begin(struct drm_crtc *crtc,
				  struct drm_crtc_state *old_crtc_state)
{
	drm_crtc_vblank_on(crtc);
}

static void ipu_crtc_atomic_flush(struct drm_crtc *crtc,
				  struct drm_crtc_state *old_crtc_state)
{
	spin_lock_irq(&crtc->dev->event_lock);
	if (crtc->state->event) {
		struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);

		WARN_ON(drm_crtc_vblank_get(crtc));
		ipu_crtc->event = crtc->state->event;
		crtc->state->event = NULL;
	}
	spin_unlock_irq(&crtc->dev->event_lock);
}

static void ipu_crtc_mode_set_nofb(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_encoder *encoder;
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	struct drm_display_mode *mode = &crtc->state->adjusted_mode;
	struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc->state);
	struct ipu_di_signal_cfg sig_cfg = {};
	unsigned long encoder_types = 0;

	dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__,
			mode->hdisplay);
	dev_dbg(ipu_crtc->dev, "%s: mode->vdisplay: %d\n", __func__,
			mode->vdisplay);

	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		if (encoder->crtc == crtc)
			encoder_types |= BIT(encoder->encoder_type);
	}

	dev_dbg(ipu_crtc->dev, "%s: attached to encoder types 0x%lx\n",
		__func__, encoder_types);

	/*
	 * If we have DAC or LDB, then we need the IPU DI clock to be
	 * the same as the LDB DI clock. For TVDAC, derive the IPU DI
	 * clock from 27 MHz TVE_DI clock, but allow to divide it.
	 */
	if (encoder_types & (BIT(DRM_MODE_ENCODER_DAC) |
			     BIT(DRM_MODE_ENCODER_LVDS)))
		sig_cfg.clkflags = IPU_DI_CLKMODE_SYNC | IPU_DI_CLKMODE_EXT;
	else if (encoder_types & BIT(DRM_MODE_ENCODER_TVDAC))
		sig_cfg.clkflags = IPU_DI_CLKMODE_EXT;
	else
		sig_cfg.clkflags = 0;

	sig_cfg.enable_pol = !(imx_crtc_state->bus_flags & DRM_BUS_FLAG_DE_LOW);
	/* Default to driving pixel data on negative clock edges */
	sig_cfg.clk_pol = !!(imx_crtc_state->bus_flags &
			     DRM_BUS_FLAG_PIXDATA_POSEDGE);
	sig_cfg.bus_format = imx_crtc_state->bus_format;
	sig_cfg.v_to_h_sync = 0;
	sig_cfg.hsync_pin = imx_crtc_state->di_hsync_pin;
	sig_cfg.vsync_pin = imx_crtc_state->di_vsync_pin;

	drm_display_mode_to_videomode(mode, &sig_cfg.mode);

	ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di,
			 mode->flags & DRM_MODE_FLAG_INTERLACE,
			 imx_crtc_state->bus_format, mode->hdisplay);
	ipu_di_init_sync_panel(ipu_crtc->di, &sig_cfg);
}

static const struct drm_crtc_helper_funcs ipu_helper_funcs = {
	.mode_fixup = ipu_crtc_mode_fixup,
	.mode_set_nofb = ipu_crtc_mode_set_nofb,
	.atomic_check = ipu_crtc_atomic_check,
	.atomic_begin = ipu_crtc_atomic_begin,
	.atomic_flush = ipu_crtc_atomic_flush,
	.atomic_disable = ipu_crtc_atomic_disable,
	.atomic_enable = ipu_crtc_atomic_enable,
};

static void ipu_put_resources(struct ipu_crtc *ipu_crtc)
{
	if (!IS_ERR_OR_NULL(ipu_crtc->dc))
		ipu_dc_put(ipu_crtc->dc);
	if (!IS_ERR_OR_NULL(ipu_crtc->di))
		ipu_di_put(ipu_crtc->di);
}

static int ipu_get_resources(struct ipu_crtc *ipu_crtc,
		struct ipu_client_platformdata *pdata)
{
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
	int ret;

	ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc);
	if (IS_ERR(ipu_crtc->dc)) {
		ret = PTR_ERR(ipu_crtc->dc);
		goto err_out;
	}

	ipu_crtc->di = ipu_di_get(ipu, pdata->di);
	if (IS_ERR(ipu_crtc->di)) {
		ret = PTR_ERR(ipu_crtc->di);
		goto err_out;
	}

	return 0;
err_out:
	ipu_put_resources(ipu_crtc);

	return ret;
}

static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
	struct ipu_client_platformdata *pdata, struct drm_device *drm)
{
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
	struct drm_crtc *crtc = &ipu_crtc->base;
	int dp = -EINVAL;
	int ret;

	ret = ipu_get_resources(ipu_crtc, pdata);
	if (ret) {
		dev_err(ipu_crtc->dev, "getting resources failed with %d.\n",
				ret);
		return ret;
	}

	if (pdata->dp >= 0)
		dp = IPU_DP_FLOW_SYNC_BG;
	ipu_crtc->plane[0] = ipu_plane_init(drm, ipu, pdata->dma[0], dp, 0,
					    DRM_PLANE_TYPE_PRIMARY);
	if (IS_ERR(ipu_crtc->plane[0])) {
		ret = PTR_ERR(ipu_crtc->plane[0]);
		goto err_put_resources;
	}

	crtc->port = pdata->of_node;
	drm_crtc_helper_add(crtc, &ipu_helper_funcs);
	drm_crtc_init_with_planes(drm, crtc, &ipu_crtc->plane[0]->base, NULL,
				  &ipu_crtc_funcs, NULL);

	ret = ipu_plane_get_resources(ipu_crtc->plane[0]);
	if (ret) {
		dev_err(ipu_crtc->dev, "getting plane 0 resources failed with %d.\n",
			ret);
		goto err_put_resources;
	}

	/* If this crtc is using the DP, add an overlay plane */
	if (pdata->dp >= 0 && pdata->dma[1] > 0) {
		ipu_crtc->plane[1] = ipu_plane_init(drm, ipu, pdata->dma[1],
						IPU_DP_FLOW_SYNC_FG,
						drm_crtc_mask(&ipu_crtc->base),
						DRM_PLANE_TYPE_OVERLAY);
		if (IS_ERR(ipu_crtc->plane[1])) {
			ipu_crtc->plane[1] = NULL;
		} else {
			ret = ipu_plane_get_resources(ipu_crtc->plane[1]);
			if (ret) {
				dev_err(ipu_crtc->dev, "getting plane 1 "
					"resources failed with %d.\n", ret);
				goto err_put_plane0_res;
			}
		}
	}

	ipu_crtc->irq = ipu_plane_irq(ipu_crtc->plane[0]);
	ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0,
			"imx_drm", ipu_crtc);
	if (ret < 0) {
		dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret);
		goto err_put_plane1_res;
	}
	/* Only enable IRQ when we actually need it to trigger work. */
	disable_irq(ipu_crtc->irq);

	return 0;

err_put_plane1_res:
	if (ipu_crtc->plane[1])
		ipu_plane_put_resources(ipu_crtc->plane[1]);
err_put_plane0_res:
	ipu_plane_put_resources(ipu_crtc->plane[0]);
err_put_resources:
	ipu_put_resources(ipu_crtc);

	return ret;
}

static int ipu_drm_bind(struct device *dev, struct device *master, void *data)
{
	struct ipu_client_platformdata *pdata = dev->platform_data;
	struct drm_device *drm = data;
	struct ipu_crtc *ipu_crtc;
	int ret;

	ipu_crtc = devm_kzalloc(dev, sizeof(*ipu_crtc), GFP_KERNEL);
	if (!ipu_crtc)
		return -ENOMEM;

	ipu_crtc->dev = dev;

	ret = ipu_crtc_init(ipu_crtc, pdata, drm);
	if (ret)
		return ret;

	dev_set_drvdata(dev, ipu_crtc);

	return 0;
}

static void ipu_drm_unbind(struct device *dev, struct device *master,
	void *data)
{
	struct ipu_crtc *ipu_crtc = dev_get_drvdata(dev);

	ipu_put_resources(ipu_crtc);
	if (ipu_crtc->plane[1])
		ipu_plane_put_resources(ipu_crtc->plane[1]);
	ipu_plane_put_resources(ipu_crtc->plane[0]);
}

static const struct component_ops ipu_crtc_ops = {
	.bind = ipu_drm_bind,
	.unbind = ipu_drm_unbind,
};

static int ipu_drm_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	int ret;

	if (!dev->platform_data)
		return -EINVAL;

	ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
	if (ret)
		return ret;

	return component_add(dev, &ipu_crtc_ops);
}

static int ipu_drm_remove(struct platform_device *pdev)
{
	component_del(&pdev->dev, &ipu_crtc_ops);
	return 0;
}

struct platform_driver ipu_drm_driver = {
	.driver = {
		.name = "imx-ipuv3-crtc",
	},
	.probe = ipu_drm_probe,
	.remove = ipu_drm_remove,
};
Commit	Line	Data
946485d0	1	// SPDX-License-Identifier: GPL-2.0+
f326f799 SH	2	/*
	3	* i.MX IPUv3 Graphics driver
	4	*
	5	* Copyright (C) 2011 Sascha Hauer, Pengutronix
f326f799	6	*/
fcd70cd3	7	#include <linux/clk.h>
17b5001b	8	#include <linux/component.h>
f326f799	9	#include <linux/device.h>
fcd70cd3 DV	10	#include <linux/errno.h>
	11	#include <linux/export.h>
	12	#include <linux/module.h>
f326f799 SH	13	#include <linux/platform_device.h>
f326f799 SH	14	#include <drm/drmP.h>
ae2531ab	15	#include <drm/drm_atomic.h>
255c35f8	16	#include <drm/drm_atomic_helper.h>
f326f799	17	#include <drm/drm_fb_cma_helper.h>
fcd70cd3 DV	18	#include <drm/drm_gem_cma_helper.h>
fcd70cd3 DV	19	#include <drm/drm_probe_helper.h>
f326f799	20
39b9004d	21	#include <video/imx-ipu-v3.h>
f326f799	22	#include "imx-drm.h"
b8d181e4	23	#include "ipuv3-plane.h"
f326f799 SH	24
	25	#define DRIVER_DESC "i.MX IPUv3 Graphics"
	26
f326f799	27	struct ipu_crtc {
f326f799 SH	28	struct device *dev;
f326f799 SH	29	struct drm_crtc base;
b8d181e4 PZ	30
	31	/* plane[0] is the full plane, plane[1] is the partial plane */
	32	struct ipu_plane *plane[2];
	33
f326f799	34	struct ipu_dc *dc;
f326f799	35	struct ipu_di *di;
f326f799	36	int irq;
a0ea4fff	37	struct drm_pending_vblank_event *event;
f326f799 SH	38	};
f326f799 SH	39
3df07390 PZ	40	static inline struct ipu_crtc to_ipu_crtc(struct drm_crtc crtc)
	41	{
	42	return container_of(crtc, struct ipu_crtc, base);
	43	}
f326f799	44
0b20a0f8 LP	45	static void ipu_crtc_atomic_enable(struct drm_crtc *crtc,
0b20a0f8 LP	46	struct drm_crtc_state *old_state)
f326f799	47	{
f6e396e5	48	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
1e6d486b PZ	49	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
1e6d486b PZ	50
e0fb7dd2	51	ipu_prg_enable(ipu);
1e6d486b	52	ipu_dc_enable(ipu);
c115edb8 PZ	53	ipu_dc_enable_channel(ipu_crtc->dc);
c115edb8 PZ	54	ipu_di_enable(ipu_crtc->di);
f326f799 SH	55	}
f326f799 SH	56
eb8c8880 PZ	57	static void ipu_crtc_disable_planes(struct ipu_crtc *ipu_crtc,
	58	struct drm_crtc_state *old_crtc_state)
	59	{
	60	bool disable_partial = false;
	61	bool disable_full = false;
	62	struct drm_plane *plane;
	63
	64	drm_atomic_crtc_state_for_each_plane(plane, old_crtc_state) {
	65	if (plane == &ipu_crtc->plane[0]->base)
	66	disable_full = true;
	67	if (&ipu_crtc->plane[1] && plane == &ipu_crtc->plane[1]->base)
	68	disable_partial = true;
	69	}
	70
	71	if (disable_partial)
	72	ipu_plane_disable(ipu_crtc->plane[1], true);
	73	if (disable_full)
	74	ipu_plane_disable(ipu_crtc->plane[0], false);
	75	}
	76
8cc17b59 LY	77	static void ipu_crtc_atomic_disable(struct drm_crtc *crtc,
8cc17b59 LY	78	struct drm_crtc_state *old_crtc_state)
f326f799	79	{
f6e396e5	80	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
1e6d486b	81	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
f326f799	82
f326f799	83	ipu_dc_disable_channel(ipu_crtc->dc);
f326f799	84	ipu_di_disable(ipu_crtc->di);
5ced937b LS	85	/*
	86	* Planes must be disabled before DC clock is removed, as otherwise the
	87	* attached IDMACs will be left in undefined state, possibly hanging
	88	* the IPU or even system.
	89	*/
eb8c8880	90	ipu_crtc_disable_planes(ipu_crtc, old_crtc_state);
1e6d486b	91	ipu_dc_disable(ipu);
e0fb7dd2	92	ipu_prg_disable(ipu);
33f14235	93
5f2f9115 LY	94	spin_lock_irq(&crtc->dev->event_lock);
	95	if (crtc->state->event) {
	96	drm_crtc_send_vblank_event(crtc, crtc->state->event);
	97	crtc->state->event = NULL;
	98	}
	99	spin_unlock_irq(&crtc->dev->event_lock);
5f4df0c7	100
a4744786	101	drm_crtc_vblank_off(crtc);
f326f799 SH	102	}
f326f799 SH	103
49f98bc4 PZ	104	static void imx_drm_crtc_reset(struct drm_crtc *crtc)
	105	{
	106	struct imx_crtc_state *state;
	107
	108	if (crtc->state) {
	109	if (crtc->state->mode_blob)
a8f2023d	110	drm_property_blob_put(crtc->state->mode_blob);
49f98bc4 PZ	111
	112	state = to_imx_crtc_state(crtc->state);
	113	memset(state, 0, sizeof(*state));
	114	} else {
	115	state = kzalloc(sizeof(*state), GFP_KERNEL);
	116	if (!state)
	117	return;
	118	crtc->state = &state->base;
	119	}
	120
	121	state->base.crtc = crtc;
	122	}
	123
	124	static struct drm_crtc_state imx_drm_crtc_duplicate_state(struct drm_crtc crtc)
	125	{
	126	struct imx_crtc_state *state;
	127
	128	state = kzalloc(sizeof(*state), GFP_KERNEL);
	129	if (!state)
	130	return NULL;
	131
	132	__drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
	133
	134	WARN_ON(state->base.crtc != crtc);
	135	state->base.crtc = crtc;
	136
	137	return &state->base;
	138	}
	139
	140	static void imx_drm_crtc_destroy_state(struct drm_crtc *crtc,
	141	struct drm_crtc_state *state)
	142	{
	143	__drm_atomic_helper_crtc_destroy_state(state);
	144	kfree(to_imx_crtc_state(state));
	145	}
	146
44b460cf SG	147	static int ipu_enable_vblank(struct drm_crtc *crtc)
	148	{
	149	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	150
	151	enable_irq(ipu_crtc->irq);
	152
	153	return 0;
	154	}
	155
	156	static void ipu_disable_vblank(struct drm_crtc *crtc)
8e3b16e2	157	{
44b460cf SG	158	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	159
	160	disable_irq_nosync(ipu_crtc->irq);
8e3b16e2 LS	161	}
8e3b16e2 LS	162
f326f799	163	static const struct drm_crtc_funcs ipu_crtc_funcs = {
5f2f9115	164	.set_config = drm_atomic_helper_set_config,
44b460cf	165	.destroy = drm_crtc_cleanup,
5f2f9115	166	.page_flip = drm_atomic_helper_page_flip,
49f98bc4 PZ	167	.reset = imx_drm_crtc_reset,
	168	.atomic_duplicate_state = imx_drm_crtc_duplicate_state,
	169	.atomic_destroy_state = imx_drm_crtc_destroy_state,
44b460cf SG	170	.enable_vblank = ipu_enable_vblank,
44b460cf SG	171	.disable_vblank = ipu_disable_vblank,
f326f799 SH	172	};
f326f799 SH	173
f326f799 SH	174	static irqreturn_t ipu_irq_handler(int irq, void *dev_id)
	175	{
	176	struct ipu_crtc *ipu_crtc = dev_id;
a0ea4fff LS	177	struct drm_crtc *crtc = &ipu_crtc->base;
	178	unsigned long flags;
	179	int i;
	180
	181	drm_crtc_handle_vblank(crtc);
	182
	183	if (ipu_crtc->event) {
	184	for (i = 0; i < ARRAY_SIZE(ipu_crtc->plane); i++) {
	185	struct ipu_plane *plane = ipu_crtc->plane[i];
	186
	187	if (!plane)
	188	continue;
	189
	190	if (ipu_plane_atomic_update_pending(&plane->base))
	191	break;
	192	}
	193
	194	if (i == ARRAY_SIZE(ipu_crtc->plane)) {
	195	spin_lock_irqsave(&crtc->dev->event_lock, flags);
	196	drm_crtc_send_vblank_event(crtc, ipu_crtc->event);
	197	ipu_crtc->event = NULL;
	198	drm_crtc_vblank_put(crtc);
	199	spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
	200	}
	201	}
f326f799	202
f326f799 SH	203	return IRQ_HANDLED;
	204	}
	205
	206	static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc,
	207	const struct drm_display_mode *mode,
	208	struct drm_display_mode *adjusted_mode)
	209	{
0c460a55 SL	210	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	211	struct videomode vm;
	212	int ret;
	213
	214	drm_display_mode_to_videomode(adjusted_mode, &vm);
	215
	216	ret = ipu_di_adjust_videomode(ipu_crtc->di, &vm);
	217	if (ret)
	218	return false;
	219
33f14235 LY	220	if ((vm.vsync_len == 0) \|\| (vm.hsync_len == 0))
	221	return false;
	222
0c460a55 SL	223	drm_display_mode_from_videomode(&vm, adjusted_mode);
0c460a55 SL	224
f326f799 SH	225	return true;
	226	}
	227
33f14235 LY	228	static int ipu_crtc_atomic_check(struct drm_crtc *crtc,
	229	struct drm_crtc_state *state)
	230	{
2d4569fd	231	u32 primary_plane_mask = drm_plane_mask(crtc->primary);
5f2f9115 LY	232
	233	if (state->active && (primary_plane_mask & state->plane_mask) == 0)
	234	return -EINVAL;
	235
33f14235 LY	236	return 0;
	237	}
	238
5f2f9115 LY	239	static void ipu_crtc_atomic_begin(struct drm_crtc *crtc,
	240	struct drm_crtc_state *old_crtc_state)
	241	{
a4744786	242	drm_crtc_vblank_on(crtc);
6a055b92	243	}
a4744786	244
6a055b92 LS	245	static void ipu_crtc_atomic_flush(struct drm_crtc *crtc,
	246	struct drm_crtc_state *old_crtc_state)
	247	{
5f2f9115 LY	248	spin_lock_irq(&crtc->dev->event_lock);
5f2f9115 LY	249	if (crtc->state->event) {
a0ea4fff LS	250	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
a0ea4fff LS	251
5f2f9115	252	WARN_ON(drm_crtc_vblank_get(crtc));
a0ea4fff	253	ipu_crtc->event = crtc->state->event;
5f2f9115 LY	254	crtc->state->event = NULL;
	255	}
	256	spin_unlock_irq(&crtc->dev->event_lock);
	257	}
	258
33f14235 LY	259	static void ipu_crtc_mode_set_nofb(struct drm_crtc *crtc)
	260	{
	261	struct drm_device *dev = crtc->dev;
	262	struct drm_encoder *encoder;
	263	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	264	struct drm_display_mode *mode = &crtc->state->adjusted_mode;
49f98bc4	265	struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc->state);
33f14235 LY	266	struct ipu_di_signal_cfg sig_cfg = {};
	267	unsigned long encoder_types = 0;
	268
	269	dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__,
	270	mode->hdisplay);
	271	dev_dbg(ipu_crtc->dev, "%s: mode->vdisplay: %d\n", __func__,
	272	mode->vdisplay);
	273
032003c5	274	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
49f98bc4	275	if (encoder->crtc == crtc)
33f14235	276	encoder_types \|= BIT(encoder->encoder_type);
032003c5	277	}
33f14235 LY	278
	279	dev_dbg(ipu_crtc->dev, "%s: attached to encoder types 0x%lx\n",
	280	__func__, encoder_types);
	281
	282	/*
	283	* If we have DAC or LDB, then we need the IPU DI clock to be
	284	* the same as the LDB DI clock. For TVDAC, derive the IPU DI
	285	* clock from 27 MHz TVE_DI clock, but allow to divide it.
	286	*/
	287	if (encoder_types & (BIT(DRM_MODE_ENCODER_DAC) \|
	288	BIT(DRM_MODE_ENCODER_LVDS)))
	289	sig_cfg.clkflags = IPU_DI_CLKMODE_SYNC \| IPU_DI_CLKMODE_EXT;
	290	else if (encoder_types & BIT(DRM_MODE_ENCODER_TVDAC))
	291	sig_cfg.clkflags = IPU_DI_CLKMODE_EXT;
	292	else
	293	sig_cfg.clkflags = 0;
	294
49f98bc4	295	sig_cfg.enable_pol = !(imx_crtc_state->bus_flags & DRM_BUS_FLAG_DE_LOW);
33f14235	296	/* Default to driving pixel data on negative clock edges */
49f98bc4	297	sig_cfg.clk_pol = !!(imx_crtc_state->bus_flags &
33f14235	298	DRM_BUS_FLAG_PIXDATA_POSEDGE);
49f98bc4	299	sig_cfg.bus_format = imx_crtc_state->bus_format;
33f14235	300	sig_cfg.v_to_h_sync = 0;
49f98bc4 PZ	301	sig_cfg.hsync_pin = imx_crtc_state->di_hsync_pin;
49f98bc4 PZ	302	sig_cfg.vsync_pin = imx_crtc_state->di_vsync_pin;
33f14235 LY	303
	304	drm_display_mode_to_videomode(mode, &sig_cfg.mode);
	305
	306	ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di,
	307	mode->flags & DRM_MODE_FLAG_INTERLACE,
49f98bc4	308	imx_crtc_state->bus_format, mode->hdisplay);
33f14235	309	ipu_di_init_sync_panel(ipu_crtc->di, &sig_cfg);
f326f799 SH	310	}
f326f799 SH	311
7ae847dd	312	static const struct drm_crtc_helper_funcs ipu_helper_funcs = {
f326f799	313	.mode_fixup = ipu_crtc_mode_fixup,
33f14235	314	.mode_set_nofb = ipu_crtc_mode_set_nofb,
33f14235	315	.atomic_check = ipu_crtc_atomic_check,
5f2f9115	316	.atomic_begin = ipu_crtc_atomic_begin,
6a055b92	317	.atomic_flush = ipu_crtc_atomic_flush,
8cc17b59	318	.atomic_disable = ipu_crtc_atomic_disable,
0b20a0f8	319	.atomic_enable = ipu_crtc_atomic_enable,
f326f799 SH	320	};
f326f799 SH	321
f326f799 SH	322	static void ipu_put_resources(struct ipu_crtc *ipu_crtc)
f326f799 SH	323	{
b8d181e4 PZ	324	if (!IS_ERR_OR_NULL(ipu_crtc->dc))
b8d181e4 PZ	325	ipu_dc_put(ipu_crtc->dc);
f326f799 SH	326	if (!IS_ERR_OR_NULL(ipu_crtc->di))
	327	ipu_di_put(ipu_crtc->di);
	328	}
	329
	330	static int ipu_get_resources(struct ipu_crtc *ipu_crtc,
	331	struct ipu_client_platformdata *pdata)
	332	{
	333	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
	334	int ret;
	335
f326f799 SH	336	ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc);
	337	if (IS_ERR(ipu_crtc->dc)) {
	338	ret = PTR_ERR(ipu_crtc->dc);
	339	goto err_out;
	340	}
	341
f326f799 SH	342	ipu_crtc->di = ipu_di_get(ipu, pdata->di);
	343	if (IS_ERR(ipu_crtc->di)) {
	344	ret = PTR_ERR(ipu_crtc->di);
	345	goto err_out;
	346	}
	347
f326f799 SH	348	return 0;
	349	err_out:
	350	ipu_put_resources(ipu_crtc);
	351
	352	return ret;
	353	}
	354
	355	static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
32266b45	356	struct ipu_client_platformdata pdata, struct drm_device drm)
f326f799	357	{
47b1be5c	358	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
44b460cf	359	struct drm_crtc *crtc = &ipu_crtc->base;
b8d181e4	360	int dp = -EINVAL;
f326f799 SH	361	int ret;
	362
	363	ret = ipu_get_resources(ipu_crtc, pdata);
	364	if (ret) {
	365	dev_err(ipu_crtc->dev, "getting resources failed with %d.\n",
	366	ret);
	367	return ret;
	368	}
	369
43895599 PZ	370	if (pdata->dp >= 0)
	371	dp = IPU_DP_FLOW_SYNC_BG;
	372	ipu_crtc->plane[0] = ipu_plane_init(drm, ipu, pdata->dma[0], dp, 0,
	373	DRM_PLANE_TYPE_PRIMARY);
a7ed3c2b LY	374	if (IS_ERR(ipu_crtc->plane[0])) {
	375	ret = PTR_ERR(ipu_crtc->plane[0]);
	376	goto err_put_resources;
	377	}
43895599	378
44b460cf SG	379	crtc->port = pdata->of_node;
	380	drm_crtc_helper_add(crtc, &ipu_helper_funcs);
	381	drm_crtc_init_with_planes(drm, crtc, &ipu_crtc->plane[0]->base, NULL,
	382	&ipu_crtc_funcs, NULL);
f326f799	383
b8d181e4 PZ	384	ret = ipu_plane_get_resources(ipu_crtc->plane[0]);
	385	if (ret) {
	386	dev_err(ipu_crtc->dev, "getting plane 0 resources failed with %d.\n",
	387	ret);
44b460cf	388	goto err_put_resources;
b8d181e4 PZ	389	}
	390
	391	/* If this crtc is using the DP, add an overlay plane */
	392	if (pdata->dp >= 0 && pdata->dma[1] > 0) {
43895599 PZ	393	ipu_crtc->plane[1] = ipu_plane_init(drm, ipu, pdata->dma[1],
	394	IPU_DP_FLOW_SYNC_FG,
	395	drm_crtc_mask(&ipu_crtc->base),
	396	DRM_PLANE_TYPE_OVERLAY);
33f14235	397	if (IS_ERR(ipu_crtc->plane[1])) {
b8d181e4	398	ipu_crtc->plane[1] = NULL;
33f14235 LY	399	} else {
	400	ret = ipu_plane_get_resources(ipu_crtc->plane[1]);
	401	if (ret) {
	402	dev_err(ipu_crtc->dev, "getting plane 1 "
	403	"resources failed with %d.\n", ret);
	404	goto err_put_plane0_res;
	405	}
	406	}
b8d181e4 PZ	407	}
	408
	409	ipu_crtc->irq = ipu_plane_irq(ipu_crtc->plane[0]);
47b1be5c PZ	410	ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0,
	411	"imx_drm", ipu_crtc);
	412	if (ret < 0) {
	413	dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret);
33f14235	414	goto err_put_plane1_res;
47b1be5c	415	}
411b0336 LS	416	/* Only enable IRQ when we actually need it to trigger work. */
411b0336 LS	417	disable_irq(ipu_crtc->irq);
47b1be5c	418
f326f799 SH	419	return 0;
f326f799 SH	420
33f14235 LY	421	err_put_plane1_res:
	422	if (ipu_crtc->plane[1])
	423	ipu_plane_put_resources(ipu_crtc->plane[1]);
	424	err_put_plane0_res:
b8d181e4	425	ipu_plane_put_resources(ipu_crtc->plane[0]);
f326f799 SH	426	err_put_resources:
	427	ipu_put_resources(ipu_crtc);
	428
	429	return ret;
	430	}
	431
17b5001b	432	static int ipu_drm_bind(struct device dev, struct device master, void *data)
f326f799	433	{
17b5001b	434	struct ipu_client_platformdata *pdata = dev->platform_data;
32266b45	435	struct drm_device *drm = data;
f326f799 SH	436	struct ipu_crtc *ipu_crtc;
	437	int ret;
	438
17b5001b	439	ipu_crtc = devm_kzalloc(dev, sizeof(*ipu_crtc), GFP_KERNEL);
f326f799 SH	440	if (!ipu_crtc)
	441	return -ENOMEM;
	442
17b5001b	443	ipu_crtc->dev = dev;
f326f799	444
32266b45	445	ret = ipu_crtc_init(ipu_crtc, pdata, drm);
9a8f3f44 LW	446	if (ret)
9a8f3f44 LW	447	return ret;
f326f799	448
17b5001b	449	dev_set_drvdata(dev, ipu_crtc);
f326f799 SH	450
	451	return 0;
	452	}
	453
17b5001b RK	454	static void ipu_drm_unbind(struct device dev, struct device master,
17b5001b RK	455	void *data)
f326f799	456	{
17b5001b	457	struct ipu_crtc *ipu_crtc = dev_get_drvdata(dev);
f326f799	458
f326f799	459	ipu_put_resources(ipu_crtc);
33f14235 LY	460	if (ipu_crtc->plane[1])
	461	ipu_plane_put_resources(ipu_crtc->plane[1]);
	462	ipu_plane_put_resources(ipu_crtc->plane[0]);
17b5001b RK	463	}
	464
	465	static const struct component_ops ipu_crtc_ops = {
	466	.bind = ipu_drm_bind,
	467	.unbind = ipu_drm_unbind,
	468	};
f326f799	469
17b5001b RK	470	static int ipu_drm_probe(struct platform_device *pdev)
17b5001b RK	471	{
655b43cc	472	struct device *dev = &pdev->dev;
17b5001b RK	473	int ret;
17b5001b RK	474
655b43cc	475	if (!dev->platform_data)
17b5001b RK	476	return -EINVAL;
17b5001b RK	477
655b43cc	478	ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
17b5001b RK	479	if (ret)
	480	return ret;
	481
655b43cc	482	return component_add(dev, &ipu_crtc_ops);
17b5001b RK	483	}
	484
	485	static int ipu_drm_remove(struct platform_device *pdev)
	486	{
	487	component_del(&pdev->dev, &ipu_crtc_ops);
f326f799 SH	488	return 0;
	489	}
	490
3d1df96a	491	struct platform_driver ipu_drm_driver = {
f326f799 SH	492	.driver = {
	493	.name = "imx-ipuv3-crtc",
	494	},
	495	.probe = ipu_drm_probe,
99c28f10	496	.remove = ipu_drm_remove,
f326f799	497	};