[linux-2.6-block.git] / drivers / gpu / drm / imx / ipuv3-crtc.c

/*
 * i.MX IPUv3 Graphics driver
 *
 * Copyright (C) 2011 Sascha Hauer, Pengutronix
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
#include <linux/component.h>
#include <linux/module.h>
#include <linux/export.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <drm/drmP.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc_helper.h>
#include <linux/clk.h>
#include <linux/errno.h>
#include <drm/drm_gem_cma_helper.h>
#include <drm/drm_fb_cma_helper.h>

#include <video/imx-ipu-v3.h>
#include "imx-drm.h"
#include "ipuv3-plane.h"

#define DRIVER_DESC		"i.MX IPUv3 Graphics"

struct ipu_crtc {
	struct device		*dev;
	struct drm_crtc		base;
	struct imx_drm_crtc	*imx_crtc;

	/* plane[0] is the full plane, plane[1] is the partial plane */
	struct ipu_plane	*plane[2];

	struct ipu_dc		*dc;
	struct ipu_di		*di;
	int			irq;
};

static inline struct ipu_crtc *to_ipu_crtc(struct drm_crtc *crtc)
{
	return container_of(crtc, struct ipu_crtc, base);
}

static void ipu_crtc_enable(struct drm_crtc *crtc)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);

	ipu_dc_enable(ipu);
	ipu_dc_enable_channel(ipu_crtc->dc);
	ipu_di_enable(ipu_crtc->di);
}

static void ipu_crtc_atomic_disable(struct drm_crtc *crtc,
				    struct drm_crtc_state *old_crtc_state)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);

	ipu_dc_disable_channel(ipu_crtc->dc);
	ipu_di_disable(ipu_crtc->di);
	/*
	 * Planes must be disabled before DC clock is removed, as otherwise the
	 * attached IDMACs will be left in undefined state, possibly hanging
	 * the IPU or even system.
	 */
	drm_atomic_helper_disable_planes_on_crtc(old_crtc_state, false);
	ipu_dc_disable(ipu);

	spin_lock_irq(&crtc->dev->event_lock);
	if (crtc->state->event) {
		drm_crtc_send_vblank_event(crtc, crtc->state->event);
		crtc->state->event = NULL;
	}
	spin_unlock_irq(&crtc->dev->event_lock);

	drm_crtc_vblank_off(crtc);
}

static void imx_drm_crtc_reset(struct drm_crtc *crtc)
{
	struct imx_crtc_state *state;

	if (crtc->state) {
		if (crtc->state->mode_blob)
			drm_property_unreference_blob(crtc->state->mode_blob);

		state = to_imx_crtc_state(crtc->state);
		memset(state, 0, sizeof(*state));
	} else {
		state = kzalloc(sizeof(*state), GFP_KERNEL);
		if (!state)
			return;
		crtc->state = &state->base;
	}

	state->base.crtc = crtc;
}

static struct drm_crtc_state *imx_drm_crtc_duplicate_state(struct drm_crtc *crtc)
{
	struct imx_crtc_state *state;

	state = kzalloc(sizeof(*state), GFP_KERNEL);
	if (!state)
		return NULL;

	__drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);

	WARN_ON(state->base.crtc != crtc);
	state->base.crtc = crtc;

	return &state->base;
}

static void imx_drm_crtc_destroy_state(struct drm_crtc *crtc,
				       struct drm_crtc_state *state)
{
	__drm_atomic_helper_crtc_destroy_state(state);
	kfree(to_imx_crtc_state(state));
}

static void imx_drm_crtc_destroy(struct drm_crtc *crtc)
{
	imx_drm_remove_crtc(to_ipu_crtc(crtc)->imx_crtc);
}

static const struct drm_crtc_funcs ipu_crtc_funcs = {
	.set_config = drm_atomic_helper_set_config,
	.destroy = imx_drm_crtc_destroy,
	.page_flip = drm_atomic_helper_page_flip,
	.reset = imx_drm_crtc_reset,
	.atomic_duplicate_state = imx_drm_crtc_duplicate_state,
	.atomic_destroy_state = imx_drm_crtc_destroy_state,
};

static irqreturn_t ipu_irq_handler(int irq, void *dev_id)
{
	struct ipu_crtc *ipu_crtc = dev_id;

	drm_crtc_handle_vblank(&ipu_crtc->base);

	return IRQ_HANDLED;
}

static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc,
				  const struct drm_display_mode *mode,
				  struct drm_display_mode *adjusted_mode)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	struct videomode vm;
	int ret;

	drm_display_mode_to_videomode(adjusted_mode, &vm);

	ret = ipu_di_adjust_videomode(ipu_crtc->di, &vm);
	if (ret)
		return false;

	if ((vm.vsync_len == 0) || (vm.hsync_len == 0))
		return false;

	drm_display_mode_from_videomode(&vm, adjusted_mode);

	return true;
}

static int ipu_crtc_atomic_check(struct drm_crtc *crtc,
				 struct drm_crtc_state *state)
{
	u32 primary_plane_mask = 1 << drm_plane_index(crtc->primary);

	if (state->active && (primary_plane_mask & state->plane_mask) == 0)
		return -EINVAL;

	return 0;
}

static void ipu_crtc_atomic_begin(struct drm_crtc *crtc,
				  struct drm_crtc_state *old_crtc_state)
{
	drm_crtc_vblank_on(crtc);

	spin_lock_irq(&crtc->dev->event_lock);
	if (crtc->state->event) {
		WARN_ON(drm_crtc_vblank_get(crtc));
		drm_crtc_arm_vblank_event(crtc, crtc->state->event);
		crtc->state->event = NULL;
	}
	spin_unlock_irq(&crtc->dev->event_lock);
}

static void ipu_crtc_mode_set_nofb(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_encoder *encoder;
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	struct drm_display_mode *mode = &crtc->state->adjusted_mode;
	struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc->state);
	struct ipu_di_signal_cfg sig_cfg = {};
	unsigned long encoder_types = 0;

	dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__,
			mode->hdisplay);
	dev_dbg(ipu_crtc->dev, "%s: mode->vdisplay: %d\n", __func__,
			mode->vdisplay);

	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		if (encoder->crtc == crtc)
			encoder_types |= BIT(encoder->encoder_type);
	}

	dev_dbg(ipu_crtc->dev, "%s: attached to encoder types 0x%lx\n",
		__func__, encoder_types);

	/*
	 * If we have DAC or LDB, then we need the IPU DI clock to be
	 * the same as the LDB DI clock. For TVDAC, derive the IPU DI
	 * clock from 27 MHz TVE_DI clock, but allow to divide it.
	 */
	if (encoder_types & (BIT(DRM_MODE_ENCODER_DAC) |
			     BIT(DRM_MODE_ENCODER_LVDS)))
		sig_cfg.clkflags = IPU_DI_CLKMODE_SYNC | IPU_DI_CLKMODE_EXT;
	else if (encoder_types & BIT(DRM_MODE_ENCODER_TVDAC))
		sig_cfg.clkflags = IPU_DI_CLKMODE_EXT;
	else
		sig_cfg.clkflags = 0;

	sig_cfg.enable_pol = !(imx_crtc_state->bus_flags & DRM_BUS_FLAG_DE_LOW);
	/* Default to driving pixel data on negative clock edges */
	sig_cfg.clk_pol = !!(imx_crtc_state->bus_flags &
			     DRM_BUS_FLAG_PIXDATA_POSEDGE);
	sig_cfg.bus_format = imx_crtc_state->bus_format;
	sig_cfg.v_to_h_sync = 0;
	sig_cfg.hsync_pin = imx_crtc_state->di_hsync_pin;
	sig_cfg.vsync_pin = imx_crtc_state->di_vsync_pin;

	drm_display_mode_to_videomode(mode, &sig_cfg.mode);

	ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di,
			 mode->flags & DRM_MODE_FLAG_INTERLACE,
			 imx_crtc_state->bus_format, mode->hdisplay);
	ipu_di_init_sync_panel(ipu_crtc->di, &sig_cfg);
}

static const struct drm_crtc_helper_funcs ipu_helper_funcs = {
	.mode_fixup = ipu_crtc_mode_fixup,
	.mode_set_nofb = ipu_crtc_mode_set_nofb,
	.atomic_check = ipu_crtc_atomic_check,
	.atomic_begin = ipu_crtc_atomic_begin,
	.atomic_disable = ipu_crtc_atomic_disable,
	.enable = ipu_crtc_enable,
};

static int ipu_enable_vblank(struct drm_crtc *crtc)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);

	enable_irq(ipu_crtc->irq);

	return 0;
}

static void ipu_disable_vblank(struct drm_crtc *crtc)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);

	disable_irq_nosync(ipu_crtc->irq);
}

static const struct imx_drm_crtc_helper_funcs ipu_crtc_helper_funcs = {
	.enable_vblank = ipu_enable_vblank,
	.disable_vblank = ipu_disable_vblank,
	.crtc_funcs = &ipu_crtc_funcs,
	.crtc_helper_funcs = &ipu_helper_funcs,
};

static void ipu_put_resources(struct ipu_crtc *ipu_crtc)
{
	if (!IS_ERR_OR_NULL(ipu_crtc->dc))
		ipu_dc_put(ipu_crtc->dc);
	if (!IS_ERR_OR_NULL(ipu_crtc->di))
		ipu_di_put(ipu_crtc->di);
}

static int ipu_get_resources(struct ipu_crtc *ipu_crtc,
		struct ipu_client_platformdata *pdata)
{
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
	int ret;

	ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc);
	if (IS_ERR(ipu_crtc->dc)) {
		ret = PTR_ERR(ipu_crtc->dc);
		goto err_out;
	}

	ipu_crtc->di = ipu_di_get(ipu, pdata->di);
	if (IS_ERR(ipu_crtc->di)) {
		ret = PTR_ERR(ipu_crtc->di);
		goto err_out;
	}

	return 0;
err_out:
	ipu_put_resources(ipu_crtc);

	return ret;
}

static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
	struct ipu_client_platformdata *pdata, struct drm_device *drm)
{
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
	int dp = -EINVAL;
	int ret;

	ret = ipu_get_resources(ipu_crtc, pdata);
	if (ret) {
		dev_err(ipu_crtc->dev, "getting resources failed with %d.\n",
				ret);
		return ret;
	}

	if (pdata->dp >= 0)
		dp = IPU_DP_FLOW_SYNC_BG;
	ipu_crtc->plane[0] = ipu_plane_init(drm, ipu, pdata->dma[0], dp, 0,
					    DRM_PLANE_TYPE_PRIMARY);
	if (IS_ERR(ipu_crtc->plane[0])) {
		ret = PTR_ERR(ipu_crtc->plane[0]);
		goto err_put_resources;
	}

	ret = imx_drm_add_crtc(drm, &ipu_crtc->base, &ipu_crtc->imx_crtc,
			&ipu_crtc->plane[0]->base, &ipu_crtc_helper_funcs,
			pdata->of_node);
	if (ret) {
		dev_err(ipu_crtc->dev, "adding crtc failed with %d.\n", ret);
		goto err_put_resources;
	}

	ret = ipu_plane_get_resources(ipu_crtc->plane[0]);
	if (ret) {
		dev_err(ipu_crtc->dev, "getting plane 0 resources failed with %d.\n",
			ret);
		goto err_remove_crtc;
	}

	/* If this crtc is using the DP, add an overlay plane */
	if (pdata->dp >= 0 && pdata->dma[1] > 0) {
		ipu_crtc->plane[1] = ipu_plane_init(drm, ipu, pdata->dma[1],
						IPU_DP_FLOW_SYNC_FG,
						drm_crtc_mask(&ipu_crtc->base),
						DRM_PLANE_TYPE_OVERLAY);
		if (IS_ERR(ipu_crtc->plane[1])) {
			ipu_crtc->plane[1] = NULL;
		} else {
			ret = ipu_plane_get_resources(ipu_crtc->plane[1]);
			if (ret) {
				dev_err(ipu_crtc->dev, "getting plane 1 "
					"resources failed with %d.\n", ret);
				goto err_put_plane0_res;
			}
		}
	}

	ipu_crtc->irq = ipu_plane_irq(ipu_crtc->plane[0]);
	ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0,
			"imx_drm", ipu_crtc);
	if (ret < 0) {
		dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret);
		goto err_put_plane1_res;
	}
	/* Only enable IRQ when we actually need it to trigger work. */
	disable_irq(ipu_crtc->irq);

	return 0;

err_put_plane1_res:
	if (ipu_crtc->plane[1])
		ipu_plane_put_resources(ipu_crtc->plane[1]);
err_put_plane0_res:
	ipu_plane_put_resources(ipu_crtc->plane[0]);
err_remove_crtc:
	imx_drm_remove_crtc(ipu_crtc->imx_crtc);
err_put_resources:
	ipu_put_resources(ipu_crtc);

	return ret;
}

static int ipu_drm_bind(struct device *dev, struct device *master, void *data)
{
	struct ipu_client_platformdata *pdata = dev->platform_data;
	struct drm_device *drm = data;
	struct ipu_crtc *ipu_crtc;
	int ret;

	ipu_crtc = devm_kzalloc(dev, sizeof(*ipu_crtc), GFP_KERNEL);
	if (!ipu_crtc)
		return -ENOMEM;

	ipu_crtc->dev = dev;

	ret = ipu_crtc_init(ipu_crtc, pdata, drm);
	if (ret)
		return ret;

	dev_set_drvdata(dev, ipu_crtc);

	return 0;
}

static void ipu_drm_unbind(struct device *dev, struct device *master,
	void *data)
{
	struct ipu_crtc *ipu_crtc = dev_get_drvdata(dev);

	ipu_put_resources(ipu_crtc);
	if (ipu_crtc->plane[1])
		ipu_plane_put_resources(ipu_crtc->plane[1]);
	ipu_plane_put_resources(ipu_crtc->plane[0]);
}

static const struct component_ops ipu_crtc_ops = {
	.bind = ipu_drm_bind,
	.unbind = ipu_drm_unbind,
};

static int ipu_drm_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	int ret;

	if (!dev->platform_data)
		return -EINVAL;

	ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
	if (ret)
		return ret;

	return component_add(dev, &ipu_crtc_ops);
}

static int ipu_drm_remove(struct platform_device *pdev)
{
	component_del(&pdev->dev, &ipu_crtc_ops);
	return 0;
}

static struct platform_driver ipu_drm_driver = {
	.driver = {
		.name = "imx-ipuv3-crtc",
	},
	.probe = ipu_drm_probe,
	.remove = ipu_drm_remove,
};
module_platform_driver(ipu_drm_driver);

MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:imx-ipuv3-crtc");
Commit	Line	Data
f326f799 SH	1	/*
	2	* i.MX IPUv3 Graphics driver
	3	*
	4	* Copyright (C) 2011 Sascha Hauer, Pengutronix
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version 2
	9	* of the License, or (at your option) any later version.
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
f326f799	14	*/
17b5001b	15	#include <linux/component.h>
f326f799 SH	16	#include <linux/module.h>
	17	#include <linux/export.h>
	18	#include <linux/device.h>
	19	#include <linux/platform_device.h>
	20	#include <drm/drmP.h>
ae2531ab	21	#include <drm/drm_atomic.h>
255c35f8	22	#include <drm/drm_atomic_helper.h>
f326f799	23	#include <drm/drm_crtc_helper.h>
f326f799	24	#include <linux/clk.h>
b8d181e4	25	#include <linux/errno.h>
f326f799 SH	26	#include <drm/drm_gem_cma_helper.h>
	27	#include <drm/drm_fb_cma_helper.h>
	28
39b9004d	29	#include <video/imx-ipu-v3.h>
f326f799	30	#include "imx-drm.h"
b8d181e4	31	#include "ipuv3-plane.h"
f326f799 SH	32
	33	#define DRIVER_DESC "i.MX IPUv3 Graphics"
	34
f326f799	35	struct ipu_crtc {
f326f799 SH	36	struct device *dev;
	37	struct drm_crtc base;
	38	struct imx_drm_crtc *imx_crtc;
b8d181e4 PZ	39
	40	/* plane[0] is the full plane, plane[1] is the partial plane */
	41	struct ipu_plane *plane[2];
	42
f326f799	43	struct ipu_dc *dc;
f326f799	44	struct ipu_di *di;
f326f799	45	int irq;
f326f799 SH	46	};
f326f799 SH	47
3df07390 PZ	48	static inline struct ipu_crtc to_ipu_crtc(struct drm_crtc crtc)
	49	{
	50	return container_of(crtc, struct ipu_crtc, base);
	51	}
f326f799	52
f6e396e5	53	static void ipu_crtc_enable(struct drm_crtc *crtc)
f326f799	54	{
f6e396e5	55	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
1e6d486b PZ	56	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
1e6d486b PZ	57
1e6d486b	58	ipu_dc_enable(ipu);
c115edb8 PZ	59	ipu_dc_enable_channel(ipu_crtc->dc);
c115edb8 PZ	60	ipu_di_enable(ipu_crtc->di);
f326f799 SH	61	}
f326f799 SH	62
8cc17b59 LY	63	static void ipu_crtc_atomic_disable(struct drm_crtc *crtc,
8cc17b59 LY	64	struct drm_crtc_state *old_crtc_state)
f326f799	65	{
f6e396e5	66	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
1e6d486b	67	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
f326f799	68
f326f799	69	ipu_dc_disable_channel(ipu_crtc->dc);
f326f799	70	ipu_di_disable(ipu_crtc->di);
5ced937b LS	71	/*
	72	* Planes must be disabled before DC clock is removed, as otherwise the
	73	* attached IDMACs will be left in undefined state, possibly hanging
	74	* the IPU or even system.
	75	*/
	76	drm_atomic_helper_disable_planes_on_crtc(old_crtc_state, false);
1e6d486b	77	ipu_dc_disable(ipu);
33f14235	78
5f2f9115 LY	79	spin_lock_irq(&crtc->dev->event_lock);
	80	if (crtc->state->event) {
	81	drm_crtc_send_vblank_event(crtc, crtc->state->event);
	82	crtc->state->event = NULL;
	83	}
	84	spin_unlock_irq(&crtc->dev->event_lock);
5f4df0c7	85
a4744786	86	drm_crtc_vblank_off(crtc);
f326f799 SH	87	}
f326f799 SH	88
49f98bc4 PZ	89	static void imx_drm_crtc_reset(struct drm_crtc *crtc)
	90	{
	91	struct imx_crtc_state *state;
	92
	93	if (crtc->state) {
	94	if (crtc->state->mode_blob)
	95	drm_property_unreference_blob(crtc->state->mode_blob);
	96
	97	state = to_imx_crtc_state(crtc->state);
	98	memset(state, 0, sizeof(*state));
	99	} else {
	100	state = kzalloc(sizeof(*state), GFP_KERNEL);
	101	if (!state)
	102	return;
	103	crtc->state = &state->base;
	104	}
	105
	106	state->base.crtc = crtc;
	107	}
	108
	109	static struct drm_crtc_state imx_drm_crtc_duplicate_state(struct drm_crtc crtc)
	110	{
	111	struct imx_crtc_state *state;
	112
	113	state = kzalloc(sizeof(*state), GFP_KERNEL);
	114	if (!state)
	115	return NULL;
	116
	117	__drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
	118
	119	WARN_ON(state->base.crtc != crtc);
	120	state->base.crtc = crtc;
	121
	122	return &state->base;
	123	}
	124
	125	static void imx_drm_crtc_destroy_state(struct drm_crtc *crtc,
	126	struct drm_crtc_state *state)
	127	{
	128	__drm_atomic_helper_crtc_destroy_state(state);
	129	kfree(to_imx_crtc_state(state));
	130	}
	131
8e3b16e2 LS	132	static void imx_drm_crtc_destroy(struct drm_crtc *crtc)
	133	{
	134	imx_drm_remove_crtc(to_ipu_crtc(crtc)->imx_crtc);
	135	}
	136
f326f799	137	static const struct drm_crtc_funcs ipu_crtc_funcs = {
5f2f9115	138	.set_config = drm_atomic_helper_set_config,
8e3b16e2	139	.destroy = imx_drm_crtc_destroy,
5f2f9115	140	.page_flip = drm_atomic_helper_page_flip,
49f98bc4 PZ	141	.reset = imx_drm_crtc_reset,
	142	.atomic_duplicate_state = imx_drm_crtc_duplicate_state,
	143	.atomic_destroy_state = imx_drm_crtc_destroy_state,
f326f799 SH	144	};
f326f799 SH	145
f326f799 SH	146	static irqreturn_t ipu_irq_handler(int irq, void *dev_id)
	147	{
	148	struct ipu_crtc *ipu_crtc = dev_id;
	149
3ec2e506	150	drm_crtc_handle_vblank(&ipu_crtc->base);
f326f799	151
f326f799 SH	152	return IRQ_HANDLED;
	153	}
	154
	155	static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc,
	156	const struct drm_display_mode *mode,
	157	struct drm_display_mode *adjusted_mode)
	158	{
0c460a55 SL	159	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	160	struct videomode vm;
	161	int ret;
	162
	163	drm_display_mode_to_videomode(adjusted_mode, &vm);
	164
	165	ret = ipu_di_adjust_videomode(ipu_crtc->di, &vm);
	166	if (ret)
	167	return false;
	168
33f14235 LY	169	if ((vm.vsync_len == 0) \|\| (vm.hsync_len == 0))
	170	return false;
	171
0c460a55 SL	172	drm_display_mode_from_videomode(&vm, adjusted_mode);
0c460a55 SL	173
f326f799 SH	174	return true;
	175	}
	176
33f14235 LY	177	static int ipu_crtc_atomic_check(struct drm_crtc *crtc,
	178	struct drm_crtc_state *state)
	179	{
5f2f9115 LY	180	u32 primary_plane_mask = 1 << drm_plane_index(crtc->primary);
	181
	182	if (state->active && (primary_plane_mask & state->plane_mask) == 0)
	183	return -EINVAL;
	184
33f14235 LY	185	return 0;
	186	}
	187
5f2f9115 LY	188	static void ipu_crtc_atomic_begin(struct drm_crtc *crtc,
	189	struct drm_crtc_state *old_crtc_state)
	190	{
a4744786 LS	191	drm_crtc_vblank_on(crtc);
a4744786 LS	192
5f2f9115 LY	193	spin_lock_irq(&crtc->dev->event_lock);
	194	if (crtc->state->event) {
	195	WARN_ON(drm_crtc_vblank_get(crtc));
	196	drm_crtc_arm_vblank_event(crtc, crtc->state->event);
	197	crtc->state->event = NULL;
	198	}
	199	spin_unlock_irq(&crtc->dev->event_lock);
	200	}
	201
33f14235 LY	202	static void ipu_crtc_mode_set_nofb(struct drm_crtc *crtc)
	203	{
	204	struct drm_device *dev = crtc->dev;
	205	struct drm_encoder *encoder;
	206	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	207	struct drm_display_mode *mode = &crtc->state->adjusted_mode;
49f98bc4	208	struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc->state);
33f14235 LY	209	struct ipu_di_signal_cfg sig_cfg = {};
	210	unsigned long encoder_types = 0;
	211
	212	dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__,
	213	mode->hdisplay);
	214	dev_dbg(ipu_crtc->dev, "%s: mode->vdisplay: %d\n", __func__,
	215	mode->vdisplay);
	216
032003c5	217	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
49f98bc4	218	if (encoder->crtc == crtc)
33f14235	219	encoder_types \|= BIT(encoder->encoder_type);
032003c5	220	}
33f14235 LY	221
	222	dev_dbg(ipu_crtc->dev, "%s: attached to encoder types 0x%lx\n",
	223	__func__, encoder_types);
	224
	225	/*
	226	* If we have DAC or LDB, then we need the IPU DI clock to be
	227	* the same as the LDB DI clock. For TVDAC, derive the IPU DI
	228	* clock from 27 MHz TVE_DI clock, but allow to divide it.
	229	*/
	230	if (encoder_types & (BIT(DRM_MODE_ENCODER_DAC) \|
	231	BIT(DRM_MODE_ENCODER_LVDS)))
	232	sig_cfg.clkflags = IPU_DI_CLKMODE_SYNC \| IPU_DI_CLKMODE_EXT;
	233	else if (encoder_types & BIT(DRM_MODE_ENCODER_TVDAC))
	234	sig_cfg.clkflags = IPU_DI_CLKMODE_EXT;
	235	else
	236	sig_cfg.clkflags = 0;
	237
49f98bc4	238	sig_cfg.enable_pol = !(imx_crtc_state->bus_flags & DRM_BUS_FLAG_DE_LOW);
33f14235	239	/* Default to driving pixel data on negative clock edges */
49f98bc4	240	sig_cfg.clk_pol = !!(imx_crtc_state->bus_flags &
33f14235	241	DRM_BUS_FLAG_PIXDATA_POSEDGE);
49f98bc4	242	sig_cfg.bus_format = imx_crtc_state->bus_format;
33f14235	243	sig_cfg.v_to_h_sync = 0;
49f98bc4 PZ	244	sig_cfg.hsync_pin = imx_crtc_state->di_hsync_pin;
49f98bc4 PZ	245	sig_cfg.vsync_pin = imx_crtc_state->di_vsync_pin;
33f14235 LY	246
	247	drm_display_mode_to_videomode(mode, &sig_cfg.mode);
	248
	249	ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di,
	250	mode->flags & DRM_MODE_FLAG_INTERLACE,
49f98bc4	251	imx_crtc_state->bus_format, mode->hdisplay);
33f14235	252	ipu_di_init_sync_panel(ipu_crtc->di, &sig_cfg);
f326f799 SH	253	}
f326f799 SH	254
7ae847dd	255	static const struct drm_crtc_helper_funcs ipu_helper_funcs = {
f326f799	256	.mode_fixup = ipu_crtc_mode_fixup,
33f14235	257	.mode_set_nofb = ipu_crtc_mode_set_nofb,
33f14235	258	.atomic_check = ipu_crtc_atomic_check,
5f2f9115	259	.atomic_begin = ipu_crtc_atomic_begin,
8cc17b59	260	.atomic_disable = ipu_crtc_atomic_disable,
f6e396e5	261	.enable = ipu_crtc_enable,
f326f799 SH	262	};
	263
	264	static int ipu_enable_vblank(struct drm_crtc *crtc)
	265	{
411b0336 LS	266	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	267
	268	enable_irq(ipu_crtc->irq);
	269
f326f799 SH	270	return 0;
	271	}
	272
	273	static void ipu_disable_vblank(struct drm_crtc *crtc)
	274	{
411b0336 LS	275	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	276
	277	disable_irq_nosync(ipu_crtc->irq);
f326f799 SH	278	}
f326f799 SH	279
f326f799 SH	280	static const struct imx_drm_crtc_helper_funcs ipu_crtc_helper_funcs = {
	281	.enable_vblank = ipu_enable_vblank,
	282	.disable_vblank = ipu_disable_vblank,
f326f799 SH	283	.crtc_funcs = &ipu_crtc_funcs,
	284	.crtc_helper_funcs = &ipu_helper_funcs,
	285	};
	286
	287	static void ipu_put_resources(struct ipu_crtc *ipu_crtc)
	288	{
b8d181e4 PZ	289	if (!IS_ERR_OR_NULL(ipu_crtc->dc))
b8d181e4 PZ	290	ipu_dc_put(ipu_crtc->dc);
f326f799 SH	291	if (!IS_ERR_OR_NULL(ipu_crtc->di))
	292	ipu_di_put(ipu_crtc->di);
	293	}
	294
	295	static int ipu_get_resources(struct ipu_crtc *ipu_crtc,
	296	struct ipu_client_platformdata *pdata)
	297	{
	298	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
	299	int ret;
	300
f326f799 SH	301	ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc);
	302	if (IS_ERR(ipu_crtc->dc)) {
	303	ret = PTR_ERR(ipu_crtc->dc);
	304	goto err_out;
	305	}
	306
f326f799 SH	307	ipu_crtc->di = ipu_di_get(ipu, pdata->di);
	308	if (IS_ERR(ipu_crtc->di)) {
	309	ret = PTR_ERR(ipu_crtc->di);
	310	goto err_out;
	311	}
	312
f326f799 SH	313	return 0;
	314	err_out:
	315	ipu_put_resources(ipu_crtc);
	316
	317	return ret;
	318	}
	319
	320	static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
32266b45	321	struct ipu_client_platformdata pdata, struct drm_device drm)
f326f799	322	{
47b1be5c	323	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
b8d181e4	324	int dp = -EINVAL;
f326f799 SH	325	int ret;
	326
	327	ret = ipu_get_resources(ipu_crtc, pdata);
	328	if (ret) {
	329	dev_err(ipu_crtc->dev, "getting resources failed with %d.\n",
	330	ret);
	331	return ret;
	332	}
	333
43895599 PZ	334	if (pdata->dp >= 0)
	335	dp = IPU_DP_FLOW_SYNC_BG;
	336	ipu_crtc->plane[0] = ipu_plane_init(drm, ipu, pdata->dma[0], dp, 0,
	337	DRM_PLANE_TYPE_PRIMARY);
a7ed3c2b LY	338	if (IS_ERR(ipu_crtc->plane[0])) {
	339	ret = PTR_ERR(ipu_crtc->plane[0]);
	340	goto err_put_resources;
	341	}
43895599	342
655b43cc	343	ret = imx_drm_add_crtc(drm, &ipu_crtc->base, &ipu_crtc->imx_crtc,
43895599	344	&ipu_crtc->plane[0]->base, &ipu_crtc_helper_funcs,
310944d1	345	pdata->of_node);
f326f799 SH	346	if (ret) {
	347	dev_err(ipu_crtc->dev, "adding crtc failed with %d.\n", ret);
	348	goto err_put_resources;
	349	}
	350
b8d181e4 PZ	351	ret = ipu_plane_get_resources(ipu_crtc->plane[0]);
	352	if (ret) {
	353	dev_err(ipu_crtc->dev, "getting plane 0 resources failed with %d.\n",
	354	ret);
	355	goto err_remove_crtc;
	356	}
	357
	358	/* If this crtc is using the DP, add an overlay plane */
	359	if (pdata->dp >= 0 && pdata->dma[1] > 0) {
43895599 PZ	360	ipu_crtc->plane[1] = ipu_plane_init(drm, ipu, pdata->dma[1],
	361	IPU_DP_FLOW_SYNC_FG,
	362	drm_crtc_mask(&ipu_crtc->base),
	363	DRM_PLANE_TYPE_OVERLAY);
33f14235	364	if (IS_ERR(ipu_crtc->plane[1])) {
b8d181e4	365	ipu_crtc->plane[1] = NULL;
33f14235 LY	366	} else {
	367	ret = ipu_plane_get_resources(ipu_crtc->plane[1]);
	368	if (ret) {
	369	dev_err(ipu_crtc->dev, "getting plane 1 "
	370	"resources failed with %d.\n", ret);
	371	goto err_put_plane0_res;
	372	}
	373	}
b8d181e4 PZ	374	}
	375
	376	ipu_crtc->irq = ipu_plane_irq(ipu_crtc->plane[0]);
47b1be5c PZ	377	ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0,
	378	"imx_drm", ipu_crtc);
	379	if (ret < 0) {
	380	dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret);
33f14235	381	goto err_put_plane1_res;
47b1be5c	382	}
411b0336 LS	383	/* Only enable IRQ when we actually need it to trigger work. */
411b0336 LS	384	disable_irq(ipu_crtc->irq);
47b1be5c	385
f326f799 SH	386	return 0;
f326f799 SH	387
33f14235 LY	388	err_put_plane1_res:
	389	if (ipu_crtc->plane[1])
	390	ipu_plane_put_resources(ipu_crtc->plane[1]);
	391	err_put_plane0_res:
b8d181e4 PZ	392	ipu_plane_put_resources(ipu_crtc->plane[0]);
	393	err_remove_crtc:
	394	imx_drm_remove_crtc(ipu_crtc->imx_crtc);
f326f799 SH	395	err_put_resources:
	396	ipu_put_resources(ipu_crtc);
	397
	398	return ret;
	399	}
	400
17b5001b	401	static int ipu_drm_bind(struct device dev, struct device master, void *data)
f326f799	402	{
17b5001b	403	struct ipu_client_platformdata *pdata = dev->platform_data;
32266b45	404	struct drm_device *drm = data;
f326f799 SH	405	struct ipu_crtc *ipu_crtc;
	406	int ret;
	407
17b5001b	408	ipu_crtc = devm_kzalloc(dev, sizeof(*ipu_crtc), GFP_KERNEL);
f326f799 SH	409	if (!ipu_crtc)
	410	return -ENOMEM;
	411
17b5001b	412	ipu_crtc->dev = dev;
f326f799	413
32266b45	414	ret = ipu_crtc_init(ipu_crtc, pdata, drm);
9a8f3f44 LW	415	if (ret)
9a8f3f44 LW	416	return ret;
f326f799	417
17b5001b	418	dev_set_drvdata(dev, ipu_crtc);
f326f799 SH	419
	420	return 0;
	421	}
	422
17b5001b RK	423	static void ipu_drm_unbind(struct device dev, struct device master,
17b5001b RK	424	void *data)
f326f799	425	{
17b5001b	426	struct ipu_crtc *ipu_crtc = dev_get_drvdata(dev);
f326f799	427
f326f799	428	ipu_put_resources(ipu_crtc);
33f14235 LY	429	if (ipu_crtc->plane[1])
	430	ipu_plane_put_resources(ipu_crtc->plane[1]);
	431	ipu_plane_put_resources(ipu_crtc->plane[0]);
17b5001b RK	432	}
	433
	434	static const struct component_ops ipu_crtc_ops = {
	435	.bind = ipu_drm_bind,
	436	.unbind = ipu_drm_unbind,
	437	};
f326f799	438
17b5001b RK	439	static int ipu_drm_probe(struct platform_device *pdev)
17b5001b RK	440	{
655b43cc	441	struct device *dev = &pdev->dev;
17b5001b RK	442	int ret;
17b5001b RK	443
655b43cc	444	if (!dev->platform_data)
17b5001b RK	445	return -EINVAL;
17b5001b RK	446
655b43cc	447	ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
17b5001b RK	448	if (ret)
	449	return ret;
	450
655b43cc	451	return component_add(dev, &ipu_crtc_ops);
17b5001b RK	452	}
	453
	454	static int ipu_drm_remove(struct platform_device *pdev)
	455	{
	456	component_del(&pdev->dev, &ipu_crtc_ops);
f326f799 SH	457	return 0;
	458	}
	459
	460	static struct platform_driver ipu_drm_driver = {
	461	.driver = {
	462	.name = "imx-ipuv3-crtc",
	463	},
	464	.probe = ipu_drm_probe,
99c28f10	465	.remove = ipu_drm_remove,
f326f799 SH	466	};
	467	module_platform_driver(ipu_drm_driver);
	468
	469	MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
	470	MODULE_DESCRIPTION(DRIVER_DESC);
	471	MODULE_LICENSE("GPL");
ce9c1cef	472	MODULE_ALIAS("platform:imx-ipuv3-crtc");