[linux-2.6-block.git] / drivers / gpu / drm / imx / ipuv3-crtc.c

/*
 * i.MX IPUv3 Graphics driver
 *
 * Copyright (C) 2011 Sascha Hauer, Pengutronix
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
#include <linux/component.h>
#include <linux/module.h>
#include <linux/export.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <drm/drmP.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc_helper.h>
#include <linux/clk.h>
#include <linux/errno.h>
#include <drm/drm_gem_cma_helper.h>
#include <drm/drm_fb_cma_helper.h>

#include <video/imx-ipu-v3.h>
#include "imx-drm.h"
#include "ipuv3-plane.h"

#define DRIVER_DESC		"i.MX IPUv3 Graphics"

struct ipu_crtc {
	struct device		*dev;
	struct drm_crtc		base;
	struct imx_drm_crtc	*imx_crtc;

	/* plane[0] is the full plane, plane[1] is the partial plane */
	struct ipu_plane	*plane[2];

	struct ipu_dc		*dc;
	struct ipu_di		*di;
	int			irq;
};

static inline struct ipu_crtc *to_ipu_crtc(struct drm_crtc *crtc)
{
	return container_of(crtc, struct ipu_crtc, base);
}

static void ipu_crtc_atomic_enable(struct drm_crtc *crtc,
				   struct drm_crtc_state *old_state)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);

	ipu_prg_enable(ipu);
	ipu_dc_enable(ipu);
	ipu_dc_enable_channel(ipu_crtc->dc);
	ipu_di_enable(ipu_crtc->di);
}

static void ipu_crtc_disable_planes(struct ipu_crtc *ipu_crtc,
				    struct drm_crtc_state *old_crtc_state)
{
	bool disable_partial = false;
	bool disable_full = false;
	struct drm_plane *plane;

	drm_atomic_crtc_state_for_each_plane(plane, old_crtc_state) {
		if (plane == &ipu_crtc->plane[0]->base)
			disable_full = true;
		if (&ipu_crtc->plane[1] && plane == &ipu_crtc->plane[1]->base)
			disable_partial = true;
	}

	if (disable_partial)
		ipu_plane_disable(ipu_crtc->plane[1], true);
	if (disable_full)
		ipu_plane_disable(ipu_crtc->plane[0], false);
}

static void ipu_crtc_atomic_disable(struct drm_crtc *crtc,
				    struct drm_crtc_state *old_crtc_state)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);

	ipu_dc_disable_channel(ipu_crtc->dc);
	ipu_di_disable(ipu_crtc->di);
	/*
	 * Planes must be disabled before DC clock is removed, as otherwise the
	 * attached IDMACs will be left in undefined state, possibly hanging
	 * the IPU or even system.
	 */
	ipu_crtc_disable_planes(ipu_crtc, old_crtc_state);
	ipu_dc_disable(ipu);
	ipu_prg_disable(ipu);

	spin_lock_irq(&crtc->dev->event_lock);
	if (crtc->state->event) {
		drm_crtc_send_vblank_event(crtc, crtc->state->event);
		crtc->state->event = NULL;
	}
	spin_unlock_irq(&crtc->dev->event_lock);

	drm_crtc_vblank_off(crtc);
}

static void imx_drm_crtc_reset(struct drm_crtc *crtc)
{
	struct imx_crtc_state *state;

	if (crtc->state) {
		if (crtc->state->mode_blob)
			drm_property_blob_put(crtc->state->mode_blob);

		state = to_imx_crtc_state(crtc->state);
		memset(state, 0, sizeof(*state));
	} else {
		state = kzalloc(sizeof(*state), GFP_KERNEL);
		if (!state)
			return;
		crtc->state = &state->base;
	}

	state->base.crtc = crtc;
}

static struct drm_crtc_state *imx_drm_crtc_duplicate_state(struct drm_crtc *crtc)
{
	struct imx_crtc_state *state;

	state = kzalloc(sizeof(*state), GFP_KERNEL);
	if (!state)
		return NULL;

	__drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);

	WARN_ON(state->base.crtc != crtc);
	state->base.crtc = crtc;

	return &state->base;
}

static void imx_drm_crtc_destroy_state(struct drm_crtc *crtc,
				       struct drm_crtc_state *state)
{
	__drm_atomic_helper_crtc_destroy_state(state);
	kfree(to_imx_crtc_state(state));
}

static int ipu_enable_vblank(struct drm_crtc *crtc)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);

	enable_irq(ipu_crtc->irq);

	return 0;
}

static void ipu_disable_vblank(struct drm_crtc *crtc)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);

	disable_irq_nosync(ipu_crtc->irq);
}

static const struct drm_crtc_funcs ipu_crtc_funcs = {
	.set_config = drm_atomic_helper_set_config,
	.destroy = drm_crtc_cleanup,
	.page_flip = drm_atomic_helper_page_flip,
	.reset = imx_drm_crtc_reset,
	.atomic_duplicate_state = imx_drm_crtc_duplicate_state,
	.atomic_destroy_state = imx_drm_crtc_destroy_state,
	.enable_vblank = ipu_enable_vblank,
	.disable_vblank = ipu_disable_vblank,
};

static irqreturn_t ipu_irq_handler(int irq, void *dev_id)
{
	struct ipu_crtc *ipu_crtc = dev_id;

	drm_crtc_handle_vblank(&ipu_crtc->base);

	return IRQ_HANDLED;
}

static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc,
				  const struct drm_display_mode *mode,
				  struct drm_display_mode *adjusted_mode)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	struct videomode vm;
	int ret;

	drm_display_mode_to_videomode(adjusted_mode, &vm);

	ret = ipu_di_adjust_videomode(ipu_crtc->di, &vm);
	if (ret)
		return false;

	if ((vm.vsync_len == 0) || (vm.hsync_len == 0))
		return false;

	drm_display_mode_from_videomode(&vm, adjusted_mode);

	return true;
}

static int ipu_crtc_atomic_check(struct drm_crtc *crtc,
				 struct drm_crtc_state *state)
{
	u32 primary_plane_mask = 1 << drm_plane_index(crtc->primary);

	if (state->active && (primary_plane_mask & state->plane_mask) == 0)
		return -EINVAL;

	return 0;
}

static void ipu_crtc_atomic_begin(struct drm_crtc *crtc,
				  struct drm_crtc_state *old_crtc_state)
{
	drm_crtc_vblank_on(crtc);
}

static void ipu_crtc_atomic_flush(struct drm_crtc *crtc,
				  struct drm_crtc_state *old_crtc_state)
{
	spin_lock_irq(&crtc->dev->event_lock);
	if (crtc->state->event) {
		WARN_ON(drm_crtc_vblank_get(crtc));
		drm_crtc_arm_vblank_event(crtc, crtc->state->event);
		crtc->state->event = NULL;
	}
	spin_unlock_irq(&crtc->dev->event_lock);
}

static void ipu_crtc_mode_set_nofb(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_encoder *encoder;
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	struct drm_display_mode *mode = &crtc->state->adjusted_mode;
	struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc->state);
	struct ipu_di_signal_cfg sig_cfg = {};
	unsigned long encoder_types = 0;

	dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__,
			mode->hdisplay);
	dev_dbg(ipu_crtc->dev, "%s: mode->vdisplay: %d\n", __func__,
			mode->vdisplay);

	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		if (encoder->crtc == crtc)
			encoder_types |= BIT(encoder->encoder_type);
	}

	dev_dbg(ipu_crtc->dev, "%s: attached to encoder types 0x%lx\n",
		__func__, encoder_types);

	/*
	 * If we have DAC or LDB, then we need the IPU DI clock to be
	 * the same as the LDB DI clock. For TVDAC, derive the IPU DI
	 * clock from 27 MHz TVE_DI clock, but allow to divide it.
	 */
	if (encoder_types & (BIT(DRM_MODE_ENCODER_DAC) |
			     BIT(DRM_MODE_ENCODER_LVDS)))
		sig_cfg.clkflags = IPU_DI_CLKMODE_SYNC | IPU_DI_CLKMODE_EXT;
	else if (encoder_types & BIT(DRM_MODE_ENCODER_TVDAC))
		sig_cfg.clkflags = IPU_DI_CLKMODE_EXT;
	else
		sig_cfg.clkflags = 0;

	sig_cfg.enable_pol = !(imx_crtc_state->bus_flags & DRM_BUS_FLAG_DE_LOW);
	/* Default to driving pixel data on negative clock edges */
	sig_cfg.clk_pol = !!(imx_crtc_state->bus_flags &
			     DRM_BUS_FLAG_PIXDATA_POSEDGE);
	sig_cfg.bus_format = imx_crtc_state->bus_format;
	sig_cfg.v_to_h_sync = 0;
	sig_cfg.hsync_pin = imx_crtc_state->di_hsync_pin;
	sig_cfg.vsync_pin = imx_crtc_state->di_vsync_pin;

	drm_display_mode_to_videomode(mode, &sig_cfg.mode);

	ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di,
			 mode->flags & DRM_MODE_FLAG_INTERLACE,
			 imx_crtc_state->bus_format, mode->hdisplay);
	ipu_di_init_sync_panel(ipu_crtc->di, &sig_cfg);
}

static const struct drm_crtc_helper_funcs ipu_helper_funcs = {
	.mode_fixup = ipu_crtc_mode_fixup,
	.mode_set_nofb = ipu_crtc_mode_set_nofb,
	.atomic_check = ipu_crtc_atomic_check,
	.atomic_begin = ipu_crtc_atomic_begin,
	.atomic_flush = ipu_crtc_atomic_flush,
	.atomic_disable = ipu_crtc_atomic_disable,
	.atomic_enable = ipu_crtc_atomic_enable,
};

static void ipu_put_resources(struct ipu_crtc *ipu_crtc)
{
	if (!IS_ERR_OR_NULL(ipu_crtc->dc))
		ipu_dc_put(ipu_crtc->dc);
	if (!IS_ERR_OR_NULL(ipu_crtc->di))
		ipu_di_put(ipu_crtc->di);
}

static int ipu_get_resources(struct ipu_crtc *ipu_crtc,
		struct ipu_client_platformdata *pdata)
{
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
	int ret;

	ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc);
	if (IS_ERR(ipu_crtc->dc)) {
		ret = PTR_ERR(ipu_crtc->dc);
		goto err_out;
	}

	ipu_crtc->di = ipu_di_get(ipu, pdata->di);
	if (IS_ERR(ipu_crtc->di)) {
		ret = PTR_ERR(ipu_crtc->di);
		goto err_out;
	}

	return 0;
err_out:
	ipu_put_resources(ipu_crtc);

	return ret;
}

static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
	struct ipu_client_platformdata *pdata, struct drm_device *drm)
{
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
	struct drm_crtc *crtc = &ipu_crtc->base;
	int dp = -EINVAL;
	int ret;

	ret = ipu_get_resources(ipu_crtc, pdata);
	if (ret) {
		dev_err(ipu_crtc->dev, "getting resources failed with %d.\n",
				ret);
		return ret;
	}

	if (pdata->dp >= 0)
		dp = IPU_DP_FLOW_SYNC_BG;
	ipu_crtc->plane[0] = ipu_plane_init(drm, ipu, pdata->dma[0], dp, 0,
					    DRM_PLANE_TYPE_PRIMARY);
	if (IS_ERR(ipu_crtc->plane[0])) {
		ret = PTR_ERR(ipu_crtc->plane[0]);
		goto err_put_resources;
	}

	crtc->port = pdata->of_node;
	drm_crtc_helper_add(crtc, &ipu_helper_funcs);
	drm_crtc_init_with_planes(drm, crtc, &ipu_crtc->plane[0]->base, NULL,
				  &ipu_crtc_funcs, NULL);

	ret = ipu_plane_get_resources(ipu_crtc->plane[0]);
	if (ret) {
		dev_err(ipu_crtc->dev, "getting plane 0 resources failed with %d.\n",
			ret);
		goto err_put_resources;
	}

	/* If this crtc is using the DP, add an overlay plane */
	if (pdata->dp >= 0 && pdata->dma[1] > 0) {
		ipu_crtc->plane[1] = ipu_plane_init(drm, ipu, pdata->dma[1],
						IPU_DP_FLOW_SYNC_FG,
						drm_crtc_mask(&ipu_crtc->base),
						DRM_PLANE_TYPE_OVERLAY);
		if (IS_ERR(ipu_crtc->plane[1])) {
			ipu_crtc->plane[1] = NULL;
		} else {
			ret = ipu_plane_get_resources(ipu_crtc->plane[1]);
			if (ret) {
				dev_err(ipu_crtc->dev, "getting plane 1 "
					"resources failed with %d.\n", ret);
				goto err_put_plane0_res;
			}
		}
	}

	ipu_crtc->irq = ipu_plane_irq(ipu_crtc->plane[0]);
	ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0,
			"imx_drm", ipu_crtc);
	if (ret < 0) {
		dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret);
		goto err_put_plane1_res;
	}
	/* Only enable IRQ when we actually need it to trigger work. */
	disable_irq(ipu_crtc->irq);

	return 0;

err_put_plane1_res:
	if (ipu_crtc->plane[1])
		ipu_plane_put_resources(ipu_crtc->plane[1]);
err_put_plane0_res:
	ipu_plane_put_resources(ipu_crtc->plane[0]);
err_put_resources:
	ipu_put_resources(ipu_crtc);

	return ret;
}

static int ipu_drm_bind(struct device *dev, struct device *master, void *data)
{
	struct ipu_client_platformdata *pdata = dev->platform_data;
	struct drm_device *drm = data;
	struct ipu_crtc *ipu_crtc;
	int ret;

	ipu_crtc = devm_kzalloc(dev, sizeof(*ipu_crtc), GFP_KERNEL);
	if (!ipu_crtc)
		return -ENOMEM;

	ipu_crtc->dev = dev;

	ret = ipu_crtc_init(ipu_crtc, pdata, drm);
	if (ret)
		return ret;

	dev_set_drvdata(dev, ipu_crtc);

	return 0;
}

static void ipu_drm_unbind(struct device *dev, struct device *master,
	void *data)
{
	struct ipu_crtc *ipu_crtc = dev_get_drvdata(dev);

	ipu_put_resources(ipu_crtc);
	if (ipu_crtc->plane[1])
		ipu_plane_put_resources(ipu_crtc->plane[1]);
	ipu_plane_put_resources(ipu_crtc->plane[0]);
}

static const struct component_ops ipu_crtc_ops = {
	.bind = ipu_drm_bind,
	.unbind = ipu_drm_unbind,
};

static int ipu_drm_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	int ret;

	if (!dev->platform_data)
		return -EINVAL;

	ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
	if (ret)
		return ret;

	return component_add(dev, &ipu_crtc_ops);
}

static int ipu_drm_remove(struct platform_device *pdev)
{
	component_del(&pdev->dev, &ipu_crtc_ops);
	return 0;
}

struct platform_driver ipu_drm_driver = {
	.driver = {
		.name = "imx-ipuv3-crtc",
	},
	.probe = ipu_drm_probe,
	.remove = ipu_drm_remove,
};
Commit	Line	Data
f326f799 SH	1	/*
	2	* i.MX IPUv3 Graphics driver
	3	*
	4	* Copyright (C) 2011 Sascha Hauer, Pengutronix
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version 2
	9	* of the License, or (at your option) any later version.
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
f326f799	14	*/
17b5001b	15	#include <linux/component.h>
f326f799 SH	16	#include <linux/module.h>
	17	#include <linux/export.h>
	18	#include <linux/device.h>
	19	#include <linux/platform_device.h>
	20	#include <drm/drmP.h>
ae2531ab	21	#include <drm/drm_atomic.h>
255c35f8	22	#include <drm/drm_atomic_helper.h>
f326f799	23	#include <drm/drm_crtc_helper.h>
f326f799	24	#include <linux/clk.h>
b8d181e4	25	#include <linux/errno.h>
f326f799 SH	26	#include <drm/drm_gem_cma_helper.h>
	27	#include <drm/drm_fb_cma_helper.h>
	28
39b9004d	29	#include <video/imx-ipu-v3.h>
f326f799	30	#include "imx-drm.h"
b8d181e4	31	#include "ipuv3-plane.h"
f326f799 SH	32
	33	#define DRIVER_DESC "i.MX IPUv3 Graphics"
	34
f326f799	35	struct ipu_crtc {
f326f799 SH	36	struct device *dev;
	37	struct drm_crtc base;
	38	struct imx_drm_crtc *imx_crtc;
b8d181e4 PZ	39
	40	/* plane[0] is the full plane, plane[1] is the partial plane */
	41	struct ipu_plane *plane[2];
	42
f326f799	43	struct ipu_dc *dc;
f326f799	44	struct ipu_di *di;
f326f799	45	int irq;
f326f799 SH	46	};
f326f799 SH	47
3df07390 PZ	48	static inline struct ipu_crtc to_ipu_crtc(struct drm_crtc crtc)
	49	{
	50	return container_of(crtc, struct ipu_crtc, base);
	51	}
f326f799	52
0b20a0f8 LP	53	static void ipu_crtc_atomic_enable(struct drm_crtc *crtc,
0b20a0f8 LP	54	struct drm_crtc_state *old_state)
f326f799	55	{
f6e396e5	56	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
1e6d486b PZ	57	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
1e6d486b PZ	58
e0fb7dd2	59	ipu_prg_enable(ipu);
1e6d486b	60	ipu_dc_enable(ipu);
c115edb8 PZ	61	ipu_dc_enable_channel(ipu_crtc->dc);
c115edb8 PZ	62	ipu_di_enable(ipu_crtc->di);
f326f799 SH	63	}
f326f799 SH	64
eb8c8880 PZ	65	static void ipu_crtc_disable_planes(struct ipu_crtc *ipu_crtc,
	66	struct drm_crtc_state *old_crtc_state)
	67	{
	68	bool disable_partial = false;
	69	bool disable_full = false;
	70	struct drm_plane *plane;
	71
	72	drm_atomic_crtc_state_for_each_plane(plane, old_crtc_state) {
	73	if (plane == &ipu_crtc->plane[0]->base)
	74	disable_full = true;
	75	if (&ipu_crtc->plane[1] && plane == &ipu_crtc->plane[1]->base)
	76	disable_partial = true;
	77	}
	78
	79	if (disable_partial)
	80	ipu_plane_disable(ipu_crtc->plane[1], true);
	81	if (disable_full)
	82	ipu_plane_disable(ipu_crtc->plane[0], false);
	83	}
	84
8cc17b59 LY	85	static void ipu_crtc_atomic_disable(struct drm_crtc *crtc,
8cc17b59 LY	86	struct drm_crtc_state *old_crtc_state)
f326f799	87	{
f6e396e5	88	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
1e6d486b	89	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
f326f799	90
f326f799	91	ipu_dc_disable_channel(ipu_crtc->dc);
f326f799	92	ipu_di_disable(ipu_crtc->di);
5ced937b LS	93	/*
	94	* Planes must be disabled before DC clock is removed, as otherwise the
	95	* attached IDMACs will be left in undefined state, possibly hanging
	96	* the IPU or even system.
	97	*/
eb8c8880	98	ipu_crtc_disable_planes(ipu_crtc, old_crtc_state);
1e6d486b	99	ipu_dc_disable(ipu);
e0fb7dd2	100	ipu_prg_disable(ipu);
33f14235	101
5f2f9115 LY	102	spin_lock_irq(&crtc->dev->event_lock);
	103	if (crtc->state->event) {
	104	drm_crtc_send_vblank_event(crtc, crtc->state->event);
	105	crtc->state->event = NULL;
	106	}
	107	spin_unlock_irq(&crtc->dev->event_lock);
5f4df0c7	108
a4744786	109	drm_crtc_vblank_off(crtc);
f326f799 SH	110	}
f326f799 SH	111
49f98bc4 PZ	112	static void imx_drm_crtc_reset(struct drm_crtc *crtc)
	113	{
	114	struct imx_crtc_state *state;
	115
	116	if (crtc->state) {
	117	if (crtc->state->mode_blob)
a8f2023d	118	drm_property_blob_put(crtc->state->mode_blob);
49f98bc4 PZ	119
	120	state = to_imx_crtc_state(crtc->state);
	121	memset(state, 0, sizeof(*state));
	122	} else {
	123	state = kzalloc(sizeof(*state), GFP_KERNEL);
	124	if (!state)
	125	return;
	126	crtc->state = &state->base;
	127	}
	128
	129	state->base.crtc = crtc;
	130	}
	131
	132	static struct drm_crtc_state imx_drm_crtc_duplicate_state(struct drm_crtc crtc)
	133	{
	134	struct imx_crtc_state *state;
	135
	136	state = kzalloc(sizeof(*state), GFP_KERNEL);
	137	if (!state)
	138	return NULL;
	139
	140	__drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
	141
	142	WARN_ON(state->base.crtc != crtc);
	143	state->base.crtc = crtc;
	144
	145	return &state->base;
	146	}
	147
	148	static void imx_drm_crtc_destroy_state(struct drm_crtc *crtc,
	149	struct drm_crtc_state *state)
	150	{
	151	__drm_atomic_helper_crtc_destroy_state(state);
	152	kfree(to_imx_crtc_state(state));
	153	}
	154
44b460cf SG	155	static int ipu_enable_vblank(struct drm_crtc *crtc)
	156	{
	157	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	158
	159	enable_irq(ipu_crtc->irq);
	160
	161	return 0;
	162	}
	163
	164	static void ipu_disable_vblank(struct drm_crtc *crtc)
8e3b16e2	165	{
44b460cf SG	166	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	167
	168	disable_irq_nosync(ipu_crtc->irq);
8e3b16e2 LS	169	}
8e3b16e2 LS	170
f326f799	171	static const struct drm_crtc_funcs ipu_crtc_funcs = {
5f2f9115	172	.set_config = drm_atomic_helper_set_config,
44b460cf	173	.destroy = drm_crtc_cleanup,
5f2f9115	174	.page_flip = drm_atomic_helper_page_flip,
49f98bc4 PZ	175	.reset = imx_drm_crtc_reset,
	176	.atomic_duplicate_state = imx_drm_crtc_duplicate_state,
	177	.atomic_destroy_state = imx_drm_crtc_destroy_state,
44b460cf SG	178	.enable_vblank = ipu_enable_vblank,
44b460cf SG	179	.disable_vblank = ipu_disable_vblank,
f326f799 SH	180	};
f326f799 SH	181
f326f799 SH	182	static irqreturn_t ipu_irq_handler(int irq, void *dev_id)
	183	{
	184	struct ipu_crtc *ipu_crtc = dev_id;
	185
3ec2e506	186	drm_crtc_handle_vblank(&ipu_crtc->base);
f326f799	187
f326f799 SH	188	return IRQ_HANDLED;
	189	}
	190
	191	static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc,
	192	const struct drm_display_mode *mode,
	193	struct drm_display_mode *adjusted_mode)
	194	{
0c460a55 SL	195	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	196	struct videomode vm;
	197	int ret;
	198
	199	drm_display_mode_to_videomode(adjusted_mode, &vm);
	200
	201	ret = ipu_di_adjust_videomode(ipu_crtc->di, &vm);
	202	if (ret)
	203	return false;
	204
33f14235 LY	205	if ((vm.vsync_len == 0) \|\| (vm.hsync_len == 0))
	206	return false;
	207
0c460a55 SL	208	drm_display_mode_from_videomode(&vm, adjusted_mode);
0c460a55 SL	209
f326f799 SH	210	return true;
	211	}
	212
33f14235 LY	213	static int ipu_crtc_atomic_check(struct drm_crtc *crtc,
	214	struct drm_crtc_state *state)
	215	{
5f2f9115 LY	216	u32 primary_plane_mask = 1 << drm_plane_index(crtc->primary);
	217
	218	if (state->active && (primary_plane_mask & state->plane_mask) == 0)
	219	return -EINVAL;
	220
33f14235 LY	221	return 0;
	222	}
	223
5f2f9115 LY	224	static void ipu_crtc_atomic_begin(struct drm_crtc *crtc,
	225	struct drm_crtc_state *old_crtc_state)
	226	{
a4744786	227	drm_crtc_vblank_on(crtc);
6a055b92	228	}
a4744786	229
6a055b92 LS	230	static void ipu_crtc_atomic_flush(struct drm_crtc *crtc,
	231	struct drm_crtc_state *old_crtc_state)
	232	{
5f2f9115 LY	233	spin_lock_irq(&crtc->dev->event_lock);
	234	if (crtc->state->event) {
	235	WARN_ON(drm_crtc_vblank_get(crtc));
	236	drm_crtc_arm_vblank_event(crtc, crtc->state->event);
	237	crtc->state->event = NULL;
	238	}
	239	spin_unlock_irq(&crtc->dev->event_lock);
	240	}
	241
33f14235 LY	242	static void ipu_crtc_mode_set_nofb(struct drm_crtc *crtc)
	243	{
	244	struct drm_device *dev = crtc->dev;
	245	struct drm_encoder *encoder;
	246	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	247	struct drm_display_mode *mode = &crtc->state->adjusted_mode;
49f98bc4	248	struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc->state);
33f14235 LY	249	struct ipu_di_signal_cfg sig_cfg = {};
	250	unsigned long encoder_types = 0;
	251
	252	dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__,
	253	mode->hdisplay);
	254	dev_dbg(ipu_crtc->dev, "%s: mode->vdisplay: %d\n", __func__,
	255	mode->vdisplay);
	256
032003c5	257	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
49f98bc4	258	if (encoder->crtc == crtc)
33f14235	259	encoder_types \|= BIT(encoder->encoder_type);
032003c5	260	}
33f14235 LY	261
	262	dev_dbg(ipu_crtc->dev, "%s: attached to encoder types 0x%lx\n",
	263	__func__, encoder_types);
	264
	265	/*
	266	* If we have DAC or LDB, then we need the IPU DI clock to be
	267	* the same as the LDB DI clock. For TVDAC, derive the IPU DI
	268	* clock from 27 MHz TVE_DI clock, but allow to divide it.
	269	*/
	270	if (encoder_types & (BIT(DRM_MODE_ENCODER_DAC) \|
	271	BIT(DRM_MODE_ENCODER_LVDS)))
	272	sig_cfg.clkflags = IPU_DI_CLKMODE_SYNC \| IPU_DI_CLKMODE_EXT;
	273	else if (encoder_types & BIT(DRM_MODE_ENCODER_TVDAC))
	274	sig_cfg.clkflags = IPU_DI_CLKMODE_EXT;
	275	else
	276	sig_cfg.clkflags = 0;
	277
49f98bc4	278	sig_cfg.enable_pol = !(imx_crtc_state->bus_flags & DRM_BUS_FLAG_DE_LOW);
33f14235	279	/* Default to driving pixel data on negative clock edges */
49f98bc4	280	sig_cfg.clk_pol = !!(imx_crtc_state->bus_flags &
33f14235	281	DRM_BUS_FLAG_PIXDATA_POSEDGE);
49f98bc4	282	sig_cfg.bus_format = imx_crtc_state->bus_format;
33f14235	283	sig_cfg.v_to_h_sync = 0;
49f98bc4 PZ	284	sig_cfg.hsync_pin = imx_crtc_state->di_hsync_pin;
49f98bc4 PZ	285	sig_cfg.vsync_pin = imx_crtc_state->di_vsync_pin;
33f14235 LY	286
	287	drm_display_mode_to_videomode(mode, &sig_cfg.mode);
	288
	289	ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di,
	290	mode->flags & DRM_MODE_FLAG_INTERLACE,
49f98bc4	291	imx_crtc_state->bus_format, mode->hdisplay);
33f14235	292	ipu_di_init_sync_panel(ipu_crtc->di, &sig_cfg);
f326f799 SH	293	}
f326f799 SH	294
7ae847dd	295	static const struct drm_crtc_helper_funcs ipu_helper_funcs = {
f326f799	296	.mode_fixup = ipu_crtc_mode_fixup,
33f14235	297	.mode_set_nofb = ipu_crtc_mode_set_nofb,
33f14235	298	.atomic_check = ipu_crtc_atomic_check,
5f2f9115	299	.atomic_begin = ipu_crtc_atomic_begin,
6a055b92	300	.atomic_flush = ipu_crtc_atomic_flush,
8cc17b59	301	.atomic_disable = ipu_crtc_atomic_disable,
0b20a0f8	302	.atomic_enable = ipu_crtc_atomic_enable,
f326f799 SH	303	};
f326f799 SH	304
f326f799 SH	305	static void ipu_put_resources(struct ipu_crtc *ipu_crtc)
f326f799 SH	306	{
b8d181e4 PZ	307	if (!IS_ERR_OR_NULL(ipu_crtc->dc))
b8d181e4 PZ	308	ipu_dc_put(ipu_crtc->dc);
f326f799 SH	309	if (!IS_ERR_OR_NULL(ipu_crtc->di))
	310	ipu_di_put(ipu_crtc->di);
	311	}
	312
	313	static int ipu_get_resources(struct ipu_crtc *ipu_crtc,
	314	struct ipu_client_platformdata *pdata)
	315	{
	316	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
	317	int ret;
	318
f326f799 SH	319	ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc);
	320	if (IS_ERR(ipu_crtc->dc)) {
	321	ret = PTR_ERR(ipu_crtc->dc);
	322	goto err_out;
	323	}
	324
f326f799 SH	325	ipu_crtc->di = ipu_di_get(ipu, pdata->di);
	326	if (IS_ERR(ipu_crtc->di)) {
	327	ret = PTR_ERR(ipu_crtc->di);
	328	goto err_out;
	329	}
	330
f326f799 SH	331	return 0;
	332	err_out:
	333	ipu_put_resources(ipu_crtc);
	334
	335	return ret;
	336	}
	337
	338	static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
32266b45	339	struct ipu_client_platformdata pdata, struct drm_device drm)
f326f799	340	{
47b1be5c	341	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
44b460cf	342	struct drm_crtc *crtc = &ipu_crtc->base;
b8d181e4	343	int dp = -EINVAL;
f326f799 SH	344	int ret;
	345
	346	ret = ipu_get_resources(ipu_crtc, pdata);
	347	if (ret) {
	348	dev_err(ipu_crtc->dev, "getting resources failed with %d.\n",
	349	ret);
	350	return ret;
	351	}
	352
43895599 PZ	353	if (pdata->dp >= 0)
	354	dp = IPU_DP_FLOW_SYNC_BG;
	355	ipu_crtc->plane[0] = ipu_plane_init(drm, ipu, pdata->dma[0], dp, 0,
	356	DRM_PLANE_TYPE_PRIMARY);
a7ed3c2b LY	357	if (IS_ERR(ipu_crtc->plane[0])) {
	358	ret = PTR_ERR(ipu_crtc->plane[0]);
	359	goto err_put_resources;
	360	}
43895599	361
44b460cf SG	362	crtc->port = pdata->of_node;
	363	drm_crtc_helper_add(crtc, &ipu_helper_funcs);
	364	drm_crtc_init_with_planes(drm, crtc, &ipu_crtc->plane[0]->base, NULL,
	365	&ipu_crtc_funcs, NULL);
f326f799	366
b8d181e4 PZ	367	ret = ipu_plane_get_resources(ipu_crtc->plane[0]);
	368	if (ret) {
	369	dev_err(ipu_crtc->dev, "getting plane 0 resources failed with %d.\n",
	370	ret);
44b460cf	371	goto err_put_resources;
b8d181e4 PZ	372	}
	373
	374	/* If this crtc is using the DP, add an overlay plane */
	375	if (pdata->dp >= 0 && pdata->dma[1] > 0) {
43895599 PZ	376	ipu_crtc->plane[1] = ipu_plane_init(drm, ipu, pdata->dma[1],
	377	IPU_DP_FLOW_SYNC_FG,
	378	drm_crtc_mask(&ipu_crtc->base),
	379	DRM_PLANE_TYPE_OVERLAY);
33f14235	380	if (IS_ERR(ipu_crtc->plane[1])) {
b8d181e4	381	ipu_crtc->plane[1] = NULL;
33f14235 LY	382	} else {
	383	ret = ipu_plane_get_resources(ipu_crtc->plane[1]);
	384	if (ret) {
	385	dev_err(ipu_crtc->dev, "getting plane 1 "
	386	"resources failed with %d.\n", ret);
	387	goto err_put_plane0_res;
	388	}
	389	}
b8d181e4 PZ	390	}
	391
	392	ipu_crtc->irq = ipu_plane_irq(ipu_crtc->plane[0]);
47b1be5c PZ	393	ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0,
	394	"imx_drm", ipu_crtc);
	395	if (ret < 0) {
	396	dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret);
33f14235	397	goto err_put_plane1_res;
47b1be5c	398	}
411b0336 LS	399	/* Only enable IRQ when we actually need it to trigger work. */
411b0336 LS	400	disable_irq(ipu_crtc->irq);
47b1be5c	401
f326f799 SH	402	return 0;
f326f799 SH	403
33f14235 LY	404	err_put_plane1_res:
	405	if (ipu_crtc->plane[1])
	406	ipu_plane_put_resources(ipu_crtc->plane[1]);
	407	err_put_plane0_res:
b8d181e4	408	ipu_plane_put_resources(ipu_crtc->plane[0]);
f326f799 SH	409	err_put_resources:
	410	ipu_put_resources(ipu_crtc);
	411
	412	return ret;
	413	}
	414
17b5001b	415	static int ipu_drm_bind(struct device dev, struct device master, void *data)
f326f799	416	{
17b5001b	417	struct ipu_client_platformdata *pdata = dev->platform_data;
32266b45	418	struct drm_device *drm = data;
f326f799 SH	419	struct ipu_crtc *ipu_crtc;
	420	int ret;
	421
17b5001b	422	ipu_crtc = devm_kzalloc(dev, sizeof(*ipu_crtc), GFP_KERNEL);
f326f799 SH	423	if (!ipu_crtc)
	424	return -ENOMEM;
	425
17b5001b	426	ipu_crtc->dev = dev;
f326f799	427
32266b45	428	ret = ipu_crtc_init(ipu_crtc, pdata, drm);
9a8f3f44 LW	429	if (ret)
9a8f3f44 LW	430	return ret;
f326f799	431
17b5001b	432	dev_set_drvdata(dev, ipu_crtc);
f326f799 SH	433
	434	return 0;
	435	}
	436
17b5001b RK	437	static void ipu_drm_unbind(struct device dev, struct device master,
17b5001b RK	438	void *data)
f326f799	439	{
17b5001b	440	struct ipu_crtc *ipu_crtc = dev_get_drvdata(dev);
f326f799	441
f326f799	442	ipu_put_resources(ipu_crtc);
33f14235 LY	443	if (ipu_crtc->plane[1])
	444	ipu_plane_put_resources(ipu_crtc->plane[1]);
	445	ipu_plane_put_resources(ipu_crtc->plane[0]);
17b5001b RK	446	}
	447
	448	static const struct component_ops ipu_crtc_ops = {
	449	.bind = ipu_drm_bind,
	450	.unbind = ipu_drm_unbind,
	451	};
f326f799	452
17b5001b RK	453	static int ipu_drm_probe(struct platform_device *pdev)
17b5001b RK	454	{
655b43cc	455	struct device *dev = &pdev->dev;
17b5001b RK	456	int ret;
17b5001b RK	457
655b43cc	458	if (!dev->platform_data)
17b5001b RK	459	return -EINVAL;
17b5001b RK	460
655b43cc	461	ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
17b5001b RK	462	if (ret)
	463	return ret;
	464
655b43cc	465	return component_add(dev, &ipu_crtc_ops);
17b5001b RK	466	}
	467
	468	static int ipu_drm_remove(struct platform_device *pdev)
	469	{
	470	component_del(&pdev->dev, &ipu_crtc_ops);
f326f799 SH	471	return 0;
	472	}
	473
3d1df96a	474	struct platform_driver ipu_drm_driver = {
f326f799 SH	475	.driver = {
	476	.name = "imx-ipuv3-crtc",
	477	},
	478	.probe = ipu_drm_probe,
99c28f10	479	.remove = ipu_drm_remove,
f326f799	480	};