[linux-2.6-block.git] / drivers / gpu / drm / imx / ipuv3-crtc.c

/*
 * i.MX IPUv3 Graphics driver
 *
 * Copyright (C) 2011 Sascha Hauer, Pengutronix
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
#include <linux/component.h>
#include <linux/module.h>
#include <linux/export.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <drm/drmP.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc_helper.h>
#include <linux/fb.h>
#include <linux/clk.h>
#include <linux/errno.h>
#include <drm/drm_gem_cma_helper.h>
#include <drm/drm_fb_cma_helper.h>

#include <video/imx-ipu-v3.h>
#include "imx-drm.h"
#include "ipuv3-plane.h"

#define DRIVER_DESC		"i.MX IPUv3 Graphics"

struct ipu_crtc {
	struct device		*dev;
	struct drm_crtc		base;
	struct imx_drm_crtc	*imx_crtc;

	/* plane[0] is the full plane, plane[1] is the partial plane */
	struct ipu_plane	*plane[2];

	struct ipu_dc		*dc;
	struct ipu_di		*di;
	int			irq;
};

static inline struct ipu_crtc *to_ipu_crtc(struct drm_crtc *crtc)
{
	return container_of(crtc, struct ipu_crtc, base);
}

static void ipu_crtc_enable(struct drm_crtc *crtc)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);

	ipu_dc_enable(ipu);
	ipu_dc_enable_channel(ipu_crtc->dc);
	ipu_di_enable(ipu_crtc->di);
}

static void ipu_crtc_disable(struct drm_crtc *crtc)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);

	ipu_dc_disable_channel(ipu_crtc->dc);
	ipu_di_disable(ipu_crtc->di);
	ipu_dc_disable(ipu);

	spin_lock_irq(&crtc->dev->event_lock);
	if (crtc->state->event) {
		drm_crtc_send_vblank_event(crtc, crtc->state->event);
		crtc->state->event = NULL;
	}
	spin_unlock_irq(&crtc->dev->event_lock);

	drm_crtc_vblank_off(crtc);
}

static void imx_drm_crtc_reset(struct drm_crtc *crtc)
{
	struct imx_crtc_state *state;

	if (crtc->state) {
		if (crtc->state->mode_blob)
			drm_property_unreference_blob(crtc->state->mode_blob);

		state = to_imx_crtc_state(crtc->state);
		memset(state, 0, sizeof(*state));
	} else {
		state = kzalloc(sizeof(*state), GFP_KERNEL);
		if (!state)
			return;
		crtc->state = &state->base;
	}

	state->base.crtc = crtc;
}

static struct drm_crtc_state *imx_drm_crtc_duplicate_state(struct drm_crtc *crtc)
{
	struct imx_crtc_state *state;

	state = kzalloc(sizeof(*state), GFP_KERNEL);
	if (!state)
		return NULL;

	__drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);

	WARN_ON(state->base.crtc != crtc);
	state->base.crtc = crtc;

	return &state->base;
}

static void imx_drm_crtc_destroy_state(struct drm_crtc *crtc,
				       struct drm_crtc_state *state)
{
	__drm_atomic_helper_crtc_destroy_state(state);
	kfree(to_imx_crtc_state(state));
}

static const struct drm_crtc_funcs ipu_crtc_funcs = {
	.set_config = drm_atomic_helper_set_config,
	.destroy = drm_crtc_cleanup,
	.page_flip = drm_atomic_helper_page_flip,
	.reset = imx_drm_crtc_reset,
	.atomic_duplicate_state = imx_drm_crtc_duplicate_state,
	.atomic_destroy_state = imx_drm_crtc_destroy_state,
};

static irqreturn_t ipu_irq_handler(int irq, void *dev_id)
{
	struct ipu_crtc *ipu_crtc = dev_id;

	imx_drm_handle_vblank(ipu_crtc->imx_crtc);

	return IRQ_HANDLED;
}

static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc,
				  const struct drm_display_mode *mode,
				  struct drm_display_mode *adjusted_mode)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	struct videomode vm;
	int ret;

	drm_display_mode_to_videomode(adjusted_mode, &vm);

	ret = ipu_di_adjust_videomode(ipu_crtc->di, &vm);
	if (ret)
		return false;

	if ((vm.vsync_len == 0) || (vm.hsync_len == 0))
		return false;

	drm_display_mode_from_videomode(&vm, adjusted_mode);

	return true;
}

static int ipu_crtc_atomic_check(struct drm_crtc *crtc,
				 struct drm_crtc_state *state)
{
	u32 primary_plane_mask = 1 << drm_plane_index(crtc->primary);

	if (state->active && (primary_plane_mask & state->plane_mask) == 0)
		return -EINVAL;

	return 0;
}

static void ipu_crtc_atomic_begin(struct drm_crtc *crtc,
				  struct drm_crtc_state *old_crtc_state)
{
	drm_crtc_vblank_on(crtc);

	spin_lock_irq(&crtc->dev->event_lock);
	if (crtc->state->event) {
		WARN_ON(drm_crtc_vblank_get(crtc));
		drm_crtc_arm_vblank_event(crtc, crtc->state->event);
		crtc->state->event = NULL;
	}
	spin_unlock_irq(&crtc->dev->event_lock);
}

static void ipu_crtc_mode_set_nofb(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_encoder *encoder;
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	struct drm_display_mode *mode = &crtc->state->adjusted_mode;
	struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc->state);
	struct ipu_di_signal_cfg sig_cfg = {};
	unsigned long encoder_types = 0;

	dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__,
			mode->hdisplay);
	dev_dbg(ipu_crtc->dev, "%s: mode->vdisplay: %d\n", __func__,
			mode->vdisplay);

	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		if (encoder->crtc == crtc)
			encoder_types |= BIT(encoder->encoder_type);
	}

	dev_dbg(ipu_crtc->dev, "%s: attached to encoder types 0x%lx\n",
		__func__, encoder_types);

	/*
	 * If we have DAC or LDB, then we need the IPU DI clock to be
	 * the same as the LDB DI clock. For TVDAC, derive the IPU DI
	 * clock from 27 MHz TVE_DI clock, but allow to divide it.
	 */
	if (encoder_types & (BIT(DRM_MODE_ENCODER_DAC) |
			     BIT(DRM_MODE_ENCODER_LVDS)))
		sig_cfg.clkflags = IPU_DI_CLKMODE_SYNC | IPU_DI_CLKMODE_EXT;
	else if (encoder_types & BIT(DRM_MODE_ENCODER_TVDAC))
		sig_cfg.clkflags = IPU_DI_CLKMODE_EXT;
	else
		sig_cfg.clkflags = 0;

	sig_cfg.enable_pol = !(imx_crtc_state->bus_flags & DRM_BUS_FLAG_DE_LOW);
	/* Default to driving pixel data on negative clock edges */
	sig_cfg.clk_pol = !!(imx_crtc_state->bus_flags &
			     DRM_BUS_FLAG_PIXDATA_POSEDGE);
	sig_cfg.bus_format = imx_crtc_state->bus_format;
	sig_cfg.v_to_h_sync = 0;
	sig_cfg.hsync_pin = imx_crtc_state->di_hsync_pin;
	sig_cfg.vsync_pin = imx_crtc_state->di_vsync_pin;

	drm_display_mode_to_videomode(mode, &sig_cfg.mode);

	ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di,
			 mode->flags & DRM_MODE_FLAG_INTERLACE,
			 imx_crtc_state->bus_format, mode->hdisplay);
	ipu_di_init_sync_panel(ipu_crtc->di, &sig_cfg);
}

static const struct drm_crtc_helper_funcs ipu_helper_funcs = {
	.mode_fixup = ipu_crtc_mode_fixup,
	.mode_set_nofb = ipu_crtc_mode_set_nofb,
	.atomic_check = ipu_crtc_atomic_check,
	.atomic_begin = ipu_crtc_atomic_begin,
	.disable = ipu_crtc_disable,
	.enable = ipu_crtc_enable,
};

static int ipu_enable_vblank(struct drm_crtc *crtc)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);

	enable_irq(ipu_crtc->irq);

	return 0;
}

static void ipu_disable_vblank(struct drm_crtc *crtc)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);

	disable_irq_nosync(ipu_crtc->irq);
}

static const struct imx_drm_crtc_helper_funcs ipu_crtc_helper_funcs = {
	.enable_vblank = ipu_enable_vblank,
	.disable_vblank = ipu_disable_vblank,
	.crtc_funcs = &ipu_crtc_funcs,
	.crtc_helper_funcs = &ipu_helper_funcs,
};

static void ipu_put_resources(struct ipu_crtc *ipu_crtc)
{
	if (!IS_ERR_OR_NULL(ipu_crtc->dc))
		ipu_dc_put(ipu_crtc->dc);
	if (!IS_ERR_OR_NULL(ipu_crtc->di))
		ipu_di_put(ipu_crtc->di);
}

static int ipu_get_resources(struct ipu_crtc *ipu_crtc,
		struct ipu_client_platformdata *pdata)
{
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
	int ret;

	ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc);
	if (IS_ERR(ipu_crtc->dc)) {
		ret = PTR_ERR(ipu_crtc->dc);
		goto err_out;
	}

	ipu_crtc->di = ipu_di_get(ipu, pdata->di);
	if (IS_ERR(ipu_crtc->di)) {
		ret = PTR_ERR(ipu_crtc->di);
		goto err_out;
	}

	return 0;
err_out:
	ipu_put_resources(ipu_crtc);

	return ret;
}

static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
	struct ipu_client_platformdata *pdata, struct drm_device *drm)
{
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
	int dp = -EINVAL;
	int ret;

	ret = ipu_get_resources(ipu_crtc, pdata);
	if (ret) {
		dev_err(ipu_crtc->dev, "getting resources failed with %d.\n",
				ret);
		return ret;
	}

	if (pdata->dp >= 0)
		dp = IPU_DP_FLOW_SYNC_BG;
	ipu_crtc->plane[0] = ipu_plane_init(drm, ipu, pdata->dma[0], dp, 0,
					    DRM_PLANE_TYPE_PRIMARY);
	if (IS_ERR(ipu_crtc->plane[0])) {
		ret = PTR_ERR(ipu_crtc->plane[0]);
		goto err_put_resources;
	}

	ret = imx_drm_add_crtc(drm, &ipu_crtc->base, &ipu_crtc->imx_crtc,
			&ipu_crtc->plane[0]->base, &ipu_crtc_helper_funcs,
			pdata->of_node);
	if (ret) {
		dev_err(ipu_crtc->dev, "adding crtc failed with %d.\n", ret);
		goto err_put_resources;
	}

	ret = ipu_plane_get_resources(ipu_crtc->plane[0]);
	if (ret) {
		dev_err(ipu_crtc->dev, "getting plane 0 resources failed with %d.\n",
			ret);
		goto err_remove_crtc;
	}

	/* If this crtc is using the DP, add an overlay plane */
	if (pdata->dp >= 0 && pdata->dma[1] > 0) {
		ipu_crtc->plane[1] = ipu_plane_init(drm, ipu, pdata->dma[1],
						IPU_DP_FLOW_SYNC_FG,
						drm_crtc_mask(&ipu_crtc->base),
						DRM_PLANE_TYPE_OVERLAY);
		if (IS_ERR(ipu_crtc->plane[1])) {
			ipu_crtc->plane[1] = NULL;
		} else {
			ret = ipu_plane_get_resources(ipu_crtc->plane[1]);
			if (ret) {
				dev_err(ipu_crtc->dev, "getting plane 1 "
					"resources failed with %d.\n", ret);
				goto err_put_plane0_res;
			}
		}
	}

	ipu_crtc->irq = ipu_plane_irq(ipu_crtc->plane[0]);
	ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0,
			"imx_drm", ipu_crtc);
	if (ret < 0) {
		dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret);
		goto err_put_plane1_res;
	}
	/* Only enable IRQ when we actually need it to trigger work. */
	disable_irq(ipu_crtc->irq);

	return 0;

err_put_plane1_res:
	if (ipu_crtc->plane[1])
		ipu_plane_put_resources(ipu_crtc->plane[1]);
err_put_plane0_res:
	ipu_plane_put_resources(ipu_crtc->plane[0]);
err_remove_crtc:
	imx_drm_remove_crtc(ipu_crtc->imx_crtc);
err_put_resources:
	ipu_put_resources(ipu_crtc);

	return ret;
}

static int ipu_drm_bind(struct device *dev, struct device *master, void *data)
{
	struct ipu_client_platformdata *pdata = dev->platform_data;
	struct drm_device *drm = data;
	struct ipu_crtc *ipu_crtc;
	int ret;

	ipu_crtc = devm_kzalloc(dev, sizeof(*ipu_crtc), GFP_KERNEL);
	if (!ipu_crtc)
		return -ENOMEM;

	ipu_crtc->dev = dev;

	ret = ipu_crtc_init(ipu_crtc, pdata, drm);
	if (ret)
		return ret;

	dev_set_drvdata(dev, ipu_crtc);

	return 0;
}

static void ipu_drm_unbind(struct device *dev, struct device *master,
	void *data)
{
	struct ipu_crtc *ipu_crtc = dev_get_drvdata(dev);

	imx_drm_remove_crtc(ipu_crtc->imx_crtc);

	ipu_put_resources(ipu_crtc);
	if (ipu_crtc->plane[1])
		ipu_plane_put_resources(ipu_crtc->plane[1]);
	ipu_plane_put_resources(ipu_crtc->plane[0]);
}

static const struct component_ops ipu_crtc_ops = {
	.bind = ipu_drm_bind,
	.unbind = ipu_drm_unbind,
};

static int ipu_drm_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	int ret;

	if (!dev->platform_data)
		return -EINVAL;

	ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
	if (ret)
		return ret;

	return component_add(dev, &ipu_crtc_ops);
}

static int ipu_drm_remove(struct platform_device *pdev)
{
	component_del(&pdev->dev, &ipu_crtc_ops);
	return 0;
}

static struct platform_driver ipu_drm_driver = {
	.driver = {
		.name = "imx-ipuv3-crtc",
	},
	.probe = ipu_drm_probe,
	.remove = ipu_drm_remove,
};
module_platform_driver(ipu_drm_driver);

MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:imx-ipuv3-crtc");
Commit	Line	Data
f326f799 SH	1	/*
	2	* i.MX IPUv3 Graphics driver
	3	*
	4	* Copyright (C) 2011 Sascha Hauer, Pengutronix
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version 2
	9	* of the License, or (at your option) any later version.
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
f326f799	14	*/
17b5001b	15	#include <linux/component.h>
f326f799 SH	16	#include <linux/module.h>
	17	#include <linux/export.h>
	18	#include <linux/device.h>
	19	#include <linux/platform_device.h>
	20	#include <drm/drmP.h>
ae2531ab	21	#include <drm/drm_atomic.h>
255c35f8	22	#include <drm/drm_atomic_helper.h>
f326f799 SH	23	#include <drm/drm_crtc_helper.h>
	24	#include <linux/fb.h>
	25	#include <linux/clk.h>
b8d181e4	26	#include <linux/errno.h>
f326f799 SH	27	#include <drm/drm_gem_cma_helper.h>
	28	#include <drm/drm_fb_cma_helper.h>
	29
39b9004d	30	#include <video/imx-ipu-v3.h>
f326f799	31	#include "imx-drm.h"
b8d181e4	32	#include "ipuv3-plane.h"
f326f799 SH	33
	34	#define DRIVER_DESC "i.MX IPUv3 Graphics"
	35
f326f799	36	struct ipu_crtc {
f326f799 SH	37	struct device *dev;
	38	struct drm_crtc base;
	39	struct imx_drm_crtc *imx_crtc;
b8d181e4 PZ	40
	41	/* plane[0] is the full plane, plane[1] is the partial plane */
	42	struct ipu_plane *plane[2];
	43
f326f799	44	struct ipu_dc *dc;
f326f799	45	struct ipu_di *di;
f326f799	46	int irq;
f326f799 SH	47	};
f326f799 SH	48
3df07390 PZ	49	static inline struct ipu_crtc to_ipu_crtc(struct drm_crtc crtc)
	50	{
	51	return container_of(crtc, struct ipu_crtc, base);
	52	}
f326f799	53
f6e396e5	54	static void ipu_crtc_enable(struct drm_crtc *crtc)
f326f799	55	{
f6e396e5	56	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
1e6d486b PZ	57	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
1e6d486b PZ	58
1e6d486b	59	ipu_dc_enable(ipu);
c115edb8 PZ	60	ipu_dc_enable_channel(ipu_crtc->dc);
c115edb8 PZ	61	ipu_di_enable(ipu_crtc->di);
f326f799 SH	62	}
f326f799 SH	63
f6e396e5	64	static void ipu_crtc_disable(struct drm_crtc *crtc)
f326f799	65	{
f6e396e5	66	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
1e6d486b	67	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
f326f799	68
f326f799	69	ipu_dc_disable_channel(ipu_crtc->dc);
f326f799	70	ipu_di_disable(ipu_crtc->di);
1e6d486b	71	ipu_dc_disable(ipu);
33f14235	72
5f2f9115 LY	73	spin_lock_irq(&crtc->dev->event_lock);
	74	if (crtc->state->event) {
	75	drm_crtc_send_vblank_event(crtc, crtc->state->event);
	76	crtc->state->event = NULL;
	77	}
	78	spin_unlock_irq(&crtc->dev->event_lock);
a4744786 LS	79
a4744786 LS	80	drm_crtc_vblank_off(crtc);
f326f799 SH	81	}
f326f799 SH	82
49f98bc4 PZ	83	static void imx_drm_crtc_reset(struct drm_crtc *crtc)
	84	{
	85	struct imx_crtc_state *state;
	86
	87	if (crtc->state) {
	88	if (crtc->state->mode_blob)
	89	drm_property_unreference_blob(crtc->state->mode_blob);
	90
	91	state = to_imx_crtc_state(crtc->state);
	92	memset(state, 0, sizeof(*state));
	93	} else {
	94	state = kzalloc(sizeof(*state), GFP_KERNEL);
	95	if (!state)
	96	return;
	97	crtc->state = &state->base;
	98	}
	99
	100	state->base.crtc = crtc;
	101	}
	102
	103	static struct drm_crtc_state imx_drm_crtc_duplicate_state(struct drm_crtc crtc)
	104	{
	105	struct imx_crtc_state *state;
	106
	107	state = kzalloc(sizeof(*state), GFP_KERNEL);
	108	if (!state)
	109	return NULL;
	110
	111	__drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
	112
	113	WARN_ON(state->base.crtc != crtc);
	114	state->base.crtc = crtc;
	115
	116	return &state->base;
	117	}
	118
	119	static void imx_drm_crtc_destroy_state(struct drm_crtc *crtc,
	120	struct drm_crtc_state *state)
	121	{
	122	__drm_atomic_helper_crtc_destroy_state(state);
	123	kfree(to_imx_crtc_state(state));
	124	}
	125
f326f799	126	static const struct drm_crtc_funcs ipu_crtc_funcs = {
5f2f9115	127	.set_config = drm_atomic_helper_set_config,
f326f799	128	.destroy = drm_crtc_cleanup,
5f2f9115	129	.page_flip = drm_atomic_helper_page_flip,
49f98bc4 PZ	130	.reset = imx_drm_crtc_reset,
	131	.atomic_duplicate_state = imx_drm_crtc_duplicate_state,
	132	.atomic_destroy_state = imx_drm_crtc_destroy_state,
f326f799 SH	133	};
f326f799 SH	134
f326f799 SH	135	static irqreturn_t ipu_irq_handler(int irq, void *dev_id)
	136	{
	137	struct ipu_crtc *ipu_crtc = dev_id;
	138
	139	imx_drm_handle_vblank(ipu_crtc->imx_crtc);
	140
f326f799 SH	141	return IRQ_HANDLED;
	142	}
	143
	144	static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc,
	145	const struct drm_display_mode *mode,
	146	struct drm_display_mode *adjusted_mode)
	147	{
0c460a55 SL	148	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	149	struct videomode vm;
	150	int ret;
	151
	152	drm_display_mode_to_videomode(adjusted_mode, &vm);
	153
	154	ret = ipu_di_adjust_videomode(ipu_crtc->di, &vm);
	155	if (ret)
	156	return false;
	157
33f14235 LY	158	if ((vm.vsync_len == 0) \|\| (vm.hsync_len == 0))
	159	return false;
	160
0c460a55 SL	161	drm_display_mode_from_videomode(&vm, adjusted_mode);
0c460a55 SL	162
f326f799 SH	163	return true;
	164	}
	165
33f14235 LY	166	static int ipu_crtc_atomic_check(struct drm_crtc *crtc,
	167	struct drm_crtc_state *state)
	168	{
5f2f9115 LY	169	u32 primary_plane_mask = 1 << drm_plane_index(crtc->primary);
	170
	171	if (state->active && (primary_plane_mask & state->plane_mask) == 0)
	172	return -EINVAL;
	173
33f14235 LY	174	return 0;
	175	}
	176
5f2f9115 LY	177	static void ipu_crtc_atomic_begin(struct drm_crtc *crtc,
	178	struct drm_crtc_state *old_crtc_state)
	179	{
a4744786 LS	180	drm_crtc_vblank_on(crtc);
a4744786 LS	181
5f2f9115 LY	182	spin_lock_irq(&crtc->dev->event_lock);
	183	if (crtc->state->event) {
	184	WARN_ON(drm_crtc_vblank_get(crtc));
	185	drm_crtc_arm_vblank_event(crtc, crtc->state->event);
	186	crtc->state->event = NULL;
	187	}
	188	spin_unlock_irq(&crtc->dev->event_lock);
	189	}
	190
33f14235 LY	191	static void ipu_crtc_mode_set_nofb(struct drm_crtc *crtc)
	192	{
	193	struct drm_device *dev = crtc->dev;
	194	struct drm_encoder *encoder;
	195	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	196	struct drm_display_mode *mode = &crtc->state->adjusted_mode;
49f98bc4	197	struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc->state);
33f14235 LY	198	struct ipu_di_signal_cfg sig_cfg = {};
	199	unsigned long encoder_types = 0;
	200
	201	dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__,
	202	mode->hdisplay);
	203	dev_dbg(ipu_crtc->dev, "%s: mode->vdisplay: %d\n", __func__,
	204	mode->vdisplay);
	205
032003c5	206	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
49f98bc4	207	if (encoder->crtc == crtc)
33f14235	208	encoder_types \|= BIT(encoder->encoder_type);
032003c5	209	}
33f14235 LY	210
	211	dev_dbg(ipu_crtc->dev, "%s: attached to encoder types 0x%lx\n",
	212	__func__, encoder_types);
	213
	214	/*
	215	* If we have DAC or LDB, then we need the IPU DI clock to be
	216	* the same as the LDB DI clock. For TVDAC, derive the IPU DI
	217	* clock from 27 MHz TVE_DI clock, but allow to divide it.
	218	*/
	219	if (encoder_types & (BIT(DRM_MODE_ENCODER_DAC) \|
	220	BIT(DRM_MODE_ENCODER_LVDS)))
	221	sig_cfg.clkflags = IPU_DI_CLKMODE_SYNC \| IPU_DI_CLKMODE_EXT;
	222	else if (encoder_types & BIT(DRM_MODE_ENCODER_TVDAC))
	223	sig_cfg.clkflags = IPU_DI_CLKMODE_EXT;
	224	else
	225	sig_cfg.clkflags = 0;
	226
49f98bc4	227	sig_cfg.enable_pol = !(imx_crtc_state->bus_flags & DRM_BUS_FLAG_DE_LOW);
33f14235	228	/* Default to driving pixel data on negative clock edges */
49f98bc4	229	sig_cfg.clk_pol = !!(imx_crtc_state->bus_flags &
33f14235	230	DRM_BUS_FLAG_PIXDATA_POSEDGE);
49f98bc4	231	sig_cfg.bus_format = imx_crtc_state->bus_format;
33f14235	232	sig_cfg.v_to_h_sync = 0;
49f98bc4 PZ	233	sig_cfg.hsync_pin = imx_crtc_state->di_hsync_pin;
49f98bc4 PZ	234	sig_cfg.vsync_pin = imx_crtc_state->di_vsync_pin;
33f14235 LY	235
	236	drm_display_mode_to_videomode(mode, &sig_cfg.mode);
	237
	238	ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di,
	239	mode->flags & DRM_MODE_FLAG_INTERLACE,
49f98bc4	240	imx_crtc_state->bus_format, mode->hdisplay);
33f14235	241	ipu_di_init_sync_panel(ipu_crtc->di, &sig_cfg);
f326f799 SH	242	}
f326f799 SH	243
7ae847dd	244	static const struct drm_crtc_helper_funcs ipu_helper_funcs = {
f326f799	245	.mode_fixup = ipu_crtc_mode_fixup,
33f14235	246	.mode_set_nofb = ipu_crtc_mode_set_nofb,
33f14235	247	.atomic_check = ipu_crtc_atomic_check,
5f2f9115	248	.atomic_begin = ipu_crtc_atomic_begin,
f6e396e5 LY	249	.disable = ipu_crtc_disable,
f6e396e5 LY	250	.enable = ipu_crtc_enable,
f326f799 SH	251	};
	252
	253	static int ipu_enable_vblank(struct drm_crtc *crtc)
	254	{
411b0336 LS	255	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	256
	257	enable_irq(ipu_crtc->irq);
	258
f326f799 SH	259	return 0;
	260	}
	261
	262	static void ipu_disable_vblank(struct drm_crtc *crtc)
	263	{
411b0336 LS	264	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	265
	266	disable_irq_nosync(ipu_crtc->irq);
f326f799 SH	267	}
f326f799 SH	268
f326f799 SH	269	static const struct imx_drm_crtc_helper_funcs ipu_crtc_helper_funcs = {
	270	.enable_vblank = ipu_enable_vblank,
	271	.disable_vblank = ipu_disable_vblank,
f326f799 SH	272	.crtc_funcs = &ipu_crtc_funcs,
	273	.crtc_helper_funcs = &ipu_helper_funcs,
	274	};
	275
	276	static void ipu_put_resources(struct ipu_crtc *ipu_crtc)
	277	{
b8d181e4 PZ	278	if (!IS_ERR_OR_NULL(ipu_crtc->dc))
b8d181e4 PZ	279	ipu_dc_put(ipu_crtc->dc);
f326f799 SH	280	if (!IS_ERR_OR_NULL(ipu_crtc->di))
	281	ipu_di_put(ipu_crtc->di);
	282	}
	283
	284	static int ipu_get_resources(struct ipu_crtc *ipu_crtc,
	285	struct ipu_client_platformdata *pdata)
	286	{
	287	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
	288	int ret;
	289
f326f799 SH	290	ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc);
	291	if (IS_ERR(ipu_crtc->dc)) {
	292	ret = PTR_ERR(ipu_crtc->dc);
	293	goto err_out;
	294	}
	295
f326f799 SH	296	ipu_crtc->di = ipu_di_get(ipu, pdata->di);
	297	if (IS_ERR(ipu_crtc->di)) {
	298	ret = PTR_ERR(ipu_crtc->di);
	299	goto err_out;
	300	}
	301
f326f799 SH	302	return 0;
	303	err_out:
	304	ipu_put_resources(ipu_crtc);
	305
	306	return ret;
	307	}
	308
	309	static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
32266b45	310	struct ipu_client_platformdata pdata, struct drm_device drm)
f326f799	311	{
47b1be5c	312	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
b8d181e4	313	int dp = -EINVAL;
f326f799 SH	314	int ret;
	315
	316	ret = ipu_get_resources(ipu_crtc, pdata);
	317	if (ret) {
	318	dev_err(ipu_crtc->dev, "getting resources failed with %d.\n",
	319	ret);
	320	return ret;
	321	}
	322
43895599 PZ	323	if (pdata->dp >= 0)
	324	dp = IPU_DP_FLOW_SYNC_BG;
	325	ipu_crtc->plane[0] = ipu_plane_init(drm, ipu, pdata->dma[0], dp, 0,
	326	DRM_PLANE_TYPE_PRIMARY);
a7ed3c2b LY	327	if (IS_ERR(ipu_crtc->plane[0])) {
	328	ret = PTR_ERR(ipu_crtc->plane[0]);
	329	goto err_put_resources;
	330	}
43895599	331
655b43cc	332	ret = imx_drm_add_crtc(drm, &ipu_crtc->base, &ipu_crtc->imx_crtc,
43895599	333	&ipu_crtc->plane[0]->base, &ipu_crtc_helper_funcs,
310944d1	334	pdata->of_node);
f326f799 SH	335	if (ret) {
	336	dev_err(ipu_crtc->dev, "adding crtc failed with %d.\n", ret);
	337	goto err_put_resources;
	338	}
	339
b8d181e4 PZ	340	ret = ipu_plane_get_resources(ipu_crtc->plane[0]);
	341	if (ret) {
	342	dev_err(ipu_crtc->dev, "getting plane 0 resources failed with %d.\n",
	343	ret);
	344	goto err_remove_crtc;
	345	}
	346
	347	/* If this crtc is using the DP, add an overlay plane */
	348	if (pdata->dp >= 0 && pdata->dma[1] > 0) {
43895599 PZ	349	ipu_crtc->plane[1] = ipu_plane_init(drm, ipu, pdata->dma[1],
	350	IPU_DP_FLOW_SYNC_FG,
	351	drm_crtc_mask(&ipu_crtc->base),
	352	DRM_PLANE_TYPE_OVERLAY);
33f14235	353	if (IS_ERR(ipu_crtc->plane[1])) {
b8d181e4	354	ipu_crtc->plane[1] = NULL;
33f14235 LY	355	} else {
	356	ret = ipu_plane_get_resources(ipu_crtc->plane[1]);
	357	if (ret) {
	358	dev_err(ipu_crtc->dev, "getting plane 1 "
	359	"resources failed with %d.\n", ret);
	360	goto err_put_plane0_res;
	361	}
	362	}
b8d181e4 PZ	363	}
	364
	365	ipu_crtc->irq = ipu_plane_irq(ipu_crtc->plane[0]);
47b1be5c PZ	366	ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0,
	367	"imx_drm", ipu_crtc);
	368	if (ret < 0) {
	369	dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret);
33f14235	370	goto err_put_plane1_res;
47b1be5c	371	}
411b0336 LS	372	/* Only enable IRQ when we actually need it to trigger work. */
411b0336 LS	373	disable_irq(ipu_crtc->irq);
47b1be5c	374
f326f799 SH	375	return 0;
f326f799 SH	376
33f14235 LY	377	err_put_plane1_res:
	378	if (ipu_crtc->plane[1])
	379	ipu_plane_put_resources(ipu_crtc->plane[1]);
	380	err_put_plane0_res:
b8d181e4 PZ	381	ipu_plane_put_resources(ipu_crtc->plane[0]);
	382	err_remove_crtc:
	383	imx_drm_remove_crtc(ipu_crtc->imx_crtc);
f326f799 SH	384	err_put_resources:
	385	ipu_put_resources(ipu_crtc);
	386
	387	return ret;
	388	}
	389
17b5001b	390	static int ipu_drm_bind(struct device dev, struct device master, void *data)
f326f799	391	{
17b5001b	392	struct ipu_client_platformdata *pdata = dev->platform_data;
32266b45	393	struct drm_device *drm = data;
f326f799 SH	394	struct ipu_crtc *ipu_crtc;
	395	int ret;
	396
17b5001b	397	ipu_crtc = devm_kzalloc(dev, sizeof(*ipu_crtc), GFP_KERNEL);
f326f799 SH	398	if (!ipu_crtc)
	399	return -ENOMEM;
	400
17b5001b	401	ipu_crtc->dev = dev;
f326f799	402
32266b45	403	ret = ipu_crtc_init(ipu_crtc, pdata, drm);
9a8f3f44 LW	404	if (ret)
9a8f3f44 LW	405	return ret;
f326f799	406
17b5001b	407	dev_set_drvdata(dev, ipu_crtc);
f326f799 SH	408
	409	return 0;
	410	}
	411
17b5001b RK	412	static void ipu_drm_unbind(struct device dev, struct device master,
17b5001b RK	413	void *data)
f326f799	414	{
17b5001b	415	struct ipu_crtc *ipu_crtc = dev_get_drvdata(dev);
f326f799 SH	416
	417	imx_drm_remove_crtc(ipu_crtc->imx_crtc);
	418
	419	ipu_put_resources(ipu_crtc);
33f14235 LY	420	if (ipu_crtc->plane[1])
	421	ipu_plane_put_resources(ipu_crtc->plane[1]);
	422	ipu_plane_put_resources(ipu_crtc->plane[0]);
17b5001b RK	423	}
	424
	425	static const struct component_ops ipu_crtc_ops = {
	426	.bind = ipu_drm_bind,
	427	.unbind = ipu_drm_unbind,
	428	};
f326f799	429
17b5001b RK	430	static int ipu_drm_probe(struct platform_device *pdev)
17b5001b RK	431	{
655b43cc	432	struct device *dev = &pdev->dev;
17b5001b RK	433	int ret;
17b5001b RK	434
655b43cc	435	if (!dev->platform_data)
17b5001b RK	436	return -EINVAL;
17b5001b RK	437
655b43cc	438	ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
17b5001b RK	439	if (ret)
	440	return ret;
	441
655b43cc	442	return component_add(dev, &ipu_crtc_ops);
17b5001b RK	443	}
	444
	445	static int ipu_drm_remove(struct platform_device *pdev)
	446	{
	447	component_del(&pdev->dev, &ipu_crtc_ops);
f326f799 SH	448	return 0;
	449	}
	450
	451	static struct platform_driver ipu_drm_driver = {
	452	.driver = {
	453	.name = "imx-ipuv3-crtc",
	454	},
	455	.probe = ipu_drm_probe,
99c28f10	456	.remove = ipu_drm_remove,
f326f799 SH	457	};
	458	module_platform_driver(ipu_drm_driver);
	459
	460	MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
	461	MODULE_DESCRIPTION(DRIVER_DESC);
	462	MODULE_LICENSE("GPL");
ce9c1cef	463	MODULE_ALIAS("platform:imx-ipuv3-crtc");