Commit | Line | Data |
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946485d0 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
ac4c1a9b SH |
2 | /* |
3 | * i.MX drm driver - LVDS display bridge | |
4 | * | |
5 | * Copyright (C) 2012 Sascha Hauer, Pengutronix | |
ac4c1a9b SH |
6 | */ |
7 | ||
8 | #include <linux/module.h> | |
9 | #include <linux/clk.h> | |
17b5001b | 10 | #include <linux/component.h> |
ac4c1a9b | 11 | #include <drm/drmP.h> |
49f98bc4 | 12 | #include <drm/drm_atomic.h> |
255c35f8 | 13 | #include <drm/drm_atomic_helper.h> |
ac4c1a9b | 14 | #include <drm/drm_fb_helper.h> |
53141e42 | 15 | #include <drm/drm_of.h> |
751e2676 | 16 | #include <drm/drm_panel.h> |
fcd70cd3 | 17 | #include <drm/drm_probe_helper.h> |
ac4c1a9b SH |
18 | #include <linux/mfd/syscon.h> |
19 | #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> | |
ac4c1a9b | 20 | #include <linux/of_device.h> |
751e2676 | 21 | #include <linux/of_graph.h> |
c82b4d73 | 22 | #include <video/of_display_timing.h> |
ac4c1a9b SH |
23 | #include <video/of_videomode.h> |
24 | #include <linux/regmap.h> | |
25 | #include <linux/videodev2.h> | |
26 | ||
27 | #include "imx-drm.h" | |
28 | ||
29 | #define DRIVER_NAME "imx-ldb" | |
30 | ||
31 | #define LDB_CH0_MODE_EN_TO_DI0 (1 << 0) | |
32 | #define LDB_CH0_MODE_EN_TO_DI1 (3 << 0) | |
33 | #define LDB_CH0_MODE_EN_MASK (3 << 0) | |
34 | #define LDB_CH1_MODE_EN_TO_DI0 (1 << 2) | |
35 | #define LDB_CH1_MODE_EN_TO_DI1 (3 << 2) | |
36 | #define LDB_CH1_MODE_EN_MASK (3 << 2) | |
37 | #define LDB_SPLIT_MODE_EN (1 << 4) | |
38 | #define LDB_DATA_WIDTH_CH0_24 (1 << 5) | |
39 | #define LDB_BIT_MAP_CH0_JEIDA (1 << 6) | |
40 | #define LDB_DATA_WIDTH_CH1_24 (1 << 7) | |
41 | #define LDB_BIT_MAP_CH1_JEIDA (1 << 8) | |
42 | #define LDB_DI0_VS_POL_ACT_LOW (1 << 9) | |
43 | #define LDB_DI1_VS_POL_ACT_LOW (1 << 10) | |
44 | #define LDB_BGREF_RMODE_INT (1 << 15) | |
45 | ||
ac4c1a9b SH |
46 | struct imx_ldb; |
47 | ||
48 | struct imx_ldb_channel { | |
49 | struct imx_ldb *ldb; | |
50 | struct drm_connector connector; | |
49f98bc4 | 51 | struct drm_encoder encoder; |
dc80d703 PST |
52 | |
53 | /* Defines what is connected to the ldb, only one at a time */ | |
751e2676 | 54 | struct drm_panel *panel; |
dc80d703 PST |
55 | struct drm_bridge *bridge; |
56 | ||
1b3f7675 | 57 | struct device_node *child; |
a6d206e2 | 58 | struct i2c_adapter *ddc; |
ac4c1a9b SH |
59 | int chno; |
60 | void *edid; | |
61 | int edid_len; | |
62 | struct drm_display_mode mode; | |
63 | int mode_valid; | |
49f98bc4 | 64 | u32 bus_format; |
fafc79ef | 65 | u32 bus_flags; |
ac4c1a9b SH |
66 | }; |
67 | ||
3df07390 PZ |
68 | static inline struct imx_ldb_channel *con_to_imx_ldb_ch(struct drm_connector *c) |
69 | { | |
70 | return container_of(c, struct imx_ldb_channel, connector); | |
71 | } | |
72 | ||
49f98bc4 PZ |
73 | static inline struct imx_ldb_channel *enc_to_imx_ldb_ch(struct drm_encoder *e) |
74 | { | |
75 | return container_of(e, struct imx_ldb_channel, encoder); | |
76 | } | |
77 | ||
ac4c1a9b SH |
78 | struct bus_mux { |
79 | int reg; | |
80 | int shift; | |
81 | int mask; | |
82 | }; | |
83 | ||
84 | struct imx_ldb { | |
85 | struct regmap *regmap; | |
86 | struct device *dev; | |
87 | struct imx_ldb_channel channel[2]; | |
88 | struct clk *clk[2]; /* our own clock */ | |
89 | struct clk *clk_sel[4]; /* parent of display clock */ | |
3973aff0 | 90 | struct clk *clk_parent[4]; /* original parent of clk_sel */ |
ac4c1a9b SH |
91 | struct clk *clk_pll[2]; /* upstream clock we can adjust */ |
92 | u32 ldb_ctrl; | |
93 | const struct bus_mux *lvds_mux; | |
94 | }; | |
95 | ||
49f98bc4 PZ |
96 | static void imx_ldb_ch_set_bus_format(struct imx_ldb_channel *imx_ldb_ch, |
97 | u32 bus_format) | |
032003c5 LY |
98 | { |
99 | struct imx_ldb *ldb = imx_ldb_ch->ldb; | |
100 | int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN; | |
101 | ||
102 | switch (bus_format) { | |
103 | case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: | |
032003c5 LY |
104 | break; |
105 | case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: | |
032003c5 LY |
106 | if (imx_ldb_ch->chno == 0 || dual) |
107 | ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24; | |
108 | if (imx_ldb_ch->chno == 1 || dual) | |
109 | ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24; | |
110 | break; | |
111 | case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: | |
032003c5 LY |
112 | if (imx_ldb_ch->chno == 0 || dual) |
113 | ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 | | |
114 | LDB_BIT_MAP_CH0_JEIDA; | |
115 | if (imx_ldb_ch->chno == 1 || dual) | |
116 | ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 | | |
117 | LDB_BIT_MAP_CH1_JEIDA; | |
118 | break; | |
119 | } | |
120 | } | |
121 | ||
ac4c1a9b SH |
122 | static int imx_ldb_connector_get_modes(struct drm_connector *connector) |
123 | { | |
124 | struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector); | |
125 | int num_modes = 0; | |
126 | ||
751e2676 PZ |
127 | if (imx_ldb_ch->panel && imx_ldb_ch->panel->funcs && |
128 | imx_ldb_ch->panel->funcs->get_modes) { | |
129 | num_modes = imx_ldb_ch->panel->funcs->get_modes(imx_ldb_ch->panel); | |
130 | if (num_modes > 0) | |
131 | return num_modes; | |
132 | } | |
133 | ||
a6d206e2 SL |
134 | if (!imx_ldb_ch->edid && imx_ldb_ch->ddc) |
135 | imx_ldb_ch->edid = drm_get_edid(connector, imx_ldb_ch->ddc); | |
136 | ||
ac4c1a9b | 137 | if (imx_ldb_ch->edid) { |
c555f023 | 138 | drm_connector_update_edid_property(connector, |
ac4c1a9b SH |
139 | imx_ldb_ch->edid); |
140 | num_modes = drm_add_edid_modes(connector, imx_ldb_ch->edid); | |
141 | } | |
142 | ||
143 | if (imx_ldb_ch->mode_valid) { | |
144 | struct drm_display_mode *mode; | |
145 | ||
146 | mode = drm_mode_create(connector->dev); | |
9f9b036f FE |
147 | if (!mode) |
148 | return -EINVAL; | |
ac4c1a9b SH |
149 | drm_mode_copy(mode, &imx_ldb_ch->mode); |
150 | mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; | |
151 | drm_mode_probed_add(connector, mode); | |
152 | num_modes++; | |
153 | } | |
154 | ||
155 | return num_modes; | |
156 | } | |
157 | ||
ac4c1a9b SH |
158 | static struct drm_encoder *imx_ldb_connector_best_encoder( |
159 | struct drm_connector *connector) | |
160 | { | |
161 | struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector); | |
162 | ||
49f98bc4 | 163 | return &imx_ldb_ch->encoder; |
ac4c1a9b SH |
164 | } |
165 | ||
ac4c1a9b SH |
166 | static void imx_ldb_set_clock(struct imx_ldb *ldb, int mux, int chno, |
167 | unsigned long serial_clk, unsigned long di_clk) | |
168 | { | |
169 | int ret; | |
170 | ||
171 | dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__, | |
172 | clk_get_rate(ldb->clk_pll[chno]), serial_clk); | |
173 | clk_set_rate(ldb->clk_pll[chno], serial_clk); | |
174 | ||
175 | dev_dbg(ldb->dev, "%s after: %ld\n", __func__, | |
176 | clk_get_rate(ldb->clk_pll[chno])); | |
177 | ||
178 | dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__, | |
179 | clk_get_rate(ldb->clk[chno]), | |
180 | (long int)di_clk); | |
181 | clk_set_rate(ldb->clk[chno], di_clk); | |
182 | ||
183 | dev_dbg(ldb->dev, "%s after: %ld\n", __func__, | |
184 | clk_get_rate(ldb->clk[chno])); | |
185 | ||
186 | /* set display clock mux to LDB input clock */ | |
187 | ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk[chno]); | |
49f4a9c8 | 188 | if (ret) |
e5e1b166 AO |
189 | dev_err(ldb->dev, |
190 | "unable to set di%d parent clock to ldb_di%d\n", mux, | |
191 | chno); | |
ac4c1a9b SH |
192 | } |
193 | ||
f6e396e5 | 194 | static void imx_ldb_encoder_enable(struct drm_encoder *encoder) |
ac4c1a9b | 195 | { |
49f98bc4 | 196 | struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder); |
ac4c1a9b SH |
197 | struct imx_ldb *ldb = imx_ldb_ch->ldb; |
198 | int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN; | |
53141e42 | 199 | int mux = drm_of_encoder_active_port_id(imx_ldb_ch->child, encoder); |
ac4c1a9b | 200 | |
751e2676 PZ |
201 | drm_panel_prepare(imx_ldb_ch->panel); |
202 | ||
ac4c1a9b | 203 | if (dual) { |
f6e396e5 LY |
204 | clk_set_parent(ldb->clk_sel[mux], ldb->clk[0]); |
205 | clk_set_parent(ldb->clk_sel[mux], ldb->clk[1]); | |
206 | ||
ac4c1a9b SH |
207 | clk_prepare_enable(ldb->clk[0]); |
208 | clk_prepare_enable(ldb->clk[1]); | |
f6e396e5 LY |
209 | } else { |
210 | clk_set_parent(ldb->clk_sel[mux], ldb->clk[imx_ldb_ch->chno]); | |
ac4c1a9b SH |
211 | } |
212 | ||
213 | if (imx_ldb_ch == &ldb->channel[0] || dual) { | |
214 | ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK; | |
215 | if (mux == 0 || ldb->lvds_mux) | |
216 | ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI0; | |
217 | else if (mux == 1) | |
218 | ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI1; | |
219 | } | |
220 | if (imx_ldb_ch == &ldb->channel[1] || dual) { | |
221 | ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK; | |
222 | if (mux == 1 || ldb->lvds_mux) | |
223 | ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI1; | |
224 | else if (mux == 0) | |
225 | ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI0; | |
226 | } | |
227 | ||
228 | if (ldb->lvds_mux) { | |
229 | const struct bus_mux *lvds_mux = NULL; | |
230 | ||
231 | if (imx_ldb_ch == &ldb->channel[0]) | |
232 | lvds_mux = &ldb->lvds_mux[0]; | |
233 | else if (imx_ldb_ch == &ldb->channel[1]) | |
234 | lvds_mux = &ldb->lvds_mux[1]; | |
235 | ||
236 | regmap_update_bits(ldb->regmap, lvds_mux->reg, lvds_mux->mask, | |
237 | mux << lvds_mux->shift); | |
238 | } | |
239 | ||
240 | regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl); | |
751e2676 PZ |
241 | |
242 | drm_panel_enable(imx_ldb_ch->panel); | |
ac4c1a9b SH |
243 | } |
244 | ||
3a2ad502 PZ |
245 | static void |
246 | imx_ldb_encoder_atomic_mode_set(struct drm_encoder *encoder, | |
247 | struct drm_crtc_state *crtc_state, | |
248 | struct drm_connector_state *connector_state) | |
ac4c1a9b | 249 | { |
49f98bc4 | 250 | struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder); |
3a2ad502 | 251 | struct drm_display_mode *mode = &crtc_state->adjusted_mode; |
ac4c1a9b SH |
252 | struct imx_ldb *ldb = imx_ldb_ch->ldb; |
253 | int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN; | |
51dac94e PZ |
254 | unsigned long serial_clk; |
255 | unsigned long di_clk = mode->clock * 1000; | |
53141e42 | 256 | int mux = drm_of_encoder_active_port_id(imx_ldb_ch->child, encoder); |
49f98bc4 | 257 | u32 bus_format = imx_ldb_ch->bus_format; |
ac4c1a9b SH |
258 | |
259 | if (mode->clock > 170000) { | |
260 | dev_warn(ldb->dev, | |
261 | "%s: mode exceeds 170 MHz pixel clock\n", __func__); | |
262 | } | |
263 | if (mode->clock > 85000 && !dual) { | |
264 | dev_warn(ldb->dev, | |
265 | "%s: mode exceeds 85 MHz pixel clock\n", __func__); | |
266 | } | |
267 | ||
51dac94e PZ |
268 | if (dual) { |
269 | serial_clk = 3500UL * mode->clock; | |
270 | imx_ldb_set_clock(ldb, mux, 0, serial_clk, di_clk); | |
271 | imx_ldb_set_clock(ldb, mux, 1, serial_clk, di_clk); | |
272 | } else { | |
273 | serial_clk = 7000UL * mode->clock; | |
274 | imx_ldb_set_clock(ldb, mux, imx_ldb_ch->chno, serial_clk, | |
275 | di_clk); | |
276 | } | |
277 | ||
ac4c1a9b | 278 | /* FIXME - assumes straight connections DI0 --> CH0, DI1 --> CH1 */ |
49f98bc4 | 279 | if (imx_ldb_ch == &ldb->channel[0] || dual) { |
ac4c1a9b SH |
280 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
281 | ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW; | |
282 | else if (mode->flags & DRM_MODE_FLAG_PVSYNC) | |
283 | ldb->ldb_ctrl &= ~LDB_DI0_VS_POL_ACT_LOW; | |
284 | } | |
49f98bc4 | 285 | if (imx_ldb_ch == &ldb->channel[1] || dual) { |
ac4c1a9b SH |
286 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
287 | ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW; | |
288 | else if (mode->flags & DRM_MODE_FLAG_PVSYNC) | |
289 | ldb->ldb_ctrl &= ~LDB_DI1_VS_POL_ACT_LOW; | |
290 | } | |
49f98bc4 PZ |
291 | |
292 | if (!bus_format) { | |
3a2ad502 PZ |
293 | struct drm_connector *connector = connector_state->connector; |
294 | struct drm_display_info *di = &connector->display_info; | |
49f98bc4 | 295 | |
3a2ad502 PZ |
296 | if (di->num_bus_formats) |
297 | bus_format = di->bus_formats[0]; | |
49f98bc4 PZ |
298 | } |
299 | imx_ldb_ch_set_bus_format(imx_ldb_ch, bus_format); | |
ac4c1a9b SH |
300 | } |
301 | ||
302 | static void imx_ldb_encoder_disable(struct drm_encoder *encoder) | |
303 | { | |
49f98bc4 | 304 | struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder); |
ac4c1a9b | 305 | struct imx_ldb *ldb = imx_ldb_ch->ldb; |
3973aff0 | 306 | int mux, ret; |
ac4c1a9b | 307 | |
751e2676 PZ |
308 | drm_panel_disable(imx_ldb_ch->panel); |
309 | ||
ac4c1a9b SH |
310 | if (imx_ldb_ch == &ldb->channel[0]) |
311 | ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK; | |
312 | else if (imx_ldb_ch == &ldb->channel[1]) | |
313 | ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK; | |
314 | ||
315 | regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl); | |
316 | ||
317 | if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) { | |
318 | clk_disable_unprepare(ldb->clk[0]); | |
319 | clk_disable_unprepare(ldb->clk[1]); | |
320 | } | |
751e2676 | 321 | |
3973aff0 PZ |
322 | if (ldb->lvds_mux) { |
323 | const struct bus_mux *lvds_mux = NULL; | |
324 | ||
325 | if (imx_ldb_ch == &ldb->channel[0]) | |
326 | lvds_mux = &ldb->lvds_mux[0]; | |
327 | else if (imx_ldb_ch == &ldb->channel[1]) | |
328 | lvds_mux = &ldb->lvds_mux[1]; | |
329 | ||
330 | regmap_read(ldb->regmap, lvds_mux->reg, &mux); | |
331 | mux &= lvds_mux->mask; | |
332 | mux >>= lvds_mux->shift; | |
333 | } else { | |
334 | mux = (imx_ldb_ch == &ldb->channel[0]) ? 0 : 1; | |
335 | } | |
336 | ||
337 | /* set display clock mux back to original input clock */ | |
338 | ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk_parent[mux]); | |
339 | if (ret) | |
340 | dev_err(ldb->dev, | |
341 | "unable to set di%d parent clock to original parent\n", | |
342 | mux); | |
343 | ||
751e2676 | 344 | drm_panel_unprepare(imx_ldb_ch->panel); |
ac4c1a9b SH |
345 | } |
346 | ||
49f98bc4 PZ |
347 | static int imx_ldb_encoder_atomic_check(struct drm_encoder *encoder, |
348 | struct drm_crtc_state *crtc_state, | |
349 | struct drm_connector_state *conn_state) | |
350 | { | |
351 | struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state); | |
352 | struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder); | |
353 | struct drm_display_info *di = &conn_state->connector->display_info; | |
354 | u32 bus_format = imx_ldb_ch->bus_format; | |
355 | ||
356 | /* Bus format description in DT overrides connector display info. */ | |
fafc79ef | 357 | if (!bus_format && di->num_bus_formats) { |
49f98bc4 | 358 | bus_format = di->bus_formats[0]; |
fafc79ef LW |
359 | imx_crtc_state->bus_flags = di->bus_flags; |
360 | } else { | |
361 | bus_format = imx_ldb_ch->bus_format; | |
362 | imx_crtc_state->bus_flags = imx_ldb_ch->bus_flags; | |
363 | } | |
49f98bc4 PZ |
364 | switch (bus_format) { |
365 | case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: | |
366 | imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB666_1X18; | |
367 | break; | |
368 | case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: | |
369 | case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: | |
370 | imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB888_1X24; | |
371 | break; | |
372 | default: | |
373 | return -EINVAL; | |
374 | } | |
375 | ||
376 | imx_crtc_state->di_hsync_pin = 2; | |
377 | imx_crtc_state->di_vsync_pin = 3; | |
378 | ||
379 | return 0; | |
380 | } | |
381 | ||
382 | ||
7ae847dd | 383 | static const struct drm_connector_funcs imx_ldb_connector_funcs = { |
ac4c1a9b | 384 | .fill_modes = drm_helper_probe_single_connector_modes, |
1b3f7675 | 385 | .destroy = imx_drm_connector_destroy, |
255c35f8 LY |
386 | .reset = drm_atomic_helper_connector_reset, |
387 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, | |
388 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, | |
ac4c1a9b SH |
389 | }; |
390 | ||
7ae847dd | 391 | static const struct drm_connector_helper_funcs imx_ldb_connector_helper_funcs = { |
ac4c1a9b SH |
392 | .get_modes = imx_ldb_connector_get_modes, |
393 | .best_encoder = imx_ldb_connector_best_encoder, | |
ac4c1a9b SH |
394 | }; |
395 | ||
7ae847dd | 396 | static const struct drm_encoder_funcs imx_ldb_encoder_funcs = { |
1b3f7675 | 397 | .destroy = imx_drm_encoder_destroy, |
ac4c1a9b SH |
398 | }; |
399 | ||
7ae847dd | 400 | static const struct drm_encoder_helper_funcs imx_ldb_encoder_helper_funcs = { |
3a2ad502 | 401 | .atomic_mode_set = imx_ldb_encoder_atomic_mode_set, |
f6e396e5 | 402 | .enable = imx_ldb_encoder_enable, |
ac4c1a9b | 403 | .disable = imx_ldb_encoder_disable, |
49f98bc4 | 404 | .atomic_check = imx_ldb_encoder_atomic_check, |
ac4c1a9b SH |
405 | }; |
406 | ||
407 | static int imx_ldb_get_clk(struct imx_ldb *ldb, int chno) | |
408 | { | |
409 | char clkname[16]; | |
410 | ||
98dd3b2a | 411 | snprintf(clkname, sizeof(clkname), "di%d", chno); |
ac4c1a9b SH |
412 | ldb->clk[chno] = devm_clk_get(ldb->dev, clkname); |
413 | if (IS_ERR(ldb->clk[chno])) | |
414 | return PTR_ERR(ldb->clk[chno]); | |
415 | ||
98dd3b2a | 416 | snprintf(clkname, sizeof(clkname), "di%d_pll", chno); |
ac4c1a9b | 417 | ldb->clk_pll[chno] = devm_clk_get(ldb->dev, clkname); |
ac4c1a9b | 418 | |
1f933fa8 | 419 | return PTR_ERR_OR_ZERO(ldb->clk_pll[chno]); |
ac4c1a9b SH |
420 | } |
421 | ||
1b3f7675 RK |
422 | static int imx_ldb_register(struct drm_device *drm, |
423 | struct imx_ldb_channel *imx_ldb_ch) | |
ac4c1a9b | 424 | { |
ac4c1a9b | 425 | struct imx_ldb *ldb = imx_ldb_ch->ldb; |
49f98bc4 | 426 | struct drm_encoder *encoder = &imx_ldb_ch->encoder; |
1b3f7675 RK |
427 | int ret; |
428 | ||
49f98bc4 | 429 | ret = imx_drm_encoder_parse_of(drm, encoder, imx_ldb_ch->child); |
1b3f7675 RK |
430 | if (ret) |
431 | return ret; | |
ac4c1a9b SH |
432 | |
433 | ret = imx_ldb_get_clk(ldb, imx_ldb_ch->chno); | |
434 | if (ret) | |
435 | return ret; | |
1b3f7675 | 436 | |
ac4c1a9b | 437 | if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) { |
1b3f7675 | 438 | ret = imx_ldb_get_clk(ldb, 1); |
ac4c1a9b SH |
439 | if (ret) |
440 | return ret; | |
441 | } | |
442 | ||
49f98bc4 PZ |
443 | drm_encoder_helper_add(encoder, &imx_ldb_encoder_helper_funcs); |
444 | drm_encoder_init(drm, encoder, &imx_ldb_encoder_funcs, | |
445 | DRM_MODE_ENCODER_LVDS, NULL); | |
ac4c1a9b | 446 | |
dc80d703 | 447 | if (imx_ldb_ch->bridge) { |
3bb80f24 LP |
448 | ret = drm_bridge_attach(&imx_ldb_ch->encoder, |
449 | imx_ldb_ch->bridge, NULL); | |
dc80d703 PST |
450 | if (ret) { |
451 | DRM_ERROR("Failed to initialize bridge with drm\n"); | |
452 | return ret; | |
453 | } | |
454 | } else { | |
455 | /* | |
456 | * We want to add the connector whenever there is no bridge | |
457 | * that brings its own, not only when there is a panel. For | |
458 | * historical reasons, the ldb driver can also work without | |
459 | * a panel. | |
460 | */ | |
461 | drm_connector_helper_add(&imx_ldb_ch->connector, | |
462 | &imx_ldb_connector_helper_funcs); | |
463 | drm_connector_init(drm, &imx_ldb_ch->connector, | |
464 | &imx_ldb_connector_funcs, | |
465 | DRM_MODE_CONNECTOR_LVDS); | |
cde4c44d | 466 | drm_connector_attach_encoder(&imx_ldb_ch->connector, encoder); |
dc80d703 | 467 | } |
ac4c1a9b | 468 | |
7075ba79 LS |
469 | if (imx_ldb_ch->panel) { |
470 | ret = drm_panel_attach(imx_ldb_ch->panel, | |
471 | &imx_ldb_ch->connector); | |
472 | if (ret) | |
473 | return ret; | |
474 | } | |
751e2676 | 475 | |
ac4c1a9b SH |
476 | return 0; |
477 | } | |
478 | ||
479 | enum { | |
480 | LVDS_BIT_MAP_SPWG, | |
481 | LVDS_BIT_MAP_JEIDA | |
482 | }; | |
483 | ||
5e501ed7 PZ |
484 | struct imx_ldb_bit_mapping { |
485 | u32 bus_format; | |
486 | u32 datawidth; | |
487 | const char * const mapping; | |
ac4c1a9b SH |
488 | }; |
489 | ||
5e501ed7 PZ |
490 | static const struct imx_ldb_bit_mapping imx_ldb_bit_mappings[] = { |
491 | { MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 18, "spwg" }, | |
492 | { MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 24, "spwg" }, | |
493 | { MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 24, "jeida" }, | |
494 | }; | |
495 | ||
496 | static u32 of_get_bus_format(struct device *dev, struct device_node *np) | |
ac4c1a9b SH |
497 | { |
498 | const char *bm; | |
5e501ed7 | 499 | u32 datawidth = 0; |
ac4c1a9b SH |
500 | int ret, i; |
501 | ||
502 | ret = of_property_read_string(np, "fsl,data-mapping", &bm); | |
503 | if (ret < 0) | |
504 | return ret; | |
505 | ||
5e501ed7 PZ |
506 | of_property_read_u32(np, "fsl,data-width", &datawidth); |
507 | ||
508 | for (i = 0; i < ARRAY_SIZE(imx_ldb_bit_mappings); i++) { | |
509 | if (!strcasecmp(bm, imx_ldb_bit_mappings[i].mapping) && | |
510 | datawidth == imx_ldb_bit_mappings[i].datawidth) | |
511 | return imx_ldb_bit_mappings[i].bus_format; | |
512 | } | |
513 | ||
514 | dev_err(dev, "invalid data mapping: %d-bit \"%s\"\n", datawidth, bm); | |
ac4c1a9b | 515 | |
5e501ed7 | 516 | return -ENOENT; |
ac4c1a9b SH |
517 | } |
518 | ||
519 | static struct bus_mux imx6q_lvds_mux[2] = { | |
520 | { | |
521 | .reg = IOMUXC_GPR3, | |
522 | .shift = 6, | |
523 | .mask = IMX6Q_GPR3_LVDS0_MUX_CTL_MASK, | |
524 | }, { | |
525 | .reg = IOMUXC_GPR3, | |
526 | .shift = 8, | |
527 | .mask = IMX6Q_GPR3_LVDS1_MUX_CTL_MASK, | |
528 | } | |
529 | }; | |
530 | ||
531 | /* | |
532 | * For a device declaring compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb", | |
533 | * of_match_device will walk through this list and take the first entry | |
534 | * matching any of its compatible values. Therefore, the more generic | |
535 | * entries (in this case fsl,imx53-ldb) need to be ordered last. | |
536 | */ | |
537 | static const struct of_device_id imx_ldb_dt_ids[] = { | |
538 | { .compatible = "fsl,imx6q-ldb", .data = imx6q_lvds_mux, }, | |
539 | { .compatible = "fsl,imx53-ldb", .data = NULL, }, | |
540 | { } | |
541 | }; | |
542 | MODULE_DEVICE_TABLE(of, imx_ldb_dt_ids); | |
543 | ||
dc80d703 PST |
544 | static int imx_ldb_panel_ddc(struct device *dev, |
545 | struct imx_ldb_channel *channel, struct device_node *child) | |
546 | { | |
547 | struct device_node *ddc_node; | |
548 | const u8 *edidp; | |
549 | int ret; | |
550 | ||
551 | ddc_node = of_parse_phandle(child, "ddc-i2c-bus", 0); | |
552 | if (ddc_node) { | |
553 | channel->ddc = of_find_i2c_adapter_by_node(ddc_node); | |
554 | of_node_put(ddc_node); | |
555 | if (!channel->ddc) { | |
556 | dev_warn(dev, "failed to get ddc i2c adapter\n"); | |
557 | return -EPROBE_DEFER; | |
558 | } | |
559 | } | |
560 | ||
561 | if (!channel->ddc) { | |
562 | /* if no DDC available, fallback to hardcoded EDID */ | |
563 | dev_dbg(dev, "no ddc available\n"); | |
564 | ||
565 | edidp = of_get_property(child, "edid", | |
566 | &channel->edid_len); | |
567 | if (edidp) { | |
568 | channel->edid = kmemdup(edidp, | |
569 | channel->edid_len, | |
570 | GFP_KERNEL); | |
571 | } else if (!channel->panel) { | |
572 | /* fallback to display-timings node */ | |
573 | ret = of_get_drm_display_mode(child, | |
574 | &channel->mode, | |
575 | &channel->bus_flags, | |
576 | OF_USE_NATIVE_MODE); | |
577 | if (!ret) | |
578 | channel->mode_valid = 1; | |
579 | } | |
580 | } | |
581 | return 0; | |
582 | } | |
583 | ||
17b5001b | 584 | static int imx_ldb_bind(struct device *dev, struct device *master, void *data) |
ac4c1a9b | 585 | { |
1b3f7675 | 586 | struct drm_device *drm = data; |
17b5001b | 587 | struct device_node *np = dev->of_node; |
ac4c1a9b | 588 | const struct of_device_id *of_id = |
17b5001b | 589 | of_match_device(imx_ldb_dt_ids, dev); |
ac4c1a9b | 590 | struct device_node *child; |
ac4c1a9b | 591 | struct imx_ldb *imx_ldb; |
ac4c1a9b SH |
592 | int dual; |
593 | int ret; | |
594 | int i; | |
595 | ||
17b5001b | 596 | imx_ldb = devm_kzalloc(dev, sizeof(*imx_ldb), GFP_KERNEL); |
ac4c1a9b SH |
597 | if (!imx_ldb) |
598 | return -ENOMEM; | |
599 | ||
600 | imx_ldb->regmap = syscon_regmap_lookup_by_phandle(np, "gpr"); | |
601 | if (IS_ERR(imx_ldb->regmap)) { | |
17b5001b | 602 | dev_err(dev, "failed to get parent regmap\n"); |
ac4c1a9b SH |
603 | return PTR_ERR(imx_ldb->regmap); |
604 | } | |
605 | ||
b5826239 LS |
606 | /* disable LDB by resetting the control register to POR default */ |
607 | regmap_write(imx_ldb->regmap, IOMUXC_GPR2, 0); | |
608 | ||
17b5001b | 609 | imx_ldb->dev = dev; |
ac4c1a9b SH |
610 | |
611 | if (of_id) | |
612 | imx_ldb->lvds_mux = of_id->data; | |
613 | ||
614 | dual = of_property_read_bool(np, "fsl,dual-channel"); | |
615 | if (dual) | |
616 | imx_ldb->ldb_ctrl |= LDB_SPLIT_MODE_EN; | |
617 | ||
618 | /* | |
4599934d | 619 | * There are three different possible clock mux configurations: |
ac4c1a9b SH |
620 | * i.MX53: ipu1_di0_sel, ipu1_di1_sel |
621 | * i.MX6q: ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel, ipu2_di1_sel | |
622 | * i.MX6dl: ipu1_di0_sel, ipu1_di1_sel, lcdif_sel | |
623 | * Map them all to di0_sel...di3_sel. | |
624 | */ | |
625 | for (i = 0; i < 4; i++) { | |
626 | char clkname[16]; | |
627 | ||
628 | sprintf(clkname, "di%d_sel", i); | |
629 | imx_ldb->clk_sel[i] = devm_clk_get(imx_ldb->dev, clkname); | |
630 | if (IS_ERR(imx_ldb->clk_sel[i])) { | |
631 | ret = PTR_ERR(imx_ldb->clk_sel[i]); | |
632 | imx_ldb->clk_sel[i] = NULL; | |
633 | break; | |
634 | } | |
3973aff0 PZ |
635 | |
636 | imx_ldb->clk_parent[i] = clk_get_parent(imx_ldb->clk_sel[i]); | |
ac4c1a9b SH |
637 | } |
638 | if (i == 0) | |
639 | return ret; | |
640 | ||
641 | for_each_child_of_node(np, child) { | |
642 | struct imx_ldb_channel *channel; | |
032003c5 | 643 | int bus_format; |
ac4c1a9b SH |
644 | |
645 | ret = of_property_read_u32(child, "reg", &i); | |
646 | if (ret || i < 0 || i > 1) | |
647 | return -EINVAL; | |
648 | ||
c80d673b LS |
649 | if (!of_device_is_available(child)) |
650 | continue; | |
651 | ||
ac4c1a9b | 652 | if (dual && i > 0) { |
17b5001b | 653 | dev_warn(dev, "dual-channel mode, ignoring second output\n"); |
ac4c1a9b SH |
654 | continue; |
655 | } | |
656 | ||
ac4c1a9b SH |
657 | channel = &imx_ldb->channel[i]; |
658 | channel->ldb = imx_ldb; | |
659 | channel->chno = i; | |
1b3f7675 | 660 | channel->child = child; |
ac4c1a9b | 661 | |
751e2676 PZ |
662 | /* |
663 | * The output port is port@4 with an external 4-port mux or | |
664 | * port@2 with the internal 2-port mux. | |
665 | */ | |
ebc94461 RH |
666 | ret = drm_of_find_panel_or_bridge(child, |
667 | imx_ldb->lvds_mux ? 4 : 2, 0, | |
668 | &channel->panel, &channel->bridge); | |
e36aecba | 669 | if (ret && ret != -ENODEV) |
ebc94461 | 670 | return ret; |
a6d206e2 | 671 | |
dc80d703 PST |
672 | /* panel ddc only if there is no bridge */ |
673 | if (!channel->bridge) { | |
674 | ret = imx_ldb_panel_ddc(dev, channel, child); | |
675 | if (ret) | |
676 | return ret; | |
ac4c1a9b SH |
677 | } |
678 | ||
032003c5 LY |
679 | bus_format = of_get_bus_format(dev, child); |
680 | if (bus_format == -EINVAL) { | |
5e501ed7 PZ |
681 | /* |
682 | * If no bus format was specified in the device tree, | |
683 | * we can still get it from the connected panel later. | |
684 | */ | |
685 | if (channel->panel && channel->panel->funcs && | |
686 | channel->panel->funcs->get_modes) | |
032003c5 | 687 | bus_format = 0; |
5e501ed7 | 688 | } |
032003c5 | 689 | if (bus_format < 0) { |
5e501ed7 | 690 | dev_err(dev, "could not determine data mapping: %d\n", |
032003c5 LY |
691 | bus_format); |
692 | return bus_format; | |
ac4c1a9b | 693 | } |
49f98bc4 | 694 | channel->bus_format = bus_format; |
ac4c1a9b | 695 | |
1b3f7675 | 696 | ret = imx_ldb_register(drm, channel); |
ac4c1a9b SH |
697 | if (ret) |
698 | return ret; | |
ac4c1a9b SH |
699 | } |
700 | ||
17b5001b | 701 | dev_set_drvdata(dev, imx_ldb); |
ac4c1a9b SH |
702 | |
703 | return 0; | |
704 | } | |
705 | ||
17b5001b RK |
706 | static void imx_ldb_unbind(struct device *dev, struct device *master, |
707 | void *data) | |
ac4c1a9b | 708 | { |
17b5001b | 709 | struct imx_ldb *imx_ldb = dev_get_drvdata(dev); |
ac4c1a9b SH |
710 | int i; |
711 | ||
712 | for (i = 0; i < 2; i++) { | |
713 | struct imx_ldb_channel *channel = &imx_ldb->channel[i]; | |
ac4c1a9b | 714 | |
b1318d50 LS |
715 | if (channel->panel) |
716 | drm_panel_detach(channel->panel); | |
717 | ||
f4876ffe | 718 | kfree(channel->edid); |
a6d206e2 | 719 | i2c_put_adapter(channel->ddc); |
ac4c1a9b | 720 | } |
17b5001b | 721 | } |
ac4c1a9b | 722 | |
17b5001b RK |
723 | static const struct component_ops imx_ldb_ops = { |
724 | .bind = imx_ldb_bind, | |
725 | .unbind = imx_ldb_unbind, | |
726 | }; | |
727 | ||
728 | static int imx_ldb_probe(struct platform_device *pdev) | |
729 | { | |
730 | return component_add(&pdev->dev, &imx_ldb_ops); | |
731 | } | |
732 | ||
733 | static int imx_ldb_remove(struct platform_device *pdev) | |
734 | { | |
735 | component_del(&pdev->dev, &imx_ldb_ops); | |
ac4c1a9b SH |
736 | return 0; |
737 | } | |
738 | ||
739 | static struct platform_driver imx_ldb_driver = { | |
740 | .probe = imx_ldb_probe, | |
741 | .remove = imx_ldb_remove, | |
742 | .driver = { | |
743 | .of_match_table = imx_ldb_dt_ids, | |
744 | .name = DRIVER_NAME, | |
ac4c1a9b SH |
745 | }, |
746 | }; | |
747 | ||
748 | module_platform_driver(imx_ldb_driver); | |
749 | ||
750 | MODULE_DESCRIPTION("i.MX LVDS driver"); | |
751 | MODULE_AUTHOR("Sascha Hauer, Pengutronix"); | |
752 | MODULE_LICENSE("GPL"); | |
bc627387 | 753 | MODULE_ALIAS("platform:" DRIVER_NAME); |