Commit | Line | Data |
---|---|---|
ac4c1a9b SH |
1 | /* |
2 | * i.MX drm driver - LVDS display bridge | |
3 | * | |
4 | * Copyright (C) 2012 Sascha Hauer, Pengutronix | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
ac4c1a9b SH |
14 | */ |
15 | ||
16 | #include <linux/module.h> | |
17 | #include <linux/clk.h> | |
17b5001b | 18 | #include <linux/component.h> |
ac4c1a9b SH |
19 | #include <drm/drmP.h> |
20 | #include <drm/drm_fb_helper.h> | |
21 | #include <drm/drm_crtc_helper.h> | |
22 | #include <linux/mfd/syscon.h> | |
23 | #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> | |
24 | #include <linux/of_address.h> | |
25 | #include <linux/of_device.h> | |
26 | #include <video/of_videomode.h> | |
27 | #include <linux/regmap.h> | |
28 | #include <linux/videodev2.h> | |
29 | ||
30 | #include "imx-drm.h" | |
31 | ||
32 | #define DRIVER_NAME "imx-ldb" | |
33 | ||
34 | #define LDB_CH0_MODE_EN_TO_DI0 (1 << 0) | |
35 | #define LDB_CH0_MODE_EN_TO_DI1 (3 << 0) | |
36 | #define LDB_CH0_MODE_EN_MASK (3 << 0) | |
37 | #define LDB_CH1_MODE_EN_TO_DI0 (1 << 2) | |
38 | #define LDB_CH1_MODE_EN_TO_DI1 (3 << 2) | |
39 | #define LDB_CH1_MODE_EN_MASK (3 << 2) | |
40 | #define LDB_SPLIT_MODE_EN (1 << 4) | |
41 | #define LDB_DATA_WIDTH_CH0_24 (1 << 5) | |
42 | #define LDB_BIT_MAP_CH0_JEIDA (1 << 6) | |
43 | #define LDB_DATA_WIDTH_CH1_24 (1 << 7) | |
44 | #define LDB_BIT_MAP_CH1_JEIDA (1 << 8) | |
45 | #define LDB_DI0_VS_POL_ACT_LOW (1 << 9) | |
46 | #define LDB_DI1_VS_POL_ACT_LOW (1 << 10) | |
47 | #define LDB_BGREF_RMODE_INT (1 << 15) | |
48 | ||
49 | #define con_to_imx_ldb_ch(x) container_of(x, struct imx_ldb_channel, connector) | |
50 | #define enc_to_imx_ldb_ch(x) container_of(x, struct imx_ldb_channel, encoder) | |
51 | ||
52 | struct imx_ldb; | |
53 | ||
54 | struct imx_ldb_channel { | |
55 | struct imx_ldb *ldb; | |
56 | struct drm_connector connector; | |
ac4c1a9b | 57 | struct drm_encoder encoder; |
1b3f7675 | 58 | struct device_node *child; |
ac4c1a9b SH |
59 | int chno; |
60 | void *edid; | |
61 | int edid_len; | |
62 | struct drm_display_mode mode; | |
63 | int mode_valid; | |
64 | }; | |
65 | ||
66 | struct bus_mux { | |
67 | int reg; | |
68 | int shift; | |
69 | int mask; | |
70 | }; | |
71 | ||
72 | struct imx_ldb { | |
73 | struct regmap *regmap; | |
74 | struct device *dev; | |
75 | struct imx_ldb_channel channel[2]; | |
76 | struct clk *clk[2]; /* our own clock */ | |
77 | struct clk *clk_sel[4]; /* parent of display clock */ | |
78 | struct clk *clk_pll[2]; /* upstream clock we can adjust */ | |
79 | u32 ldb_ctrl; | |
80 | const struct bus_mux *lvds_mux; | |
81 | }; | |
82 | ||
83 | static enum drm_connector_status imx_ldb_connector_detect( | |
84 | struct drm_connector *connector, bool force) | |
85 | { | |
86 | return connector_status_connected; | |
87 | } | |
88 | ||
ac4c1a9b SH |
89 | static int imx_ldb_connector_get_modes(struct drm_connector *connector) |
90 | { | |
91 | struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector); | |
92 | int num_modes = 0; | |
93 | ||
94 | if (imx_ldb_ch->edid) { | |
95 | drm_mode_connector_update_edid_property(connector, | |
96 | imx_ldb_ch->edid); | |
97 | num_modes = drm_add_edid_modes(connector, imx_ldb_ch->edid); | |
98 | } | |
99 | ||
100 | if (imx_ldb_ch->mode_valid) { | |
101 | struct drm_display_mode *mode; | |
102 | ||
103 | mode = drm_mode_create(connector->dev); | |
9f9b036f FE |
104 | if (!mode) |
105 | return -EINVAL; | |
ac4c1a9b SH |
106 | drm_mode_copy(mode, &imx_ldb_ch->mode); |
107 | mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; | |
108 | drm_mode_probed_add(connector, mode); | |
109 | num_modes++; | |
110 | } | |
111 | ||
112 | return num_modes; | |
113 | } | |
114 | ||
ac4c1a9b SH |
115 | static struct drm_encoder *imx_ldb_connector_best_encoder( |
116 | struct drm_connector *connector) | |
117 | { | |
118 | struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector); | |
119 | ||
120 | return &imx_ldb_ch->encoder; | |
121 | } | |
122 | ||
123 | static void imx_ldb_encoder_dpms(struct drm_encoder *encoder, int mode) | |
124 | { | |
125 | } | |
126 | ||
127 | static bool imx_ldb_encoder_mode_fixup(struct drm_encoder *encoder, | |
128 | const struct drm_display_mode *mode, | |
129 | struct drm_display_mode *adjusted_mode) | |
130 | { | |
131 | return true; | |
132 | } | |
133 | ||
134 | static void imx_ldb_set_clock(struct imx_ldb *ldb, int mux, int chno, | |
135 | unsigned long serial_clk, unsigned long di_clk) | |
136 | { | |
137 | int ret; | |
138 | ||
139 | dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__, | |
140 | clk_get_rate(ldb->clk_pll[chno]), serial_clk); | |
141 | clk_set_rate(ldb->clk_pll[chno], serial_clk); | |
142 | ||
143 | dev_dbg(ldb->dev, "%s after: %ld\n", __func__, | |
144 | clk_get_rate(ldb->clk_pll[chno])); | |
145 | ||
146 | dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__, | |
147 | clk_get_rate(ldb->clk[chno]), | |
148 | (long int)di_clk); | |
149 | clk_set_rate(ldb->clk[chno], di_clk); | |
150 | ||
151 | dev_dbg(ldb->dev, "%s after: %ld\n", __func__, | |
152 | clk_get_rate(ldb->clk[chno])); | |
153 | ||
154 | /* set display clock mux to LDB input clock */ | |
155 | ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk[chno]); | |
49f4a9c8 | 156 | if (ret) |
e5e1b166 AO |
157 | dev_err(ldb->dev, |
158 | "unable to set di%d parent clock to ldb_di%d\n", mux, | |
159 | chno); | |
ac4c1a9b SH |
160 | } |
161 | ||
162 | static void imx_ldb_encoder_prepare(struct drm_encoder *encoder) | |
163 | { | |
164 | struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder); | |
165 | struct imx_ldb *ldb = imx_ldb_ch->ldb; | |
000d73fc | 166 | u32 pixel_fmt; |
ac4c1a9b | 167 | |
000d73fc MN |
168 | switch (imx_ldb_ch->chno) { |
169 | case 0: | |
170 | pixel_fmt = (ldb->ldb_ctrl & LDB_DATA_WIDTH_CH0_24) ? | |
171 | V4L2_PIX_FMT_RGB24 : V4L2_PIX_FMT_BGR666; | |
172 | break; | |
173 | case 1: | |
174 | pixel_fmt = (ldb->ldb_ctrl & LDB_DATA_WIDTH_CH1_24) ? | |
175 | V4L2_PIX_FMT_RGB24 : V4L2_PIX_FMT_BGR666; | |
176 | break; | |
177 | default: | |
178 | dev_err(ldb->dev, "unable to config di%d panel format\n", | |
179 | imx_ldb_ch->chno); | |
180 | pixel_fmt = V4L2_PIX_FMT_RGB24; | |
181 | } | |
182 | ||
f2d66aad | 183 | imx_drm_panel_format(encoder, pixel_fmt); |
ac4c1a9b SH |
184 | } |
185 | ||
186 | static void imx_ldb_encoder_commit(struct drm_encoder *encoder) | |
187 | { | |
188 | struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder); | |
189 | struct imx_ldb *ldb = imx_ldb_ch->ldb; | |
190 | int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN; | |
655b43cc | 191 | int mux = imx_drm_encoder_get_mux_id(imx_ldb_ch->child, encoder); |
ac4c1a9b SH |
192 | |
193 | if (dual) { | |
194 | clk_prepare_enable(ldb->clk[0]); | |
195 | clk_prepare_enable(ldb->clk[1]); | |
196 | } | |
197 | ||
198 | if (imx_ldb_ch == &ldb->channel[0] || dual) { | |
199 | ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK; | |
200 | if (mux == 0 || ldb->lvds_mux) | |
201 | ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI0; | |
202 | else if (mux == 1) | |
203 | ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI1; | |
204 | } | |
205 | if (imx_ldb_ch == &ldb->channel[1] || dual) { | |
206 | ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK; | |
207 | if (mux == 1 || ldb->lvds_mux) | |
208 | ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI1; | |
209 | else if (mux == 0) | |
210 | ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI0; | |
211 | } | |
212 | ||
213 | if (ldb->lvds_mux) { | |
214 | const struct bus_mux *lvds_mux = NULL; | |
215 | ||
216 | if (imx_ldb_ch == &ldb->channel[0]) | |
217 | lvds_mux = &ldb->lvds_mux[0]; | |
218 | else if (imx_ldb_ch == &ldb->channel[1]) | |
219 | lvds_mux = &ldb->lvds_mux[1]; | |
220 | ||
221 | regmap_update_bits(ldb->regmap, lvds_mux->reg, lvds_mux->mask, | |
222 | mux << lvds_mux->shift); | |
223 | } | |
224 | ||
225 | regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl); | |
226 | } | |
227 | ||
228 | static void imx_ldb_encoder_mode_set(struct drm_encoder *encoder, | |
eb10d635 SL |
229 | struct drm_display_mode *orig_mode, |
230 | struct drm_display_mode *mode) | |
ac4c1a9b SH |
231 | { |
232 | struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder); | |
233 | struct imx_ldb *ldb = imx_ldb_ch->ldb; | |
234 | int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN; | |
51dac94e PZ |
235 | unsigned long serial_clk; |
236 | unsigned long di_clk = mode->clock * 1000; | |
237 | int mux = imx_drm_encoder_get_mux_id(imx_ldb_ch->child, encoder); | |
ac4c1a9b SH |
238 | |
239 | if (mode->clock > 170000) { | |
240 | dev_warn(ldb->dev, | |
241 | "%s: mode exceeds 170 MHz pixel clock\n", __func__); | |
242 | } | |
243 | if (mode->clock > 85000 && !dual) { | |
244 | dev_warn(ldb->dev, | |
245 | "%s: mode exceeds 85 MHz pixel clock\n", __func__); | |
246 | } | |
247 | ||
51dac94e PZ |
248 | if (dual) { |
249 | serial_clk = 3500UL * mode->clock; | |
250 | imx_ldb_set_clock(ldb, mux, 0, serial_clk, di_clk); | |
251 | imx_ldb_set_clock(ldb, mux, 1, serial_clk, di_clk); | |
252 | } else { | |
253 | serial_clk = 7000UL * mode->clock; | |
254 | imx_ldb_set_clock(ldb, mux, imx_ldb_ch->chno, serial_clk, | |
255 | di_clk); | |
256 | } | |
257 | ||
ac4c1a9b SH |
258 | /* FIXME - assumes straight connections DI0 --> CH0, DI1 --> CH1 */ |
259 | if (imx_ldb_ch == &ldb->channel[0]) { | |
260 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
261 | ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW; | |
262 | else if (mode->flags & DRM_MODE_FLAG_PVSYNC) | |
263 | ldb->ldb_ctrl &= ~LDB_DI0_VS_POL_ACT_LOW; | |
264 | } | |
265 | if (imx_ldb_ch == &ldb->channel[1]) { | |
266 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
267 | ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW; | |
268 | else if (mode->flags & DRM_MODE_FLAG_PVSYNC) | |
269 | ldb->ldb_ctrl &= ~LDB_DI1_VS_POL_ACT_LOW; | |
270 | } | |
271 | } | |
272 | ||
273 | static void imx_ldb_encoder_disable(struct drm_encoder *encoder) | |
274 | { | |
275 | struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder); | |
276 | struct imx_ldb *ldb = imx_ldb_ch->ldb; | |
277 | ||
278 | /* | |
279 | * imx_ldb_encoder_disable is called by | |
280 | * drm_helper_disable_unused_functions without | |
281 | * the encoder being enabled before. | |
282 | */ | |
283 | if (imx_ldb_ch == &ldb->channel[0] && | |
284 | (ldb->ldb_ctrl & LDB_CH0_MODE_EN_MASK) == 0) | |
285 | return; | |
286 | else if (imx_ldb_ch == &ldb->channel[1] && | |
287 | (ldb->ldb_ctrl & LDB_CH1_MODE_EN_MASK) == 0) | |
288 | return; | |
289 | ||
290 | if (imx_ldb_ch == &ldb->channel[0]) | |
291 | ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK; | |
292 | else if (imx_ldb_ch == &ldb->channel[1]) | |
293 | ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK; | |
294 | ||
295 | regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl); | |
296 | ||
297 | if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) { | |
298 | clk_disable_unprepare(ldb->clk[0]); | |
299 | clk_disable_unprepare(ldb->clk[1]); | |
300 | } | |
301 | } | |
302 | ||
ac4c1a9b SH |
303 | static struct drm_connector_funcs imx_ldb_connector_funcs = { |
304 | .dpms = drm_helper_connector_dpms, | |
305 | .fill_modes = drm_helper_probe_single_connector_modes, | |
306 | .detect = imx_ldb_connector_detect, | |
1b3f7675 | 307 | .destroy = imx_drm_connector_destroy, |
ac4c1a9b SH |
308 | }; |
309 | ||
310 | static struct drm_connector_helper_funcs imx_ldb_connector_helper_funcs = { | |
311 | .get_modes = imx_ldb_connector_get_modes, | |
312 | .best_encoder = imx_ldb_connector_best_encoder, | |
ac4c1a9b SH |
313 | }; |
314 | ||
315 | static struct drm_encoder_funcs imx_ldb_encoder_funcs = { | |
1b3f7675 | 316 | .destroy = imx_drm_encoder_destroy, |
ac4c1a9b SH |
317 | }; |
318 | ||
319 | static struct drm_encoder_helper_funcs imx_ldb_encoder_helper_funcs = { | |
320 | .dpms = imx_ldb_encoder_dpms, | |
321 | .mode_fixup = imx_ldb_encoder_mode_fixup, | |
322 | .prepare = imx_ldb_encoder_prepare, | |
323 | .commit = imx_ldb_encoder_commit, | |
324 | .mode_set = imx_ldb_encoder_mode_set, | |
325 | .disable = imx_ldb_encoder_disable, | |
326 | }; | |
327 | ||
328 | static int imx_ldb_get_clk(struct imx_ldb *ldb, int chno) | |
329 | { | |
330 | char clkname[16]; | |
331 | ||
98dd3b2a | 332 | snprintf(clkname, sizeof(clkname), "di%d", chno); |
ac4c1a9b SH |
333 | ldb->clk[chno] = devm_clk_get(ldb->dev, clkname); |
334 | if (IS_ERR(ldb->clk[chno])) | |
335 | return PTR_ERR(ldb->clk[chno]); | |
336 | ||
98dd3b2a | 337 | snprintf(clkname, sizeof(clkname), "di%d_pll", chno); |
ac4c1a9b | 338 | ldb->clk_pll[chno] = devm_clk_get(ldb->dev, clkname); |
ac4c1a9b | 339 | |
1f933fa8 | 340 | return PTR_ERR_OR_ZERO(ldb->clk_pll[chno]); |
ac4c1a9b SH |
341 | } |
342 | ||
1b3f7675 RK |
343 | static int imx_ldb_register(struct drm_device *drm, |
344 | struct imx_ldb_channel *imx_ldb_ch) | |
ac4c1a9b | 345 | { |
ac4c1a9b | 346 | struct imx_ldb *ldb = imx_ldb_ch->ldb; |
1b3f7675 RK |
347 | int ret; |
348 | ||
349 | ret = imx_drm_encoder_parse_of(drm, &imx_ldb_ch->encoder, | |
350 | imx_ldb_ch->child); | |
351 | if (ret) | |
352 | return ret; | |
ac4c1a9b SH |
353 | |
354 | ret = imx_ldb_get_clk(ldb, imx_ldb_ch->chno); | |
355 | if (ret) | |
356 | return ret; | |
1b3f7675 | 357 | |
ac4c1a9b | 358 | if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) { |
1b3f7675 | 359 | ret = imx_ldb_get_clk(ldb, 1); |
ac4c1a9b SH |
360 | if (ret) |
361 | return ret; | |
362 | } | |
363 | ||
ac4c1a9b SH |
364 | drm_encoder_helper_add(&imx_ldb_ch->encoder, |
365 | &imx_ldb_encoder_helper_funcs); | |
1b3f7675 RK |
366 | drm_encoder_init(drm, &imx_ldb_ch->encoder, &imx_ldb_encoder_funcs, |
367 | DRM_MODE_ENCODER_LVDS); | |
ac4c1a9b SH |
368 | |
369 | drm_connector_helper_add(&imx_ldb_ch->connector, | |
370 | &imx_ldb_connector_helper_funcs); | |
1b3f7675 RK |
371 | drm_connector_init(drm, &imx_ldb_ch->connector, |
372 | &imx_ldb_connector_funcs, DRM_MODE_CONNECTOR_LVDS); | |
ac4c1a9b SH |
373 | |
374 | drm_mode_connector_attach_encoder(&imx_ldb_ch->connector, | |
375 | &imx_ldb_ch->encoder); | |
376 | ||
377 | return 0; | |
378 | } | |
379 | ||
380 | enum { | |
381 | LVDS_BIT_MAP_SPWG, | |
382 | LVDS_BIT_MAP_JEIDA | |
383 | }; | |
384 | ||
5354cb64 | 385 | static const char * const imx_ldb_bit_mappings[] = { |
ac4c1a9b SH |
386 | [LVDS_BIT_MAP_SPWG] = "spwg", |
387 | [LVDS_BIT_MAP_JEIDA] = "jeida", | |
388 | }; | |
389 | ||
d78b1406 | 390 | static const int of_get_data_mapping(struct device_node *np) |
ac4c1a9b SH |
391 | { |
392 | const char *bm; | |
393 | int ret, i; | |
394 | ||
395 | ret = of_property_read_string(np, "fsl,data-mapping", &bm); | |
396 | if (ret < 0) | |
397 | return ret; | |
398 | ||
399 | for (i = 0; i < ARRAY_SIZE(imx_ldb_bit_mappings); i++) | |
400 | if (!strcasecmp(bm, imx_ldb_bit_mappings[i])) | |
401 | return i; | |
402 | ||
403 | return -EINVAL; | |
404 | } | |
405 | ||
406 | static struct bus_mux imx6q_lvds_mux[2] = { | |
407 | { | |
408 | .reg = IOMUXC_GPR3, | |
409 | .shift = 6, | |
410 | .mask = IMX6Q_GPR3_LVDS0_MUX_CTL_MASK, | |
411 | }, { | |
412 | .reg = IOMUXC_GPR3, | |
413 | .shift = 8, | |
414 | .mask = IMX6Q_GPR3_LVDS1_MUX_CTL_MASK, | |
415 | } | |
416 | }; | |
417 | ||
418 | /* | |
419 | * For a device declaring compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb", | |
420 | * of_match_device will walk through this list and take the first entry | |
421 | * matching any of its compatible values. Therefore, the more generic | |
422 | * entries (in this case fsl,imx53-ldb) need to be ordered last. | |
423 | */ | |
424 | static const struct of_device_id imx_ldb_dt_ids[] = { | |
425 | { .compatible = "fsl,imx6q-ldb", .data = imx6q_lvds_mux, }, | |
426 | { .compatible = "fsl,imx53-ldb", .data = NULL, }, | |
427 | { } | |
428 | }; | |
429 | MODULE_DEVICE_TABLE(of, imx_ldb_dt_ids); | |
430 | ||
17b5001b | 431 | static int imx_ldb_bind(struct device *dev, struct device *master, void *data) |
ac4c1a9b | 432 | { |
1b3f7675 | 433 | struct drm_device *drm = data; |
17b5001b | 434 | struct device_node *np = dev->of_node; |
ac4c1a9b | 435 | const struct of_device_id *of_id = |
17b5001b | 436 | of_match_device(imx_ldb_dt_ids, dev); |
ac4c1a9b SH |
437 | struct device_node *child; |
438 | const u8 *edidp; | |
439 | struct imx_ldb *imx_ldb; | |
440 | int datawidth; | |
441 | int mapping; | |
442 | int dual; | |
443 | int ret; | |
444 | int i; | |
445 | ||
17b5001b | 446 | imx_ldb = devm_kzalloc(dev, sizeof(*imx_ldb), GFP_KERNEL); |
ac4c1a9b SH |
447 | if (!imx_ldb) |
448 | return -ENOMEM; | |
449 | ||
450 | imx_ldb->regmap = syscon_regmap_lookup_by_phandle(np, "gpr"); | |
451 | if (IS_ERR(imx_ldb->regmap)) { | |
17b5001b | 452 | dev_err(dev, "failed to get parent regmap\n"); |
ac4c1a9b SH |
453 | return PTR_ERR(imx_ldb->regmap); |
454 | } | |
455 | ||
17b5001b | 456 | imx_ldb->dev = dev; |
ac4c1a9b SH |
457 | |
458 | if (of_id) | |
459 | imx_ldb->lvds_mux = of_id->data; | |
460 | ||
461 | dual = of_property_read_bool(np, "fsl,dual-channel"); | |
462 | if (dual) | |
463 | imx_ldb->ldb_ctrl |= LDB_SPLIT_MODE_EN; | |
464 | ||
465 | /* | |
4599934d | 466 | * There are three different possible clock mux configurations: |
ac4c1a9b SH |
467 | * i.MX53: ipu1_di0_sel, ipu1_di1_sel |
468 | * i.MX6q: ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel, ipu2_di1_sel | |
469 | * i.MX6dl: ipu1_di0_sel, ipu1_di1_sel, lcdif_sel | |
470 | * Map them all to di0_sel...di3_sel. | |
471 | */ | |
472 | for (i = 0; i < 4; i++) { | |
473 | char clkname[16]; | |
474 | ||
475 | sprintf(clkname, "di%d_sel", i); | |
476 | imx_ldb->clk_sel[i] = devm_clk_get(imx_ldb->dev, clkname); | |
477 | if (IS_ERR(imx_ldb->clk_sel[i])) { | |
478 | ret = PTR_ERR(imx_ldb->clk_sel[i]); | |
479 | imx_ldb->clk_sel[i] = NULL; | |
480 | break; | |
481 | } | |
482 | } | |
483 | if (i == 0) | |
484 | return ret; | |
485 | ||
486 | for_each_child_of_node(np, child) { | |
487 | struct imx_ldb_channel *channel; | |
488 | ||
489 | ret = of_property_read_u32(child, "reg", &i); | |
490 | if (ret || i < 0 || i > 1) | |
491 | return -EINVAL; | |
492 | ||
493 | if (dual && i > 0) { | |
17b5001b | 494 | dev_warn(dev, "dual-channel mode, ignoring second output\n"); |
ac4c1a9b SH |
495 | continue; |
496 | } | |
497 | ||
498 | if (!of_device_is_available(child)) | |
499 | continue; | |
500 | ||
501 | channel = &imx_ldb->channel[i]; | |
502 | channel->ldb = imx_ldb; | |
503 | channel->chno = i; | |
1b3f7675 | 504 | channel->child = child; |
ac4c1a9b SH |
505 | |
506 | edidp = of_get_property(child, "edid", &channel->edid_len); | |
507 | if (edidp) { | |
508 | channel->edid = kmemdup(edidp, channel->edid_len, | |
509 | GFP_KERNEL); | |
510 | } else { | |
511 | ret = of_get_drm_display_mode(child, &channel->mode, 0); | |
512 | if (!ret) | |
513 | channel->mode_valid = 1; | |
514 | } | |
515 | ||
516 | ret = of_property_read_u32(child, "fsl,data-width", &datawidth); | |
517 | if (ret) | |
518 | datawidth = 0; | |
519 | else if (datawidth != 18 && datawidth != 24) | |
520 | return -EINVAL; | |
521 | ||
522 | mapping = of_get_data_mapping(child); | |
523 | switch (mapping) { | |
524 | case LVDS_BIT_MAP_SPWG: | |
525 | if (datawidth == 24) { | |
526 | if (i == 0 || dual) | |
e5e1b166 AO |
527 | imx_ldb->ldb_ctrl |= |
528 | LDB_DATA_WIDTH_CH0_24; | |
ac4c1a9b | 529 | if (i == 1 || dual) |
e5e1b166 AO |
530 | imx_ldb->ldb_ctrl |= |
531 | LDB_DATA_WIDTH_CH1_24; | |
ac4c1a9b SH |
532 | } |
533 | break; | |
534 | case LVDS_BIT_MAP_JEIDA: | |
535 | if (datawidth == 18) { | |
17b5001b | 536 | dev_err(dev, "JEIDA standard only supported in 24 bit\n"); |
ac4c1a9b SH |
537 | return -EINVAL; |
538 | } | |
539 | if (i == 0 || dual) | |
e5e1b166 AO |
540 | imx_ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 | |
541 | LDB_BIT_MAP_CH0_JEIDA; | |
ac4c1a9b | 542 | if (i == 1 || dual) |
e5e1b166 AO |
543 | imx_ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 | |
544 | LDB_BIT_MAP_CH1_JEIDA; | |
ac4c1a9b SH |
545 | break; |
546 | default: | |
17b5001b | 547 | dev_err(dev, "data mapping not specified or invalid\n"); |
ac4c1a9b SH |
548 | return -EINVAL; |
549 | } | |
550 | ||
1b3f7675 | 551 | ret = imx_ldb_register(drm, channel); |
ac4c1a9b SH |
552 | if (ret) |
553 | return ret; | |
ac4c1a9b SH |
554 | } |
555 | ||
17b5001b | 556 | dev_set_drvdata(dev, imx_ldb); |
ac4c1a9b SH |
557 | |
558 | return 0; | |
559 | } | |
560 | ||
17b5001b RK |
561 | static void imx_ldb_unbind(struct device *dev, struct device *master, |
562 | void *data) | |
ac4c1a9b | 563 | { |
17b5001b | 564 | struct imx_ldb *imx_ldb = dev_get_drvdata(dev); |
ac4c1a9b SH |
565 | int i; |
566 | ||
567 | for (i = 0; i < 2; i++) { | |
568 | struct imx_ldb_channel *channel = &imx_ldb->channel[i]; | |
ac4c1a9b | 569 | |
d9fdb9fb RK |
570 | if (!channel->connector.funcs) |
571 | continue; | |
572 | ||
1b3f7675 RK |
573 | channel->connector.funcs->destroy(&channel->connector); |
574 | channel->encoder.funcs->destroy(&channel->encoder); | |
f4876ffe PS |
575 | |
576 | kfree(channel->edid); | |
ac4c1a9b | 577 | } |
17b5001b | 578 | } |
ac4c1a9b | 579 | |
17b5001b RK |
580 | static const struct component_ops imx_ldb_ops = { |
581 | .bind = imx_ldb_bind, | |
582 | .unbind = imx_ldb_unbind, | |
583 | }; | |
584 | ||
585 | static int imx_ldb_probe(struct platform_device *pdev) | |
586 | { | |
587 | return component_add(&pdev->dev, &imx_ldb_ops); | |
588 | } | |
589 | ||
590 | static int imx_ldb_remove(struct platform_device *pdev) | |
591 | { | |
592 | component_del(&pdev->dev, &imx_ldb_ops); | |
ac4c1a9b SH |
593 | return 0; |
594 | } | |
595 | ||
596 | static struct platform_driver imx_ldb_driver = { | |
597 | .probe = imx_ldb_probe, | |
598 | .remove = imx_ldb_remove, | |
599 | .driver = { | |
600 | .of_match_table = imx_ldb_dt_ids, | |
601 | .name = DRIVER_NAME, | |
ac4c1a9b SH |
602 | }, |
603 | }; | |
604 | ||
605 | module_platform_driver(imx_ldb_driver); | |
606 | ||
607 | MODULE_DESCRIPTION("i.MX LVDS driver"); | |
608 | MODULE_AUTHOR("Sascha Hauer, Pengutronix"); | |
609 | MODULE_LICENSE("GPL"); | |
bc627387 | 610 | MODULE_ALIAS("platform:" DRIVER_NAME); |