projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: Let's use more enum intel_dpll_id pll_id.
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_vbt_defs.h
CommitLineData
72341af4
JN		 1/*
2 * Copyright © 2006-2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28/*
29 * This information is private to VBT parsing in intel_bios.c.
30 *
31 * Please do NOT include anywhere else.
32 */
33#ifndef _INTEL_BIOS_PRIVATE
34#error "intel_vbt_defs.h is private to intel_bios.c"
35#endif
36
37#ifndef _INTEL_VBT_DEFS_H_
38#define _INTEL_VBT_DEFS_H_
39
40#include "intel_bios.h"
41
42/**
43 * struct vbt_header - VBT Header structure
44 * @signature: VBT signature, always starts with "$VBT"
45 * @version: Version of this structure
46 * @header_size: Size of this structure
47 * @vbt_size: Size of VBT (VBT Header, BDB Header and data blocks)
48 * @vbt_checksum: Checksum
49 * @reserved0: Reserved
50 * @bdb_offset: Offset of &struct bdb_header from beginning of VBT
51 * @aim_offset: Offsets of add-in data blocks from beginning of VBT
52 */
53struct vbt_header {
54 u8 signature[20];
55 u16 version;
56 u16 header_size;
57 u16 vbt_size;
58 u8 vbt_checksum;
59 u8 reserved0;
60 u32 bdb_offset;
61 u32 aim_offset[4];
62} __packed;
63
64/**
65 * struct bdb_header - BDB Header structure
66 * @signature: BDB signature "BIOS_DATA_BLOCK"
67 * @version: Version of the data block definitions
68 * @header_size: Size of this structure
69 * @bdb_size: Size of BDB (BDB Header and data blocks)
70 */
71struct bdb_header {
72 u8 signature[16];
73 u16 version;
74 u16 header_size;
75 u16 bdb_size;
76} __packed;
77
78/* strictly speaking, this is a "skip" block, but it has interesting info */
79struct vbios_data {
80 u8 type; /* 0 == desktop, 1 == mobile */
81 u8 relstage;
82 u8 chipset;
83 u8 lvds_present:1;
84 u8 tv_present:1;
85 u8 rsvd2:6; /* finish byte */
86 u8 rsvd3[4];
87 u8 signon[155];
88 u8 copyright[61];
89 u16 code_segment;
90 u8 dos_boot_mode;
91 u8 bandwidth_percent;
92 u8 rsvd4; /* popup memory size */
93 u8 resize_pci_bios;
94 u8 rsvd5; /* is crt already on ddc2 */
95} __packed;
96
97/*
98 * There are several types of BIOS data blocks (BDBs), each block has
99 * an ID and size in the first 3 bytes (ID in first, size in next 2).
100 * Known types are listed below.
101 */
102#define BDB_GENERAL_FEATURES 1
103#define BDB_GENERAL_DEFINITIONS 2
104#define BDB_OLD_TOGGLE_LIST 3
105#define BDB_MODE_SUPPORT_LIST 4
106#define BDB_GENERIC_MODE_TABLE 5
107#define BDB_EXT_MMIO_REGS 6
108#define BDB_SWF_IO 7
109#define BDB_SWF_MMIO 8
110#define BDB_PSR 9
111#define BDB_MODE_REMOVAL_TABLE 10
112#define BDB_CHILD_DEVICE_TABLE 11
113#define BDB_DRIVER_FEATURES 12
114#define BDB_DRIVER_PERSISTENCE 13
115#define BDB_EXT_TABLE_PTRS 14
116#define BDB_DOT_CLOCK_OVERRIDE 15
117#define BDB_DISPLAY_SELECT 16
118/* 17 rsvd */
119#define BDB_DRIVER_ROTATION 18
120#define BDB_DISPLAY_REMOVE 19
121#define BDB_OEM_CUSTOM 20
122#define BDB_EFP_LIST 21 /* workarounds for VGA hsync/vsync */
123#define BDB_SDVO_LVDS_OPTIONS 22
124#define BDB_SDVO_PANEL_DTDS 23
125#define BDB_SDVO_LVDS_PNP_IDS 24
126#define BDB_SDVO_LVDS_POWER_SEQ 25
127#define BDB_TV_OPTIONS 26
128#define BDB_EDP 27
129#define BDB_LVDS_OPTIONS 40
130#define BDB_LVDS_LFP_DATA_PTRS 41
131#define BDB_LVDS_LFP_DATA 42
132#define BDB_LVDS_BACKLIGHT 43
133#define BDB_LVDS_POWER 44
134#define BDB_MIPI_CONFIG 52
135#define BDB_MIPI_SEQUENCE 53
136#define BDB_SKIP 254 /* VBIOS private block, ignore */
137
138struct bdb_general_features {
139 /* bits 1 */
140 u8 panel_fitting:2;
141 u8 flexaim:1;
142 u8 msg_enable:1;
143 u8 clear_screen:3;
144 u8 color_flip:1;
145
146 /* bits 2 */
147 u8 download_ext_vbt:1;
148 u8 enable_ssc:1;
149 u8 ssc_freq:1;
150 u8 enable_lfp_on_override:1;
151 u8 disable_ssc_ddt:1;
e445dd18 152 u8 underscan_vga_timings:1;
72341af4 153 u8 display_clock_mode:1;
e445dd18 154 u8 vbios_hotplug_support:1;
72341af4
JN		 155
156 /* bits 3 */
157 u8 disable_smooth_vision:1;
158 u8 single_dvi:1;
e445dd18 159 u8 rotate_180:1; /* 181 */
72341af4 160 u8 fdi_rx_polarity_inverted:1;
e445dd18
JN		 161 u8 vbios_extended_mode:1; /* 160 */
162 u8 copy_ilfp_dtd_to_sdvo_lvds_dtd:1; /* 160 */
163 u8 panel_best_fit_timing:1; /* 160 */
164 u8 ignore_strap_state:1; /* 160 */
72341af4
JN		 165
166 /* bits 4 */
167 u8 legacy_monitor_detect;
168
169 /* bits 5 */
170 u8 int_crt_support:1;
171 u8 int_tv_support:1;
172 u8 int_efp_support:1;
e445dd18 173 u8 dp_ssc_enable:1; /* PCH attached eDP supports SSC */
72341af4 174 u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */
e445dd18
JN		 175 u8 dp_ssc_dongle_supported:1;
176 u8 rsvd11:2; /* finish byte */
72341af4
JN		 177} __packed;
178
179/* pre-915 */
180#define GPIO_PIN_DVI_LVDS 0x03 /* "DVI/LVDS DDC GPIO pins" */
181#define GPIO_PIN_ADD_I2C 0x05 /* "ADDCARD I2C GPIO pins" */
182#define GPIO_PIN_ADD_DDC 0x04 /* "ADDCARD DDC GPIO pins" */
183#define GPIO_PIN_ADD_DDC_I2C 0x06 /* "ADDCARD DDC/I2C GPIO pins" */
184
185/* Pre 915 */
186#define DEVICE_TYPE_NONE 0x00
187#define DEVICE_TYPE_CRT 0x01
188#define DEVICE_TYPE_TV 0x09
189#define DEVICE_TYPE_EFP 0x12
190#define DEVICE_TYPE_LFP 0x22
191/* On 915+ */
192#define DEVICE_TYPE_CRT_DPMS 0x6001
193#define DEVICE_TYPE_CRT_DPMS_HOTPLUG 0x4001
194#define DEVICE_TYPE_TV_COMPOSITE 0x0209
195#define DEVICE_TYPE_TV_MACROVISION 0x0289
196#define DEVICE_TYPE_TV_RF_COMPOSITE 0x020c
197#define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609
198#define DEVICE_TYPE_TV_SCART 0x0209
199#define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009
200#define DEVICE_TYPE_EFP_HOTPLUG_PWR 0x6012
201#define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052
202#define DEVICE_TYPE_EFP_DVI_I 0x6053
203#define DEVICE_TYPE_EFP_DVI_D_DUAL 0x6152
204#define DEVICE_TYPE_EFP_DVI_D_HDCP 0x60d2
205#define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062
206#define DEVICE_TYPE_OPENLDI_DUALPIX 0x6162
207#define DEVICE_TYPE_LFP_PANELLINK 0x5012
208#define DEVICE_TYPE_LFP_CMOS_PWR 0x5042
209#define DEVICE_TYPE_LFP_LVDS_PWR 0x5062
210#define DEVICE_TYPE_LFP_LVDS_DUAL 0x5162
211#define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP 0x51e2
212
6a794c8a
JN		 213/* Add the device class for LFP, TV, HDMI */
214#define DEVICE_TYPE_INT_LFP 0x1022
215#define DEVICE_TYPE_INT_TV 0x1009
216#define DEVICE_TYPE_HDMI 0x60D2
217#define DEVICE_TYPE_DP 0x68C6
218#define DEVICE_TYPE_DP_DUAL_MODE 0x60D6
219#define DEVICE_TYPE_eDP 0x78C6
220
221#define DEVICE_TYPE_CLASS_EXTENSION (1 << 15)
222#define DEVICE_TYPE_POWER_MANAGEMENT (1 << 14)
223#define DEVICE_TYPE_HOTPLUG_SIGNALING (1 << 13)
224#define DEVICE_TYPE_INTERNAL_CONNECTOR (1 << 12)
225#define DEVICE_TYPE_NOT_HDMI_OUTPUT (1 << 11)
226#define DEVICE_TYPE_MIPI_OUTPUT (1 << 10)
227#define DEVICE_TYPE_COMPOSITE_OUTPUT (1 << 9)
228#define DEVICE_TYPE_DUAL_CHANNEL (1 << 8)
229#define DEVICE_TYPE_HIGH_SPEED_LINK (1 << 6)
230#define DEVICE_TYPE_LVDS_SINGALING (1 << 5)
231#define DEVICE_TYPE_TMDS_DVI_SIGNALING (1 << 4)
232#define DEVICE_TYPE_VIDEO_SIGNALING (1 << 3)
233#define DEVICE_TYPE_DISPLAYPORT_OUTPUT (1 << 2)
234#define DEVICE_TYPE_DIGITAL_OUTPUT (1 << 1)
235#define DEVICE_TYPE_ANALOG_OUTPUT (1 << 0)
236
237/*
238 * Bits we care about when checking for DEVICE_TYPE_eDP. Depending on the
239 * system, the other bits may or may not be set for eDP outputs.
240 */
241#define DEVICE_TYPE_eDP_BITS \
242 (DEVICE_TYPE_INTERNAL_CONNECTOR | \
243 DEVICE_TYPE_MIPI_OUTPUT | \
244 DEVICE_TYPE_COMPOSITE_OUTPUT | \
245 DEVICE_TYPE_DUAL_CHANNEL | \
246 DEVICE_TYPE_LVDS_SINGALING | \
247 DEVICE_TYPE_TMDS_DVI_SIGNALING | \
248 DEVICE_TYPE_VIDEO_SIGNALING | \
249 DEVICE_TYPE_DISPLAYPORT_OUTPUT | \
250 DEVICE_TYPE_ANALOG_OUTPUT)
251
252#define DEVICE_TYPE_DP_DUAL_MODE_BITS \
253 (DEVICE_TYPE_INTERNAL_CONNECTOR | \
254 DEVICE_TYPE_MIPI_OUTPUT | \
255 DEVICE_TYPE_COMPOSITE_OUTPUT | \
256 DEVICE_TYPE_LVDS_SINGALING | \
257 DEVICE_TYPE_TMDS_DVI_SIGNALING | \
258 DEVICE_TYPE_VIDEO_SIGNALING | \
259 DEVICE_TYPE_DISPLAYPORT_OUTPUT | \
260 DEVICE_TYPE_DIGITAL_OUTPUT | \
261 DEVICE_TYPE_ANALOG_OUTPUT)
262
72341af4
JN		 263#define DEVICE_CFG_NONE 0x00
264#define DEVICE_CFG_12BIT_DVOB 0x01
265#define DEVICE_CFG_12BIT_DVOC 0x02
266#define DEVICE_CFG_24BIT_DVOBC 0x09
267#define DEVICE_CFG_24BIT_DVOCB 0x0a
268#define DEVICE_CFG_DUAL_DVOB 0x11
269#define DEVICE_CFG_DUAL_DVOC 0x12
270#define DEVICE_CFG_DUAL_DVOBC 0x13
271#define DEVICE_CFG_DUAL_LINK_DVOBC 0x19
272#define DEVICE_CFG_DUAL_LINK_DVOCB 0x1a
273
274#define DEVICE_WIRE_NONE 0x00
275#define DEVICE_WIRE_DVOB 0x01
276#define DEVICE_WIRE_DVOC 0x02
277#define DEVICE_WIRE_DVOBC 0x03
278#define DEVICE_WIRE_DVOBB 0x05
279#define DEVICE_WIRE_DVOCC 0x06
280#define DEVICE_WIRE_DVOB_MASTER 0x0d
281#define DEVICE_WIRE_DVOC_MASTER 0x0e
282
fca36df5 283/* dvo_port pre BDB 155 */
72341af4
JN		 284#define DEVICE_PORT_DVOA 0x00 /* none on 845+ */
285#define DEVICE_PORT_DVOB 0x01
286#define DEVICE_PORT_DVOC 0x02
287
fca36df5
JN		 288/* dvo_port BDB 155+ */
289#define DVO_PORT_HDMIA 0
290#define DVO_PORT_HDMIB 1
291#define DVO_PORT_HDMIC 2
292#define DVO_PORT_HDMID 3
293#define DVO_PORT_LVDS 4
294#define DVO_PORT_TV 5
295#define DVO_PORT_CRT 6
296#define DVO_PORT_DPB 7
297#define DVO_PORT_DPC 8
298#define DVO_PORT_DPD 9
299#define DVO_PORT_DPA 10
300#define DVO_PORT_DPE 11 /* 193 */
301#define DVO_PORT_HDMIE 12 /* 193 */
302#define DVO_PORT_MIPIA 21 /* 171 */
303#define DVO_PORT_MIPIB 22 /* 171 */
304#define DVO_PORT_MIPIC 23 /* 171 */
305#define DVO_PORT_MIPID 24 /* 171 */
306
21907e72 307#define LEGACY_CHILD_DEVICE_CONFIG_SIZE 33
72341af4 308
56f304e9
JN		 309/*
310 * The child device config, aka the display device data structure, provides a
311 * description of a port and its configuration on the platform.
312 *
313 * The child device config size has been increased, and fields have been added
314 * and their meaning has changed over time. Care must be taken when accessing
315 * basically any of the fields to ensure the correct interpretation for the BDB
316 * version in question.
317 *
318 * When we copy the child device configs to dev_priv->vbt.child_dev, we reserve
319 * space for the full structure below, and initialize the tail not actually
320 * present in VBT to zeros. Accessing those fields is fine, as long as the
321 * default zero is taken into account, again according to the BDB version.
322 *
323 * BDB versions 155 and below are considered legacy, and version 155 seems to be
324 * a baseline for some of the VBT documentation. When adding new fields, please
325 * include the BDB version when the field was added, if it's above that.
326 */
cc998589 327struct child_device_config {
72341af4 328 u16 handle;
6a794c8a 329 u16 device_type; /* See DEVICE_TYPE_* above */
56f304e9
JN		 330
331 union {
332 u8 device_id[10]; /* ascii string */
333 struct {
334 u8 i2c_speed;
335 u8 dp_onboard_redriver; /* 158 */
336 u8 dp_ondock_redriver; /* 158 */
337 u8 hdmi_level_shifter_value:4; /* 169 */
338 u8 hdmi_max_data_rate:4; /* 204 */
339 u16 dtd_buf_ptr; /* 161 */
340 u8 edidless_efp:1; /* 161 */
341 u8 compression_enable:1; /* 198 */
342 u8 compression_method:1; /* 198 */
343 u8 ganged_edp:1; /* 202 */
344 u8 reserved0:4;
345 u8 compression_structure_index:4; /* 198 */
346 u8 reserved1:4;
347 u8 slave_port; /* 202 */
348 u8 reserved2;
349 } __packed;
350 } __packed;
351
f865f7e1 352 u16 addin_offset;
fca36df5 353 u8 dvo_port; /* See DEVICE_PORT_* and DVO_PORT_* above */
f865f7e1
JN		 354 u8 i2c_pin;
355 u8 slave_addr;
72341af4
JN		 356 u8 ddc_pin;
357 u16 edid_ptr;
4e27bd50 358 u8 dvo_cfg; /* See DEVICE_CFG_* above */
56f304e9
JN		 359
360 union {
361 struct {
362 u8 dvo2_port;
363 u8 i2c2_pin;
364 u8 slave2_addr;
365 u8 ddc2_pin;
366 } __packed;
367 struct {
368 u8 efp_routed:1; /* 158 */
369 u8 lane_reversal:1; /* 184 */
370 u8 lspcon:1; /* 192 */
371 u8 iboost:1; /* 196 */
372 u8 hpd_invert:1; /* 196 */
373 u8 flag_reserved:3;
374 u8 hdmi_support:1; /* 158 */
375 u8 dp_support:1; /* 158 */
376 u8 tmds_support:1; /* 158 */
377 u8 support_reserved:5;
378 u8 aux_channel;
379 u8 dongle_detect;
380 } __packed;
381 } __packed;
382
b7c7c3ea
JN		 383 u8 pipe_cap:2;
384 u8 sdvo_stall:1; /* 158 */
385 u8 hpd_status:2;
386 u8 integrated_encoder:1;
387 u8 capabilities_reserved:2;
f865f7e1 388 u8 dvo_wiring; /* See DEVICE_WIRE_* above */
56f304e9
JN		 389
390 union {
391 u8 dvo2_wiring;
392 u8 mipi_bridge_type; /* 171 */
393 } __packed;
394
f865f7e1
JN		 395 u16 extended_type;
396 u8 dvo_function;
b7c7c3ea
JN		 397 u8 dp_usb_type_c:1; /* 195 */
398 u8 flags2_reserved:7; /* 195 */
f865f7e1
JN		 399 u8 dp_gpio_index; /* 195 */
400 u16 dp_gpio_pin_num; /* 195 */
f22bb358
JN		 401 u8 dp_iboost_level:4; /* 196 */
402 u8 hdmi_iboost_level:4; /* 196 */
72341af4
JN		 403} __packed;
404
72341af4
JN		 405struct bdb_general_definitions {
406 /* DDC GPIO */
407 u8 crt_ddc_gmbus_pin;
408
409 /* DPMS bits */
410 u8 dpms_acpi:1;
411 u8 skip_boot_crt_detect:1;
412 u8 dpms_aim:1;
413 u8 rsvd1:5; /* finish byte */
414
415 /* boot device bits */
416 u8 boot_display[2];
417 u8 child_dev_size;
418
419 /*
420 * Device info:
421 * If TV is present, it'll be at devices[0].
422 * LVDS will be next, either devices[0] or [1], if present.
423 * On some platforms the number of device is 6. But could be as few as
424 * 4 if both TV and LVDS are missing.
425 * And the device num is related with the size of general definition
426 * block. It is obtained by using the following formula:
427 * number = (block_size - sizeof(bdb_general_definitions))/
428 * defs->child_dev_size;
429 */
430 uint8_t devices[0];
431} __packed;
432
433/* Mask for DRRS / Panel Channel / SSC / BLT control bits extraction */
434#define MODE_MASK 0x3
435
436struct bdb_lvds_options {
437 u8 panel_type;
438 u8 rsvd1;
439 /* LVDS capabilities, stored in a dword */
440 u8 pfit_mode:2;
441 u8 pfit_text_mode_enhanced:1;
442 u8 pfit_gfx_mode_enhanced:1;
443 u8 pfit_ratio_auto:1;
444 u8 pixel_dither:1;
445 u8 lvds_edid:1;
446 u8 rsvd2:1;
447 u8 rsvd4;
448 /* LVDS Panel channel bits stored here */
449 u32 lvds_panel_channel_bits;
450 /* LVDS SSC (Spread Spectrum Clock) bits stored here. */
451 u16 ssc_bits;
452 u16 ssc_freq;
453 u16 ssc_ddt;
454 /* Panel color depth defined here */
455 u16 panel_color_depth;
456 /* LVDS panel type bits stored here */
457 u32 dps_panel_type_bits;
458 /* LVDS backlight control type bits stored here */
459 u32 blt_control_type_bits;
460} __packed;
461
462/* LFP pointer table contains entries to the struct below */
463struct bdb_lvds_lfp_data_ptr {
464 u16 fp_timing_offset; /* offsets are from start of bdb */
465 u8 fp_table_size;
466 u16 dvo_timing_offset;
467 u8 dvo_table_size;
468 u16 panel_pnp_id_offset;
469 u8 pnp_table_size;
470} __packed;
471
472struct bdb_lvds_lfp_data_ptrs {
473 u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */
474 struct bdb_lvds_lfp_data_ptr ptr[16];
475} __packed;
476
477/* LFP data has 3 blocks per entry */
478struct lvds_fp_timing {
479 u16 x_res;
480 u16 y_res;
481 u32 lvds_reg;
482 u32 lvds_reg_val;
483 u32 pp_on_reg;
484 u32 pp_on_reg_val;
485 u32 pp_off_reg;
486 u32 pp_off_reg_val;
487 u32 pp_cycle_reg;
488 u32 pp_cycle_reg_val;
489 u32 pfit_reg;
490 u32 pfit_reg_val;
491 u16 terminator;
492} __packed;
493
494struct lvds_dvo_timing {
495 u16 clock; /**< In 10khz */
496 u8 hactive_lo;
497 u8 hblank_lo;
498 u8 hblank_hi:4;
499 u8 hactive_hi:4;
500 u8 vactive_lo;
501 u8 vblank_lo;
502 u8 vblank_hi:4;
503 u8 vactive_hi:4;
504 u8 hsync_off_lo;
ce2e87b4
VT		 505 u8 hsync_pulse_width_lo;
506 u8 vsync_pulse_width_lo:4;
507 u8 vsync_off_lo:4;
508 u8 vsync_pulse_width_hi:2;
509 u8 vsync_off_hi:2;
510 u8 hsync_pulse_width_hi:2;
72341af4 511 u8 hsync_off_hi:2;
df457245
VS		 512 u8 himage_lo;
513 u8 vimage_lo;
514 u8 vimage_hi:4;
515 u8 himage_hi:4;
72341af4
JN		 516 u8 h_border;
517 u8 v_border;
518 u8 rsvd1:3;
519 u8 digital:2;
520 u8 vsync_positive:1;
521 u8 hsync_positive:1;
ce2e87b4 522 u8 non_interlaced:1;
72341af4
JN		 523} __packed;
524
525struct lvds_pnp_id {
526 u16 mfg_name;
527 u16 product_code;
528 u32 serial;
529 u8 mfg_week;
530 u8 mfg_year;
531} __packed;
532
533struct bdb_lvds_lfp_data_entry {
534 struct lvds_fp_timing fp_timing;
535 struct lvds_dvo_timing dvo_timing;
536 struct lvds_pnp_id pnp_id;
537} __packed;
538
539struct bdb_lvds_lfp_data {
540 struct bdb_lvds_lfp_data_entry data[16];
541} __packed;
542
543#define BDB_BACKLIGHT_TYPE_NONE 0
544#define BDB_BACKLIGHT_TYPE_PWM 2
545
546struct bdb_lfp_backlight_data_entry {
547 u8 type:2;
548 u8 active_low_pwm:1;
549 u8 obsolete1:5;
550 u16 pwm_freq_hz;
551 u8 min_brightness;
552 u8 obsolete2;
553 u8 obsolete3;
554} __packed;
555
9a41e17d
D		 556struct bdb_lfp_backlight_control_method {
557 u8 type:4;
558 u8 controller:4;
559} __packed;
560
72341af4
JN		 561struct bdb_lfp_backlight_data {
562 u8 entry_size;
563 struct bdb_lfp_backlight_data_entry data[16];
564 u8 level[16];
9a41e17d 565 struct bdb_lfp_backlight_control_method backlight_control[16];
72341af4
JN		 566} __packed;
567
568struct aimdb_header {
569 char signature[16];
570 char oem_device[20];
571 u16 aimdb_version;
572 u16 aimdb_header_size;
573 u16 aimdb_size;
574} __packed;
575
576struct aimdb_block {
577 u8 aimdb_id;
578 u16 aimdb_size;
579} __packed;
580
581struct vch_panel_data {
582 u16 fp_timing_offset;
583 u8 fp_timing_size;
584 u16 dvo_timing_offset;
585 u8 dvo_timing_size;
586 u16 text_fitting_offset;
587 u8 text_fitting_size;
588 u16 graphics_fitting_offset;
589 u8 graphics_fitting_size;
590} __packed;
591
592struct vch_bdb_22 {
593 struct aimdb_block aimdb_block;
594 struct vch_panel_data panels[16];
595} __packed;
596
597struct bdb_sdvo_lvds_options {
598 u8 panel_backlight;
599 u8 h40_set_panel_type;
600 u8 panel_type;
601 u8 ssc_clk_freq;
602 u16 als_low_trip;
603 u16 als_high_trip;
604 u8 sclalarcoeff_tab_row_num;
605 u8 sclalarcoeff_tab_row_size;
606 u8 coefficient[8];
607 u8 panel_misc_bits_1;
608 u8 panel_misc_bits_2;
609 u8 panel_misc_bits_3;
610 u8 panel_misc_bits_4;
611} __packed;
612
613
614#define BDB_DRIVER_FEATURE_NO_LVDS 0
615#define BDB_DRIVER_FEATURE_INT_LVDS 1
616#define BDB_DRIVER_FEATURE_SDVO_LVDS 2
617#define BDB_DRIVER_FEATURE_EDP 3
618
619struct bdb_driver_features {
620 u8 boot_dev_algorithm:1;
621 u8 block_display_switch:1;
622 u8 allow_display_switch:1;
623 u8 hotplug_dvo:1;
624 u8 dual_view_zoom:1;
625 u8 int15h_hook:1;
626 u8 sprite_in_clone:1;
627 u8 primary_lfp_id:1;
628
629 u16 boot_mode_x;
630 u16 boot_mode_y;
631 u8 boot_mode_bpp;
632 u8 boot_mode_refresh;
633
634 u16 enable_lfp_primary:1;
635 u16 selective_mode_pruning:1;
636 u16 dual_frequency:1;
637 u16 render_clock_freq:1; /* 0: high freq; 1: low freq */
638 u16 nt_clone_support:1;
639 u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */
640 u16 sprite_display_assign:1; /* 0: secondary; 1: primary */
641 u16 cui_aspect_scaling:1;
642 u16 preserve_aspect_ratio:1;
643 u16 sdvo_device_power_down:1;
644 u16 crt_hotplug:1;
645 u16 lvds_config:2;
646 u16 tv_hotplug:1;
647 u16 hdmi_config:2;
648
649 u8 static_display:1;
650 u8 reserved2:7;
651 u16 legacy_crt_max_x;
652 u16 legacy_crt_max_y;
653 u8 legacy_crt_max_refresh;
654
655 u8 hdmi_termination;
656 u8 custom_vbt_version;
657 /* Driver features data block */
658 u16 rmpm_enabled:1;
659 u16 s2ddt_enabled:1;
660 u16 dpst_enabled:1;
661 u16 bltclt_enabled:1;
662 u16 adb_enabled:1;
663 u16 drrs_enabled:1;
664 u16 grs_enabled:1;
665 u16 gpmt_enabled:1;
666 u16 tbt_enabled:1;
667 u16 psr_enabled:1;
668 u16 ips_enabled:1;
669 u16 reserved3:4;
670 u16 pc_feature_valid:1;
671} __packed;
672
673#define EDP_18BPP 0
674#define EDP_24BPP 1
675#define EDP_30BPP 2
676#define EDP_RATE_1_62 0
677#define EDP_RATE_2_7 1
678#define EDP_LANE_1 0
679#define EDP_LANE_2 1
680#define EDP_LANE_4 3
681#define EDP_PREEMPHASIS_NONE 0
682#define EDP_PREEMPHASIS_3_5dB 1
683#define EDP_PREEMPHASIS_6dB 2
684#define EDP_PREEMPHASIS_9_5dB 3
685#define EDP_VSWING_0_4V 0
686#define EDP_VSWING_0_6V 1
687#define EDP_VSWING_0_8V 2
688#define EDP_VSWING_1_2V 3
689
690
058727ee 691struct edp_fast_link_params {
72341af4
JN		 692 u8 rate:4;
693 u8 lanes:4;
694 u8 preemphasis:4;
695 u8 vswing:4;
696} __packed;
697
058727ee
JN		 698struct edp_pwm_delays {
699 u16 pwm_on_to_backlight_enable;
700 u16 backlight_disable_to_pwm_off;
701} __packed;
702
703struct edp_full_link_params {
704 u8 preemphasis:4;
705 u8 vswing:4;
706} __packed;
707
72341af4
JN		 708struct bdb_edp {
709 struct edp_power_seq power_seqs[16];
710 u32 color_depth;
058727ee 711 struct edp_fast_link_params fast_link_params[16];
72341af4
JN		 712 u32 sdrrs_msa_timing_delay;
713
714 /* ith bit indicates enabled/disabled for (i+1)th panel */
058727ee
JN		 715 u16 edp_s3d_feature; /* 162 */
716 u16 edp_t3_optimization; /* 165 */
717 u64 edp_vswing_preemph; /* 173 */
718 u16 fast_link_training; /* 182 */
719 u16 dpcd_600h_write_required; /* 185 */
720 struct edp_pwm_delays pwm_delays[16]; /* 186 */
721 u16 full_link_params_provided; /* 199 */
722 struct edp_full_link_params full_link_params[16]; /* 199 */
72341af4
JN		 723} __packed;
724
725struct psr_table {
726 /* Feature bits */
727 u8 full_link:1;
728 u8 require_aux_to_wakeup:1;
729 u8 feature_bits_rsvd:6;
730
731 /* Wait times */
732 u8 idle_frames:4;
733 u8 lines_to_wait:3;
734 u8 wait_times_rsvd:1;
735
736 /* TP wake up time in multiple of 100 */
737 u16 tp1_wakeup_time;
738 u16 tp2_tp3_wakeup_time;
739} __packed;
740
741struct bdb_psr {
742 struct psr_table psr_table[16];
743} __packed;
744
745/*
746 * Driver<->VBIOS interaction occurs through scratch bits in
747 * GR18 & SWF*.
748 */
749
750/* GR18 bits are set on display switch and hotkey events */
751#define GR18_DRIVER_SWITCH_EN (1<<7) /* 0: VBIOS control, 1: driver control */
752#define GR18_HOTKEY_MASK 0x78 /* See also SWF4 15:0 */
753#define GR18_HK_NONE (0x0<<3)
754#define GR18_HK_LFP_STRETCH (0x1<<3)
755#define GR18_HK_TOGGLE_DISP (0x2<<3)
756#define GR18_HK_DISP_SWITCH (0x4<<3) /* see SWF14 15:0 for what to enable */
757#define GR18_HK_POPUP_DISABLED (0x6<<3)
758#define GR18_HK_POPUP_ENABLED (0x7<<3)
759#define GR18_HK_PFIT (0x8<<3)
760#define GR18_HK_APM_CHANGE (0xa<<3)
761#define GR18_HK_MULTIPLE (0xc<<3)
762#define GR18_USER_INT_EN (1<<2)
763#define GR18_A0000_FLUSH_EN (1<<1)
764#define GR18_SMM_EN (1<<0)
765
766/* Set by driver, cleared by VBIOS */
767#define SWF00_YRES_SHIFT 16
768#define SWF00_XRES_SHIFT 0
769#define SWF00_RES_MASK 0xffff
770
771/* Set by VBIOS at boot time and driver at runtime */
772#define SWF01_TV2_FORMAT_SHIFT 8
773#define SWF01_TV1_FORMAT_SHIFT 0
774#define SWF01_TV_FORMAT_MASK 0xffff
775
776#define SWF10_VBIOS_BLC_I2C_EN (1<<29)
777#define SWF10_GTT_OVERRIDE_EN (1<<28)
778#define SWF10_LFP_DPMS_OVR (1<<27) /* override DPMS on display switch */
779#define SWF10_ACTIVE_TOGGLE_LIST_MASK (7<<24)
780#define SWF10_OLD_TOGGLE 0x0
781#define SWF10_TOGGLE_LIST_1 0x1
782#define SWF10_TOGGLE_LIST_2 0x2
783#define SWF10_TOGGLE_LIST_3 0x3
784#define SWF10_TOGGLE_LIST_4 0x4
785#define SWF10_PANNING_EN (1<<23)
786#define SWF10_DRIVER_LOADED (1<<22)
787#define SWF10_EXTENDED_DESKTOP (1<<21)
788#define SWF10_EXCLUSIVE_MODE (1<<20)
789#define SWF10_OVERLAY_EN (1<<19)
790#define SWF10_PLANEB_HOLDOFF (1<<18)
791#define SWF10_PLANEA_HOLDOFF (1<<17)
792#define SWF10_VGA_HOLDOFF (1<<16)
793#define SWF10_ACTIVE_DISP_MASK 0xffff
794#define SWF10_PIPEB_LFP2 (1<<15)
795#define SWF10_PIPEB_EFP2 (1<<14)
796#define SWF10_PIPEB_TV2 (1<<13)
797#define SWF10_PIPEB_CRT2 (1<<12)
798#define SWF10_PIPEB_LFP (1<<11)
799#define SWF10_PIPEB_EFP (1<<10)
800#define SWF10_PIPEB_TV (1<<9)
801#define SWF10_PIPEB_CRT (1<<8)
802#define SWF10_PIPEA_LFP2 (1<<7)
803#define SWF10_PIPEA_EFP2 (1<<6)
804#define SWF10_PIPEA_TV2 (1<<5)
805#define SWF10_PIPEA_CRT2 (1<<4)
806#define SWF10_PIPEA_LFP (1<<3)
807#define SWF10_PIPEA_EFP (1<<2)
808#define SWF10_PIPEA_TV (1<<1)
809#define SWF10_PIPEA_CRT (1<<0)
810
811#define SWF11_MEMORY_SIZE_SHIFT 16
812#define SWF11_SV_TEST_EN (1<<15)
813#define SWF11_IS_AGP (1<<14)
814#define SWF11_DISPLAY_HOLDOFF (1<<13)
815#define SWF11_DPMS_REDUCED (1<<12)
816#define SWF11_IS_VBE_MODE (1<<11)
817#define SWF11_PIPEB_ACCESS (1<<10) /* 0 here means pipe a */
818#define SWF11_DPMS_MASK 0x07
819#define SWF11_DPMS_OFF (1<<2)
820#define SWF11_DPMS_SUSPEND (1<<1)
821#define SWF11_DPMS_STANDBY (1<<0)
822#define SWF11_DPMS_ON 0
823
824#define SWF14_GFX_PFIT_EN (1<<31)
825#define SWF14_TEXT_PFIT_EN (1<<30)
826#define SWF14_LID_STATUS_CLOSED (1<<29) /* 0 here means open */
827#define SWF14_POPUP_EN (1<<28)
828#define SWF14_DISPLAY_HOLDOFF (1<<27)
829#define SWF14_DISP_DETECT_EN (1<<26)
830#define SWF14_DOCKING_STATUS_DOCKED (1<<25) /* 0 here means undocked */
831#define SWF14_DRIVER_STATUS (1<<24)
832#define SWF14_OS_TYPE_WIN9X (1<<23)
833#define SWF14_OS_TYPE_WINNT (1<<22)
834/* 21:19 rsvd */
835#define SWF14_PM_TYPE_MASK 0x00070000
836#define SWF14_PM_ACPI_VIDEO (0x4 << 16)
837#define SWF14_PM_ACPI (0x3 << 16)
838#define SWF14_PM_APM_12 (0x2 << 16)
839#define SWF14_PM_APM_11 (0x1 << 16)
840#define SWF14_HK_REQUEST_MASK 0x0000ffff /* see GR18 6:3 for event type */
841 /* if GR18 indicates a display switch */
842#define SWF14_DS_PIPEB_LFP2_EN (1<<15)
843#define SWF14_DS_PIPEB_EFP2_EN (1<<14)
844#define SWF14_DS_PIPEB_TV2_EN (1<<13)
845#define SWF14_DS_PIPEB_CRT2_EN (1<<12)
846#define SWF14_DS_PIPEB_LFP_EN (1<<11)
847#define SWF14_DS_PIPEB_EFP_EN (1<<10)
848#define SWF14_DS_PIPEB_TV_EN (1<<9)
849#define SWF14_DS_PIPEB_CRT_EN (1<<8)
850#define SWF14_DS_PIPEA_LFP2_EN (1<<7)
851#define SWF14_DS_PIPEA_EFP2_EN (1<<6)
852#define SWF14_DS_PIPEA_TV2_EN (1<<5)
853#define SWF14_DS_PIPEA_CRT2_EN (1<<4)
854#define SWF14_DS_PIPEA_LFP_EN (1<<3)
855#define SWF14_DS_PIPEA_EFP_EN (1<<2)
856#define SWF14_DS_PIPEA_TV_EN (1<<1)
857#define SWF14_DS_PIPEA_CRT_EN (1<<0)
858 /* if GR18 indicates a panel fitting request */
859#define SWF14_PFIT_EN (1<<0) /* 0 means disable */
860 /* if GR18 indicates an APM change request */
861#define SWF14_APM_HIBERNATE 0x4
862#define SWF14_APM_SUSPEND 0x3
863#define SWF14_APM_STANDBY 0x1
864#define SWF14_APM_RESTORE 0x0
865
72341af4
JN		 866/* Block 52 contains MIPI configuration block
867 * 6 * bdb_mipi_config, followed by 6 pps data block
868 * block below
869 */
870#define MAX_MIPI_CONFIGURATIONS 6
871
872struct bdb_mipi_config {
873 struct mipi_config config[MAX_MIPI_CONFIGURATIONS];
874 struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS];
875} __packed;
876
877/* Block 53 contains MIPI sequences as needed by the panel
878 * for enabling it. This block can be variable in size and
879 * can be maximum of 6 blocks
880 */
881struct bdb_mipi_sequence {
882 u8 version;
883 u8 data[0];
884} __packed;
885
886enum mipi_gpio_pin_index {
887 MIPI_GPIO_UNDEFINED = 0,
888 MIPI_GPIO_PANEL_ENABLE,
889 MIPI_GPIO_BL_ENABLE,
890 MIPI_GPIO_PWM_ENABLE,
891 MIPI_GPIO_RESET_N,
892 MIPI_GPIO_PWR_DOWN_R,
893 MIPI_GPIO_STDBY_RST_N,
894 MIPI_GPIO_MAX
895};
896
897#endif /* _INTEL_VBT_DEFS_H_ */
Linux 6.x block layer and io_uring tree(s)