Commit | Line | Data |
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907b28c5 CW |
1 | /* |
2 | * Copyright © 2013 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | */ | |
23 | ||
696173b0 JN |
24 | #include <linux/pm_runtime.h> |
25 | #include <asm/iosf_mbi.h> | |
26 | ||
907b28c5 | 27 | #include "i915_drv.h" |
cf9d2890 | 28 | #include "i915_vgpu.h" |
696173b0 JN |
29 | #include "intel_drv.h" |
30 | #include "intel_pm.h" | |
6daccb0b | 31 | |
83e33372 | 32 | #define FORCEWAKE_ACK_TIMEOUT_MS 50 |
6b07b6d2 | 33 | #define GT_FIFO_TIMEOUT_MS 10 |
907b28c5 | 34 | |
6cc5ca76 | 35 | #define __raw_posting_read(...) ((void)__raw_uncore_read32(__VA_ARGS__)) |
6af5d92f | 36 | |
05a2fb15 MK |
37 | static const char * const forcewake_domain_names[] = { |
38 | "render", | |
39 | "blitter", | |
40 | "media", | |
a89a70a8 DCS |
41 | "vdbox0", |
42 | "vdbox1", | |
43 | "vdbox2", | |
44 | "vdbox3", | |
45 | "vebox0", | |
46 | "vebox1", | |
05a2fb15 MK |
47 | }; |
48 | ||
49 | const char * | |
48c1026a | 50 | intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id) |
05a2fb15 | 51 | { |
53abb679 | 52 | BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT); |
05a2fb15 MK |
53 | |
54 | if (id >= 0 && id < FW_DOMAIN_ID_COUNT) | |
55 | return forcewake_domain_names[id]; | |
56 | ||
57 | WARN_ON(id); | |
58 | ||
59 | return "unknown"; | |
60 | } | |
61 | ||
535d8d27 | 62 | #define fw_ack(d) readl((d)->reg_ack) |
159367bb DCS |
63 | #define fw_set(d, val) writel(_MASKED_BIT_ENABLE((val)), (d)->reg_set) |
64 | #define fw_clear(d, val) writel(_MASKED_BIT_DISABLE((val)), (d)->reg_set) | |
535d8d27 | 65 | |
05a2fb15 | 66 | static inline void |
159367bb | 67 | fw_domain_reset(const struct intel_uncore_forcewake_domain *d) |
907b28c5 | 68 | { |
26376a7e OM |
69 | /* |
70 | * We don't really know if the powerwell for the forcewake domain we are | |
71 | * trying to reset here does exist at this point (engines could be fused | |
72 | * off in ICL+), so no waiting for acks | |
73 | */ | |
159367bb DCS |
74 | /* WaRsClearFWBitsAtReset:bdw,skl */ |
75 | fw_clear(d, 0xffff); | |
907b28c5 CW |
76 | } |
77 | ||
05a2fb15 MK |
78 | static inline void |
79 | fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d) | |
907b28c5 | 80 | { |
a57a4a67 TU |
81 | d->wake_count++; |
82 | hrtimer_start_range_ns(&d->timer, | |
8b0e1953 | 83 | NSEC_PER_MSEC, |
a57a4a67 TU |
84 | NSEC_PER_MSEC, |
85 | HRTIMER_MODE_REL); | |
907b28c5 CW |
86 | } |
87 | ||
71306303 | 88 | static inline int |
535d8d27 | 89 | __wait_for_ack(const struct intel_uncore_forcewake_domain *d, |
71306303 MK |
90 | const u32 ack, |
91 | const u32 value) | |
92 | { | |
535d8d27 | 93 | return wait_for_atomic((fw_ack(d) & ack) == value, |
71306303 MK |
94 | FORCEWAKE_ACK_TIMEOUT_MS); |
95 | } | |
96 | ||
97 | static inline int | |
535d8d27 | 98 | wait_ack_clear(const struct intel_uncore_forcewake_domain *d, |
71306303 MK |
99 | const u32 ack) |
100 | { | |
535d8d27 | 101 | return __wait_for_ack(d, ack, 0); |
71306303 MK |
102 | } |
103 | ||
104 | static inline int | |
535d8d27 | 105 | wait_ack_set(const struct intel_uncore_forcewake_domain *d, |
71306303 MK |
106 | const u32 ack) |
107 | { | |
535d8d27 | 108 | return __wait_for_ack(d, ack, ack); |
71306303 MK |
109 | } |
110 | ||
05a2fb15 | 111 | static inline void |
535d8d27 | 112 | fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d) |
907b28c5 | 113 | { |
18ecc6c5 | 114 | if (wait_ack_clear(d, FORCEWAKE_KERNEL)) { |
05a2fb15 MK |
115 | DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n", |
116 | intel_uncore_forcewake_domain_to_str(d->id)); | |
18ecc6c5 CW |
117 | add_taint_for_CI(TAINT_WARN); /* CI now unreliable */ |
118 | } | |
05a2fb15 | 119 | } |
907b28c5 | 120 | |
71306303 MK |
121 | enum ack_type { |
122 | ACK_CLEAR = 0, | |
123 | ACK_SET | |
124 | }; | |
125 | ||
126 | static int | |
535d8d27 | 127 | fw_domain_wait_ack_with_fallback(const struct intel_uncore_forcewake_domain *d, |
71306303 MK |
128 | const enum ack_type type) |
129 | { | |
130 | const u32 ack_bit = FORCEWAKE_KERNEL; | |
131 | const u32 value = type == ACK_SET ? ack_bit : 0; | |
132 | unsigned int pass; | |
133 | bool ack_detected; | |
134 | ||
135 | /* | |
136 | * There is a possibility of driver's wake request colliding | |
137 | * with hardware's own wake requests and that can cause | |
138 | * hardware to not deliver the driver's ack message. | |
139 | * | |
140 | * Use a fallback bit toggle to kick the gpu state machine | |
141 | * in the hope that the original ack will be delivered along with | |
142 | * the fallback ack. | |
143 | * | |
cc38cae7 OM |
144 | * This workaround is described in HSDES #1604254524 and it's known as: |
145 | * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl | |
146 | * although the name is a bit misleading. | |
71306303 MK |
147 | */ |
148 | ||
149 | pass = 1; | |
150 | do { | |
535d8d27 | 151 | wait_ack_clear(d, FORCEWAKE_KERNEL_FALLBACK); |
71306303 | 152 | |
159367bb | 153 | fw_set(d, FORCEWAKE_KERNEL_FALLBACK); |
71306303 MK |
154 | /* Give gt some time to relax before the polling frenzy */ |
155 | udelay(10 * pass); | |
535d8d27 | 156 | wait_ack_set(d, FORCEWAKE_KERNEL_FALLBACK); |
71306303 | 157 | |
535d8d27 | 158 | ack_detected = (fw_ack(d) & ack_bit) == value; |
71306303 | 159 | |
159367bb | 160 | fw_clear(d, FORCEWAKE_KERNEL_FALLBACK); |
71306303 MK |
161 | } while (!ack_detected && pass++ < 10); |
162 | ||
163 | DRM_DEBUG_DRIVER("%s had to use fallback to %s ack, 0x%x (passes %u)\n", | |
164 | intel_uncore_forcewake_domain_to_str(d->id), | |
165 | type == ACK_SET ? "set" : "clear", | |
535d8d27 | 166 | fw_ack(d), |
71306303 MK |
167 | pass); |
168 | ||
169 | return ack_detected ? 0 : -ETIMEDOUT; | |
170 | } | |
171 | ||
172 | static inline void | |
535d8d27 | 173 | fw_domain_wait_ack_clear_fallback(const struct intel_uncore_forcewake_domain *d) |
71306303 | 174 | { |
535d8d27 | 175 | if (likely(!wait_ack_clear(d, FORCEWAKE_KERNEL))) |
71306303 MK |
176 | return; |
177 | ||
535d8d27 DCS |
178 | if (fw_domain_wait_ack_with_fallback(d, ACK_CLEAR)) |
179 | fw_domain_wait_ack_clear(d); | |
71306303 MK |
180 | } |
181 | ||
05a2fb15 | 182 | static inline void |
159367bb | 183 | fw_domain_get(const struct intel_uncore_forcewake_domain *d) |
05a2fb15 | 184 | { |
159367bb | 185 | fw_set(d, FORCEWAKE_KERNEL); |
05a2fb15 | 186 | } |
907b28c5 | 187 | |
05a2fb15 | 188 | static inline void |
535d8d27 | 189 | fw_domain_wait_ack_set(const struct intel_uncore_forcewake_domain *d) |
05a2fb15 | 190 | { |
18ecc6c5 | 191 | if (wait_ack_set(d, FORCEWAKE_KERNEL)) { |
05a2fb15 MK |
192 | DRM_ERROR("%s: timed out waiting for forcewake ack request.\n", |
193 | intel_uncore_forcewake_domain_to_str(d->id)); | |
18ecc6c5 CW |
194 | add_taint_for_CI(TAINT_WARN); /* CI now unreliable */ |
195 | } | |
05a2fb15 | 196 | } |
907b28c5 | 197 | |
71306303 | 198 | static inline void |
535d8d27 | 199 | fw_domain_wait_ack_set_fallback(const struct intel_uncore_forcewake_domain *d) |
71306303 | 200 | { |
535d8d27 | 201 | if (likely(!wait_ack_set(d, FORCEWAKE_KERNEL))) |
71306303 MK |
202 | return; |
203 | ||
535d8d27 DCS |
204 | if (fw_domain_wait_ack_with_fallback(d, ACK_SET)) |
205 | fw_domain_wait_ack_set(d); | |
71306303 MK |
206 | } |
207 | ||
05a2fb15 | 208 | static inline void |
159367bb | 209 | fw_domain_put(const struct intel_uncore_forcewake_domain *d) |
05a2fb15 | 210 | { |
159367bb | 211 | fw_clear(d, FORCEWAKE_KERNEL); |
907b28c5 CW |
212 | } |
213 | ||
05a2fb15 | 214 | static void |
f568eeee | 215 | fw_domains_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains) |
907b28c5 | 216 | { |
05a2fb15 | 217 | struct intel_uncore_forcewake_domain *d; |
d2dc94bc | 218 | unsigned int tmp; |
907b28c5 | 219 | |
535d8d27 | 220 | GEM_BUG_ON(fw_domains & ~uncore->fw_domains); |
d2dc94bc | 221 | |
f568eeee | 222 | for_each_fw_domain_masked(d, fw_domains, uncore, tmp) { |
535d8d27 | 223 | fw_domain_wait_ack_clear(d); |
159367bb | 224 | fw_domain_get(d); |
05a2fb15 | 225 | } |
4e1176dd | 226 | |
f568eeee | 227 | for_each_fw_domain_masked(d, fw_domains, uncore, tmp) |
535d8d27 | 228 | fw_domain_wait_ack_set(d); |
71306303 | 229 | |
535d8d27 | 230 | uncore->fw_domains_active |= fw_domains; |
71306303 MK |
231 | } |
232 | ||
233 | static void | |
f568eeee | 234 | fw_domains_get_with_fallback(struct intel_uncore *uncore, |
71306303 MK |
235 | enum forcewake_domains fw_domains) |
236 | { | |
237 | struct intel_uncore_forcewake_domain *d; | |
238 | unsigned int tmp; | |
239 | ||
535d8d27 | 240 | GEM_BUG_ON(fw_domains & ~uncore->fw_domains); |
71306303 | 241 | |
f568eeee | 242 | for_each_fw_domain_masked(d, fw_domains, uncore, tmp) { |
535d8d27 | 243 | fw_domain_wait_ack_clear_fallback(d); |
159367bb | 244 | fw_domain_get(d); |
71306303 MK |
245 | } |
246 | ||
f568eeee | 247 | for_each_fw_domain_masked(d, fw_domains, uncore, tmp) |
535d8d27 | 248 | fw_domain_wait_ack_set_fallback(d); |
b8473050 | 249 | |
535d8d27 | 250 | uncore->fw_domains_active |= fw_domains; |
05a2fb15 | 251 | } |
907b28c5 | 252 | |
05a2fb15 | 253 | static void |
f568eeee | 254 | fw_domains_put(struct intel_uncore *uncore, enum forcewake_domains fw_domains) |
05a2fb15 MK |
255 | { |
256 | struct intel_uncore_forcewake_domain *d; | |
d2dc94bc CW |
257 | unsigned int tmp; |
258 | ||
535d8d27 | 259 | GEM_BUG_ON(fw_domains & ~uncore->fw_domains); |
907b28c5 | 260 | |
f568eeee | 261 | for_each_fw_domain_masked(d, fw_domains, uncore, tmp) |
159367bb | 262 | fw_domain_put(d); |
b8473050 | 263 | |
535d8d27 | 264 | uncore->fw_domains_active &= ~fw_domains; |
05a2fb15 | 265 | } |
907b28c5 | 266 | |
05a2fb15 | 267 | static void |
f568eeee | 268 | fw_domains_reset(struct intel_uncore *uncore, |
577ac4bd | 269 | enum forcewake_domains fw_domains) |
05a2fb15 MK |
270 | { |
271 | struct intel_uncore_forcewake_domain *d; | |
d2dc94bc | 272 | unsigned int tmp; |
05a2fb15 | 273 | |
d2dc94bc | 274 | if (!fw_domains) |
3225b2f9 | 275 | return; |
f9b3927a | 276 | |
535d8d27 | 277 | GEM_BUG_ON(fw_domains & ~uncore->fw_domains); |
d2dc94bc | 278 | |
f568eeee | 279 | for_each_fw_domain_masked(d, fw_domains, uncore, tmp) |
159367bb | 280 | fw_domain_reset(d); |
05a2fb15 MK |
281 | } |
282 | ||
6ebc9692 | 283 | static inline u32 gt_thread_status(struct intel_uncore *uncore) |
a5b22b5e CW |
284 | { |
285 | u32 val; | |
286 | ||
6cc5ca76 | 287 | val = __raw_uncore_read32(uncore, GEN6_GT_THREAD_STATUS_REG); |
a5b22b5e CW |
288 | val &= GEN6_GT_THREAD_STATUS_CORE_MASK; |
289 | ||
290 | return val; | |
291 | } | |
292 | ||
6ebc9692 | 293 | static void __gen6_gt_wait_for_thread_c0(struct intel_uncore *uncore) |
05a2fb15 | 294 | { |
a5b22b5e CW |
295 | /* |
296 | * w/a for a sporadic read returning 0 by waiting for the GT | |
05a2fb15 MK |
297 | * thread to wake up. |
298 | */ | |
6ebc9692 | 299 | WARN_ONCE(wait_for_atomic_us(gt_thread_status(uncore) == 0, 5000), |
a5b22b5e | 300 | "GT thread status wait timed out\n"); |
05a2fb15 MK |
301 | } |
302 | ||
f568eeee | 303 | static void fw_domains_get_with_thread_status(struct intel_uncore *uncore, |
48c1026a | 304 | enum forcewake_domains fw_domains) |
05a2fb15 | 305 | { |
f568eeee | 306 | fw_domains_get(uncore, fw_domains); |
907b28c5 | 307 | |
05a2fb15 | 308 | /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */ |
6ebc9692 | 309 | __gen6_gt_wait_for_thread_c0(uncore); |
907b28c5 CW |
310 | } |
311 | ||
6ebc9692 | 312 | static inline u32 fifo_free_entries(struct intel_uncore *uncore) |
c32e3788 | 313 | { |
6cc5ca76 | 314 | u32 count = __raw_uncore_read32(uncore, GTFIFOCTL); |
c32e3788 DG |
315 | |
316 | return count & GT_FIFO_FREE_ENTRIES_MASK; | |
317 | } | |
318 | ||
6ebc9692 | 319 | static void __gen6_gt_wait_for_fifo(struct intel_uncore *uncore) |
907b28c5 | 320 | { |
6b07b6d2 | 321 | u32 n; |
907b28c5 | 322 | |
5135d64b D |
323 | /* On VLV, FIFO will be shared by both SW and HW. |
324 | * So, we need to read the FREE_ENTRIES everytime */ | |
01385758 | 325 | if (IS_VALLEYVIEW(uncore->i915)) |
6ebc9692 | 326 | n = fifo_free_entries(uncore); |
6b07b6d2 | 327 | else |
272c7e52 | 328 | n = uncore->fifo_count; |
6b07b6d2 MK |
329 | |
330 | if (n <= GT_FIFO_NUM_RESERVED_ENTRIES) { | |
6ebc9692 | 331 | if (wait_for_atomic((n = fifo_free_entries(uncore)) > |
6b07b6d2 MK |
332 | GT_FIFO_NUM_RESERVED_ENTRIES, |
333 | GT_FIFO_TIMEOUT_MS)) { | |
334 | DRM_DEBUG("GT_FIFO timeout, entries: %u\n", n); | |
335 | return; | |
907b28c5 | 336 | } |
907b28c5 | 337 | } |
907b28c5 | 338 | |
272c7e52 | 339 | uncore->fifo_count = n - 1; |
907b28c5 CW |
340 | } |
341 | ||
a57a4a67 TU |
342 | static enum hrtimer_restart |
343 | intel_uncore_fw_release_timer(struct hrtimer *timer) | |
38cff0b1 | 344 | { |
a57a4a67 TU |
345 | struct intel_uncore_forcewake_domain *domain = |
346 | container_of(timer, struct intel_uncore_forcewake_domain, timer); | |
f833cdb0 | 347 | struct intel_uncore *uncore = domain->uncore; |
b2cff0db | 348 | unsigned long irqflags; |
38cff0b1 | 349 | |
eb17af67 | 350 | assert_rpm_device_not_suspended(uncore->rpm); |
38cff0b1 | 351 | |
c9e0c6da CW |
352 | if (xchg(&domain->active, false)) |
353 | return HRTIMER_RESTART; | |
354 | ||
f568eeee | 355 | spin_lock_irqsave(&uncore->lock, irqflags); |
b2cff0db CW |
356 | if (WARN_ON(domain->wake_count == 0)) |
357 | domain->wake_count++; | |
358 | ||
b8473050 | 359 | if (--domain->wake_count == 0) |
f568eeee | 360 | uncore->funcs.force_wake_put(uncore, domain->mask); |
b2cff0db | 361 | |
f568eeee | 362 | spin_unlock_irqrestore(&uncore->lock, irqflags); |
a57a4a67 TU |
363 | |
364 | return HRTIMER_NORESTART; | |
38cff0b1 ZW |
365 | } |
366 | ||
a5266db4 | 367 | /* Note callers must have acquired the PUNIT->PMIC bus, before calling this. */ |
d60996ab | 368 | static unsigned int |
f568eeee | 369 | intel_uncore_forcewake_reset(struct intel_uncore *uncore) |
38cff0b1 | 370 | { |
48c1026a | 371 | unsigned long irqflags; |
b2cff0db | 372 | struct intel_uncore_forcewake_domain *domain; |
48c1026a | 373 | int retry_count = 100; |
003342a5 | 374 | enum forcewake_domains fw, active_domains; |
38cff0b1 | 375 | |
a5266db4 HG |
376 | iosf_mbi_assert_punit_acquired(); |
377 | ||
b2cff0db CW |
378 | /* Hold uncore.lock across reset to prevent any register access |
379 | * with forcewake not set correctly. Wait until all pending | |
380 | * timers are run before holding. | |
381 | */ | |
382 | while (1) { | |
d2dc94bc CW |
383 | unsigned int tmp; |
384 | ||
b2cff0db | 385 | active_domains = 0; |
38cff0b1 | 386 | |
f568eeee | 387 | for_each_fw_domain(domain, uncore, tmp) { |
c9e0c6da | 388 | smp_store_mb(domain->active, false); |
a57a4a67 | 389 | if (hrtimer_cancel(&domain->timer) == 0) |
b2cff0db | 390 | continue; |
38cff0b1 | 391 | |
a57a4a67 | 392 | intel_uncore_fw_release_timer(&domain->timer); |
b2cff0db | 393 | } |
aec347ab | 394 | |
f568eeee | 395 | spin_lock_irqsave(&uncore->lock, irqflags); |
b2ec142c | 396 | |
f568eeee | 397 | for_each_fw_domain(domain, uncore, tmp) { |
a57a4a67 | 398 | if (hrtimer_active(&domain->timer)) |
33c582c1 | 399 | active_domains |= domain->mask; |
b2cff0db | 400 | } |
3123fcaf | 401 | |
b2cff0db CW |
402 | if (active_domains == 0) |
403 | break; | |
aec347ab | 404 | |
b2cff0db CW |
405 | if (--retry_count == 0) { |
406 | DRM_ERROR("Timed out waiting for forcewake timers to finish\n"); | |
407 | break; | |
408 | } | |
0294ae7b | 409 | |
f568eeee | 410 | spin_unlock_irqrestore(&uncore->lock, irqflags); |
b2cff0db CW |
411 | cond_resched(); |
412 | } | |
0294ae7b | 413 | |
b2cff0db CW |
414 | WARN_ON(active_domains); |
415 | ||
f568eeee | 416 | fw = uncore->fw_domains_active; |
b2cff0db | 417 | if (fw) |
f568eeee | 418 | uncore->funcs.force_wake_put(uncore, fw); |
ef46e0d2 | 419 | |
f568eeee DCS |
420 | fw_domains_reset(uncore, uncore->fw_domains); |
421 | assert_forcewakes_inactive(uncore); | |
b2cff0db | 422 | |
f568eeee | 423 | spin_unlock_irqrestore(&uncore->lock, irqflags); |
d60996ab CW |
424 | |
425 | return fw; /* track the lost user forcewake domains */ | |
ef46e0d2 DV |
426 | } |
427 | ||
8a47eb19 | 428 | static bool |
6ebc9692 | 429 | fpga_check_for_unclaimed_mmio(struct intel_uncore *uncore) |
8a47eb19 MK |
430 | { |
431 | u32 dbg; | |
432 | ||
6cc5ca76 | 433 | dbg = __raw_uncore_read32(uncore, FPGA_DBG); |
8a47eb19 MK |
434 | if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM))) |
435 | return false; | |
436 | ||
6cc5ca76 | 437 | __raw_uncore_write32(uncore, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
8a47eb19 MK |
438 | |
439 | return true; | |
440 | } | |
441 | ||
8ac3e1bb | 442 | static bool |
6ebc9692 | 443 | vlv_check_for_unclaimed_mmio(struct intel_uncore *uncore) |
8ac3e1bb MK |
444 | { |
445 | u32 cer; | |
446 | ||
6cc5ca76 | 447 | cer = __raw_uncore_read32(uncore, CLAIM_ER); |
8ac3e1bb MK |
448 | if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK)))) |
449 | return false; | |
450 | ||
6cc5ca76 | 451 | __raw_uncore_write32(uncore, CLAIM_ER, CLAIM_ER_CLR); |
8ac3e1bb MK |
452 | |
453 | return true; | |
454 | } | |
455 | ||
a338908c | 456 | static bool |
6ebc9692 | 457 | gen6_check_for_fifo_debug(struct intel_uncore *uncore) |
a338908c MK |
458 | { |
459 | u32 fifodbg; | |
460 | ||
6cc5ca76 | 461 | fifodbg = __raw_uncore_read32(uncore, GTFIFODBG); |
a338908c MK |
462 | |
463 | if (unlikely(fifodbg)) { | |
464 | DRM_DEBUG_DRIVER("GTFIFODBG = 0x08%x\n", fifodbg); | |
6cc5ca76 | 465 | __raw_uncore_write32(uncore, GTFIFODBG, fifodbg); |
a338908c MK |
466 | } |
467 | ||
468 | return fifodbg; | |
469 | } | |
470 | ||
8ac3e1bb | 471 | static bool |
2cf7bf6f | 472 | check_for_unclaimed_mmio(struct intel_uncore *uncore) |
8ac3e1bb | 473 | { |
a338908c MK |
474 | bool ret = false; |
475 | ||
2cf7bf6f | 476 | if (intel_uncore_has_fpga_dbg_unclaimed(uncore)) |
6ebc9692 | 477 | ret |= fpga_check_for_unclaimed_mmio(uncore); |
8ac3e1bb | 478 | |
2cf7bf6f | 479 | if (intel_uncore_has_dbg_unclaimed(uncore)) |
6ebc9692 | 480 | ret |= vlv_check_for_unclaimed_mmio(uncore); |
a338908c | 481 | |
2cf7bf6f | 482 | if (intel_uncore_has_fifo(uncore)) |
6ebc9692 | 483 | ret |= gen6_check_for_fifo_debug(uncore); |
8ac3e1bb | 484 | |
a338908c | 485 | return ret; |
8ac3e1bb MK |
486 | } |
487 | ||
2e81bc61 DCS |
488 | static void forcewake_early_sanitize(struct intel_uncore *uncore, |
489 | unsigned int restore_forcewake) | |
f9b3927a | 490 | { |
2e81bc61 | 491 | GEM_BUG_ON(!intel_uncore_has_forcewake(uncore)); |
907b28c5 | 492 | |
a04f90a3 | 493 | /* WaDisableShadowRegForCpd:chv */ |
01385758 | 494 | if (IS_CHERRYVIEW(uncore->i915)) { |
6cc5ca76 DCS |
495 | __raw_uncore_write32(uncore, GTFIFOCTL, |
496 | __raw_uncore_read32(uncore, GTFIFOCTL) | | |
497 | GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL | | |
498 | GT_FIFO_CTL_RC6_POLICY_STALL); | |
a04f90a3 D |
499 | } |
500 | ||
a5266db4 | 501 | iosf_mbi_punit_acquire(); |
f7de5027 | 502 | intel_uncore_forcewake_reset(uncore); |
d60996ab | 503 | if (restore_forcewake) { |
f7de5027 DCS |
504 | spin_lock_irq(&uncore->lock); |
505 | uncore->funcs.force_wake_get(uncore, restore_forcewake); | |
506 | ||
2cf7bf6f | 507 | if (intel_uncore_has_fifo(uncore)) |
6ebc9692 | 508 | uncore->fifo_count = fifo_free_entries(uncore); |
f7de5027 | 509 | spin_unlock_irq(&uncore->lock); |
d60996ab | 510 | } |
a5266db4 | 511 | iosf_mbi_punit_release(); |
521198a2 MK |
512 | } |
513 | ||
f7de5027 | 514 | void intel_uncore_suspend(struct intel_uncore *uncore) |
ed493883 | 515 | { |
2e81bc61 DCS |
516 | if (!intel_uncore_has_forcewake(uncore)) |
517 | return; | |
518 | ||
a5266db4 HG |
519 | iosf_mbi_punit_acquire(); |
520 | iosf_mbi_unregister_pmic_bus_access_notifier_unlocked( | |
f7de5027 DCS |
521 | &uncore->pmic_bus_access_nb); |
522 | uncore->fw_domains_saved = intel_uncore_forcewake_reset(uncore); | |
a5266db4 | 523 | iosf_mbi_punit_release(); |
68f60946 HG |
524 | } |
525 | ||
f7de5027 | 526 | void intel_uncore_resume_early(struct intel_uncore *uncore) |
68f60946 | 527 | { |
d60996ab CW |
528 | unsigned int restore_forcewake; |
529 | ||
2e81bc61 DCS |
530 | if (intel_uncore_unclaimed_mmio(uncore)) |
531 | DRM_DEBUG("unclaimed mmio detected on resume, clearing\n"); | |
532 | ||
533 | if (!intel_uncore_has_forcewake(uncore)) | |
534 | return; | |
535 | ||
f7de5027 | 536 | restore_forcewake = fetch_and_zero(&uncore->fw_domains_saved); |
2e81bc61 | 537 | forcewake_early_sanitize(uncore, restore_forcewake); |
d60996ab | 538 | |
f7de5027 | 539 | iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb); |
ed493883 ID |
540 | } |
541 | ||
f7de5027 | 542 | void intel_uncore_runtime_resume(struct intel_uncore *uncore) |
bedf4d79 | 543 | { |
2e81bc61 DCS |
544 | if (!intel_uncore_has_forcewake(uncore)) |
545 | return; | |
546 | ||
f7de5027 | 547 | iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb); |
bedf4d79 HG |
548 | } |
549 | ||
f568eeee | 550 | static void __intel_uncore_forcewake_get(struct intel_uncore *uncore, |
a6111f7b CW |
551 | enum forcewake_domains fw_domains) |
552 | { | |
553 | struct intel_uncore_forcewake_domain *domain; | |
d2dc94bc | 554 | unsigned int tmp; |
a6111f7b | 555 | |
f568eeee | 556 | fw_domains &= uncore->fw_domains; |
a6111f7b | 557 | |
f568eeee | 558 | for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) { |
c9e0c6da | 559 | if (domain->wake_count++) { |
33c582c1 | 560 | fw_domains &= ~domain->mask; |
c9e0c6da CW |
561 | domain->active = true; |
562 | } | |
563 | } | |
a6111f7b | 564 | |
b8473050 | 565 | if (fw_domains) |
f568eeee | 566 | uncore->funcs.force_wake_get(uncore, fw_domains); |
a6111f7b CW |
567 | } |
568 | ||
59bad947 MK |
569 | /** |
570 | * intel_uncore_forcewake_get - grab forcewake domain references | |
3ceea6a1 | 571 | * @uncore: the intel_uncore structure |
59bad947 MK |
572 | * @fw_domains: forcewake domains to get reference on |
573 | * | |
574 | * This function can be used get GT's forcewake domain references. | |
575 | * Normal register access will handle the forcewake domains automatically. | |
576 | * However if some sequence requires the GT to not power down a particular | |
577 | * forcewake domains this function should be called at the beginning of the | |
578 | * sequence. And subsequently the reference should be dropped by symmetric | |
579 | * call to intel_unforce_forcewake_put(). Usually caller wants all the domains | |
580 | * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL. | |
907b28c5 | 581 | */ |
3ceea6a1 | 582 | void intel_uncore_forcewake_get(struct intel_uncore *uncore, |
48c1026a | 583 | enum forcewake_domains fw_domains) |
907b28c5 CW |
584 | { |
585 | unsigned long irqflags; | |
586 | ||
f568eeee | 587 | if (!uncore->funcs.force_wake_get) |
ab484f8f BW |
588 | return; |
589 | ||
87b391b9 | 590 | assert_rpm_wakelock_held(uncore->rpm); |
c8c8fb33 | 591 | |
f568eeee DCS |
592 | spin_lock_irqsave(&uncore->lock, irqflags); |
593 | __intel_uncore_forcewake_get(uncore, fw_domains); | |
594 | spin_unlock_irqrestore(&uncore->lock, irqflags); | |
907b28c5 CW |
595 | } |
596 | ||
d7a133d8 CW |
597 | /** |
598 | * intel_uncore_forcewake_user_get - claim forcewake on behalf of userspace | |
3ceea6a1 | 599 | * @uncore: the intel_uncore structure |
d7a133d8 CW |
600 | * |
601 | * This function is a wrapper around intel_uncore_forcewake_get() to acquire | |
602 | * the GT powerwell and in the process disable our debugging for the | |
603 | * duration of userspace's bypass. | |
604 | */ | |
3ceea6a1 | 605 | void intel_uncore_forcewake_user_get(struct intel_uncore *uncore) |
d7a133d8 | 606 | { |
f568eeee DCS |
607 | spin_lock_irq(&uncore->lock); |
608 | if (!uncore->user_forcewake.count++) { | |
3ceea6a1 | 609 | intel_uncore_forcewake_get__locked(uncore, FORCEWAKE_ALL); |
d7a133d8 CW |
610 | |
611 | /* Save and disable mmio debugging for the user bypass */ | |
f568eeee DCS |
612 | uncore->user_forcewake.saved_mmio_check = |
613 | uncore->unclaimed_mmio_check; | |
614 | uncore->user_forcewake.saved_mmio_debug = | |
4f044a88 | 615 | i915_modparams.mmio_debug; |
d7a133d8 | 616 | |
f568eeee | 617 | uncore->unclaimed_mmio_check = 0; |
4f044a88 | 618 | i915_modparams.mmio_debug = 0; |
d7a133d8 | 619 | } |
f568eeee | 620 | spin_unlock_irq(&uncore->lock); |
d7a133d8 CW |
621 | } |
622 | ||
623 | /** | |
624 | * intel_uncore_forcewake_user_put - release forcewake on behalf of userspace | |
3ceea6a1 | 625 | * @uncore: the intel_uncore structure |
d7a133d8 CW |
626 | * |
627 | * This function complements intel_uncore_forcewake_user_get() and releases | |
628 | * the GT powerwell taken on behalf of the userspace bypass. | |
629 | */ | |
3ceea6a1 | 630 | void intel_uncore_forcewake_user_put(struct intel_uncore *uncore) |
d7a133d8 | 631 | { |
f568eeee DCS |
632 | spin_lock_irq(&uncore->lock); |
633 | if (!--uncore->user_forcewake.count) { | |
2cf7bf6f | 634 | if (intel_uncore_unclaimed_mmio(uncore)) |
01385758 | 635 | dev_info(uncore->i915->drm.dev, |
d7a133d8 CW |
636 | "Invalid mmio detected during user access\n"); |
637 | ||
f568eeee DCS |
638 | uncore->unclaimed_mmio_check = |
639 | uncore->user_forcewake.saved_mmio_check; | |
4f044a88 | 640 | i915_modparams.mmio_debug = |
f568eeee | 641 | uncore->user_forcewake.saved_mmio_debug; |
d7a133d8 | 642 | |
3ceea6a1 | 643 | intel_uncore_forcewake_put__locked(uncore, FORCEWAKE_ALL); |
d7a133d8 | 644 | } |
f568eeee | 645 | spin_unlock_irq(&uncore->lock); |
d7a133d8 CW |
646 | } |
647 | ||
59bad947 | 648 | /** |
a6111f7b | 649 | * intel_uncore_forcewake_get__locked - grab forcewake domain references |
3ceea6a1 | 650 | * @uncore: the intel_uncore structure |
a6111f7b | 651 | * @fw_domains: forcewake domains to get reference on |
59bad947 | 652 | * |
a6111f7b CW |
653 | * See intel_uncore_forcewake_get(). This variant places the onus |
654 | * on the caller to explicitly handle the dev_priv->uncore.lock spinlock. | |
907b28c5 | 655 | */ |
3ceea6a1 | 656 | void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore, |
a6111f7b CW |
657 | enum forcewake_domains fw_domains) |
658 | { | |
f568eeee DCS |
659 | lockdep_assert_held(&uncore->lock); |
660 | ||
661 | if (!uncore->funcs.force_wake_get) | |
a6111f7b CW |
662 | return; |
663 | ||
f568eeee | 664 | __intel_uncore_forcewake_get(uncore, fw_domains); |
a6111f7b CW |
665 | } |
666 | ||
f568eeee | 667 | static void __intel_uncore_forcewake_put(struct intel_uncore *uncore, |
a6111f7b | 668 | enum forcewake_domains fw_domains) |
907b28c5 | 669 | { |
b2cff0db | 670 | struct intel_uncore_forcewake_domain *domain; |
d2dc94bc | 671 | unsigned int tmp; |
907b28c5 | 672 | |
f568eeee | 673 | fw_domains &= uncore->fw_domains; |
b2cff0db | 674 | |
f568eeee | 675 | for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) { |
b2cff0db CW |
676 | if (WARN_ON(domain->wake_count == 0)) |
677 | continue; | |
678 | ||
c9e0c6da CW |
679 | if (--domain->wake_count) { |
680 | domain->active = true; | |
b2cff0db | 681 | continue; |
c9e0c6da | 682 | } |
b2cff0db | 683 | |
05a2fb15 | 684 | fw_domain_arm_timer(domain); |
aec347ab | 685 | } |
a6111f7b | 686 | } |
dc9fb09c | 687 | |
a6111f7b CW |
688 | /** |
689 | * intel_uncore_forcewake_put - release a forcewake domain reference | |
3ceea6a1 | 690 | * @uncore: the intel_uncore structure |
a6111f7b CW |
691 | * @fw_domains: forcewake domains to put references |
692 | * | |
693 | * This function drops the device-level forcewakes for specified | |
694 | * domains obtained by intel_uncore_forcewake_get(). | |
695 | */ | |
3ceea6a1 | 696 | void intel_uncore_forcewake_put(struct intel_uncore *uncore, |
a6111f7b CW |
697 | enum forcewake_domains fw_domains) |
698 | { | |
699 | unsigned long irqflags; | |
700 | ||
f568eeee | 701 | if (!uncore->funcs.force_wake_put) |
a6111f7b CW |
702 | return; |
703 | ||
f568eeee DCS |
704 | spin_lock_irqsave(&uncore->lock, irqflags); |
705 | __intel_uncore_forcewake_put(uncore, fw_domains); | |
706 | spin_unlock_irqrestore(&uncore->lock, irqflags); | |
907b28c5 CW |
707 | } |
708 | ||
a6111f7b CW |
709 | /** |
710 | * intel_uncore_forcewake_put__locked - grab forcewake domain references | |
3ceea6a1 | 711 | * @uncore: the intel_uncore structure |
a6111f7b CW |
712 | * @fw_domains: forcewake domains to get reference on |
713 | * | |
714 | * See intel_uncore_forcewake_put(). This variant places the onus | |
715 | * on the caller to explicitly handle the dev_priv->uncore.lock spinlock. | |
716 | */ | |
3ceea6a1 | 717 | void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore, |
a6111f7b CW |
718 | enum forcewake_domains fw_domains) |
719 | { | |
f568eeee DCS |
720 | lockdep_assert_held(&uncore->lock); |
721 | ||
722 | if (!uncore->funcs.force_wake_put) | |
a6111f7b CW |
723 | return; |
724 | ||
f568eeee | 725 | __intel_uncore_forcewake_put(uncore, fw_domains); |
a6111f7b CW |
726 | } |
727 | ||
f568eeee | 728 | void assert_forcewakes_inactive(struct intel_uncore *uncore) |
e998c40f | 729 | { |
f568eeee | 730 | if (!uncore->funcs.force_wake_get) |
e998c40f PZ |
731 | return; |
732 | ||
f568eeee | 733 | WARN(uncore->fw_domains_active, |
67e64564 | 734 | "Expected all fw_domains to be inactive, but %08x are still on\n", |
f568eeee | 735 | uncore->fw_domains_active); |
67e64564 CW |
736 | } |
737 | ||
f568eeee | 738 | void assert_forcewakes_active(struct intel_uncore *uncore, |
67e64564 CW |
739 | enum forcewake_domains fw_domains) |
740 | { | |
b7dc9395 CW |
741 | struct intel_uncore_forcewake_domain *domain; |
742 | unsigned int tmp; | |
743 | ||
744 | if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) | |
745 | return; | |
746 | ||
f568eeee | 747 | if (!uncore->funcs.force_wake_get) |
67e64564 CW |
748 | return; |
749 | ||
87b391b9 | 750 | assert_rpm_wakelock_held(uncore->rpm); |
67e64564 | 751 | |
f568eeee DCS |
752 | fw_domains &= uncore->fw_domains; |
753 | WARN(fw_domains & ~uncore->fw_domains_active, | |
67e64564 | 754 | "Expected %08x fw_domains to be active, but %08x are off\n", |
f568eeee | 755 | fw_domains, fw_domains & ~uncore->fw_domains_active); |
b7dc9395 CW |
756 | |
757 | /* | |
758 | * Check that the caller has an explicit wakeref and we don't mistake | |
759 | * it for the auto wakeref. | |
760 | */ | |
761 | local_irq_disable(); | |
762 | for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) { | |
763 | unsigned int expect = 1; | |
764 | ||
765 | if (hrtimer_active(&domain->timer) && READ_ONCE(domain->active)) | |
766 | expect++; /* pending automatic release */ | |
767 | ||
768 | if (WARN(domain->wake_count < expect, | |
769 | "Expected domain %d to be held awake by caller, count=%d\n", | |
770 | domain->id, domain->wake_count)) | |
771 | break; | |
772 | } | |
773 | local_irq_enable(); | |
e998c40f PZ |
774 | } |
775 | ||
907b28c5 | 776 | /* We give fast paths for the really cool registers */ |
40181697 | 777 | #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000) |
907b28c5 | 778 | |
a89a70a8 DCS |
779 | #define GEN11_NEEDS_FORCE_WAKE(reg) \ |
780 | ((reg) < 0x40000 || ((reg) >= 0x1c0000 && (reg) < 0x1dc000)) | |
781 | ||
272c7e52 | 782 | #define __gen6_reg_read_fw_domains(uncore, offset) \ |
6863b76c TU |
783 | ({ \ |
784 | enum forcewake_domains __fwd; \ | |
785 | if (NEEDS_FORCE_WAKE(offset)) \ | |
786 | __fwd = FORCEWAKE_RENDER; \ | |
787 | else \ | |
788 | __fwd = 0; \ | |
789 | __fwd; \ | |
790 | }) | |
791 | ||
9480dbf0 | 792 | static int fw_range_cmp(u32 offset, const struct intel_forcewake_range *entry) |
91e630b9 | 793 | { |
91e630b9 TU |
794 | if (offset < entry->start) |
795 | return -1; | |
796 | else if (offset > entry->end) | |
797 | return 1; | |
798 | else | |
799 | return 0; | |
800 | } | |
801 | ||
9480dbf0 TU |
802 | /* Copied and "macroized" from lib/bsearch.c */ |
803 | #define BSEARCH(key, base, num, cmp) ({ \ | |
804 | unsigned int start__ = 0, end__ = (num); \ | |
805 | typeof(base) result__ = NULL; \ | |
806 | while (start__ < end__) { \ | |
807 | unsigned int mid__ = start__ + (end__ - start__) / 2; \ | |
808 | int ret__ = (cmp)((key), (base) + mid__); \ | |
809 | if (ret__ < 0) { \ | |
810 | end__ = mid__; \ | |
811 | } else if (ret__ > 0) { \ | |
812 | start__ = mid__ + 1; \ | |
813 | } else { \ | |
814 | result__ = (base) + mid__; \ | |
815 | break; \ | |
816 | } \ | |
817 | } \ | |
818 | result__; \ | |
819 | }) | |
820 | ||
9fc1117c | 821 | static enum forcewake_domains |
cb7ee690 | 822 | find_fw_domain(struct intel_uncore *uncore, u32 offset) |
9fc1117c | 823 | { |
9480dbf0 | 824 | const struct intel_forcewake_range *entry; |
9fc1117c | 825 | |
9480dbf0 | 826 | entry = BSEARCH(offset, |
cb7ee690 DCS |
827 | uncore->fw_domains_table, |
828 | uncore->fw_domains_table_entries, | |
91e630b9 | 829 | fw_range_cmp); |
38fb6a40 | 830 | |
99191427 JL |
831 | if (!entry) |
832 | return 0; | |
833 | ||
a89a70a8 DCS |
834 | /* |
835 | * The list of FW domains depends on the SKU in gen11+ so we | |
836 | * can't determine it statically. We use FORCEWAKE_ALL and | |
837 | * translate it here to the list of available domains. | |
838 | */ | |
839 | if (entry->domains == FORCEWAKE_ALL) | |
cb7ee690 | 840 | return uncore->fw_domains; |
a89a70a8 | 841 | |
cb7ee690 | 842 | WARN(entry->domains & ~uncore->fw_domains, |
99191427 | 843 | "Uninitialized forcewake domain(s) 0x%x accessed at 0x%x\n", |
cb7ee690 | 844 | entry->domains & ~uncore->fw_domains, offset); |
99191427 JL |
845 | |
846 | return entry->domains; | |
9fc1117c TU |
847 | } |
848 | ||
849 | #define GEN_FW_RANGE(s, e, d) \ | |
850 | { .start = (s), .end = (e), .domains = (d) } | |
1938e59a | 851 | |
895833bd | 852 | #define HAS_FWTABLE(dev_priv) \ |
3d16ca58 | 853 | (INTEL_GEN(dev_priv) >= 9 || \ |
895833bd TU |
854 | IS_CHERRYVIEW(dev_priv) || \ |
855 | IS_VALLEYVIEW(dev_priv)) | |
856 | ||
b0081239 | 857 | /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */ |
9fc1117c TU |
858 | static const struct intel_forcewake_range __vlv_fw_ranges[] = { |
859 | GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER), | |
860 | GEN_FW_RANGE(0x5000, 0x7fff, FORCEWAKE_RENDER), | |
861 | GEN_FW_RANGE(0xb000, 0x11fff, FORCEWAKE_RENDER), | |
9fc1117c TU |
862 | GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA), |
863 | GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_MEDIA), | |
b0081239 | 864 | GEN_FW_RANGE(0x2e000, 0x2ffff, FORCEWAKE_RENDER), |
9fc1117c TU |
865 | GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA), |
866 | }; | |
1938e59a | 867 | |
272c7e52 | 868 | #define __fwtable_reg_read_fw_domains(uncore, offset) \ |
6863b76c TU |
869 | ({ \ |
870 | enum forcewake_domains __fwd = 0; \ | |
0dd356bb | 871 | if (NEEDS_FORCE_WAKE((offset))) \ |
272c7e52 | 872 | __fwd = find_fw_domain(uncore, offset); \ |
6863b76c TU |
873 | __fwd; \ |
874 | }) | |
875 | ||
272c7e52 | 876 | #define __gen11_fwtable_reg_read_fw_domains(uncore, offset) \ |
a89a70a8 DCS |
877 | ({ \ |
878 | enum forcewake_domains __fwd = 0; \ | |
879 | if (GEN11_NEEDS_FORCE_WAKE((offset))) \ | |
272c7e52 | 880 | __fwd = find_fw_domain(uncore, offset); \ |
a89a70a8 DCS |
881 | __fwd; \ |
882 | }) | |
883 | ||
47188574 | 884 | /* *Must* be sorted by offset! See intel_shadow_table_check(). */ |
6863b76c | 885 | static const i915_reg_t gen8_shadowed_regs[] = { |
47188574 TU |
886 | RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */ |
887 | GEN6_RPNSWREQ, /* 0xA008 */ | |
888 | GEN6_RC_VIDEO_FREQ, /* 0xA00C */ | |
889 | RING_TAIL(GEN6_BSD_RING_BASE), /* 0x12000 (base) */ | |
890 | RING_TAIL(VEBOX_RING_BASE), /* 0x1a000 (base) */ | |
891 | RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */ | |
6863b76c TU |
892 | /* TODO: Other registers are not yet used */ |
893 | }; | |
894 | ||
a89a70a8 DCS |
895 | static const i915_reg_t gen11_shadowed_regs[] = { |
896 | RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */ | |
897 | GEN6_RPNSWREQ, /* 0xA008 */ | |
898 | GEN6_RC_VIDEO_FREQ, /* 0xA00C */ | |
899 | RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */ | |
900 | RING_TAIL(GEN11_BSD_RING_BASE), /* 0x1C0000 (base) */ | |
901 | RING_TAIL(GEN11_BSD2_RING_BASE), /* 0x1C4000 (base) */ | |
902 | RING_TAIL(GEN11_VEBOX_RING_BASE), /* 0x1C8000 (base) */ | |
903 | RING_TAIL(GEN11_BSD3_RING_BASE), /* 0x1D0000 (base) */ | |
904 | RING_TAIL(GEN11_BSD4_RING_BASE), /* 0x1D4000 (base) */ | |
905 | RING_TAIL(GEN11_VEBOX2_RING_BASE), /* 0x1D8000 (base) */ | |
906 | /* TODO: Other registers are not yet used */ | |
907 | }; | |
908 | ||
9480dbf0 | 909 | static int mmio_reg_cmp(u32 key, const i915_reg_t *reg) |
5a659383 | 910 | { |
9480dbf0 | 911 | u32 offset = i915_mmio_reg_offset(*reg); |
5a659383 | 912 | |
9480dbf0 | 913 | if (key < offset) |
5a659383 | 914 | return -1; |
9480dbf0 | 915 | else if (key > offset) |
5a659383 TU |
916 | return 1; |
917 | else | |
918 | return 0; | |
919 | } | |
920 | ||
a89a70a8 DCS |
921 | #define __is_genX_shadowed(x) \ |
922 | static bool is_gen##x##_shadowed(u32 offset) \ | |
923 | { \ | |
924 | const i915_reg_t *regs = gen##x##_shadowed_regs; \ | |
925 | return BSEARCH(offset, regs, ARRAY_SIZE(gen##x##_shadowed_regs), \ | |
926 | mmio_reg_cmp); \ | |
6863b76c TU |
927 | } |
928 | ||
a89a70a8 DCS |
929 | __is_genX_shadowed(8) |
930 | __is_genX_shadowed(11) | |
931 | ||
ccb2acea DCS |
932 | static enum forcewake_domains |
933 | gen6_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) | |
934 | { | |
935 | return FORCEWAKE_RENDER; | |
936 | } | |
937 | ||
272c7e52 | 938 | #define __gen8_reg_write_fw_domains(uncore, offset) \ |
6863b76c TU |
939 | ({ \ |
940 | enum forcewake_domains __fwd; \ | |
941 | if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(offset)) \ | |
942 | __fwd = FORCEWAKE_RENDER; \ | |
943 | else \ | |
944 | __fwd = 0; \ | |
945 | __fwd; \ | |
946 | }) | |
947 | ||
b0081239 | 948 | /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */ |
9fc1117c TU |
949 | static const struct intel_forcewake_range __chv_fw_ranges[] = { |
950 | GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER), | |
b0081239 | 951 | GEN_FW_RANGE(0x4000, 0x4fff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), |
9fc1117c | 952 | GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), |
b0081239 | 953 | GEN_FW_RANGE(0x8000, 0x82ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), |
9fc1117c | 954 | GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), |
b0081239 | 955 | GEN_FW_RANGE(0x8500, 0x85ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), |
9fc1117c | 956 | GEN_FW_RANGE(0x8800, 0x88ff, FORCEWAKE_MEDIA), |
b0081239 TU |
957 | GEN_FW_RANGE(0x9000, 0xafff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), |
958 | GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER), | |
9fc1117c | 959 | GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA), |
b0081239 TU |
960 | GEN_FW_RANGE(0xe000, 0xe7ff, FORCEWAKE_RENDER), |
961 | GEN_FW_RANGE(0xf000, 0xffff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), | |
9fc1117c TU |
962 | GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA), |
963 | GEN_FW_RANGE(0x1a000, 0x1bfff, FORCEWAKE_MEDIA), | |
964 | GEN_FW_RANGE(0x1e800, 0x1e9ff, FORCEWAKE_MEDIA), | |
965 | GEN_FW_RANGE(0x30000, 0x37fff, FORCEWAKE_MEDIA), | |
9fc1117c | 966 | }; |
38fb6a40 | 967 | |
272c7e52 | 968 | #define __fwtable_reg_write_fw_domains(uncore, offset) \ |
6863b76c TU |
969 | ({ \ |
970 | enum forcewake_domains __fwd = 0; \ | |
0dd356bb | 971 | if (NEEDS_FORCE_WAKE((offset)) && !is_gen8_shadowed(offset)) \ |
272c7e52 | 972 | __fwd = find_fw_domain(uncore, offset); \ |
6863b76c TU |
973 | __fwd; \ |
974 | }) | |
975 | ||
272c7e52 | 976 | #define __gen11_fwtable_reg_write_fw_domains(uncore, offset) \ |
a89a70a8 DCS |
977 | ({ \ |
978 | enum forcewake_domains __fwd = 0; \ | |
979 | if (GEN11_NEEDS_FORCE_WAKE((offset)) && !is_gen11_shadowed(offset)) \ | |
272c7e52 | 980 | __fwd = find_fw_domain(uncore, offset); \ |
a89a70a8 DCS |
981 | __fwd; \ |
982 | }) | |
983 | ||
b0081239 | 984 | /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */ |
9fc1117c | 985 | static const struct intel_forcewake_range __gen9_fw_ranges[] = { |
0dd356bb | 986 | GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER), |
9fc1117c TU |
987 | GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */ |
988 | GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), | |
0dd356bb | 989 | GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER), |
9fc1117c | 990 | GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER), |
0dd356bb | 991 | GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER), |
9fc1117c | 992 | GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), |
0dd356bb | 993 | GEN_FW_RANGE(0x8000, 0x812f, FORCEWAKE_BLITTER), |
b0081239 | 994 | GEN_FW_RANGE(0x8130, 0x813f, FORCEWAKE_MEDIA), |
9fc1117c | 995 | GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER), |
0dd356bb | 996 | GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER), |
9fc1117c | 997 | GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), |
0dd356bb | 998 | GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_BLITTER), |
b0081239 | 999 | GEN_FW_RANGE(0x8800, 0x89ff, FORCEWAKE_MEDIA), |
0dd356bb | 1000 | GEN_FW_RANGE(0x8a00, 0x8bff, FORCEWAKE_BLITTER), |
9fc1117c | 1001 | GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER), |
0dd356bb | 1002 | GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER), |
9fc1117c | 1003 | GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), |
0dd356bb | 1004 | GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER), |
b0081239 | 1005 | GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER), |
78424c92 | 1006 | GEN_FW_RANGE(0xb480, 0xcfff, FORCEWAKE_BLITTER), |
9fc1117c | 1007 | GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA), |
0dd356bb | 1008 | GEN_FW_RANGE(0xd800, 0xdfff, FORCEWAKE_BLITTER), |
b0081239 | 1009 | GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER), |
0dd356bb | 1010 | GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_BLITTER), |
9fc1117c | 1011 | GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA), |
0dd356bb | 1012 | GEN_FW_RANGE(0x14000, 0x19fff, FORCEWAKE_BLITTER), |
9fc1117c | 1013 | GEN_FW_RANGE(0x1a000, 0x1e9ff, FORCEWAKE_MEDIA), |
0dd356bb | 1014 | GEN_FW_RANGE(0x1ea00, 0x243ff, FORCEWAKE_BLITTER), |
b0081239 | 1015 | GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER), |
0dd356bb | 1016 | GEN_FW_RANGE(0x24800, 0x2ffff, FORCEWAKE_BLITTER), |
9fc1117c TU |
1017 | GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA), |
1018 | }; | |
6863b76c | 1019 | |
a89a70a8 DCS |
1020 | /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */ |
1021 | static const struct intel_forcewake_range __gen11_fw_ranges[] = { | |
1022 | GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER), | |
1023 | GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */ | |
1024 | GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), | |
1025 | GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER), | |
1026 | GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER), | |
1027 | GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER), | |
1028 | GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), | |
1029 | GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_BLITTER), | |
1030 | GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER), | |
1031 | GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER), | |
1032 | GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), | |
1033 | GEN_FW_RANGE(0x8500, 0x8bff, FORCEWAKE_BLITTER), | |
1034 | GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER), | |
1035 | GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER), | |
1036 | GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_ALL), | |
1037 | GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER), | |
1038 | GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER), | |
1039 | GEN_FW_RANGE(0xb480, 0xdfff, FORCEWAKE_BLITTER), | |
1040 | GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER), | |
1041 | GEN_FW_RANGE(0xe900, 0x243ff, FORCEWAKE_BLITTER), | |
1042 | GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER), | |
1043 | GEN_FW_RANGE(0x24800, 0x3ffff, FORCEWAKE_BLITTER), | |
1044 | GEN_FW_RANGE(0x40000, 0x1bffff, 0), | |
1045 | GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), | |
1046 | GEN_FW_RANGE(0x1c4000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX1), | |
1047 | GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0), | |
1048 | GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_BLITTER), | |
1049 | GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2), | |
1050 | GEN_FW_RANGE(0x1d4000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX3), | |
1051 | GEN_FW_RANGE(0x1d8000, 0x1dbfff, FORCEWAKE_MEDIA_VEBOX1) | |
1052 | }; | |
1053 | ||
907b28c5 | 1054 | static void |
6ebc9692 | 1055 | ilk_dummy_write(struct intel_uncore *uncore) |
907b28c5 CW |
1056 | { |
1057 | /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up | |
1058 | * the chip from rc6 before touching it for real. MI_MODE is masked, | |
1059 | * hence harmless to write 0 into. */ | |
6cc5ca76 | 1060 | __raw_uncore_write32(uncore, MI_MODE, 0); |
907b28c5 CW |
1061 | } |
1062 | ||
1063 | static void | |
2cf7bf6f | 1064 | __unclaimed_reg_debug(struct intel_uncore *uncore, |
9c053501 MK |
1065 | const i915_reg_t reg, |
1066 | const bool read, | |
1067 | const bool before) | |
907b28c5 | 1068 | { |
2cf7bf6f | 1069 | if (WARN(check_for_unclaimed_mmio(uncore) && !before, |
dda96033 CW |
1070 | "Unclaimed %s register 0x%x\n", |
1071 | read ? "read from" : "write to", | |
4bd0a25d | 1072 | i915_mmio_reg_offset(reg))) |
4f044a88 MW |
1073 | /* Only report the first N failures */ |
1074 | i915_modparams.mmio_debug--; | |
907b28c5 CW |
1075 | } |
1076 | ||
9c053501 | 1077 | static inline void |
2cf7bf6f | 1078 | unclaimed_reg_debug(struct intel_uncore *uncore, |
9c053501 MK |
1079 | const i915_reg_t reg, |
1080 | const bool read, | |
1081 | const bool before) | |
1082 | { | |
4f044a88 | 1083 | if (likely(!i915_modparams.mmio_debug)) |
9c053501 MK |
1084 | return; |
1085 | ||
2cf7bf6f | 1086 | __unclaimed_reg_debug(uncore, reg, read, before); |
9c053501 MK |
1087 | } |
1088 | ||
51f67885 | 1089 | #define GEN2_READ_HEADER(x) \ |
5d738795 | 1090 | u##x val = 0; \ |
87b391b9 | 1091 | assert_rpm_wakelock_held(uncore->rpm); |
5d738795 | 1092 | |
51f67885 | 1093 | #define GEN2_READ_FOOTER \ |
5d738795 BW |
1094 | trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ |
1095 | return val | |
1096 | ||
51f67885 | 1097 | #define __gen2_read(x) \ |
0b274481 | 1098 | static u##x \ |
a2b4abfc | 1099 | gen2_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \ |
51f67885 | 1100 | GEN2_READ_HEADER(x); \ |
6cc5ca76 | 1101 | val = __raw_uncore_read##x(uncore, reg); \ |
51f67885 | 1102 | GEN2_READ_FOOTER; \ |
3967018e BW |
1103 | } |
1104 | ||
1105 | #define __gen5_read(x) \ | |
1106 | static u##x \ | |
a2b4abfc | 1107 | gen5_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \ |
51f67885 | 1108 | GEN2_READ_HEADER(x); \ |
6ebc9692 | 1109 | ilk_dummy_write(uncore); \ |
6cc5ca76 | 1110 | val = __raw_uncore_read##x(uncore, reg); \ |
51f67885 | 1111 | GEN2_READ_FOOTER; \ |
3967018e BW |
1112 | } |
1113 | ||
51f67885 CW |
1114 | __gen5_read(8) |
1115 | __gen5_read(16) | |
1116 | __gen5_read(32) | |
1117 | __gen5_read(64) | |
1118 | __gen2_read(8) | |
1119 | __gen2_read(16) | |
1120 | __gen2_read(32) | |
1121 | __gen2_read(64) | |
1122 | ||
1123 | #undef __gen5_read | |
1124 | #undef __gen2_read | |
1125 | ||
1126 | #undef GEN2_READ_FOOTER | |
1127 | #undef GEN2_READ_HEADER | |
1128 | ||
1129 | #define GEN6_READ_HEADER(x) \ | |
f0f59a00 | 1130 | u32 offset = i915_mmio_reg_offset(reg); \ |
51f67885 CW |
1131 | unsigned long irqflags; \ |
1132 | u##x val = 0; \ | |
87b391b9 | 1133 | assert_rpm_wakelock_held(uncore->rpm); \ |
272c7e52 | 1134 | spin_lock_irqsave(&uncore->lock, irqflags); \ |
2cf7bf6f | 1135 | unclaimed_reg_debug(uncore, reg, true, true) |
51f67885 CW |
1136 | |
1137 | #define GEN6_READ_FOOTER \ | |
2cf7bf6f | 1138 | unclaimed_reg_debug(uncore, reg, true, false); \ |
272c7e52 | 1139 | spin_unlock_irqrestore(&uncore->lock, irqflags); \ |
51f67885 CW |
1140 | trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ |
1141 | return val | |
1142 | ||
f568eeee | 1143 | static noinline void ___force_wake_auto(struct intel_uncore *uncore, |
c521b0c8 | 1144 | enum forcewake_domains fw_domains) |
b2cff0db CW |
1145 | { |
1146 | struct intel_uncore_forcewake_domain *domain; | |
d2dc94bc CW |
1147 | unsigned int tmp; |
1148 | ||
f568eeee | 1149 | GEM_BUG_ON(fw_domains & ~uncore->fw_domains); |
b2cff0db | 1150 | |
f568eeee | 1151 | for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) |
c521b0c8 TU |
1152 | fw_domain_arm_timer(domain); |
1153 | ||
f568eeee | 1154 | uncore->funcs.force_wake_get(uncore, fw_domains); |
c521b0c8 TU |
1155 | } |
1156 | ||
f568eeee | 1157 | static inline void __force_wake_auto(struct intel_uncore *uncore, |
c521b0c8 TU |
1158 | enum forcewake_domains fw_domains) |
1159 | { | |
b2cff0db CW |
1160 | if (WARN_ON(!fw_domains)) |
1161 | return; | |
1162 | ||
003342a5 | 1163 | /* Turn on all requested but inactive supported forcewake domains. */ |
f568eeee DCS |
1164 | fw_domains &= uncore->fw_domains; |
1165 | fw_domains &= ~uncore->fw_domains_active; | |
b2cff0db | 1166 | |
c521b0c8 | 1167 | if (fw_domains) |
f568eeee | 1168 | ___force_wake_auto(uncore, fw_domains); |
b2cff0db CW |
1169 | } |
1170 | ||
ccfceda2 | 1171 | #define __gen_read(func, x) \ |
3967018e | 1172 | static u##x \ |
a2b4abfc | 1173 | func##_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \ |
6863b76c | 1174 | enum forcewake_domains fw_engine; \ |
51f67885 | 1175 | GEN6_READ_HEADER(x); \ |
272c7e52 | 1176 | fw_engine = __##func##_reg_read_fw_domains(uncore, offset); \ |
6a42d0f4 | 1177 | if (fw_engine) \ |
272c7e52 | 1178 | __force_wake_auto(uncore, fw_engine); \ |
6cc5ca76 | 1179 | val = __raw_uncore_read##x(uncore, reg); \ |
51f67885 | 1180 | GEN6_READ_FOOTER; \ |
940aece4 | 1181 | } |
ccb2acea DCS |
1182 | |
1183 | #define __gen_reg_read_funcs(func) \ | |
1184 | static enum forcewake_domains \ | |
1185 | func##_reg_read_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) { \ | |
1186 | return __##func##_reg_read_fw_domains(uncore, i915_mmio_reg_offset(reg)); \ | |
1187 | } \ | |
1188 | \ | |
1189 | __gen_read(func, 8) \ | |
1190 | __gen_read(func, 16) \ | |
1191 | __gen_read(func, 32) \ | |
1192 | __gen_read(func, 64) | |
1193 | ||
1194 | __gen_reg_read_funcs(gen11_fwtable); | |
1195 | __gen_reg_read_funcs(fwtable); | |
1196 | __gen_reg_read_funcs(gen6); | |
1197 | ||
1198 | #undef __gen_reg_read_funcs | |
51f67885 CW |
1199 | #undef GEN6_READ_FOOTER |
1200 | #undef GEN6_READ_HEADER | |
5d738795 | 1201 | |
51f67885 | 1202 | #define GEN2_WRITE_HEADER \ |
5d738795 | 1203 | trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ |
87b391b9 | 1204 | assert_rpm_wakelock_held(uncore->rpm); \ |
907b28c5 | 1205 | |
51f67885 | 1206 | #define GEN2_WRITE_FOOTER |
0d965301 | 1207 | |
51f67885 | 1208 | #define __gen2_write(x) \ |
0b274481 | 1209 | static void \ |
a2b4abfc | 1210 | gen2_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ |
51f67885 | 1211 | GEN2_WRITE_HEADER; \ |
6cc5ca76 | 1212 | __raw_uncore_write##x(uncore, reg, val); \ |
51f67885 | 1213 | GEN2_WRITE_FOOTER; \ |
4032ef43 BW |
1214 | } |
1215 | ||
1216 | #define __gen5_write(x) \ | |
1217 | static void \ | |
a2b4abfc | 1218 | gen5_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ |
51f67885 | 1219 | GEN2_WRITE_HEADER; \ |
6ebc9692 | 1220 | ilk_dummy_write(uncore); \ |
6cc5ca76 | 1221 | __raw_uncore_write##x(uncore, reg, val); \ |
51f67885 | 1222 | GEN2_WRITE_FOOTER; \ |
4032ef43 BW |
1223 | } |
1224 | ||
51f67885 CW |
1225 | __gen5_write(8) |
1226 | __gen5_write(16) | |
1227 | __gen5_write(32) | |
51f67885 CW |
1228 | __gen2_write(8) |
1229 | __gen2_write(16) | |
1230 | __gen2_write(32) | |
51f67885 CW |
1231 | |
1232 | #undef __gen5_write | |
1233 | #undef __gen2_write | |
1234 | ||
1235 | #undef GEN2_WRITE_FOOTER | |
1236 | #undef GEN2_WRITE_HEADER | |
1237 | ||
1238 | #define GEN6_WRITE_HEADER \ | |
f0f59a00 | 1239 | u32 offset = i915_mmio_reg_offset(reg); \ |
51f67885 CW |
1240 | unsigned long irqflags; \ |
1241 | trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ | |
87b391b9 | 1242 | assert_rpm_wakelock_held(uncore->rpm); \ |
272c7e52 | 1243 | spin_lock_irqsave(&uncore->lock, irqflags); \ |
2cf7bf6f | 1244 | unclaimed_reg_debug(uncore, reg, false, true) |
51f67885 CW |
1245 | |
1246 | #define GEN6_WRITE_FOOTER \ | |
2cf7bf6f | 1247 | unclaimed_reg_debug(uncore, reg, false, false); \ |
272c7e52 | 1248 | spin_unlock_irqrestore(&uncore->lock, irqflags) |
51f67885 | 1249 | |
4032ef43 BW |
1250 | #define __gen6_write(x) \ |
1251 | static void \ | |
a2b4abfc | 1252 | gen6_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ |
51f67885 | 1253 | GEN6_WRITE_HEADER; \ |
a338908c | 1254 | if (NEEDS_FORCE_WAKE(offset)) \ |
6ebc9692 | 1255 | __gen6_gt_wait_for_fifo(uncore); \ |
6cc5ca76 | 1256 | __raw_uncore_write##x(uncore, reg, val); \ |
51f67885 | 1257 | GEN6_WRITE_FOOTER; \ |
4032ef43 | 1258 | } |
ccb2acea DCS |
1259 | __gen6_write(8) |
1260 | __gen6_write(16) | |
1261 | __gen6_write(32) | |
4032ef43 | 1262 | |
ccfceda2 | 1263 | #define __gen_write(func, x) \ |
ab2aa47e | 1264 | static void \ |
a2b4abfc | 1265 | func##_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ |
6863b76c | 1266 | enum forcewake_domains fw_engine; \ |
51f67885 | 1267 | GEN6_WRITE_HEADER; \ |
272c7e52 | 1268 | fw_engine = __##func##_reg_write_fw_domains(uncore, offset); \ |
6a42d0f4 | 1269 | if (fw_engine) \ |
272c7e52 | 1270 | __force_wake_auto(uncore, fw_engine); \ |
6cc5ca76 | 1271 | __raw_uncore_write##x(uncore, reg, val); \ |
51f67885 | 1272 | GEN6_WRITE_FOOTER; \ |
1938e59a | 1273 | } |
4032ef43 | 1274 | |
ccb2acea DCS |
1275 | #define __gen_reg_write_funcs(func) \ |
1276 | static enum forcewake_domains \ | |
1277 | func##_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) { \ | |
1278 | return __##func##_reg_write_fw_domains(uncore, i915_mmio_reg_offset(reg)); \ | |
1279 | } \ | |
1280 | \ | |
1281 | __gen_write(func, 8) \ | |
1282 | __gen_write(func, 16) \ | |
1283 | __gen_write(func, 32) | |
1284 | ||
1285 | __gen_reg_write_funcs(gen11_fwtable); | |
1286 | __gen_reg_write_funcs(fwtable); | |
1287 | __gen_reg_write_funcs(gen8); | |
1288 | ||
1289 | #undef __gen_reg_write_funcs | |
51f67885 CW |
1290 | #undef GEN6_WRITE_FOOTER |
1291 | #undef GEN6_WRITE_HEADER | |
907b28c5 | 1292 | |
ccb2acea | 1293 | #define ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, x) \ |
43d942a7 | 1294 | do { \ |
f7de5027 DCS |
1295 | (uncore)->funcs.mmio_writeb = x##_write8; \ |
1296 | (uncore)->funcs.mmio_writew = x##_write16; \ | |
1297 | (uncore)->funcs.mmio_writel = x##_write32; \ | |
43d942a7 YZ |
1298 | } while (0) |
1299 | ||
ccb2acea | 1300 | #define ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, x) \ |
43d942a7 | 1301 | do { \ |
f7de5027 DCS |
1302 | (uncore)->funcs.mmio_readb = x##_read8; \ |
1303 | (uncore)->funcs.mmio_readw = x##_read16; \ | |
1304 | (uncore)->funcs.mmio_readl = x##_read32; \ | |
1305 | (uncore)->funcs.mmio_readq = x##_read64; \ | |
43d942a7 YZ |
1306 | } while (0) |
1307 | ||
ccb2acea DCS |
1308 | #define ASSIGN_WRITE_MMIO_VFUNCS(uncore, x) \ |
1309 | do { \ | |
1310 | ASSIGN_RAW_WRITE_MMIO_VFUNCS((uncore), x); \ | |
1311 | (uncore)->funcs.write_fw_domains = x##_reg_write_fw_domains; \ | |
1312 | } while (0) | |
1313 | ||
1314 | #define ASSIGN_READ_MMIO_VFUNCS(uncore, x) \ | |
1315 | do { \ | |
1316 | ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, x); \ | |
1317 | (uncore)->funcs.read_fw_domains = x##_reg_read_fw_domains; \ | |
1318 | } while (0) | |
05a2fb15 | 1319 | |
f833cdb0 DCS |
1320 | static int __fw_domain_init(struct intel_uncore *uncore, |
1321 | enum forcewake_domain_id domain_id, | |
1322 | i915_reg_t reg_set, | |
1323 | i915_reg_t reg_ack) | |
05a2fb15 MK |
1324 | { |
1325 | struct intel_uncore_forcewake_domain *d; | |
1326 | ||
f833cdb0 DCS |
1327 | GEM_BUG_ON(domain_id >= FW_DOMAIN_ID_COUNT); |
1328 | GEM_BUG_ON(uncore->fw_domain[domain_id]); | |
05a2fb15 | 1329 | |
f833cdb0 DCS |
1330 | if (i915_inject_load_failure()) |
1331 | return -ENOMEM; | |
05a2fb15 | 1332 | |
f833cdb0 DCS |
1333 | d = kzalloc(sizeof(*d), GFP_KERNEL); |
1334 | if (!d) | |
1335 | return -ENOMEM; | |
05a2fb15 | 1336 | |
6e3955a5 CW |
1337 | WARN_ON(!i915_mmio_reg_valid(reg_set)); |
1338 | WARN_ON(!i915_mmio_reg_valid(reg_ack)); | |
1339 | ||
f833cdb0 | 1340 | d->uncore = uncore; |
05a2fb15 | 1341 | d->wake_count = 0; |
25286aac DCS |
1342 | d->reg_set = uncore->regs + i915_mmio_reg_offset(reg_set); |
1343 | d->reg_ack = uncore->regs + i915_mmio_reg_offset(reg_ack); | |
05a2fb15 | 1344 | |
05a2fb15 MK |
1345 | d->id = domain_id; |
1346 | ||
33c582c1 TU |
1347 | BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER)); |
1348 | BUILD_BUG_ON(FORCEWAKE_BLITTER != (1 << FW_DOMAIN_ID_BLITTER)); | |
1349 | BUILD_BUG_ON(FORCEWAKE_MEDIA != (1 << FW_DOMAIN_ID_MEDIA)); | |
a89a70a8 DCS |
1350 | BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX0)); |
1351 | BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX1)); | |
1352 | BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX2 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX2)); | |
1353 | BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX3 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX3)); | |
1354 | BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX0)); | |
1355 | BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX1)); | |
1356 | ||
d2dc94bc | 1357 | d->mask = BIT(domain_id); |
33c582c1 | 1358 | |
a57a4a67 TU |
1359 | hrtimer_init(&d->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); |
1360 | d->timer.function = intel_uncore_fw_release_timer; | |
05a2fb15 | 1361 | |
535d8d27 | 1362 | uncore->fw_domains |= BIT(domain_id); |
f9b3927a | 1363 | |
159367bb | 1364 | fw_domain_reset(d); |
f833cdb0 DCS |
1365 | |
1366 | uncore->fw_domain[domain_id] = d; | |
1367 | ||
1368 | return 0; | |
05a2fb15 MK |
1369 | } |
1370 | ||
f7de5027 | 1371 | static void fw_domain_fini(struct intel_uncore *uncore, |
26376a7e OM |
1372 | enum forcewake_domain_id domain_id) |
1373 | { | |
1374 | struct intel_uncore_forcewake_domain *d; | |
1375 | ||
f833cdb0 | 1376 | GEM_BUG_ON(domain_id >= FW_DOMAIN_ID_COUNT); |
26376a7e | 1377 | |
f833cdb0 DCS |
1378 | d = fetch_and_zero(&uncore->fw_domain[domain_id]); |
1379 | if (!d) | |
1380 | return; | |
26376a7e | 1381 | |
f833cdb0 | 1382 | uncore->fw_domains &= ~BIT(domain_id); |
26376a7e OM |
1383 | WARN_ON(d->wake_count); |
1384 | WARN_ON(hrtimer_cancel(&d->timer)); | |
f833cdb0 DCS |
1385 | kfree(d); |
1386 | } | |
26376a7e | 1387 | |
f833cdb0 DCS |
1388 | static void intel_uncore_fw_domains_fini(struct intel_uncore *uncore) |
1389 | { | |
1390 | struct intel_uncore_forcewake_domain *d; | |
1391 | int tmp; | |
1392 | ||
1393 | for_each_fw_domain(d, uncore, tmp) | |
1394 | fw_domain_fini(uncore, d->id); | |
26376a7e OM |
1395 | } |
1396 | ||
f833cdb0 | 1397 | static int intel_uncore_fw_domains_init(struct intel_uncore *uncore) |
0b274481 | 1398 | { |
01385758 | 1399 | struct drm_i915_private *i915 = uncore->i915; |
f833cdb0 | 1400 | int ret = 0; |
f7de5027 | 1401 | |
2e81bc61 | 1402 | GEM_BUG_ON(!intel_uncore_has_forcewake(uncore)); |
3225b2f9 | 1403 | |
f833cdb0 DCS |
1404 | #define fw_domain_init(uncore__, id__, set__, ack__) \ |
1405 | (ret ?: (ret = __fw_domain_init((uncore__), (id__), (set__), (ack__)))) | |
1406 | ||
f7de5027 | 1407 | if (INTEL_GEN(i915) >= 11) { |
a89a70a8 DCS |
1408 | int i; |
1409 | ||
f833cdb0 | 1410 | uncore->funcs.force_wake_get = fw_domains_get_with_fallback; |
f7de5027 DCS |
1411 | uncore->funcs.force_wake_put = fw_domains_put; |
1412 | fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, | |
a89a70a8 DCS |
1413 | FORCEWAKE_RENDER_GEN9, |
1414 | FORCEWAKE_ACK_RENDER_GEN9); | |
f7de5027 | 1415 | fw_domain_init(uncore, FW_DOMAIN_ID_BLITTER, |
a89a70a8 DCS |
1416 | FORCEWAKE_BLITTER_GEN9, |
1417 | FORCEWAKE_ACK_BLITTER_GEN9); | |
f833cdb0 | 1418 | |
a89a70a8 | 1419 | for (i = 0; i < I915_MAX_VCS; i++) { |
f7de5027 | 1420 | if (!HAS_ENGINE(i915, _VCS(i))) |
a89a70a8 DCS |
1421 | continue; |
1422 | ||
f7de5027 | 1423 | fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VDBOX0 + i, |
a89a70a8 DCS |
1424 | FORCEWAKE_MEDIA_VDBOX_GEN11(i), |
1425 | FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(i)); | |
1426 | } | |
1427 | for (i = 0; i < I915_MAX_VECS; i++) { | |
f7de5027 | 1428 | if (!HAS_ENGINE(i915, _VECS(i))) |
a89a70a8 DCS |
1429 | continue; |
1430 | ||
f7de5027 | 1431 | fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VEBOX0 + i, |
a89a70a8 DCS |
1432 | FORCEWAKE_MEDIA_VEBOX_GEN11(i), |
1433 | FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i)); | |
1434 | } | |
f7de5027 | 1435 | } else if (IS_GEN_RANGE(i915, 9, 10)) { |
f833cdb0 | 1436 | uncore->funcs.force_wake_get = fw_domains_get_with_fallback; |
f7de5027 DCS |
1437 | uncore->funcs.force_wake_put = fw_domains_put; |
1438 | fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, | |
05a2fb15 MK |
1439 | FORCEWAKE_RENDER_GEN9, |
1440 | FORCEWAKE_ACK_RENDER_GEN9); | |
f7de5027 | 1441 | fw_domain_init(uncore, FW_DOMAIN_ID_BLITTER, |
05a2fb15 MK |
1442 | FORCEWAKE_BLITTER_GEN9, |
1443 | FORCEWAKE_ACK_BLITTER_GEN9); | |
f7de5027 | 1444 | fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA, |
05a2fb15 | 1445 | FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9); |
f7de5027 DCS |
1446 | } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { |
1447 | uncore->funcs.force_wake_get = fw_domains_get; | |
1448 | uncore->funcs.force_wake_put = fw_domains_put; | |
1449 | fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, | |
05a2fb15 | 1450 | FORCEWAKE_VLV, FORCEWAKE_ACK_VLV); |
f7de5027 | 1451 | fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA, |
05a2fb15 | 1452 | FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV); |
f7de5027 DCS |
1453 | } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { |
1454 | uncore->funcs.force_wake_get = | |
05a2fb15 | 1455 | fw_domains_get_with_thread_status; |
f7de5027 DCS |
1456 | uncore->funcs.force_wake_put = fw_domains_put; |
1457 | fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, | |
05a2fb15 | 1458 | FORCEWAKE_MT, FORCEWAKE_ACK_HSW); |
f7de5027 | 1459 | } else if (IS_IVYBRIDGE(i915)) { |
0b274481 BW |
1460 | u32 ecobus; |
1461 | ||
1462 | /* IVB configs may use multi-threaded forcewake */ | |
1463 | ||
1464 | /* A small trick here - if the bios hasn't configured | |
1465 | * MT forcewake, and if the device is in RC6, then | |
1466 | * force_wake_mt_get will not wake the device and the | |
1467 | * ECOBUS read will return zero. Which will be | |
1468 | * (correctly) interpreted by the test below as MT | |
1469 | * forcewake being disabled. | |
1470 | */ | |
f7de5027 | 1471 | uncore->funcs.force_wake_get = |
05a2fb15 | 1472 | fw_domains_get_with_thread_status; |
f7de5027 | 1473 | uncore->funcs.force_wake_put = fw_domains_put; |
05a2fb15 | 1474 | |
f9b3927a MK |
1475 | /* We need to init first for ECOBUS access and then |
1476 | * determine later if we want to reinit, in case of MT access is | |
6ea2556f MK |
1477 | * not working. In this stage we don't know which flavour this |
1478 | * ivb is, so it is better to reset also the gen6 fw registers | |
1479 | * before the ecobus check. | |
f9b3927a | 1480 | */ |
6ea2556f | 1481 | |
6cc5ca76 | 1482 | __raw_uncore_write32(uncore, FORCEWAKE, 0); |
6ebc9692 | 1483 | __raw_posting_read(uncore, ECOBUS); |
6ea2556f | 1484 | |
f833cdb0 DCS |
1485 | ret = __fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, |
1486 | FORCEWAKE_MT, FORCEWAKE_MT_ACK); | |
1487 | if (ret) | |
1488 | goto out; | |
f9b3927a | 1489 | |
f7de5027 DCS |
1490 | spin_lock_irq(&uncore->lock); |
1491 | fw_domains_get_with_thread_status(uncore, FORCEWAKE_RENDER); | |
6cc5ca76 | 1492 | ecobus = __raw_uncore_read32(uncore, ECOBUS); |
f7de5027 DCS |
1493 | fw_domains_put(uncore, FORCEWAKE_RENDER); |
1494 | spin_unlock_irq(&uncore->lock); | |
0b274481 | 1495 | |
05a2fb15 | 1496 | if (!(ecobus & FORCEWAKE_MT_ENABLE)) { |
0b274481 BW |
1497 | DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n"); |
1498 | DRM_INFO("when using vblank-synced partial screen updates.\n"); | |
f833cdb0 | 1499 | fw_domain_fini(uncore, FW_DOMAIN_ID_RENDER); |
f7de5027 | 1500 | fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, |
05a2fb15 | 1501 | FORCEWAKE, FORCEWAKE_ACK); |
0b274481 | 1502 | } |
f7de5027 DCS |
1503 | } else if (IS_GEN(i915, 6)) { |
1504 | uncore->funcs.force_wake_get = | |
05a2fb15 | 1505 | fw_domains_get_with_thread_status; |
f7de5027 DCS |
1506 | uncore->funcs.force_wake_put = fw_domains_put; |
1507 | fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, | |
05a2fb15 | 1508 | FORCEWAKE, FORCEWAKE_ACK); |
0b274481 | 1509 | } |
3225b2f9 | 1510 | |
f833cdb0 DCS |
1511 | #undef fw_domain_init |
1512 | ||
3225b2f9 | 1513 | /* All future platforms are expected to require complex power gating */ |
f833cdb0 DCS |
1514 | WARN_ON(!ret && uncore->fw_domains == 0); |
1515 | ||
1516 | out: | |
1517 | if (ret) | |
1518 | intel_uncore_fw_domains_fini(uncore); | |
1519 | ||
1520 | return ret; | |
f9b3927a MK |
1521 | } |
1522 | ||
f7de5027 | 1523 | #define ASSIGN_FW_DOMAINS_TABLE(uncore, d) \ |
15157970 | 1524 | { \ |
f7de5027 | 1525 | (uncore)->fw_domains_table = \ |
15157970 | 1526 | (struct intel_forcewake_range *)(d); \ |
f7de5027 | 1527 | (uncore)->fw_domains_table_entries = ARRAY_SIZE((d)); \ |
15157970 TU |
1528 | } |
1529 | ||
264ec1a8 HG |
1530 | static int i915_pmic_bus_access_notifier(struct notifier_block *nb, |
1531 | unsigned long action, void *data) | |
1532 | { | |
9102650f DCS |
1533 | struct intel_uncore *uncore = container_of(nb, |
1534 | struct intel_uncore, pmic_bus_access_nb); | |
264ec1a8 HG |
1535 | |
1536 | switch (action) { | |
1537 | case MBI_PMIC_BUS_ACCESS_BEGIN: | |
1538 | /* | |
1539 | * forcewake all now to make sure that we don't need to do a | |
1540 | * forcewake later which on systems where this notifier gets | |
1541 | * called requires the punit to access to the shared pmic i2c | |
1542 | * bus, which will be busy after this notification, leading to: | |
1543 | * "render: timed out waiting for forcewake ack request." | |
1544 | * errors. | |
ce30560c HG |
1545 | * |
1546 | * The notifier is unregistered during intel_runtime_suspend(), | |
1547 | * so it's ok to access the HW here without holding a RPM | |
1548 | * wake reference -> disable wakeref asserts for the time of | |
1549 | * the access. | |
264ec1a8 | 1550 | */ |
9102650f DCS |
1551 | disable_rpm_wakeref_asserts(uncore->rpm); |
1552 | intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); | |
1553 | enable_rpm_wakeref_asserts(uncore->rpm); | |
264ec1a8 HG |
1554 | break; |
1555 | case MBI_PMIC_BUS_ACCESS_END: | |
9102650f | 1556 | intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); |
264ec1a8 HG |
1557 | break; |
1558 | } | |
1559 | ||
1560 | return NOTIFY_OK; | |
1561 | } | |
1562 | ||
25286aac DCS |
1563 | static int uncore_mmio_setup(struct intel_uncore *uncore) |
1564 | { | |
01385758 | 1565 | struct drm_i915_private *i915 = uncore->i915; |
25286aac DCS |
1566 | struct pci_dev *pdev = i915->drm.pdev; |
1567 | int mmio_bar; | |
1568 | int mmio_size; | |
1569 | ||
1570 | mmio_bar = IS_GEN(i915, 2) ? 1 : 0; | |
1571 | /* | |
1572 | * Before gen4, the registers and the GTT are behind different BARs. | |
1573 | * However, from gen4 onwards, the registers and the GTT are shared | |
1574 | * in the same BAR, so we want to restrict this ioremap from | |
1575 | * clobbering the GTT which we want ioremap_wc instead. Fortunately, | |
1576 | * the register BAR remains the same size for all the earlier | |
1577 | * generations up to Ironlake. | |
1578 | */ | |
1579 | if (INTEL_GEN(i915) < 5) | |
1580 | mmio_size = 512 * 1024; | |
1581 | else | |
1582 | mmio_size = 2 * 1024 * 1024; | |
1583 | uncore->regs = pci_iomap(pdev, mmio_bar, mmio_size); | |
1584 | if (uncore->regs == NULL) { | |
1585 | DRM_ERROR("failed to map registers\n"); | |
1586 | ||
1587 | return -EIO; | |
1588 | } | |
1589 | ||
1590 | return 0; | |
1591 | } | |
1592 | ||
1593 | static void uncore_mmio_cleanup(struct intel_uncore *uncore) | |
1594 | { | |
01385758 | 1595 | struct pci_dev *pdev = uncore->i915->drm.pdev; |
25286aac DCS |
1596 | |
1597 | pci_iounmap(pdev, uncore->regs); | |
1598 | } | |
1599 | ||
01385758 DCS |
1600 | void intel_uncore_init_early(struct intel_uncore *uncore, |
1601 | struct drm_i915_private *i915) | |
6cbe8830 DCS |
1602 | { |
1603 | spin_lock_init(&uncore->lock); | |
01385758 DCS |
1604 | uncore->i915 = i915; |
1605 | uncore->rpm = &i915->runtime_pm; | |
6cbe8830 | 1606 | } |
25286aac | 1607 | |
2e81bc61 | 1608 | static void uncore_raw_init(struct intel_uncore *uncore) |
f9b3927a | 1609 | { |
2e81bc61 | 1610 | GEM_BUG_ON(intel_uncore_has_forcewake(uncore)); |
25286aac | 1611 | |
2e81bc61 DCS |
1612 | if (IS_GEN(uncore->i915, 5)) { |
1613 | ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen5); | |
1614 | ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen5); | |
1615 | } else { | |
1616 | ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen2); | |
1617 | ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen2); | |
1618 | } | |
1619 | } | |
f7de5027 | 1620 | |
f833cdb0 | 1621 | static int uncore_forcewake_init(struct intel_uncore *uncore) |
2e81bc61 DCS |
1622 | { |
1623 | struct drm_i915_private *i915 = uncore->i915; | |
f833cdb0 | 1624 | int ret; |
cf9d2890 | 1625 | |
2e81bc61 | 1626 | GEM_BUG_ON(!intel_uncore_has_forcewake(uncore)); |
5a0ba777 | 1627 | |
f833cdb0 DCS |
1628 | ret = intel_uncore_fw_domains_init(uncore); |
1629 | if (ret) | |
1630 | return ret; | |
1631 | ||
2e81bc61 | 1632 | forcewake_early_sanitize(uncore, 0); |
75714940 | 1633 | |
2e81bc61 | 1634 | if (IS_GEN_RANGE(i915, 6, 7)) { |
f7de5027 DCS |
1635 | ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6); |
1636 | ||
1637 | if (IS_VALLEYVIEW(i915)) { | |
1638 | ASSIGN_FW_DOMAINS_TABLE(uncore, __vlv_fw_ranges); | |
1639 | ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable); | |
e3b1895f | 1640 | } else { |
f7de5027 | 1641 | ASSIGN_READ_MMIO_VFUNCS(uncore, gen6); |
85ee17eb | 1642 | } |
f7de5027 DCS |
1643 | } else if (IS_GEN(i915, 8)) { |
1644 | if (IS_CHERRYVIEW(i915)) { | |
1645 | ASSIGN_FW_DOMAINS_TABLE(uncore, __chv_fw_ranges); | |
1646 | ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable); | |
1647 | ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable); | |
1938e59a | 1648 | } else { |
f7de5027 DCS |
1649 | ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen8); |
1650 | ASSIGN_READ_MMIO_VFUNCS(uncore, gen6); | |
1938e59a | 1651 | } |
f7de5027 DCS |
1652 | } else if (IS_GEN_RANGE(i915, 9, 10)) { |
1653 | ASSIGN_FW_DOMAINS_TABLE(uncore, __gen9_fw_ranges); | |
1654 | ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable); | |
1655 | ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable); | |
a89a70a8 | 1656 | } else { |
f7de5027 DCS |
1657 | ASSIGN_FW_DOMAINS_TABLE(uncore, __gen11_fw_ranges); |
1658 | ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen11_fwtable); | |
1659 | ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable); | |
3967018e | 1660 | } |
ed493883 | 1661 | |
2e81bc61 DCS |
1662 | uncore->pmic_bus_access_nb.notifier_call = i915_pmic_bus_access_notifier; |
1663 | iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb); | |
f833cdb0 DCS |
1664 | |
1665 | return 0; | |
2e81bc61 DCS |
1666 | } |
1667 | ||
1668 | int intel_uncore_init_mmio(struct intel_uncore *uncore) | |
1669 | { | |
1670 | struct drm_i915_private *i915 = uncore->i915; | |
1671 | int ret; | |
1672 | ||
1673 | ret = uncore_mmio_setup(uncore); | |
1674 | if (ret) | |
1675 | return ret; | |
1676 | ||
2e81bc61 DCS |
1677 | if (INTEL_GEN(i915) > 5 && !intel_vgpu_active(i915)) |
1678 | uncore->flags |= UNCORE_HAS_FORCEWAKE; | |
1679 | ||
1680 | uncore->unclaimed_mmio_check = 1; | |
1681 | ||
f833cdb0 | 1682 | if (!intel_uncore_has_forcewake(uncore)) { |
2e81bc61 | 1683 | uncore_raw_init(uncore); |
f833cdb0 DCS |
1684 | } else { |
1685 | ret = uncore_forcewake_init(uncore); | |
1686 | if (ret) | |
1687 | goto out_mmio_cleanup; | |
1688 | } | |
2e81bc61 | 1689 | |
ccb2acea DCS |
1690 | /* make sure fw funcs are set if and only if we have fw*/ |
1691 | GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.force_wake_get); | |
1692 | GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.force_wake_put); | |
1693 | GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.read_fw_domains); | |
1694 | GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.write_fw_domains); | |
1695 | ||
2cf7bf6f DCS |
1696 | if (HAS_FPGA_DBG_UNCLAIMED(i915)) |
1697 | uncore->flags |= UNCORE_HAS_FPGA_DBG_UNCLAIMED; | |
1698 | ||
1699 | if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) | |
1700 | uncore->flags |= UNCORE_HAS_DBG_UNCLAIMED; | |
1701 | ||
1702 | if (IS_GEN_RANGE(i915, 6, 7)) | |
1703 | uncore->flags |= UNCORE_HAS_FIFO; | |
1704 | ||
2e81bc61 DCS |
1705 | /* clear out unclaimed reg detection bit */ |
1706 | if (check_for_unclaimed_mmio(uncore)) | |
1707 | DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n"); | |
25286aac DCS |
1708 | |
1709 | return 0; | |
f833cdb0 DCS |
1710 | |
1711 | out_mmio_cleanup: | |
1712 | uncore_mmio_cleanup(uncore); | |
1713 | ||
1714 | return ret; | |
0b274481 BW |
1715 | } |
1716 | ||
26376a7e OM |
1717 | /* |
1718 | * We might have detected that some engines are fused off after we initialized | |
1719 | * the forcewake domains. Prune them, to make sure they only reference existing | |
1720 | * engines. | |
1721 | */ | |
3de6f852 | 1722 | void intel_uncore_prune_mmio_domains(struct intel_uncore *uncore) |
26376a7e | 1723 | { |
01385758 | 1724 | struct drm_i915_private *i915 = uncore->i915; |
2e81bc61 DCS |
1725 | enum forcewake_domains fw_domains = uncore->fw_domains; |
1726 | enum forcewake_domain_id domain_id; | |
1727 | int i; | |
f7de5027 | 1728 | |
2e81bc61 DCS |
1729 | if (!intel_uncore_has_forcewake(uncore) || INTEL_GEN(i915) < 11) |
1730 | return; | |
26376a7e | 1731 | |
2e81bc61 DCS |
1732 | for (i = 0; i < I915_MAX_VCS; i++) { |
1733 | domain_id = FW_DOMAIN_ID_MEDIA_VDBOX0 + i; | |
26376a7e | 1734 | |
2e81bc61 DCS |
1735 | if (HAS_ENGINE(i915, _VCS(i))) |
1736 | continue; | |
26376a7e | 1737 | |
2e81bc61 DCS |
1738 | if (fw_domains & BIT(domain_id)) |
1739 | fw_domain_fini(uncore, domain_id); | |
1740 | } | |
26376a7e | 1741 | |
2e81bc61 DCS |
1742 | for (i = 0; i < I915_MAX_VECS; i++) { |
1743 | domain_id = FW_DOMAIN_ID_MEDIA_VEBOX0 + i; | |
26376a7e | 1744 | |
2e81bc61 DCS |
1745 | if (HAS_ENGINE(i915, _VECS(i))) |
1746 | continue; | |
26376a7e | 1747 | |
2e81bc61 DCS |
1748 | if (fw_domains & BIT(domain_id)) |
1749 | fw_domain_fini(uncore, domain_id); | |
26376a7e OM |
1750 | } |
1751 | } | |
1752 | ||
3de6f852 | 1753 | void intel_uncore_fini_mmio(struct intel_uncore *uncore) |
0b274481 | 1754 | { |
2e81bc61 DCS |
1755 | if (intel_uncore_has_forcewake(uncore)) { |
1756 | iosf_mbi_punit_acquire(); | |
1757 | iosf_mbi_unregister_pmic_bus_access_notifier_unlocked( | |
1758 | &uncore->pmic_bus_access_nb); | |
1759 | intel_uncore_forcewake_reset(uncore); | |
f833cdb0 | 1760 | intel_uncore_fw_domains_fini(uncore); |
2e81bc61 DCS |
1761 | iosf_mbi_punit_release(); |
1762 | } | |
1763 | ||
25286aac | 1764 | uncore_mmio_cleanup(uncore); |
0b274481 BW |
1765 | } |
1766 | ||
3fd3a6ff JL |
1767 | static const struct reg_whitelist { |
1768 | i915_reg_t offset_ldw; | |
1769 | i915_reg_t offset_udw; | |
1770 | u16 gen_mask; | |
1771 | u8 size; | |
1772 | } reg_read_whitelist[] = { { | |
1773 | .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE), | |
1774 | .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE), | |
164daaf2 | 1775 | .gen_mask = INTEL_GEN_MASK(4, 11), |
3fd3a6ff JL |
1776 | .size = 8 |
1777 | } }; | |
907b28c5 CW |
1778 | |
1779 | int i915_reg_read_ioctl(struct drm_device *dev, | |
1780 | void *data, struct drm_file *file) | |
1781 | { | |
8ed3a623 TU |
1782 | struct drm_i915_private *i915 = to_i915(dev); |
1783 | struct intel_uncore *uncore = &i915->uncore; | |
907b28c5 | 1784 | struct drm_i915_reg_read *reg = data; |
3fd3a6ff | 1785 | struct reg_whitelist const *entry; |
538ef96b | 1786 | intel_wakeref_t wakeref; |
3fd3a6ff JL |
1787 | unsigned int flags; |
1788 | int remain; | |
1789 | int ret = 0; | |
1790 | ||
1791 | entry = reg_read_whitelist; | |
1792 | remain = ARRAY_SIZE(reg_read_whitelist); | |
1793 | while (remain) { | |
1794 | u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw); | |
1795 | ||
1796 | GEM_BUG_ON(!is_power_of_2(entry->size)); | |
1797 | GEM_BUG_ON(entry->size > 8); | |
1798 | GEM_BUG_ON(entry_offset & (entry->size - 1)); | |
1799 | ||
8ed3a623 | 1800 | if (INTEL_INFO(i915)->gen_mask & entry->gen_mask && |
3fd3a6ff | 1801 | entry_offset == (reg->offset & -entry->size)) |
907b28c5 | 1802 | break; |
3fd3a6ff JL |
1803 | entry++; |
1804 | remain--; | |
907b28c5 CW |
1805 | } |
1806 | ||
3fd3a6ff | 1807 | if (!remain) |
907b28c5 CW |
1808 | return -EINVAL; |
1809 | ||
3fd3a6ff | 1810 | flags = reg->offset & (entry->size - 1); |
648a9bc5 | 1811 | |
c447ff7d | 1812 | with_intel_runtime_pm(&i915->runtime_pm, wakeref) { |
d4225a53 | 1813 | if (entry->size == 8 && flags == I915_REG_READ_8B_WA) |
8ed3a623 TU |
1814 | reg->val = intel_uncore_read64_2x32(uncore, |
1815 | entry->offset_ldw, | |
1816 | entry->offset_udw); | |
d4225a53 | 1817 | else if (entry->size == 8 && flags == 0) |
8ed3a623 TU |
1818 | reg->val = intel_uncore_read64(uncore, |
1819 | entry->offset_ldw); | |
d4225a53 | 1820 | else if (entry->size == 4 && flags == 0) |
8ed3a623 | 1821 | reg->val = intel_uncore_read(uncore, entry->offset_ldw); |
d4225a53 | 1822 | else if (entry->size == 2 && flags == 0) |
8ed3a623 TU |
1823 | reg->val = intel_uncore_read16(uncore, |
1824 | entry->offset_ldw); | |
d4225a53 | 1825 | else if (entry->size == 1 && flags == 0) |
8ed3a623 TU |
1826 | reg->val = intel_uncore_read8(uncore, |
1827 | entry->offset_ldw); | |
d4225a53 CW |
1828 | else |
1829 | ret = -EINVAL; | |
1830 | } | |
3fd3a6ff | 1831 | |
cf67c70f | 1832 | return ret; |
907b28c5 CW |
1833 | } |
1834 | ||
1758b90e | 1835 | /** |
1d1a9774 | 1836 | * __intel_wait_for_register_fw - wait until register matches expected state |
d2d551c0 | 1837 | * @uncore: the struct intel_uncore |
1758b90e CW |
1838 | * @reg: the register to read |
1839 | * @mask: mask to apply to register value | |
1840 | * @value: expected value | |
1d1a9774 MW |
1841 | * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait |
1842 | * @slow_timeout_ms: slow timeout in millisecond | |
1843 | * @out_value: optional placeholder to hold registry value | |
1758b90e CW |
1844 | * |
1845 | * This routine waits until the target register @reg contains the expected | |
3d466cd6 DV |
1846 | * @value after applying the @mask, i.e. it waits until :: |
1847 | * | |
1848 | * (I915_READ_FW(reg) & mask) == value | |
1849 | * | |
1d1a9774 | 1850 | * Otherwise, the wait will timeout after @slow_timeout_ms milliseconds. |
6976e74b | 1851 | * For atomic context @slow_timeout_ms must be zero and @fast_timeout_us |
84d84cb7 | 1852 | * must be not larger than 20,0000 microseconds. |
1758b90e CW |
1853 | * |
1854 | * Note that this routine assumes the caller holds forcewake asserted, it is | |
1855 | * not suitable for very long waits. See intel_wait_for_register() if you | |
1856 | * wish to wait without holding forcewake for the duration (i.e. you expect | |
1857 | * the wait to be slow). | |
1858 | * | |
1859 | * Returns 0 if the register matches the desired condition, or -ETIMEOUT. | |
1860 | */ | |
d2d551c0 | 1861 | int __intel_wait_for_register_fw(struct intel_uncore *uncore, |
1d1a9774 | 1862 | i915_reg_t reg, |
3fc7d86b MW |
1863 | u32 mask, |
1864 | u32 value, | |
1865 | unsigned int fast_timeout_us, | |
1866 | unsigned int slow_timeout_ms, | |
1d1a9774 | 1867 | u32 *out_value) |
1758b90e | 1868 | { |
ff26ffa8 | 1869 | u32 uninitialized_var(reg_value); |
d2d551c0 | 1870 | #define done (((reg_value = intel_uncore_read_fw(uncore, reg)) & mask) == value) |
1d1a9774 MW |
1871 | int ret; |
1872 | ||
6976e74b | 1873 | /* Catch any overuse of this function */ |
84d84cb7 CW |
1874 | might_sleep_if(slow_timeout_ms); |
1875 | GEM_BUG_ON(fast_timeout_us > 20000); | |
6976e74b | 1876 | |
84d84cb7 CW |
1877 | ret = -ETIMEDOUT; |
1878 | if (fast_timeout_us && fast_timeout_us <= 20000) | |
1d1a9774 | 1879 | ret = _wait_for_atomic(done, fast_timeout_us, 0); |
ff26ffa8 | 1880 | if (ret && slow_timeout_ms) |
1d1a9774 | 1881 | ret = wait_for(done, slow_timeout_ms); |
84d84cb7 | 1882 | |
1d1a9774 MW |
1883 | if (out_value) |
1884 | *out_value = reg_value; | |
84d84cb7 | 1885 | |
1758b90e CW |
1886 | return ret; |
1887 | #undef done | |
1888 | } | |
1889 | ||
1890 | /** | |
23fdbdd7 | 1891 | * __intel_wait_for_register - wait until register matches expected state |
baba6e57 | 1892 | * @uncore: the struct intel_uncore |
1758b90e CW |
1893 | * @reg: the register to read |
1894 | * @mask: mask to apply to register value | |
1895 | * @value: expected value | |
23fdbdd7 SP |
1896 | * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait |
1897 | * @slow_timeout_ms: slow timeout in millisecond | |
1898 | * @out_value: optional placeholder to hold registry value | |
1758b90e CW |
1899 | * |
1900 | * This routine waits until the target register @reg contains the expected | |
3d466cd6 DV |
1901 | * @value after applying the @mask, i.e. it waits until :: |
1902 | * | |
1903 | * (I915_READ(reg) & mask) == value | |
1904 | * | |
1758b90e CW |
1905 | * Otherwise, the wait will timeout after @timeout_ms milliseconds. |
1906 | * | |
1907 | * Returns 0 if the register matches the desired condition, or -ETIMEOUT. | |
1908 | */ | |
97a04e0d DCS |
1909 | int __intel_wait_for_register(struct intel_uncore *uncore, |
1910 | i915_reg_t reg, | |
1911 | u32 mask, | |
1912 | u32 value, | |
1913 | unsigned int fast_timeout_us, | |
1914 | unsigned int slow_timeout_ms, | |
1915 | u32 *out_value) | |
1916 | { | |
1758b90e | 1917 | unsigned fw = |
4319382e | 1918 | intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ); |
23fdbdd7 | 1919 | u32 reg_value; |
1758b90e CW |
1920 | int ret; |
1921 | ||
3df82dd4 | 1922 | might_sleep_if(slow_timeout_ms); |
05646543 | 1923 | |
272c7e52 DCS |
1924 | spin_lock_irq(&uncore->lock); |
1925 | intel_uncore_forcewake_get__locked(uncore, fw); | |
05646543 | 1926 | |
d2d551c0 | 1927 | ret = __intel_wait_for_register_fw(uncore, |
05646543 | 1928 | reg, mask, value, |
23fdbdd7 | 1929 | fast_timeout_us, 0, ®_value); |
05646543 | 1930 | |
272c7e52 DCS |
1931 | intel_uncore_forcewake_put__locked(uncore, fw); |
1932 | spin_unlock_irq(&uncore->lock); | |
05646543 | 1933 | |
3df82dd4 | 1934 | if (ret && slow_timeout_ms) |
d2d551c0 DCS |
1935 | ret = __wait_for(reg_value = intel_uncore_read_notrace(uncore, |
1936 | reg), | |
23fdbdd7 SP |
1937 | (reg_value & mask) == value, |
1938 | slow_timeout_ms * 1000, 10, 1000); | |
1939 | ||
39806c3f VS |
1940 | /* just trace the final value */ |
1941 | trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true); | |
1942 | ||
23fdbdd7 SP |
1943 | if (out_value) |
1944 | *out_value = reg_value; | |
1758b90e CW |
1945 | |
1946 | return ret; | |
d431440c TE |
1947 | } |
1948 | ||
2cf7bf6f | 1949 | bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore) |
907b28c5 | 1950 | { |
2cf7bf6f | 1951 | return check_for_unclaimed_mmio(uncore); |
907b28c5 | 1952 | } |
75714940 | 1953 | |
bc3b9346 | 1954 | bool |
2cf7bf6f | 1955 | intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore) |
75714940 | 1956 | { |
a167b1e1 CW |
1957 | bool ret = false; |
1958 | ||
272c7e52 | 1959 | spin_lock_irq(&uncore->lock); |
a167b1e1 | 1960 | |
272c7e52 | 1961 | if (unlikely(uncore->unclaimed_mmio_check <= 0)) |
a167b1e1 | 1962 | goto out; |
75714940 | 1963 | |
2cf7bf6f | 1964 | if (unlikely(intel_uncore_unclaimed_mmio(uncore))) { |
7ef4ac6e CW |
1965 | if (!i915_modparams.mmio_debug) { |
1966 | DRM_DEBUG("Unclaimed register detected, " | |
1967 | "enabling oneshot unclaimed register reporting. " | |
1968 | "Please use i915.mmio_debug=N for more information.\n"); | |
1969 | i915_modparams.mmio_debug++; | |
1970 | } | |
272c7e52 | 1971 | uncore->unclaimed_mmio_check--; |
a167b1e1 | 1972 | ret = true; |
75714940 | 1973 | } |
bc3b9346 | 1974 | |
a167b1e1 | 1975 | out: |
272c7e52 | 1976 | spin_unlock_irq(&uncore->lock); |
a167b1e1 CW |
1977 | |
1978 | return ret; | |
75714940 | 1979 | } |
3756685a | 1980 | |
3756685a TU |
1981 | /** |
1982 | * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access | |
1983 | * a register | |
4319382e | 1984 | * @uncore: pointer to struct intel_uncore |
3756685a TU |
1985 | * @reg: register in question |
1986 | * @op: operation bitmask of FW_REG_READ and/or FW_REG_WRITE | |
1987 | * | |
1988 | * Returns a set of forcewake domains required to be taken with for example | |
1989 | * intel_uncore_forcewake_get for the specified register to be accessible in the | |
1990 | * specified mode (read, write or read/write) with raw mmio accessors. | |
1991 | * | |
1992 | * NOTE: On Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the | |
1993 | * callers to do FIFO management on their own or risk losing writes. | |
1994 | */ | |
1995 | enum forcewake_domains | |
4319382e | 1996 | intel_uncore_forcewake_for_reg(struct intel_uncore *uncore, |
3756685a TU |
1997 | i915_reg_t reg, unsigned int op) |
1998 | { | |
1999 | enum forcewake_domains fw_domains = 0; | |
2000 | ||
2001 | WARN_ON(!op); | |
2002 | ||
4319382e | 2003 | if (!intel_uncore_has_forcewake(uncore)) |
895833bd TU |
2004 | return 0; |
2005 | ||
3756685a | 2006 | if (op & FW_REG_READ) |
ccb2acea | 2007 | fw_domains = uncore->funcs.read_fw_domains(uncore, reg); |
3756685a TU |
2008 | |
2009 | if (op & FW_REG_WRITE) | |
ccb2acea DCS |
2010 | fw_domains |= uncore->funcs.write_fw_domains(uncore, reg); |
2011 | ||
2012 | WARN_ON(fw_domains & ~uncore->fw_domains); | |
3756685a TU |
2013 | |
2014 | return fw_domains; | |
2015 | } | |
26e7a2a1 CW |
2016 | |
2017 | #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) | |
0757ac8f | 2018 | #include "selftests/mock_uncore.c" |
26e7a2a1 CW |
2019 | #include "selftests/intel_uncore.c" |
2020 | #endif |