Commit | Line | Data |
---|---|---|
907b28c5 CW |
1 | /* |
2 | * Copyright © 2013 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | */ | |
23 | ||
696173b0 JN |
24 | #include <linux/pm_runtime.h> |
25 | #include <asm/iosf_mbi.h> | |
26 | ||
907b28c5 | 27 | #include "i915_drv.h" |
a09d9a80 | 28 | #include "i915_trace.h" |
cf9d2890 | 29 | #include "i915_vgpu.h" |
696173b0 | 30 | #include "intel_pm.h" |
6daccb0b | 31 | |
83e33372 | 32 | #define FORCEWAKE_ACK_TIMEOUT_MS 50 |
6b07b6d2 | 33 | #define GT_FIFO_TIMEOUT_MS 10 |
907b28c5 | 34 | |
6cc5ca76 | 35 | #define __raw_posting_read(...) ((void)__raw_uncore_read32(__VA_ARGS__)) |
6af5d92f | 36 | |
0a9b2630 DCS |
37 | void |
38 | intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug) | |
39 | { | |
40 | spin_lock_init(&mmio_debug->lock); | |
41 | mmio_debug->unclaimed_mmio_check = 1; | |
42 | } | |
43 | ||
44 | static void mmio_debug_suspend(struct intel_uncore_mmio_debug *mmio_debug) | |
45 | { | |
46 | lockdep_assert_held(&mmio_debug->lock); | |
47 | ||
48 | /* Save and disable mmio debugging for the user bypass */ | |
49 | if (!mmio_debug->suspend_count++) { | |
50 | mmio_debug->saved_mmio_check = mmio_debug->unclaimed_mmio_check; | |
51 | mmio_debug->unclaimed_mmio_check = 0; | |
52 | } | |
53 | } | |
54 | ||
55 | static void mmio_debug_resume(struct intel_uncore_mmio_debug *mmio_debug) | |
56 | { | |
57 | lockdep_assert_held(&mmio_debug->lock); | |
58 | ||
59 | if (!--mmio_debug->suspend_count) | |
60 | mmio_debug->unclaimed_mmio_check = mmio_debug->saved_mmio_check; | |
61 | } | |
62 | ||
05a2fb15 MK |
63 | static const char * const forcewake_domain_names[] = { |
64 | "render", | |
65 | "blitter", | |
66 | "media", | |
a89a70a8 DCS |
67 | "vdbox0", |
68 | "vdbox1", | |
69 | "vdbox2", | |
70 | "vdbox3", | |
71 | "vebox0", | |
72 | "vebox1", | |
05a2fb15 MK |
73 | }; |
74 | ||
75 | const char * | |
48c1026a | 76 | intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id) |
05a2fb15 | 77 | { |
53abb679 | 78 | BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT); |
05a2fb15 MK |
79 | |
80 | if (id >= 0 && id < FW_DOMAIN_ID_COUNT) | |
81 | return forcewake_domain_names[id]; | |
82 | ||
83 | WARN_ON(id); | |
84 | ||
85 | return "unknown"; | |
86 | } | |
87 | ||
535d8d27 | 88 | #define fw_ack(d) readl((d)->reg_ack) |
159367bb DCS |
89 | #define fw_set(d, val) writel(_MASKED_BIT_ENABLE((val)), (d)->reg_set) |
90 | #define fw_clear(d, val) writel(_MASKED_BIT_DISABLE((val)), (d)->reg_set) | |
535d8d27 | 91 | |
05a2fb15 | 92 | static inline void |
159367bb | 93 | fw_domain_reset(const struct intel_uncore_forcewake_domain *d) |
907b28c5 | 94 | { |
26376a7e OM |
95 | /* |
96 | * We don't really know if the powerwell for the forcewake domain we are | |
97 | * trying to reset here does exist at this point (engines could be fused | |
98 | * off in ICL+), so no waiting for acks | |
99 | */ | |
159367bb DCS |
100 | /* WaRsClearFWBitsAtReset:bdw,skl */ |
101 | fw_clear(d, 0xffff); | |
907b28c5 CW |
102 | } |
103 | ||
05a2fb15 MK |
104 | static inline void |
105 | fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d) | |
907b28c5 | 106 | { |
77adbd8f CW |
107 | GEM_BUG_ON(d->uncore->fw_domains_timer & d->mask); |
108 | d->uncore->fw_domains_timer |= d->mask; | |
a57a4a67 TU |
109 | d->wake_count++; |
110 | hrtimer_start_range_ns(&d->timer, | |
8b0e1953 | 111 | NSEC_PER_MSEC, |
a57a4a67 TU |
112 | NSEC_PER_MSEC, |
113 | HRTIMER_MODE_REL); | |
907b28c5 CW |
114 | } |
115 | ||
71306303 | 116 | static inline int |
535d8d27 | 117 | __wait_for_ack(const struct intel_uncore_forcewake_domain *d, |
71306303 MK |
118 | const u32 ack, |
119 | const u32 value) | |
120 | { | |
535d8d27 | 121 | return wait_for_atomic((fw_ack(d) & ack) == value, |
71306303 MK |
122 | FORCEWAKE_ACK_TIMEOUT_MS); |
123 | } | |
124 | ||
125 | static inline int | |
535d8d27 | 126 | wait_ack_clear(const struct intel_uncore_forcewake_domain *d, |
71306303 MK |
127 | const u32 ack) |
128 | { | |
535d8d27 | 129 | return __wait_for_ack(d, ack, 0); |
71306303 MK |
130 | } |
131 | ||
132 | static inline int | |
535d8d27 | 133 | wait_ack_set(const struct intel_uncore_forcewake_domain *d, |
71306303 MK |
134 | const u32 ack) |
135 | { | |
535d8d27 | 136 | return __wait_for_ack(d, ack, ack); |
71306303 MK |
137 | } |
138 | ||
05a2fb15 | 139 | static inline void |
535d8d27 | 140 | fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d) |
907b28c5 | 141 | { |
18ecc6c5 | 142 | if (wait_ack_clear(d, FORCEWAKE_KERNEL)) { |
05a2fb15 MK |
143 | DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n", |
144 | intel_uncore_forcewake_domain_to_str(d->id)); | |
18ecc6c5 CW |
145 | add_taint_for_CI(TAINT_WARN); /* CI now unreliable */ |
146 | } | |
05a2fb15 | 147 | } |
907b28c5 | 148 | |
71306303 MK |
149 | enum ack_type { |
150 | ACK_CLEAR = 0, | |
151 | ACK_SET | |
152 | }; | |
153 | ||
154 | static int | |
535d8d27 | 155 | fw_domain_wait_ack_with_fallback(const struct intel_uncore_forcewake_domain *d, |
71306303 MK |
156 | const enum ack_type type) |
157 | { | |
158 | const u32 ack_bit = FORCEWAKE_KERNEL; | |
159 | const u32 value = type == ACK_SET ? ack_bit : 0; | |
160 | unsigned int pass; | |
161 | bool ack_detected; | |
162 | ||
163 | /* | |
164 | * There is a possibility of driver's wake request colliding | |
165 | * with hardware's own wake requests and that can cause | |
166 | * hardware to not deliver the driver's ack message. | |
167 | * | |
168 | * Use a fallback bit toggle to kick the gpu state machine | |
169 | * in the hope that the original ack will be delivered along with | |
170 | * the fallback ack. | |
171 | * | |
cc38cae7 OM |
172 | * This workaround is described in HSDES #1604254524 and it's known as: |
173 | * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl | |
174 | * although the name is a bit misleading. | |
71306303 MK |
175 | */ |
176 | ||
177 | pass = 1; | |
178 | do { | |
535d8d27 | 179 | wait_ack_clear(d, FORCEWAKE_KERNEL_FALLBACK); |
71306303 | 180 | |
159367bb | 181 | fw_set(d, FORCEWAKE_KERNEL_FALLBACK); |
71306303 MK |
182 | /* Give gt some time to relax before the polling frenzy */ |
183 | udelay(10 * pass); | |
535d8d27 | 184 | wait_ack_set(d, FORCEWAKE_KERNEL_FALLBACK); |
71306303 | 185 | |
535d8d27 | 186 | ack_detected = (fw_ack(d) & ack_bit) == value; |
71306303 | 187 | |
159367bb | 188 | fw_clear(d, FORCEWAKE_KERNEL_FALLBACK); |
71306303 MK |
189 | } while (!ack_detected && pass++ < 10); |
190 | ||
191 | DRM_DEBUG_DRIVER("%s had to use fallback to %s ack, 0x%x (passes %u)\n", | |
192 | intel_uncore_forcewake_domain_to_str(d->id), | |
193 | type == ACK_SET ? "set" : "clear", | |
535d8d27 | 194 | fw_ack(d), |
71306303 MK |
195 | pass); |
196 | ||
197 | return ack_detected ? 0 : -ETIMEDOUT; | |
198 | } | |
199 | ||
200 | static inline void | |
535d8d27 | 201 | fw_domain_wait_ack_clear_fallback(const struct intel_uncore_forcewake_domain *d) |
71306303 | 202 | { |
535d8d27 | 203 | if (likely(!wait_ack_clear(d, FORCEWAKE_KERNEL))) |
71306303 MK |
204 | return; |
205 | ||
535d8d27 DCS |
206 | if (fw_domain_wait_ack_with_fallback(d, ACK_CLEAR)) |
207 | fw_domain_wait_ack_clear(d); | |
71306303 MK |
208 | } |
209 | ||
05a2fb15 | 210 | static inline void |
159367bb | 211 | fw_domain_get(const struct intel_uncore_forcewake_domain *d) |
05a2fb15 | 212 | { |
159367bb | 213 | fw_set(d, FORCEWAKE_KERNEL); |
05a2fb15 | 214 | } |
907b28c5 | 215 | |
05a2fb15 | 216 | static inline void |
535d8d27 | 217 | fw_domain_wait_ack_set(const struct intel_uncore_forcewake_domain *d) |
05a2fb15 | 218 | { |
18ecc6c5 | 219 | if (wait_ack_set(d, FORCEWAKE_KERNEL)) { |
05a2fb15 MK |
220 | DRM_ERROR("%s: timed out waiting for forcewake ack request.\n", |
221 | intel_uncore_forcewake_domain_to_str(d->id)); | |
18ecc6c5 CW |
222 | add_taint_for_CI(TAINT_WARN); /* CI now unreliable */ |
223 | } | |
05a2fb15 | 224 | } |
907b28c5 | 225 | |
71306303 | 226 | static inline void |
535d8d27 | 227 | fw_domain_wait_ack_set_fallback(const struct intel_uncore_forcewake_domain *d) |
71306303 | 228 | { |
535d8d27 | 229 | if (likely(!wait_ack_set(d, FORCEWAKE_KERNEL))) |
71306303 MK |
230 | return; |
231 | ||
535d8d27 DCS |
232 | if (fw_domain_wait_ack_with_fallback(d, ACK_SET)) |
233 | fw_domain_wait_ack_set(d); | |
71306303 MK |
234 | } |
235 | ||
05a2fb15 | 236 | static inline void |
159367bb | 237 | fw_domain_put(const struct intel_uncore_forcewake_domain *d) |
05a2fb15 | 238 | { |
159367bb | 239 | fw_clear(d, FORCEWAKE_KERNEL); |
907b28c5 CW |
240 | } |
241 | ||
05a2fb15 | 242 | static void |
f568eeee | 243 | fw_domains_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains) |
907b28c5 | 244 | { |
05a2fb15 | 245 | struct intel_uncore_forcewake_domain *d; |
d2dc94bc | 246 | unsigned int tmp; |
907b28c5 | 247 | |
535d8d27 | 248 | GEM_BUG_ON(fw_domains & ~uncore->fw_domains); |
d2dc94bc | 249 | |
f568eeee | 250 | for_each_fw_domain_masked(d, fw_domains, uncore, tmp) { |
535d8d27 | 251 | fw_domain_wait_ack_clear(d); |
159367bb | 252 | fw_domain_get(d); |
05a2fb15 | 253 | } |
4e1176dd | 254 | |
f568eeee | 255 | for_each_fw_domain_masked(d, fw_domains, uncore, tmp) |
535d8d27 | 256 | fw_domain_wait_ack_set(d); |
71306303 | 257 | |
535d8d27 | 258 | uncore->fw_domains_active |= fw_domains; |
71306303 MK |
259 | } |
260 | ||
261 | static void | |
f568eeee | 262 | fw_domains_get_with_fallback(struct intel_uncore *uncore, |
71306303 MK |
263 | enum forcewake_domains fw_domains) |
264 | { | |
265 | struct intel_uncore_forcewake_domain *d; | |
266 | unsigned int tmp; | |
267 | ||
535d8d27 | 268 | GEM_BUG_ON(fw_domains & ~uncore->fw_domains); |
71306303 | 269 | |
f568eeee | 270 | for_each_fw_domain_masked(d, fw_domains, uncore, tmp) { |
535d8d27 | 271 | fw_domain_wait_ack_clear_fallback(d); |
159367bb | 272 | fw_domain_get(d); |
71306303 MK |
273 | } |
274 | ||
f568eeee | 275 | for_each_fw_domain_masked(d, fw_domains, uncore, tmp) |
535d8d27 | 276 | fw_domain_wait_ack_set_fallback(d); |
b8473050 | 277 | |
535d8d27 | 278 | uncore->fw_domains_active |= fw_domains; |
05a2fb15 | 279 | } |
907b28c5 | 280 | |
05a2fb15 | 281 | static void |
f568eeee | 282 | fw_domains_put(struct intel_uncore *uncore, enum forcewake_domains fw_domains) |
05a2fb15 MK |
283 | { |
284 | struct intel_uncore_forcewake_domain *d; | |
d2dc94bc CW |
285 | unsigned int tmp; |
286 | ||
535d8d27 | 287 | GEM_BUG_ON(fw_domains & ~uncore->fw_domains); |
907b28c5 | 288 | |
f568eeee | 289 | for_each_fw_domain_masked(d, fw_domains, uncore, tmp) |
159367bb | 290 | fw_domain_put(d); |
b8473050 | 291 | |
535d8d27 | 292 | uncore->fw_domains_active &= ~fw_domains; |
05a2fb15 | 293 | } |
907b28c5 | 294 | |
05a2fb15 | 295 | static void |
f568eeee | 296 | fw_domains_reset(struct intel_uncore *uncore, |
577ac4bd | 297 | enum forcewake_domains fw_domains) |
05a2fb15 MK |
298 | { |
299 | struct intel_uncore_forcewake_domain *d; | |
d2dc94bc | 300 | unsigned int tmp; |
05a2fb15 | 301 | |
d2dc94bc | 302 | if (!fw_domains) |
3225b2f9 | 303 | return; |
f9b3927a | 304 | |
535d8d27 | 305 | GEM_BUG_ON(fw_domains & ~uncore->fw_domains); |
d2dc94bc | 306 | |
f568eeee | 307 | for_each_fw_domain_masked(d, fw_domains, uncore, tmp) |
159367bb | 308 | fw_domain_reset(d); |
05a2fb15 MK |
309 | } |
310 | ||
6ebc9692 | 311 | static inline u32 gt_thread_status(struct intel_uncore *uncore) |
a5b22b5e CW |
312 | { |
313 | u32 val; | |
314 | ||
6cc5ca76 | 315 | val = __raw_uncore_read32(uncore, GEN6_GT_THREAD_STATUS_REG); |
a5b22b5e CW |
316 | val &= GEN6_GT_THREAD_STATUS_CORE_MASK; |
317 | ||
318 | return val; | |
319 | } | |
320 | ||
6ebc9692 | 321 | static void __gen6_gt_wait_for_thread_c0(struct intel_uncore *uncore) |
05a2fb15 | 322 | { |
a5b22b5e CW |
323 | /* |
324 | * w/a for a sporadic read returning 0 by waiting for the GT | |
05a2fb15 MK |
325 | * thread to wake up. |
326 | */ | |
a9f236d1 PB |
327 | drm_WARN_ONCE(&uncore->i915->drm, |
328 | wait_for_atomic_us(gt_thread_status(uncore) == 0, 5000), | |
329 | "GT thread status wait timed out\n"); | |
05a2fb15 MK |
330 | } |
331 | ||
f568eeee | 332 | static void fw_domains_get_with_thread_status(struct intel_uncore *uncore, |
48c1026a | 333 | enum forcewake_domains fw_domains) |
05a2fb15 | 334 | { |
f568eeee | 335 | fw_domains_get(uncore, fw_domains); |
907b28c5 | 336 | |
05a2fb15 | 337 | /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */ |
6ebc9692 | 338 | __gen6_gt_wait_for_thread_c0(uncore); |
907b28c5 CW |
339 | } |
340 | ||
6ebc9692 | 341 | static inline u32 fifo_free_entries(struct intel_uncore *uncore) |
c32e3788 | 342 | { |
6cc5ca76 | 343 | u32 count = __raw_uncore_read32(uncore, GTFIFOCTL); |
c32e3788 DG |
344 | |
345 | return count & GT_FIFO_FREE_ENTRIES_MASK; | |
346 | } | |
347 | ||
6ebc9692 | 348 | static void __gen6_gt_wait_for_fifo(struct intel_uncore *uncore) |
907b28c5 | 349 | { |
6b07b6d2 | 350 | u32 n; |
907b28c5 | 351 | |
5135d64b D |
352 | /* On VLV, FIFO will be shared by both SW and HW. |
353 | * So, we need to read the FREE_ENTRIES everytime */ | |
01385758 | 354 | if (IS_VALLEYVIEW(uncore->i915)) |
6ebc9692 | 355 | n = fifo_free_entries(uncore); |
6b07b6d2 | 356 | else |
272c7e52 | 357 | n = uncore->fifo_count; |
6b07b6d2 MK |
358 | |
359 | if (n <= GT_FIFO_NUM_RESERVED_ENTRIES) { | |
6ebc9692 | 360 | if (wait_for_atomic((n = fifo_free_entries(uncore)) > |
6b07b6d2 MK |
361 | GT_FIFO_NUM_RESERVED_ENTRIES, |
362 | GT_FIFO_TIMEOUT_MS)) { | |
d0208cfa WK |
363 | drm_dbg(&uncore->i915->drm, |
364 | "GT_FIFO timeout, entries: %u\n", n); | |
6b07b6d2 | 365 | return; |
907b28c5 | 366 | } |
907b28c5 | 367 | } |
907b28c5 | 368 | |
272c7e52 | 369 | uncore->fifo_count = n - 1; |
907b28c5 CW |
370 | } |
371 | ||
a57a4a67 TU |
372 | static enum hrtimer_restart |
373 | intel_uncore_fw_release_timer(struct hrtimer *timer) | |
38cff0b1 | 374 | { |
a57a4a67 TU |
375 | struct intel_uncore_forcewake_domain *domain = |
376 | container_of(timer, struct intel_uncore_forcewake_domain, timer); | |
f833cdb0 | 377 | struct intel_uncore *uncore = domain->uncore; |
b2cff0db | 378 | unsigned long irqflags; |
38cff0b1 | 379 | |
eb17af67 | 380 | assert_rpm_device_not_suspended(uncore->rpm); |
38cff0b1 | 381 | |
c9e0c6da CW |
382 | if (xchg(&domain->active, false)) |
383 | return HRTIMER_RESTART; | |
384 | ||
f568eeee | 385 | spin_lock_irqsave(&uncore->lock, irqflags); |
b2cff0db | 386 | |
77adbd8f CW |
387 | uncore->fw_domains_timer &= ~domain->mask; |
388 | ||
389 | GEM_BUG_ON(!domain->wake_count); | |
b8473050 | 390 | if (--domain->wake_count == 0) |
f568eeee | 391 | uncore->funcs.force_wake_put(uncore, domain->mask); |
b2cff0db | 392 | |
f568eeee | 393 | spin_unlock_irqrestore(&uncore->lock, irqflags); |
a57a4a67 TU |
394 | |
395 | return HRTIMER_NORESTART; | |
38cff0b1 ZW |
396 | } |
397 | ||
a5266db4 | 398 | /* Note callers must have acquired the PUNIT->PMIC bus, before calling this. */ |
d60996ab | 399 | static unsigned int |
f568eeee | 400 | intel_uncore_forcewake_reset(struct intel_uncore *uncore) |
38cff0b1 | 401 | { |
48c1026a | 402 | unsigned long irqflags; |
b2cff0db | 403 | struct intel_uncore_forcewake_domain *domain; |
48c1026a | 404 | int retry_count = 100; |
003342a5 | 405 | enum forcewake_domains fw, active_domains; |
38cff0b1 | 406 | |
a5266db4 HG |
407 | iosf_mbi_assert_punit_acquired(); |
408 | ||
b2cff0db CW |
409 | /* Hold uncore.lock across reset to prevent any register access |
410 | * with forcewake not set correctly. Wait until all pending | |
411 | * timers are run before holding. | |
412 | */ | |
413 | while (1) { | |
d2dc94bc CW |
414 | unsigned int tmp; |
415 | ||
b2cff0db | 416 | active_domains = 0; |
38cff0b1 | 417 | |
f568eeee | 418 | for_each_fw_domain(domain, uncore, tmp) { |
c9e0c6da | 419 | smp_store_mb(domain->active, false); |
a57a4a67 | 420 | if (hrtimer_cancel(&domain->timer) == 0) |
b2cff0db | 421 | continue; |
38cff0b1 | 422 | |
a57a4a67 | 423 | intel_uncore_fw_release_timer(&domain->timer); |
b2cff0db | 424 | } |
aec347ab | 425 | |
f568eeee | 426 | spin_lock_irqsave(&uncore->lock, irqflags); |
b2ec142c | 427 | |
f568eeee | 428 | for_each_fw_domain(domain, uncore, tmp) { |
a57a4a67 | 429 | if (hrtimer_active(&domain->timer)) |
33c582c1 | 430 | active_domains |= domain->mask; |
b2cff0db | 431 | } |
3123fcaf | 432 | |
b2cff0db CW |
433 | if (active_domains == 0) |
434 | break; | |
aec347ab | 435 | |
b2cff0db | 436 | if (--retry_count == 0) { |
d0208cfa | 437 | drm_err(&uncore->i915->drm, "Timed out waiting for forcewake timers to finish\n"); |
b2cff0db CW |
438 | break; |
439 | } | |
0294ae7b | 440 | |
f568eeee | 441 | spin_unlock_irqrestore(&uncore->lock, irqflags); |
b2cff0db CW |
442 | cond_resched(); |
443 | } | |
0294ae7b | 444 | |
a9f236d1 | 445 | drm_WARN_ON(&uncore->i915->drm, active_domains); |
b2cff0db | 446 | |
f568eeee | 447 | fw = uncore->fw_domains_active; |
b2cff0db | 448 | if (fw) |
f568eeee | 449 | uncore->funcs.force_wake_put(uncore, fw); |
ef46e0d2 | 450 | |
f568eeee DCS |
451 | fw_domains_reset(uncore, uncore->fw_domains); |
452 | assert_forcewakes_inactive(uncore); | |
b2cff0db | 453 | |
f568eeee | 454 | spin_unlock_irqrestore(&uncore->lock, irqflags); |
d60996ab CW |
455 | |
456 | return fw; /* track the lost user forcewake domains */ | |
ef46e0d2 DV |
457 | } |
458 | ||
8a47eb19 | 459 | static bool |
6ebc9692 | 460 | fpga_check_for_unclaimed_mmio(struct intel_uncore *uncore) |
8a47eb19 MK |
461 | { |
462 | u32 dbg; | |
463 | ||
6cc5ca76 | 464 | dbg = __raw_uncore_read32(uncore, FPGA_DBG); |
8a47eb19 MK |
465 | if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM))) |
466 | return false; | |
467 | ||
6cc5ca76 | 468 | __raw_uncore_write32(uncore, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
8a47eb19 MK |
469 | |
470 | return true; | |
471 | } | |
472 | ||
8ac3e1bb | 473 | static bool |
6ebc9692 | 474 | vlv_check_for_unclaimed_mmio(struct intel_uncore *uncore) |
8ac3e1bb MK |
475 | { |
476 | u32 cer; | |
477 | ||
6cc5ca76 | 478 | cer = __raw_uncore_read32(uncore, CLAIM_ER); |
8ac3e1bb MK |
479 | if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK)))) |
480 | return false; | |
481 | ||
6cc5ca76 | 482 | __raw_uncore_write32(uncore, CLAIM_ER, CLAIM_ER_CLR); |
8ac3e1bb MK |
483 | |
484 | return true; | |
485 | } | |
486 | ||
a338908c | 487 | static bool |
6ebc9692 | 488 | gen6_check_for_fifo_debug(struct intel_uncore *uncore) |
a338908c MK |
489 | { |
490 | u32 fifodbg; | |
491 | ||
6cc5ca76 | 492 | fifodbg = __raw_uncore_read32(uncore, GTFIFODBG); |
a338908c MK |
493 | |
494 | if (unlikely(fifodbg)) { | |
d0208cfa | 495 | drm_dbg(&uncore->i915->drm, "GTFIFODBG = 0x08%x\n", fifodbg); |
6cc5ca76 | 496 | __raw_uncore_write32(uncore, GTFIFODBG, fifodbg); |
a338908c MK |
497 | } |
498 | ||
499 | return fifodbg; | |
500 | } | |
501 | ||
8ac3e1bb | 502 | static bool |
2cf7bf6f | 503 | check_for_unclaimed_mmio(struct intel_uncore *uncore) |
8ac3e1bb | 504 | { |
a338908c MK |
505 | bool ret = false; |
506 | ||
0a9b2630 DCS |
507 | lockdep_assert_held(&uncore->debug->lock); |
508 | ||
509 | if (uncore->debug->suspend_count) | |
510 | return false; | |
511 | ||
2cf7bf6f | 512 | if (intel_uncore_has_fpga_dbg_unclaimed(uncore)) |
6ebc9692 | 513 | ret |= fpga_check_for_unclaimed_mmio(uncore); |
8ac3e1bb | 514 | |
2cf7bf6f | 515 | if (intel_uncore_has_dbg_unclaimed(uncore)) |
6ebc9692 | 516 | ret |= vlv_check_for_unclaimed_mmio(uncore); |
a338908c | 517 | |
2cf7bf6f | 518 | if (intel_uncore_has_fifo(uncore)) |
6ebc9692 | 519 | ret |= gen6_check_for_fifo_debug(uncore); |
8ac3e1bb | 520 | |
a338908c | 521 | return ret; |
8ac3e1bb MK |
522 | } |
523 | ||
2e81bc61 DCS |
524 | static void forcewake_early_sanitize(struct intel_uncore *uncore, |
525 | unsigned int restore_forcewake) | |
f9b3927a | 526 | { |
2e81bc61 | 527 | GEM_BUG_ON(!intel_uncore_has_forcewake(uncore)); |
907b28c5 | 528 | |
a04f90a3 | 529 | /* WaDisableShadowRegForCpd:chv */ |
01385758 | 530 | if (IS_CHERRYVIEW(uncore->i915)) { |
6cc5ca76 DCS |
531 | __raw_uncore_write32(uncore, GTFIFOCTL, |
532 | __raw_uncore_read32(uncore, GTFIFOCTL) | | |
533 | GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL | | |
534 | GT_FIFO_CTL_RC6_POLICY_STALL); | |
a04f90a3 D |
535 | } |
536 | ||
a5266db4 | 537 | iosf_mbi_punit_acquire(); |
f7de5027 | 538 | intel_uncore_forcewake_reset(uncore); |
d60996ab | 539 | if (restore_forcewake) { |
f7de5027 DCS |
540 | spin_lock_irq(&uncore->lock); |
541 | uncore->funcs.force_wake_get(uncore, restore_forcewake); | |
542 | ||
2cf7bf6f | 543 | if (intel_uncore_has_fifo(uncore)) |
6ebc9692 | 544 | uncore->fifo_count = fifo_free_entries(uncore); |
f7de5027 | 545 | spin_unlock_irq(&uncore->lock); |
d60996ab | 546 | } |
a5266db4 | 547 | iosf_mbi_punit_release(); |
521198a2 MK |
548 | } |
549 | ||
f7de5027 | 550 | void intel_uncore_suspend(struct intel_uncore *uncore) |
ed493883 | 551 | { |
2e81bc61 DCS |
552 | if (!intel_uncore_has_forcewake(uncore)) |
553 | return; | |
554 | ||
a5266db4 HG |
555 | iosf_mbi_punit_acquire(); |
556 | iosf_mbi_unregister_pmic_bus_access_notifier_unlocked( | |
f7de5027 DCS |
557 | &uncore->pmic_bus_access_nb); |
558 | uncore->fw_domains_saved = intel_uncore_forcewake_reset(uncore); | |
a5266db4 | 559 | iosf_mbi_punit_release(); |
68f60946 HG |
560 | } |
561 | ||
f7de5027 | 562 | void intel_uncore_resume_early(struct intel_uncore *uncore) |
68f60946 | 563 | { |
d60996ab CW |
564 | unsigned int restore_forcewake; |
565 | ||
2e81bc61 | 566 | if (intel_uncore_unclaimed_mmio(uncore)) |
d0208cfa | 567 | drm_dbg(&uncore->i915->drm, "unclaimed mmio detected on resume, clearing\n"); |
2e81bc61 DCS |
568 | |
569 | if (!intel_uncore_has_forcewake(uncore)) | |
570 | return; | |
571 | ||
f7de5027 | 572 | restore_forcewake = fetch_and_zero(&uncore->fw_domains_saved); |
2e81bc61 | 573 | forcewake_early_sanitize(uncore, restore_forcewake); |
d60996ab | 574 | |
f7de5027 | 575 | iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb); |
ed493883 ID |
576 | } |
577 | ||
f7de5027 | 578 | void intel_uncore_runtime_resume(struct intel_uncore *uncore) |
bedf4d79 | 579 | { |
2e81bc61 DCS |
580 | if (!intel_uncore_has_forcewake(uncore)) |
581 | return; | |
582 | ||
f7de5027 | 583 | iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb); |
bedf4d79 HG |
584 | } |
585 | ||
f568eeee | 586 | static void __intel_uncore_forcewake_get(struct intel_uncore *uncore, |
a6111f7b CW |
587 | enum forcewake_domains fw_domains) |
588 | { | |
589 | struct intel_uncore_forcewake_domain *domain; | |
d2dc94bc | 590 | unsigned int tmp; |
a6111f7b | 591 | |
f568eeee | 592 | fw_domains &= uncore->fw_domains; |
a6111f7b | 593 | |
f568eeee | 594 | for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) { |
c9e0c6da | 595 | if (domain->wake_count++) { |
33c582c1 | 596 | fw_domains &= ~domain->mask; |
c9e0c6da CW |
597 | domain->active = true; |
598 | } | |
599 | } | |
a6111f7b | 600 | |
b8473050 | 601 | if (fw_domains) |
f568eeee | 602 | uncore->funcs.force_wake_get(uncore, fw_domains); |
a6111f7b CW |
603 | } |
604 | ||
59bad947 MK |
605 | /** |
606 | * intel_uncore_forcewake_get - grab forcewake domain references | |
3ceea6a1 | 607 | * @uncore: the intel_uncore structure |
59bad947 MK |
608 | * @fw_domains: forcewake domains to get reference on |
609 | * | |
610 | * This function can be used get GT's forcewake domain references. | |
611 | * Normal register access will handle the forcewake domains automatically. | |
612 | * However if some sequence requires the GT to not power down a particular | |
613 | * forcewake domains this function should be called at the beginning of the | |
614 | * sequence. And subsequently the reference should be dropped by symmetric | |
615 | * call to intel_unforce_forcewake_put(). Usually caller wants all the domains | |
616 | * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL. | |
907b28c5 | 617 | */ |
3ceea6a1 | 618 | void intel_uncore_forcewake_get(struct intel_uncore *uncore, |
48c1026a | 619 | enum forcewake_domains fw_domains) |
907b28c5 CW |
620 | { |
621 | unsigned long irqflags; | |
622 | ||
f568eeee | 623 | if (!uncore->funcs.force_wake_get) |
ab484f8f BW |
624 | return; |
625 | ||
87b391b9 | 626 | assert_rpm_wakelock_held(uncore->rpm); |
c8c8fb33 | 627 | |
f568eeee DCS |
628 | spin_lock_irqsave(&uncore->lock, irqflags); |
629 | __intel_uncore_forcewake_get(uncore, fw_domains); | |
630 | spin_unlock_irqrestore(&uncore->lock, irqflags); | |
907b28c5 CW |
631 | } |
632 | ||
d7a133d8 CW |
633 | /** |
634 | * intel_uncore_forcewake_user_get - claim forcewake on behalf of userspace | |
3ceea6a1 | 635 | * @uncore: the intel_uncore structure |
d7a133d8 CW |
636 | * |
637 | * This function is a wrapper around intel_uncore_forcewake_get() to acquire | |
638 | * the GT powerwell and in the process disable our debugging for the | |
639 | * duration of userspace's bypass. | |
640 | */ | |
3ceea6a1 | 641 | void intel_uncore_forcewake_user_get(struct intel_uncore *uncore) |
d7a133d8 | 642 | { |
f568eeee | 643 | spin_lock_irq(&uncore->lock); |
0a9b2630 | 644 | if (!uncore->user_forcewake_count++) { |
3ceea6a1 | 645 | intel_uncore_forcewake_get__locked(uncore, FORCEWAKE_ALL); |
0a9b2630 DCS |
646 | spin_lock(&uncore->debug->lock); |
647 | mmio_debug_suspend(uncore->debug); | |
648 | spin_unlock(&uncore->debug->lock); | |
d7a133d8 | 649 | } |
f568eeee | 650 | spin_unlock_irq(&uncore->lock); |
d7a133d8 CW |
651 | } |
652 | ||
653 | /** | |
654 | * intel_uncore_forcewake_user_put - release forcewake on behalf of userspace | |
3ceea6a1 | 655 | * @uncore: the intel_uncore structure |
d7a133d8 CW |
656 | * |
657 | * This function complements intel_uncore_forcewake_user_get() and releases | |
658 | * the GT powerwell taken on behalf of the userspace bypass. | |
659 | */ | |
3ceea6a1 | 660 | void intel_uncore_forcewake_user_put(struct intel_uncore *uncore) |
d7a133d8 | 661 | { |
f568eeee | 662 | spin_lock_irq(&uncore->lock); |
0a9b2630 DCS |
663 | if (!--uncore->user_forcewake_count) { |
664 | spin_lock(&uncore->debug->lock); | |
665 | mmio_debug_resume(uncore->debug); | |
666 | ||
667 | if (check_for_unclaimed_mmio(uncore)) | |
01385758 | 668 | dev_info(uncore->i915->drm.dev, |
d7a133d8 | 669 | "Invalid mmio detected during user access\n"); |
0a9b2630 | 670 | spin_unlock(&uncore->debug->lock); |
d7a133d8 | 671 | |
3ceea6a1 | 672 | intel_uncore_forcewake_put__locked(uncore, FORCEWAKE_ALL); |
d7a133d8 | 673 | } |
f568eeee | 674 | spin_unlock_irq(&uncore->lock); |
d7a133d8 CW |
675 | } |
676 | ||
59bad947 | 677 | /** |
a6111f7b | 678 | * intel_uncore_forcewake_get__locked - grab forcewake domain references |
3ceea6a1 | 679 | * @uncore: the intel_uncore structure |
a6111f7b | 680 | * @fw_domains: forcewake domains to get reference on |
59bad947 | 681 | * |
a6111f7b CW |
682 | * See intel_uncore_forcewake_get(). This variant places the onus |
683 | * on the caller to explicitly handle the dev_priv->uncore.lock spinlock. | |
907b28c5 | 684 | */ |
3ceea6a1 | 685 | void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore, |
a6111f7b CW |
686 | enum forcewake_domains fw_domains) |
687 | { | |
f568eeee DCS |
688 | lockdep_assert_held(&uncore->lock); |
689 | ||
690 | if (!uncore->funcs.force_wake_get) | |
a6111f7b CW |
691 | return; |
692 | ||
f568eeee | 693 | __intel_uncore_forcewake_get(uncore, fw_domains); |
a6111f7b CW |
694 | } |
695 | ||
f568eeee | 696 | static void __intel_uncore_forcewake_put(struct intel_uncore *uncore, |
a6111f7b | 697 | enum forcewake_domains fw_domains) |
907b28c5 | 698 | { |
b2cff0db | 699 | struct intel_uncore_forcewake_domain *domain; |
d2dc94bc | 700 | unsigned int tmp; |
907b28c5 | 701 | |
f568eeee | 702 | fw_domains &= uncore->fw_domains; |
b2cff0db | 703 | |
f568eeee | 704 | for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) { |
77adbd8f | 705 | GEM_BUG_ON(!domain->wake_count); |
b2cff0db | 706 | |
c9e0c6da CW |
707 | if (--domain->wake_count) { |
708 | domain->active = true; | |
b2cff0db | 709 | continue; |
c9e0c6da | 710 | } |
b2cff0db | 711 | |
05a2fb15 | 712 | fw_domain_arm_timer(domain); |
aec347ab | 713 | } |
a6111f7b | 714 | } |
dc9fb09c | 715 | |
a6111f7b CW |
716 | /** |
717 | * intel_uncore_forcewake_put - release a forcewake domain reference | |
3ceea6a1 | 718 | * @uncore: the intel_uncore structure |
a6111f7b CW |
719 | * @fw_domains: forcewake domains to put references |
720 | * | |
721 | * This function drops the device-level forcewakes for specified | |
722 | * domains obtained by intel_uncore_forcewake_get(). | |
723 | */ | |
3ceea6a1 | 724 | void intel_uncore_forcewake_put(struct intel_uncore *uncore, |
a6111f7b CW |
725 | enum forcewake_domains fw_domains) |
726 | { | |
727 | unsigned long irqflags; | |
728 | ||
f568eeee | 729 | if (!uncore->funcs.force_wake_put) |
a6111f7b CW |
730 | return; |
731 | ||
f568eeee DCS |
732 | spin_lock_irqsave(&uncore->lock, irqflags); |
733 | __intel_uncore_forcewake_put(uncore, fw_domains); | |
734 | spin_unlock_irqrestore(&uncore->lock, irqflags); | |
907b28c5 CW |
735 | } |
736 | ||
a6111f7b CW |
737 | /** |
738 | * intel_uncore_forcewake_put__locked - grab forcewake domain references | |
3ceea6a1 | 739 | * @uncore: the intel_uncore structure |
a6111f7b CW |
740 | * @fw_domains: forcewake domains to get reference on |
741 | * | |
742 | * See intel_uncore_forcewake_put(). This variant places the onus | |
743 | * on the caller to explicitly handle the dev_priv->uncore.lock spinlock. | |
744 | */ | |
3ceea6a1 | 745 | void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore, |
a6111f7b CW |
746 | enum forcewake_domains fw_domains) |
747 | { | |
f568eeee DCS |
748 | lockdep_assert_held(&uncore->lock); |
749 | ||
750 | if (!uncore->funcs.force_wake_put) | |
a6111f7b CW |
751 | return; |
752 | ||
f568eeee | 753 | __intel_uncore_forcewake_put(uncore, fw_domains); |
a6111f7b CW |
754 | } |
755 | ||
f568eeee | 756 | void assert_forcewakes_inactive(struct intel_uncore *uncore) |
e998c40f | 757 | { |
f568eeee | 758 | if (!uncore->funcs.force_wake_get) |
e998c40f PZ |
759 | return; |
760 | ||
a9f236d1 PB |
761 | drm_WARN(&uncore->i915->drm, uncore->fw_domains_active, |
762 | "Expected all fw_domains to be inactive, but %08x are still on\n", | |
763 | uncore->fw_domains_active); | |
67e64564 CW |
764 | } |
765 | ||
f568eeee | 766 | void assert_forcewakes_active(struct intel_uncore *uncore, |
67e64564 CW |
767 | enum forcewake_domains fw_domains) |
768 | { | |
b7dc9395 CW |
769 | struct intel_uncore_forcewake_domain *domain; |
770 | unsigned int tmp; | |
771 | ||
772 | if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) | |
773 | return; | |
774 | ||
f568eeee | 775 | if (!uncore->funcs.force_wake_get) |
67e64564 CW |
776 | return; |
777 | ||
15e7facb CW |
778 | spin_lock_irq(&uncore->lock); |
779 | ||
87b391b9 | 780 | assert_rpm_wakelock_held(uncore->rpm); |
67e64564 | 781 | |
f568eeee | 782 | fw_domains &= uncore->fw_domains; |
a9f236d1 PB |
783 | drm_WARN(&uncore->i915->drm, fw_domains & ~uncore->fw_domains_active, |
784 | "Expected %08x fw_domains to be active, but %08x are off\n", | |
785 | fw_domains, fw_domains & ~uncore->fw_domains_active); | |
b7dc9395 CW |
786 | |
787 | /* | |
788 | * Check that the caller has an explicit wakeref and we don't mistake | |
789 | * it for the auto wakeref. | |
790 | */ | |
b7dc9395 | 791 | for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) { |
badf1f27 | 792 | unsigned int actual = READ_ONCE(domain->wake_count); |
b7dc9395 CW |
793 | unsigned int expect = 1; |
794 | ||
77adbd8f | 795 | if (uncore->fw_domains_timer & domain->mask) |
b7dc9395 CW |
796 | expect++; /* pending automatic release */ |
797 | ||
a9f236d1 PB |
798 | if (drm_WARN(&uncore->i915->drm, actual < expect, |
799 | "Expected domain %d to be held awake by caller, count=%d\n", | |
800 | domain->id, actual)) | |
b7dc9395 CW |
801 | break; |
802 | } | |
15e7facb CW |
803 | |
804 | spin_unlock_irq(&uncore->lock); | |
e998c40f PZ |
805 | } |
806 | ||
907b28c5 | 807 | /* We give fast paths for the really cool registers */ |
40181697 | 808 | #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000) |
907b28c5 | 809 | |
272c7e52 | 810 | #define __gen6_reg_read_fw_domains(uncore, offset) \ |
6863b76c TU |
811 | ({ \ |
812 | enum forcewake_domains __fwd; \ | |
813 | if (NEEDS_FORCE_WAKE(offset)) \ | |
814 | __fwd = FORCEWAKE_RENDER; \ | |
815 | else \ | |
816 | __fwd = 0; \ | |
817 | __fwd; \ | |
818 | }) | |
819 | ||
9480dbf0 | 820 | static int fw_range_cmp(u32 offset, const struct intel_forcewake_range *entry) |
91e630b9 | 821 | { |
91e630b9 TU |
822 | if (offset < entry->start) |
823 | return -1; | |
824 | else if (offset > entry->end) | |
825 | return 1; | |
826 | else | |
827 | return 0; | |
828 | } | |
829 | ||
9480dbf0 TU |
830 | /* Copied and "macroized" from lib/bsearch.c */ |
831 | #define BSEARCH(key, base, num, cmp) ({ \ | |
832 | unsigned int start__ = 0, end__ = (num); \ | |
833 | typeof(base) result__ = NULL; \ | |
834 | while (start__ < end__) { \ | |
835 | unsigned int mid__ = start__ + (end__ - start__) / 2; \ | |
836 | int ret__ = (cmp)((key), (base) + mid__); \ | |
837 | if (ret__ < 0) { \ | |
838 | end__ = mid__; \ | |
839 | } else if (ret__ > 0) { \ | |
840 | start__ = mid__ + 1; \ | |
841 | } else { \ | |
842 | result__ = (base) + mid__; \ | |
843 | break; \ | |
844 | } \ | |
845 | } \ | |
846 | result__; \ | |
847 | }) | |
848 | ||
9fc1117c | 849 | static enum forcewake_domains |
cb7ee690 | 850 | find_fw_domain(struct intel_uncore *uncore, u32 offset) |
9fc1117c | 851 | { |
9480dbf0 | 852 | const struct intel_forcewake_range *entry; |
9fc1117c | 853 | |
9480dbf0 | 854 | entry = BSEARCH(offset, |
cb7ee690 DCS |
855 | uncore->fw_domains_table, |
856 | uncore->fw_domains_table_entries, | |
91e630b9 | 857 | fw_range_cmp); |
38fb6a40 | 858 | |
99191427 JL |
859 | if (!entry) |
860 | return 0; | |
861 | ||
a89a70a8 DCS |
862 | /* |
863 | * The list of FW domains depends on the SKU in gen11+ so we | |
864 | * can't determine it statically. We use FORCEWAKE_ALL and | |
865 | * translate it here to the list of available domains. | |
866 | */ | |
867 | if (entry->domains == FORCEWAKE_ALL) | |
cb7ee690 | 868 | return uncore->fw_domains; |
a89a70a8 | 869 | |
a9f236d1 PB |
870 | drm_WARN(&uncore->i915->drm, entry->domains & ~uncore->fw_domains, |
871 | "Uninitialized forcewake domain(s) 0x%x accessed at 0x%x\n", | |
872 | entry->domains & ~uncore->fw_domains, offset); | |
99191427 JL |
873 | |
874 | return entry->domains; | |
9fc1117c TU |
875 | } |
876 | ||
877 | #define GEN_FW_RANGE(s, e, d) \ | |
878 | { .start = (s), .end = (e), .domains = (d) } | |
1938e59a | 879 | |
895833bd | 880 | #define HAS_FWTABLE(dev_priv) \ |
3d16ca58 | 881 | (INTEL_GEN(dev_priv) >= 9 || \ |
895833bd TU |
882 | IS_CHERRYVIEW(dev_priv) || \ |
883 | IS_VALLEYVIEW(dev_priv)) | |
884 | ||
b0081239 | 885 | /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */ |
9fc1117c TU |
886 | static const struct intel_forcewake_range __vlv_fw_ranges[] = { |
887 | GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER), | |
888 | GEN_FW_RANGE(0x5000, 0x7fff, FORCEWAKE_RENDER), | |
889 | GEN_FW_RANGE(0xb000, 0x11fff, FORCEWAKE_RENDER), | |
9fc1117c TU |
890 | GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA), |
891 | GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_MEDIA), | |
b0081239 | 892 | GEN_FW_RANGE(0x2e000, 0x2ffff, FORCEWAKE_RENDER), |
9fc1117c TU |
893 | GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA), |
894 | }; | |
1938e59a | 895 | |
272c7e52 | 896 | #define __fwtable_reg_read_fw_domains(uncore, offset) \ |
6863b76c TU |
897 | ({ \ |
898 | enum forcewake_domains __fwd = 0; \ | |
0dd356bb | 899 | if (NEEDS_FORCE_WAKE((offset))) \ |
272c7e52 | 900 | __fwd = find_fw_domain(uncore, offset); \ |
6863b76c TU |
901 | __fwd; \ |
902 | }) | |
903 | ||
272c7e52 | 904 | #define __gen11_fwtable_reg_read_fw_domains(uncore, offset) \ |
c9f8d187 | 905 | find_fw_domain(uncore, offset) |
a89a70a8 | 906 | |
cf82d9dd MT |
907 | #define __gen12_fwtable_reg_read_fw_domains(uncore, offset) \ |
908 | find_fw_domain(uncore, offset) | |
909 | ||
47188574 | 910 | /* *Must* be sorted by offset! See intel_shadow_table_check(). */ |
6863b76c | 911 | static const i915_reg_t gen8_shadowed_regs[] = { |
47188574 TU |
912 | RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */ |
913 | GEN6_RPNSWREQ, /* 0xA008 */ | |
914 | GEN6_RC_VIDEO_FREQ, /* 0xA00C */ | |
915 | RING_TAIL(GEN6_BSD_RING_BASE), /* 0x12000 (base) */ | |
916 | RING_TAIL(VEBOX_RING_BASE), /* 0x1a000 (base) */ | |
917 | RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */ | |
6863b76c TU |
918 | /* TODO: Other registers are not yet used */ |
919 | }; | |
920 | ||
a89a70a8 DCS |
921 | static const i915_reg_t gen11_shadowed_regs[] = { |
922 | RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */ | |
923 | GEN6_RPNSWREQ, /* 0xA008 */ | |
924 | GEN6_RC_VIDEO_FREQ, /* 0xA00C */ | |
925 | RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */ | |
926 | RING_TAIL(GEN11_BSD_RING_BASE), /* 0x1C0000 (base) */ | |
927 | RING_TAIL(GEN11_BSD2_RING_BASE), /* 0x1C4000 (base) */ | |
928 | RING_TAIL(GEN11_VEBOX_RING_BASE), /* 0x1C8000 (base) */ | |
929 | RING_TAIL(GEN11_BSD3_RING_BASE), /* 0x1D0000 (base) */ | |
930 | RING_TAIL(GEN11_BSD4_RING_BASE), /* 0x1D4000 (base) */ | |
931 | RING_TAIL(GEN11_VEBOX2_RING_BASE), /* 0x1D8000 (base) */ | |
932 | /* TODO: Other registers are not yet used */ | |
933 | }; | |
934 | ||
cf82d9dd MT |
935 | static const i915_reg_t gen12_shadowed_regs[] = { |
936 | RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */ | |
937 | GEN6_RPNSWREQ, /* 0xA008 */ | |
938 | GEN6_RC_VIDEO_FREQ, /* 0xA00C */ | |
939 | RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */ | |
940 | RING_TAIL(GEN11_BSD_RING_BASE), /* 0x1C0000 (base) */ | |
941 | RING_TAIL(GEN11_BSD2_RING_BASE), /* 0x1C4000 (base) */ | |
942 | RING_TAIL(GEN11_VEBOX_RING_BASE), /* 0x1C8000 (base) */ | |
943 | RING_TAIL(GEN11_BSD3_RING_BASE), /* 0x1D0000 (base) */ | |
944 | RING_TAIL(GEN11_BSD4_RING_BASE), /* 0x1D4000 (base) */ | |
945 | RING_TAIL(GEN11_VEBOX2_RING_BASE), /* 0x1D8000 (base) */ | |
946 | /* TODO: Other registers are not yet used */ | |
947 | }; | |
948 | ||
9480dbf0 | 949 | static int mmio_reg_cmp(u32 key, const i915_reg_t *reg) |
5a659383 | 950 | { |
9480dbf0 | 951 | u32 offset = i915_mmio_reg_offset(*reg); |
5a659383 | 952 | |
9480dbf0 | 953 | if (key < offset) |
5a659383 | 954 | return -1; |
9480dbf0 | 955 | else if (key > offset) |
5a659383 TU |
956 | return 1; |
957 | else | |
958 | return 0; | |
959 | } | |
960 | ||
a89a70a8 DCS |
961 | #define __is_genX_shadowed(x) \ |
962 | static bool is_gen##x##_shadowed(u32 offset) \ | |
963 | { \ | |
964 | const i915_reg_t *regs = gen##x##_shadowed_regs; \ | |
965 | return BSEARCH(offset, regs, ARRAY_SIZE(gen##x##_shadowed_regs), \ | |
966 | mmio_reg_cmp); \ | |
6863b76c TU |
967 | } |
968 | ||
a89a70a8 DCS |
969 | __is_genX_shadowed(8) |
970 | __is_genX_shadowed(11) | |
cf82d9dd | 971 | __is_genX_shadowed(12) |
a89a70a8 | 972 | |
ccb2acea DCS |
973 | static enum forcewake_domains |
974 | gen6_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) | |
975 | { | |
976 | return FORCEWAKE_RENDER; | |
977 | } | |
978 | ||
272c7e52 | 979 | #define __gen8_reg_write_fw_domains(uncore, offset) \ |
6863b76c TU |
980 | ({ \ |
981 | enum forcewake_domains __fwd; \ | |
982 | if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(offset)) \ | |
983 | __fwd = FORCEWAKE_RENDER; \ | |
984 | else \ | |
985 | __fwd = 0; \ | |
986 | __fwd; \ | |
987 | }) | |
988 | ||
b0081239 | 989 | /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */ |
9fc1117c TU |
990 | static const struct intel_forcewake_range __chv_fw_ranges[] = { |
991 | GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER), | |
b0081239 | 992 | GEN_FW_RANGE(0x4000, 0x4fff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), |
9fc1117c | 993 | GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), |
b0081239 | 994 | GEN_FW_RANGE(0x8000, 0x82ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), |
9fc1117c | 995 | GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), |
b0081239 | 996 | GEN_FW_RANGE(0x8500, 0x85ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), |
9fc1117c | 997 | GEN_FW_RANGE(0x8800, 0x88ff, FORCEWAKE_MEDIA), |
b0081239 TU |
998 | GEN_FW_RANGE(0x9000, 0xafff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), |
999 | GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER), | |
9fc1117c | 1000 | GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA), |
b0081239 TU |
1001 | GEN_FW_RANGE(0xe000, 0xe7ff, FORCEWAKE_RENDER), |
1002 | GEN_FW_RANGE(0xf000, 0xffff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), | |
9fc1117c TU |
1003 | GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA), |
1004 | GEN_FW_RANGE(0x1a000, 0x1bfff, FORCEWAKE_MEDIA), | |
1005 | GEN_FW_RANGE(0x1e800, 0x1e9ff, FORCEWAKE_MEDIA), | |
1006 | GEN_FW_RANGE(0x30000, 0x37fff, FORCEWAKE_MEDIA), | |
9fc1117c | 1007 | }; |
38fb6a40 | 1008 | |
272c7e52 | 1009 | #define __fwtable_reg_write_fw_domains(uncore, offset) \ |
6863b76c TU |
1010 | ({ \ |
1011 | enum forcewake_domains __fwd = 0; \ | |
0dd356bb | 1012 | if (NEEDS_FORCE_WAKE((offset)) && !is_gen8_shadowed(offset)) \ |
272c7e52 | 1013 | __fwd = find_fw_domain(uncore, offset); \ |
6863b76c TU |
1014 | __fwd; \ |
1015 | }) | |
1016 | ||
272c7e52 | 1017 | #define __gen11_fwtable_reg_write_fw_domains(uncore, offset) \ |
a89a70a8 DCS |
1018 | ({ \ |
1019 | enum forcewake_domains __fwd = 0; \ | |
c9f8d187 MK |
1020 | const u32 __offset = (offset); \ |
1021 | if (!is_gen11_shadowed(__offset)) \ | |
1022 | __fwd = find_fw_domain(uncore, __offset); \ | |
a89a70a8 DCS |
1023 | __fwd; \ |
1024 | }) | |
1025 | ||
cf82d9dd MT |
1026 | #define __gen12_fwtable_reg_write_fw_domains(uncore, offset) \ |
1027 | ({ \ | |
1028 | enum forcewake_domains __fwd = 0; \ | |
1029 | const u32 __offset = (offset); \ | |
1030 | if (!is_gen12_shadowed(__offset)) \ | |
1031 | __fwd = find_fw_domain(uncore, __offset); \ | |
1032 | __fwd; \ | |
1033 | }) | |
1034 | ||
b0081239 | 1035 | /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */ |
9fc1117c | 1036 | static const struct intel_forcewake_range __gen9_fw_ranges[] = { |
0dd356bb | 1037 | GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER), |
9fc1117c TU |
1038 | GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */ |
1039 | GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), | |
0dd356bb | 1040 | GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER), |
9fc1117c | 1041 | GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER), |
0dd356bb | 1042 | GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER), |
9fc1117c | 1043 | GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), |
0dd356bb | 1044 | GEN_FW_RANGE(0x8000, 0x812f, FORCEWAKE_BLITTER), |
b0081239 | 1045 | GEN_FW_RANGE(0x8130, 0x813f, FORCEWAKE_MEDIA), |
9fc1117c | 1046 | GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER), |
0dd356bb | 1047 | GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER), |
9fc1117c | 1048 | GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), |
0dd356bb | 1049 | GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_BLITTER), |
b0081239 | 1050 | GEN_FW_RANGE(0x8800, 0x89ff, FORCEWAKE_MEDIA), |
0dd356bb | 1051 | GEN_FW_RANGE(0x8a00, 0x8bff, FORCEWAKE_BLITTER), |
9fc1117c | 1052 | GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER), |
0dd356bb | 1053 | GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER), |
9fc1117c | 1054 | GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), |
0dd356bb | 1055 | GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER), |
b0081239 | 1056 | GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER), |
78424c92 | 1057 | GEN_FW_RANGE(0xb480, 0xcfff, FORCEWAKE_BLITTER), |
9fc1117c | 1058 | GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA), |
0dd356bb | 1059 | GEN_FW_RANGE(0xd800, 0xdfff, FORCEWAKE_BLITTER), |
b0081239 | 1060 | GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER), |
0dd356bb | 1061 | GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_BLITTER), |
9fc1117c | 1062 | GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA), |
0dd356bb | 1063 | GEN_FW_RANGE(0x14000, 0x19fff, FORCEWAKE_BLITTER), |
9fc1117c | 1064 | GEN_FW_RANGE(0x1a000, 0x1e9ff, FORCEWAKE_MEDIA), |
0dd356bb | 1065 | GEN_FW_RANGE(0x1ea00, 0x243ff, FORCEWAKE_BLITTER), |
b0081239 | 1066 | GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER), |
0dd356bb | 1067 | GEN_FW_RANGE(0x24800, 0x2ffff, FORCEWAKE_BLITTER), |
9fc1117c TU |
1068 | GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA), |
1069 | }; | |
6863b76c | 1070 | |
a89a70a8 DCS |
1071 | /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */ |
1072 | static const struct intel_forcewake_range __gen11_fw_ranges[] = { | |
1073 | GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER), | |
1074 | GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */ | |
1075 | GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), | |
1076 | GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER), | |
1077 | GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER), | |
1078 | GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER), | |
1079 | GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), | |
1080 | GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_BLITTER), | |
1081 | GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER), | |
1082 | GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER), | |
1083 | GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), | |
1084 | GEN_FW_RANGE(0x8500, 0x8bff, FORCEWAKE_BLITTER), | |
1085 | GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER), | |
1086 | GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER), | |
1087 | GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_ALL), | |
1088 | GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER), | |
1089 | GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER), | |
c9f8d187 MK |
1090 | GEN_FW_RANGE(0xb480, 0xdeff, FORCEWAKE_BLITTER), |
1091 | GEN_FW_RANGE(0xdf00, 0xe8ff, FORCEWAKE_RENDER), | |
1092 | GEN_FW_RANGE(0xe900, 0x16dff, FORCEWAKE_BLITTER), | |
1093 | GEN_FW_RANGE(0x16e00, 0x19fff, FORCEWAKE_RENDER), | |
1094 | GEN_FW_RANGE(0x1a000, 0x243ff, FORCEWAKE_BLITTER), | |
a89a70a8 DCS |
1095 | GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER), |
1096 | GEN_FW_RANGE(0x24800, 0x3ffff, FORCEWAKE_BLITTER), | |
1097 | GEN_FW_RANGE(0x40000, 0x1bffff, 0), | |
1098 | GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), | |
1099 | GEN_FW_RANGE(0x1c4000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX1), | |
1100 | GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0), | |
1101 | GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_BLITTER), | |
1102 | GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2), | |
1103 | GEN_FW_RANGE(0x1d4000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX3), | |
1104 | GEN_FW_RANGE(0x1d8000, 0x1dbfff, FORCEWAKE_MEDIA_VEBOX1) | |
1105 | }; | |
1106 | ||
cf82d9dd MT |
1107 | /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */ |
1108 | static const struct intel_forcewake_range __gen12_fw_ranges[] = { | |
1109 | GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER), | |
1110 | GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */ | |
1111 | GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), | |
1112 | GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER), | |
1113 | GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER), | |
1114 | GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER), | |
1115 | GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), | |
1116 | GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_BLITTER), | |
1117 | GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER), | |
1118 | GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER), | |
1119 | GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), | |
1120 | GEN_FW_RANGE(0x8500, 0x8bff, FORCEWAKE_BLITTER), | |
1121 | GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER), | |
1122 | GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER), | |
1123 | GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_ALL), | |
1124 | GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER), | |
1125 | GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER), | |
1126 | GEN_FW_RANGE(0xb480, 0xdfff, FORCEWAKE_BLITTER), | |
1127 | GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER), | |
1128 | GEN_FW_RANGE(0xe900, 0x147ff, FORCEWAKE_BLITTER), | |
1129 | GEN_FW_RANGE(0x14800, 0x148ff, FORCEWAKE_RENDER), | |
1130 | GEN_FW_RANGE(0x14900, 0x19fff, FORCEWAKE_BLITTER), | |
1131 | GEN_FW_RANGE(0x1a000, 0x1a7ff, FORCEWAKE_RENDER), | |
1132 | GEN_FW_RANGE(0x1a800, 0x1afff, FORCEWAKE_BLITTER), | |
1133 | GEN_FW_RANGE(0x1b000, 0x1bfff, FORCEWAKE_RENDER), | |
1134 | GEN_FW_RANGE(0x1c000, 0x243ff, FORCEWAKE_BLITTER), | |
1135 | GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER), | |
1136 | GEN_FW_RANGE(0x24800, 0x3ffff, FORCEWAKE_BLITTER), | |
1137 | GEN_FW_RANGE(0x40000, 0x1bffff, 0), | |
1138 | GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), | |
1139 | GEN_FW_RANGE(0x1c4000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX1), | |
1140 | GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0), | |
1141 | GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_BLITTER), | |
1142 | GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2), | |
1143 | GEN_FW_RANGE(0x1d4000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX3), | |
1144 | GEN_FW_RANGE(0x1d8000, 0x1dbfff, FORCEWAKE_MEDIA_VEBOX1) | |
1145 | }; | |
1146 | ||
907b28c5 | 1147 | static void |
6ebc9692 | 1148 | ilk_dummy_write(struct intel_uncore *uncore) |
907b28c5 CW |
1149 | { |
1150 | /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up | |
1151 | * the chip from rc6 before touching it for real. MI_MODE is masked, | |
1152 | * hence harmless to write 0 into. */ | |
6cc5ca76 | 1153 | __raw_uncore_write32(uncore, MI_MODE, 0); |
907b28c5 CW |
1154 | } |
1155 | ||
1156 | static void | |
2cf7bf6f | 1157 | __unclaimed_reg_debug(struct intel_uncore *uncore, |
9c053501 MK |
1158 | const i915_reg_t reg, |
1159 | const bool read, | |
1160 | const bool before) | |
907b28c5 | 1161 | { |
a9f236d1 PB |
1162 | if (drm_WARN(&uncore->i915->drm, |
1163 | check_for_unclaimed_mmio(uncore) && !before, | |
1164 | "Unclaimed %s register 0x%x\n", | |
1165 | read ? "read from" : "write to", | |
1166 | i915_mmio_reg_offset(reg))) | |
4f044a88 MW |
1167 | /* Only report the first N failures */ |
1168 | i915_modparams.mmio_debug--; | |
907b28c5 CW |
1169 | } |
1170 | ||
9c053501 | 1171 | static inline void |
2cf7bf6f | 1172 | unclaimed_reg_debug(struct intel_uncore *uncore, |
9c053501 MK |
1173 | const i915_reg_t reg, |
1174 | const bool read, | |
1175 | const bool before) | |
1176 | { | |
4f044a88 | 1177 | if (likely(!i915_modparams.mmio_debug)) |
9c053501 MK |
1178 | return; |
1179 | ||
0a9b2630 DCS |
1180 | /* interrupts are disabled and re-enabled around uncore->lock usage */ |
1181 | lockdep_assert_held(&uncore->lock); | |
1182 | ||
1183 | if (before) | |
1184 | spin_lock(&uncore->debug->lock); | |
1185 | ||
2cf7bf6f | 1186 | __unclaimed_reg_debug(uncore, reg, read, before); |
0a9b2630 DCS |
1187 | |
1188 | if (!before) | |
1189 | spin_unlock(&uncore->debug->lock); | |
9c053501 MK |
1190 | } |
1191 | ||
51f67885 | 1192 | #define GEN2_READ_HEADER(x) \ |
5d738795 | 1193 | u##x val = 0; \ |
87b391b9 | 1194 | assert_rpm_wakelock_held(uncore->rpm); |
5d738795 | 1195 | |
51f67885 | 1196 | #define GEN2_READ_FOOTER \ |
5d738795 BW |
1197 | trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ |
1198 | return val | |
1199 | ||
51f67885 | 1200 | #define __gen2_read(x) \ |
0b274481 | 1201 | static u##x \ |
a2b4abfc | 1202 | gen2_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \ |
51f67885 | 1203 | GEN2_READ_HEADER(x); \ |
6cc5ca76 | 1204 | val = __raw_uncore_read##x(uncore, reg); \ |
51f67885 | 1205 | GEN2_READ_FOOTER; \ |
3967018e BW |
1206 | } |
1207 | ||
1208 | #define __gen5_read(x) \ | |
1209 | static u##x \ | |
a2b4abfc | 1210 | gen5_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \ |
51f67885 | 1211 | GEN2_READ_HEADER(x); \ |
6ebc9692 | 1212 | ilk_dummy_write(uncore); \ |
6cc5ca76 | 1213 | val = __raw_uncore_read##x(uncore, reg); \ |
51f67885 | 1214 | GEN2_READ_FOOTER; \ |
3967018e BW |
1215 | } |
1216 | ||
51f67885 CW |
1217 | __gen5_read(8) |
1218 | __gen5_read(16) | |
1219 | __gen5_read(32) | |
1220 | __gen5_read(64) | |
1221 | __gen2_read(8) | |
1222 | __gen2_read(16) | |
1223 | __gen2_read(32) | |
1224 | __gen2_read(64) | |
1225 | ||
1226 | #undef __gen5_read | |
1227 | #undef __gen2_read | |
1228 | ||
1229 | #undef GEN2_READ_FOOTER | |
1230 | #undef GEN2_READ_HEADER | |
1231 | ||
1232 | #define GEN6_READ_HEADER(x) \ | |
f0f59a00 | 1233 | u32 offset = i915_mmio_reg_offset(reg); \ |
51f67885 CW |
1234 | unsigned long irqflags; \ |
1235 | u##x val = 0; \ | |
87b391b9 | 1236 | assert_rpm_wakelock_held(uncore->rpm); \ |
272c7e52 | 1237 | spin_lock_irqsave(&uncore->lock, irqflags); \ |
2cf7bf6f | 1238 | unclaimed_reg_debug(uncore, reg, true, true) |
51f67885 CW |
1239 | |
1240 | #define GEN6_READ_FOOTER \ | |
2cf7bf6f | 1241 | unclaimed_reg_debug(uncore, reg, true, false); \ |
272c7e52 | 1242 | spin_unlock_irqrestore(&uncore->lock, irqflags); \ |
51f67885 CW |
1243 | trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ |
1244 | return val | |
1245 | ||
f568eeee | 1246 | static noinline void ___force_wake_auto(struct intel_uncore *uncore, |
c521b0c8 | 1247 | enum forcewake_domains fw_domains) |
b2cff0db CW |
1248 | { |
1249 | struct intel_uncore_forcewake_domain *domain; | |
d2dc94bc CW |
1250 | unsigned int tmp; |
1251 | ||
f568eeee | 1252 | GEM_BUG_ON(fw_domains & ~uncore->fw_domains); |
b2cff0db | 1253 | |
f568eeee | 1254 | for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) |
c521b0c8 TU |
1255 | fw_domain_arm_timer(domain); |
1256 | ||
f568eeee | 1257 | uncore->funcs.force_wake_get(uncore, fw_domains); |
c521b0c8 TU |
1258 | } |
1259 | ||
f568eeee | 1260 | static inline void __force_wake_auto(struct intel_uncore *uncore, |
c521b0c8 TU |
1261 | enum forcewake_domains fw_domains) |
1262 | { | |
77adbd8f | 1263 | GEM_BUG_ON(!fw_domains); |
b2cff0db | 1264 | |
003342a5 | 1265 | /* Turn on all requested but inactive supported forcewake domains. */ |
f568eeee DCS |
1266 | fw_domains &= uncore->fw_domains; |
1267 | fw_domains &= ~uncore->fw_domains_active; | |
b2cff0db | 1268 | |
c521b0c8 | 1269 | if (fw_domains) |
f568eeee | 1270 | ___force_wake_auto(uncore, fw_domains); |
b2cff0db CW |
1271 | } |
1272 | ||
ccfceda2 | 1273 | #define __gen_read(func, x) \ |
3967018e | 1274 | static u##x \ |
a2b4abfc | 1275 | func##_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \ |
6863b76c | 1276 | enum forcewake_domains fw_engine; \ |
51f67885 | 1277 | GEN6_READ_HEADER(x); \ |
272c7e52 | 1278 | fw_engine = __##func##_reg_read_fw_domains(uncore, offset); \ |
6a42d0f4 | 1279 | if (fw_engine) \ |
272c7e52 | 1280 | __force_wake_auto(uncore, fw_engine); \ |
6cc5ca76 | 1281 | val = __raw_uncore_read##x(uncore, reg); \ |
51f67885 | 1282 | GEN6_READ_FOOTER; \ |
940aece4 | 1283 | } |
ccb2acea DCS |
1284 | |
1285 | #define __gen_reg_read_funcs(func) \ | |
1286 | static enum forcewake_domains \ | |
1287 | func##_reg_read_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) { \ | |
1288 | return __##func##_reg_read_fw_domains(uncore, i915_mmio_reg_offset(reg)); \ | |
1289 | } \ | |
1290 | \ | |
1291 | __gen_read(func, 8) \ | |
1292 | __gen_read(func, 16) \ | |
1293 | __gen_read(func, 32) \ | |
1294 | __gen_read(func, 64) | |
1295 | ||
cf82d9dd | 1296 | __gen_reg_read_funcs(gen12_fwtable); |
ccb2acea DCS |
1297 | __gen_reg_read_funcs(gen11_fwtable); |
1298 | __gen_reg_read_funcs(fwtable); | |
1299 | __gen_reg_read_funcs(gen6); | |
1300 | ||
1301 | #undef __gen_reg_read_funcs | |
51f67885 CW |
1302 | #undef GEN6_READ_FOOTER |
1303 | #undef GEN6_READ_HEADER | |
5d738795 | 1304 | |
51f67885 | 1305 | #define GEN2_WRITE_HEADER \ |
5d738795 | 1306 | trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ |
87b391b9 | 1307 | assert_rpm_wakelock_held(uncore->rpm); \ |
907b28c5 | 1308 | |
51f67885 | 1309 | #define GEN2_WRITE_FOOTER |
0d965301 | 1310 | |
51f67885 | 1311 | #define __gen2_write(x) \ |
0b274481 | 1312 | static void \ |
a2b4abfc | 1313 | gen2_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ |
51f67885 | 1314 | GEN2_WRITE_HEADER; \ |
6cc5ca76 | 1315 | __raw_uncore_write##x(uncore, reg, val); \ |
51f67885 | 1316 | GEN2_WRITE_FOOTER; \ |
4032ef43 BW |
1317 | } |
1318 | ||
1319 | #define __gen5_write(x) \ | |
1320 | static void \ | |
a2b4abfc | 1321 | gen5_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ |
51f67885 | 1322 | GEN2_WRITE_HEADER; \ |
6ebc9692 | 1323 | ilk_dummy_write(uncore); \ |
6cc5ca76 | 1324 | __raw_uncore_write##x(uncore, reg, val); \ |
51f67885 | 1325 | GEN2_WRITE_FOOTER; \ |
4032ef43 BW |
1326 | } |
1327 | ||
51f67885 CW |
1328 | __gen5_write(8) |
1329 | __gen5_write(16) | |
1330 | __gen5_write(32) | |
51f67885 CW |
1331 | __gen2_write(8) |
1332 | __gen2_write(16) | |
1333 | __gen2_write(32) | |
51f67885 CW |
1334 | |
1335 | #undef __gen5_write | |
1336 | #undef __gen2_write | |
1337 | ||
1338 | #undef GEN2_WRITE_FOOTER | |
1339 | #undef GEN2_WRITE_HEADER | |
1340 | ||
1341 | #define GEN6_WRITE_HEADER \ | |
f0f59a00 | 1342 | u32 offset = i915_mmio_reg_offset(reg); \ |
51f67885 CW |
1343 | unsigned long irqflags; \ |
1344 | trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ | |
87b391b9 | 1345 | assert_rpm_wakelock_held(uncore->rpm); \ |
272c7e52 | 1346 | spin_lock_irqsave(&uncore->lock, irqflags); \ |
2cf7bf6f | 1347 | unclaimed_reg_debug(uncore, reg, false, true) |
51f67885 CW |
1348 | |
1349 | #define GEN6_WRITE_FOOTER \ | |
2cf7bf6f | 1350 | unclaimed_reg_debug(uncore, reg, false, false); \ |
272c7e52 | 1351 | spin_unlock_irqrestore(&uncore->lock, irqflags) |
51f67885 | 1352 | |
4032ef43 BW |
1353 | #define __gen6_write(x) \ |
1354 | static void \ | |
a2b4abfc | 1355 | gen6_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ |
51f67885 | 1356 | GEN6_WRITE_HEADER; \ |
a338908c | 1357 | if (NEEDS_FORCE_WAKE(offset)) \ |
6ebc9692 | 1358 | __gen6_gt_wait_for_fifo(uncore); \ |
6cc5ca76 | 1359 | __raw_uncore_write##x(uncore, reg, val); \ |
51f67885 | 1360 | GEN6_WRITE_FOOTER; \ |
4032ef43 | 1361 | } |
ccb2acea DCS |
1362 | __gen6_write(8) |
1363 | __gen6_write(16) | |
1364 | __gen6_write(32) | |
4032ef43 | 1365 | |
ccfceda2 | 1366 | #define __gen_write(func, x) \ |
ab2aa47e | 1367 | static void \ |
a2b4abfc | 1368 | func##_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ |
6863b76c | 1369 | enum forcewake_domains fw_engine; \ |
51f67885 | 1370 | GEN6_WRITE_HEADER; \ |
272c7e52 | 1371 | fw_engine = __##func##_reg_write_fw_domains(uncore, offset); \ |
6a42d0f4 | 1372 | if (fw_engine) \ |
272c7e52 | 1373 | __force_wake_auto(uncore, fw_engine); \ |
6cc5ca76 | 1374 | __raw_uncore_write##x(uncore, reg, val); \ |
51f67885 | 1375 | GEN6_WRITE_FOOTER; \ |
1938e59a | 1376 | } |
4032ef43 | 1377 | |
ccb2acea DCS |
1378 | #define __gen_reg_write_funcs(func) \ |
1379 | static enum forcewake_domains \ | |
1380 | func##_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) { \ | |
1381 | return __##func##_reg_write_fw_domains(uncore, i915_mmio_reg_offset(reg)); \ | |
1382 | } \ | |
1383 | \ | |
1384 | __gen_write(func, 8) \ | |
1385 | __gen_write(func, 16) \ | |
1386 | __gen_write(func, 32) | |
1387 | ||
cf82d9dd | 1388 | __gen_reg_write_funcs(gen12_fwtable); |
ccb2acea DCS |
1389 | __gen_reg_write_funcs(gen11_fwtable); |
1390 | __gen_reg_write_funcs(fwtable); | |
1391 | __gen_reg_write_funcs(gen8); | |
1392 | ||
1393 | #undef __gen_reg_write_funcs | |
51f67885 CW |
1394 | #undef GEN6_WRITE_FOOTER |
1395 | #undef GEN6_WRITE_HEADER | |
907b28c5 | 1396 | |
ccb2acea | 1397 | #define ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, x) \ |
43d942a7 | 1398 | do { \ |
f7de5027 DCS |
1399 | (uncore)->funcs.mmio_writeb = x##_write8; \ |
1400 | (uncore)->funcs.mmio_writew = x##_write16; \ | |
1401 | (uncore)->funcs.mmio_writel = x##_write32; \ | |
43d942a7 YZ |
1402 | } while (0) |
1403 | ||
ccb2acea | 1404 | #define ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, x) \ |
43d942a7 | 1405 | do { \ |
f7de5027 DCS |
1406 | (uncore)->funcs.mmio_readb = x##_read8; \ |
1407 | (uncore)->funcs.mmio_readw = x##_read16; \ | |
1408 | (uncore)->funcs.mmio_readl = x##_read32; \ | |
1409 | (uncore)->funcs.mmio_readq = x##_read64; \ | |
43d942a7 YZ |
1410 | } while (0) |
1411 | ||
ccb2acea DCS |
1412 | #define ASSIGN_WRITE_MMIO_VFUNCS(uncore, x) \ |
1413 | do { \ | |
1414 | ASSIGN_RAW_WRITE_MMIO_VFUNCS((uncore), x); \ | |
1415 | (uncore)->funcs.write_fw_domains = x##_reg_write_fw_domains; \ | |
1416 | } while (0) | |
1417 | ||
1418 | #define ASSIGN_READ_MMIO_VFUNCS(uncore, x) \ | |
1419 | do { \ | |
1420 | ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, x); \ | |
1421 | (uncore)->funcs.read_fw_domains = x##_reg_read_fw_domains; \ | |
1422 | } while (0) | |
05a2fb15 | 1423 | |
f833cdb0 DCS |
1424 | static int __fw_domain_init(struct intel_uncore *uncore, |
1425 | enum forcewake_domain_id domain_id, | |
1426 | i915_reg_t reg_set, | |
1427 | i915_reg_t reg_ack) | |
05a2fb15 MK |
1428 | { |
1429 | struct intel_uncore_forcewake_domain *d; | |
1430 | ||
f833cdb0 DCS |
1431 | GEM_BUG_ON(domain_id >= FW_DOMAIN_ID_COUNT); |
1432 | GEM_BUG_ON(uncore->fw_domain[domain_id]); | |
05a2fb15 | 1433 | |
50d84418 | 1434 | if (i915_inject_probe_failure(uncore->i915)) |
f833cdb0 | 1435 | return -ENOMEM; |
05a2fb15 | 1436 | |
f833cdb0 DCS |
1437 | d = kzalloc(sizeof(*d), GFP_KERNEL); |
1438 | if (!d) | |
1439 | return -ENOMEM; | |
05a2fb15 | 1440 | |
a9f236d1 PB |
1441 | drm_WARN_ON(&uncore->i915->drm, !i915_mmio_reg_valid(reg_set)); |
1442 | drm_WARN_ON(&uncore->i915->drm, !i915_mmio_reg_valid(reg_ack)); | |
6e3955a5 | 1443 | |
f833cdb0 | 1444 | d->uncore = uncore; |
05a2fb15 | 1445 | d->wake_count = 0; |
25286aac DCS |
1446 | d->reg_set = uncore->regs + i915_mmio_reg_offset(reg_set); |
1447 | d->reg_ack = uncore->regs + i915_mmio_reg_offset(reg_ack); | |
05a2fb15 | 1448 | |
05a2fb15 MK |
1449 | d->id = domain_id; |
1450 | ||
33c582c1 TU |
1451 | BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER)); |
1452 | BUILD_BUG_ON(FORCEWAKE_BLITTER != (1 << FW_DOMAIN_ID_BLITTER)); | |
1453 | BUILD_BUG_ON(FORCEWAKE_MEDIA != (1 << FW_DOMAIN_ID_MEDIA)); | |
a89a70a8 DCS |
1454 | BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX0)); |
1455 | BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX1)); | |
1456 | BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX2 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX2)); | |
1457 | BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX3 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX3)); | |
1458 | BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX0)); | |
1459 | BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX1)); | |
1460 | ||
d2dc94bc | 1461 | d->mask = BIT(domain_id); |
33c582c1 | 1462 | |
a57a4a67 TU |
1463 | hrtimer_init(&d->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); |
1464 | d->timer.function = intel_uncore_fw_release_timer; | |
05a2fb15 | 1465 | |
535d8d27 | 1466 | uncore->fw_domains |= BIT(domain_id); |
f9b3927a | 1467 | |
159367bb | 1468 | fw_domain_reset(d); |
f833cdb0 DCS |
1469 | |
1470 | uncore->fw_domain[domain_id] = d; | |
1471 | ||
1472 | return 0; | |
05a2fb15 MK |
1473 | } |
1474 | ||
f7de5027 | 1475 | static void fw_domain_fini(struct intel_uncore *uncore, |
26376a7e OM |
1476 | enum forcewake_domain_id domain_id) |
1477 | { | |
1478 | struct intel_uncore_forcewake_domain *d; | |
1479 | ||
f833cdb0 | 1480 | GEM_BUG_ON(domain_id >= FW_DOMAIN_ID_COUNT); |
26376a7e | 1481 | |
f833cdb0 DCS |
1482 | d = fetch_and_zero(&uncore->fw_domain[domain_id]); |
1483 | if (!d) | |
1484 | return; | |
26376a7e | 1485 | |
f833cdb0 | 1486 | uncore->fw_domains &= ~BIT(domain_id); |
a9f236d1 PB |
1487 | drm_WARN_ON(&uncore->i915->drm, d->wake_count); |
1488 | drm_WARN_ON(&uncore->i915->drm, hrtimer_cancel(&d->timer)); | |
f833cdb0 DCS |
1489 | kfree(d); |
1490 | } | |
26376a7e | 1491 | |
f833cdb0 DCS |
1492 | static void intel_uncore_fw_domains_fini(struct intel_uncore *uncore) |
1493 | { | |
1494 | struct intel_uncore_forcewake_domain *d; | |
1495 | int tmp; | |
1496 | ||
1497 | for_each_fw_domain(d, uncore, tmp) | |
1498 | fw_domain_fini(uncore, d->id); | |
26376a7e OM |
1499 | } |
1500 | ||
f833cdb0 | 1501 | static int intel_uncore_fw_domains_init(struct intel_uncore *uncore) |
0b274481 | 1502 | { |
01385758 | 1503 | struct drm_i915_private *i915 = uncore->i915; |
f833cdb0 | 1504 | int ret = 0; |
f7de5027 | 1505 | |
2e81bc61 | 1506 | GEM_BUG_ON(!intel_uncore_has_forcewake(uncore)); |
3225b2f9 | 1507 | |
f833cdb0 DCS |
1508 | #define fw_domain_init(uncore__, id__, set__, ack__) \ |
1509 | (ret ?: (ret = __fw_domain_init((uncore__), (id__), (set__), (ack__)))) | |
1510 | ||
f7de5027 | 1511 | if (INTEL_GEN(i915) >= 11) { |
a89a70a8 DCS |
1512 | int i; |
1513 | ||
f833cdb0 | 1514 | uncore->funcs.force_wake_get = fw_domains_get_with_fallback; |
f7de5027 DCS |
1515 | uncore->funcs.force_wake_put = fw_domains_put; |
1516 | fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, | |
a89a70a8 DCS |
1517 | FORCEWAKE_RENDER_GEN9, |
1518 | FORCEWAKE_ACK_RENDER_GEN9); | |
f7de5027 | 1519 | fw_domain_init(uncore, FW_DOMAIN_ID_BLITTER, |
a89a70a8 DCS |
1520 | FORCEWAKE_BLITTER_GEN9, |
1521 | FORCEWAKE_ACK_BLITTER_GEN9); | |
f833cdb0 | 1522 | |
a89a70a8 | 1523 | for (i = 0; i < I915_MAX_VCS; i++) { |
f7de5027 | 1524 | if (!HAS_ENGINE(i915, _VCS(i))) |
a89a70a8 DCS |
1525 | continue; |
1526 | ||
f7de5027 | 1527 | fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VDBOX0 + i, |
a89a70a8 DCS |
1528 | FORCEWAKE_MEDIA_VDBOX_GEN11(i), |
1529 | FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(i)); | |
1530 | } | |
1531 | for (i = 0; i < I915_MAX_VECS; i++) { | |
f7de5027 | 1532 | if (!HAS_ENGINE(i915, _VECS(i))) |
a89a70a8 DCS |
1533 | continue; |
1534 | ||
f7de5027 | 1535 | fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VEBOX0 + i, |
a89a70a8 DCS |
1536 | FORCEWAKE_MEDIA_VEBOX_GEN11(i), |
1537 | FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i)); | |
1538 | } | |
f7de5027 | 1539 | } else if (IS_GEN_RANGE(i915, 9, 10)) { |
f833cdb0 | 1540 | uncore->funcs.force_wake_get = fw_domains_get_with_fallback; |
f7de5027 DCS |
1541 | uncore->funcs.force_wake_put = fw_domains_put; |
1542 | fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, | |
05a2fb15 MK |
1543 | FORCEWAKE_RENDER_GEN9, |
1544 | FORCEWAKE_ACK_RENDER_GEN9); | |
f7de5027 | 1545 | fw_domain_init(uncore, FW_DOMAIN_ID_BLITTER, |
05a2fb15 MK |
1546 | FORCEWAKE_BLITTER_GEN9, |
1547 | FORCEWAKE_ACK_BLITTER_GEN9); | |
f7de5027 | 1548 | fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA, |
05a2fb15 | 1549 | FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9); |
f7de5027 DCS |
1550 | } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { |
1551 | uncore->funcs.force_wake_get = fw_domains_get; | |
1552 | uncore->funcs.force_wake_put = fw_domains_put; | |
1553 | fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, | |
05a2fb15 | 1554 | FORCEWAKE_VLV, FORCEWAKE_ACK_VLV); |
f7de5027 | 1555 | fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA, |
05a2fb15 | 1556 | FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV); |
f7de5027 DCS |
1557 | } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { |
1558 | uncore->funcs.force_wake_get = | |
05a2fb15 | 1559 | fw_domains_get_with_thread_status; |
f7de5027 DCS |
1560 | uncore->funcs.force_wake_put = fw_domains_put; |
1561 | fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, | |
05a2fb15 | 1562 | FORCEWAKE_MT, FORCEWAKE_ACK_HSW); |
f7de5027 | 1563 | } else if (IS_IVYBRIDGE(i915)) { |
0b274481 BW |
1564 | u32 ecobus; |
1565 | ||
1566 | /* IVB configs may use multi-threaded forcewake */ | |
1567 | ||
1568 | /* A small trick here - if the bios hasn't configured | |
1569 | * MT forcewake, and if the device is in RC6, then | |
1570 | * force_wake_mt_get will not wake the device and the | |
1571 | * ECOBUS read will return zero. Which will be | |
1572 | * (correctly) interpreted by the test below as MT | |
1573 | * forcewake being disabled. | |
1574 | */ | |
f7de5027 | 1575 | uncore->funcs.force_wake_get = |
05a2fb15 | 1576 | fw_domains_get_with_thread_status; |
f7de5027 | 1577 | uncore->funcs.force_wake_put = fw_domains_put; |
05a2fb15 | 1578 | |
f9b3927a MK |
1579 | /* We need to init first for ECOBUS access and then |
1580 | * determine later if we want to reinit, in case of MT access is | |
6ea2556f MK |
1581 | * not working. In this stage we don't know which flavour this |
1582 | * ivb is, so it is better to reset also the gen6 fw registers | |
1583 | * before the ecobus check. | |
f9b3927a | 1584 | */ |
6ea2556f | 1585 | |
6cc5ca76 | 1586 | __raw_uncore_write32(uncore, FORCEWAKE, 0); |
6ebc9692 | 1587 | __raw_posting_read(uncore, ECOBUS); |
6ea2556f | 1588 | |
f833cdb0 DCS |
1589 | ret = __fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, |
1590 | FORCEWAKE_MT, FORCEWAKE_MT_ACK); | |
1591 | if (ret) | |
1592 | goto out; | |
f9b3927a | 1593 | |
f7de5027 DCS |
1594 | spin_lock_irq(&uncore->lock); |
1595 | fw_domains_get_with_thread_status(uncore, FORCEWAKE_RENDER); | |
6cc5ca76 | 1596 | ecobus = __raw_uncore_read32(uncore, ECOBUS); |
f7de5027 DCS |
1597 | fw_domains_put(uncore, FORCEWAKE_RENDER); |
1598 | spin_unlock_irq(&uncore->lock); | |
0b274481 | 1599 | |
05a2fb15 | 1600 | if (!(ecobus & FORCEWAKE_MT_ENABLE)) { |
d0208cfa WK |
1601 | drm_info(&i915->drm, "No MT forcewake available on Ivybridge, this can result in issues\n"); |
1602 | drm_info(&i915->drm, "when using vblank-synced partial screen updates.\n"); | |
f833cdb0 | 1603 | fw_domain_fini(uncore, FW_DOMAIN_ID_RENDER); |
f7de5027 | 1604 | fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, |
05a2fb15 | 1605 | FORCEWAKE, FORCEWAKE_ACK); |
0b274481 | 1606 | } |
f7de5027 DCS |
1607 | } else if (IS_GEN(i915, 6)) { |
1608 | uncore->funcs.force_wake_get = | |
05a2fb15 | 1609 | fw_domains_get_with_thread_status; |
f7de5027 DCS |
1610 | uncore->funcs.force_wake_put = fw_domains_put; |
1611 | fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, | |
05a2fb15 | 1612 | FORCEWAKE, FORCEWAKE_ACK); |
0b274481 | 1613 | } |
3225b2f9 | 1614 | |
f833cdb0 DCS |
1615 | #undef fw_domain_init |
1616 | ||
3225b2f9 | 1617 | /* All future platforms are expected to require complex power gating */ |
48a1b8d4 | 1618 | drm_WARN_ON(&i915->drm, !ret && uncore->fw_domains == 0); |
f833cdb0 DCS |
1619 | |
1620 | out: | |
1621 | if (ret) | |
1622 | intel_uncore_fw_domains_fini(uncore); | |
1623 | ||
1624 | return ret; | |
f9b3927a MK |
1625 | } |
1626 | ||
f7de5027 | 1627 | #define ASSIGN_FW_DOMAINS_TABLE(uncore, d) \ |
15157970 | 1628 | { \ |
f7de5027 | 1629 | (uncore)->fw_domains_table = \ |
15157970 | 1630 | (struct intel_forcewake_range *)(d); \ |
f7de5027 | 1631 | (uncore)->fw_domains_table_entries = ARRAY_SIZE((d)); \ |
15157970 TU |
1632 | } |
1633 | ||
264ec1a8 HG |
1634 | static int i915_pmic_bus_access_notifier(struct notifier_block *nb, |
1635 | unsigned long action, void *data) | |
1636 | { | |
9102650f DCS |
1637 | struct intel_uncore *uncore = container_of(nb, |
1638 | struct intel_uncore, pmic_bus_access_nb); | |
264ec1a8 HG |
1639 | |
1640 | switch (action) { | |
1641 | case MBI_PMIC_BUS_ACCESS_BEGIN: | |
1642 | /* | |
1643 | * forcewake all now to make sure that we don't need to do a | |
1644 | * forcewake later which on systems where this notifier gets | |
1645 | * called requires the punit to access to the shared pmic i2c | |
1646 | * bus, which will be busy after this notification, leading to: | |
1647 | * "render: timed out waiting for forcewake ack request." | |
1648 | * errors. | |
ce30560c HG |
1649 | * |
1650 | * The notifier is unregistered during intel_runtime_suspend(), | |
1651 | * so it's ok to access the HW here without holding a RPM | |
1652 | * wake reference -> disable wakeref asserts for the time of | |
1653 | * the access. | |
264ec1a8 | 1654 | */ |
9102650f DCS |
1655 | disable_rpm_wakeref_asserts(uncore->rpm); |
1656 | intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); | |
1657 | enable_rpm_wakeref_asserts(uncore->rpm); | |
264ec1a8 HG |
1658 | break; |
1659 | case MBI_PMIC_BUS_ACCESS_END: | |
9102650f | 1660 | intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); |
264ec1a8 HG |
1661 | break; |
1662 | } | |
1663 | ||
1664 | return NOTIFY_OK; | |
1665 | } | |
1666 | ||
25286aac DCS |
1667 | static int uncore_mmio_setup(struct intel_uncore *uncore) |
1668 | { | |
01385758 | 1669 | struct drm_i915_private *i915 = uncore->i915; |
25286aac DCS |
1670 | struct pci_dev *pdev = i915->drm.pdev; |
1671 | int mmio_bar; | |
1672 | int mmio_size; | |
1673 | ||
1674 | mmio_bar = IS_GEN(i915, 2) ? 1 : 0; | |
1675 | /* | |
1676 | * Before gen4, the registers and the GTT are behind different BARs. | |
1677 | * However, from gen4 onwards, the registers and the GTT are shared | |
1678 | * in the same BAR, so we want to restrict this ioremap from | |
1679 | * clobbering the GTT which we want ioremap_wc instead. Fortunately, | |
1680 | * the register BAR remains the same size for all the earlier | |
1681 | * generations up to Ironlake. | |
1682 | */ | |
1683 | if (INTEL_GEN(i915) < 5) | |
1684 | mmio_size = 512 * 1024; | |
1685 | else | |
1686 | mmio_size = 2 * 1024 * 1024; | |
1687 | uncore->regs = pci_iomap(pdev, mmio_bar, mmio_size); | |
1688 | if (uncore->regs == NULL) { | |
d0208cfa | 1689 | drm_err(&i915->drm, "failed to map registers\n"); |
25286aac DCS |
1690 | return -EIO; |
1691 | } | |
1692 | ||
1693 | return 0; | |
1694 | } | |
1695 | ||
1696 | static void uncore_mmio_cleanup(struct intel_uncore *uncore) | |
1697 | { | |
01385758 | 1698 | struct pci_dev *pdev = uncore->i915->drm.pdev; |
25286aac DCS |
1699 | |
1700 | pci_iounmap(pdev, uncore->regs); | |
1701 | } | |
1702 | ||
01385758 DCS |
1703 | void intel_uncore_init_early(struct intel_uncore *uncore, |
1704 | struct drm_i915_private *i915) | |
6cbe8830 DCS |
1705 | { |
1706 | spin_lock_init(&uncore->lock); | |
01385758 DCS |
1707 | uncore->i915 = i915; |
1708 | uncore->rpm = &i915->runtime_pm; | |
0a9b2630 | 1709 | uncore->debug = &i915->mmio_debug; |
6cbe8830 | 1710 | } |
25286aac | 1711 | |
2e81bc61 | 1712 | static void uncore_raw_init(struct intel_uncore *uncore) |
f9b3927a | 1713 | { |
2e81bc61 | 1714 | GEM_BUG_ON(intel_uncore_has_forcewake(uncore)); |
25286aac | 1715 | |
2e81bc61 DCS |
1716 | if (IS_GEN(uncore->i915, 5)) { |
1717 | ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen5); | |
1718 | ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen5); | |
1719 | } else { | |
1720 | ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen2); | |
1721 | ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen2); | |
1722 | } | |
1723 | } | |
f7de5027 | 1724 | |
f833cdb0 | 1725 | static int uncore_forcewake_init(struct intel_uncore *uncore) |
2e81bc61 DCS |
1726 | { |
1727 | struct drm_i915_private *i915 = uncore->i915; | |
f833cdb0 | 1728 | int ret; |
cf9d2890 | 1729 | |
2e81bc61 | 1730 | GEM_BUG_ON(!intel_uncore_has_forcewake(uncore)); |
5a0ba777 | 1731 | |
f833cdb0 DCS |
1732 | ret = intel_uncore_fw_domains_init(uncore); |
1733 | if (ret) | |
1734 | return ret; | |
2e81bc61 | 1735 | forcewake_early_sanitize(uncore, 0); |
75714940 | 1736 | |
2e81bc61 | 1737 | if (IS_GEN_RANGE(i915, 6, 7)) { |
f7de5027 DCS |
1738 | ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6); |
1739 | ||
1740 | if (IS_VALLEYVIEW(i915)) { | |
1741 | ASSIGN_FW_DOMAINS_TABLE(uncore, __vlv_fw_ranges); | |
1742 | ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable); | |
e3b1895f | 1743 | } else { |
f7de5027 | 1744 | ASSIGN_READ_MMIO_VFUNCS(uncore, gen6); |
85ee17eb | 1745 | } |
f7de5027 DCS |
1746 | } else if (IS_GEN(i915, 8)) { |
1747 | if (IS_CHERRYVIEW(i915)) { | |
1748 | ASSIGN_FW_DOMAINS_TABLE(uncore, __chv_fw_ranges); | |
1749 | ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable); | |
1750 | ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable); | |
1938e59a | 1751 | } else { |
f7de5027 DCS |
1752 | ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen8); |
1753 | ASSIGN_READ_MMIO_VFUNCS(uncore, gen6); | |
1938e59a | 1754 | } |
f7de5027 DCS |
1755 | } else if (IS_GEN_RANGE(i915, 9, 10)) { |
1756 | ASSIGN_FW_DOMAINS_TABLE(uncore, __gen9_fw_ranges); | |
1757 | ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable); | |
1758 | ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable); | |
cf82d9dd | 1759 | } else if (IS_GEN(i915, 11)) { |
f7de5027 DCS |
1760 | ASSIGN_FW_DOMAINS_TABLE(uncore, __gen11_fw_ranges); |
1761 | ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen11_fwtable); | |
1762 | ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable); | |
cf82d9dd MT |
1763 | } else { |
1764 | ASSIGN_FW_DOMAINS_TABLE(uncore, __gen12_fw_ranges); | |
1765 | ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen12_fwtable); | |
1766 | ASSIGN_READ_MMIO_VFUNCS(uncore, gen12_fwtable); | |
3967018e | 1767 | } |
ed493883 | 1768 | |
2e81bc61 DCS |
1769 | uncore->pmic_bus_access_nb.notifier_call = i915_pmic_bus_access_notifier; |
1770 | iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb); | |
f833cdb0 DCS |
1771 | |
1772 | return 0; | |
2e81bc61 DCS |
1773 | } |
1774 | ||
1775 | int intel_uncore_init_mmio(struct intel_uncore *uncore) | |
1776 | { | |
1777 | struct drm_i915_private *i915 = uncore->i915; | |
1778 | int ret; | |
1779 | ||
1780 | ret = uncore_mmio_setup(uncore); | |
1781 | if (ret) | |
1782 | return ret; | |
1783 | ||
2e81bc61 DCS |
1784 | if (INTEL_GEN(i915) > 5 && !intel_vgpu_active(i915)) |
1785 | uncore->flags |= UNCORE_HAS_FORCEWAKE; | |
1786 | ||
f833cdb0 | 1787 | if (!intel_uncore_has_forcewake(uncore)) { |
2e81bc61 | 1788 | uncore_raw_init(uncore); |
f833cdb0 DCS |
1789 | } else { |
1790 | ret = uncore_forcewake_init(uncore); | |
1791 | if (ret) | |
1792 | goto out_mmio_cleanup; | |
1793 | } | |
2e81bc61 | 1794 | |
ccb2acea DCS |
1795 | /* make sure fw funcs are set if and only if we have fw*/ |
1796 | GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.force_wake_get); | |
1797 | GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.force_wake_put); | |
1798 | GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.read_fw_domains); | |
1799 | GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.write_fw_domains); | |
1800 | ||
2cf7bf6f DCS |
1801 | if (HAS_FPGA_DBG_UNCLAIMED(i915)) |
1802 | uncore->flags |= UNCORE_HAS_FPGA_DBG_UNCLAIMED; | |
1803 | ||
1804 | if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) | |
1805 | uncore->flags |= UNCORE_HAS_DBG_UNCLAIMED; | |
1806 | ||
1807 | if (IS_GEN_RANGE(i915, 6, 7)) | |
1808 | uncore->flags |= UNCORE_HAS_FIFO; | |
1809 | ||
2e81bc61 | 1810 | /* clear out unclaimed reg detection bit */ |
0a9b2630 | 1811 | if (intel_uncore_unclaimed_mmio(uncore)) |
d0208cfa | 1812 | drm_dbg(&i915->drm, "unclaimed mmio detected on uncore init, clearing\n"); |
25286aac DCS |
1813 | |
1814 | return 0; | |
f833cdb0 DCS |
1815 | |
1816 | out_mmio_cleanup: | |
1817 | uncore_mmio_cleanup(uncore); | |
1818 | ||
1819 | return ret; | |
0b274481 BW |
1820 | } |
1821 | ||
26376a7e OM |
1822 | /* |
1823 | * We might have detected that some engines are fused off after we initialized | |
1824 | * the forcewake domains. Prune them, to make sure they only reference existing | |
1825 | * engines. | |
1826 | */ | |
3de6f852 | 1827 | void intel_uncore_prune_mmio_domains(struct intel_uncore *uncore) |
26376a7e | 1828 | { |
01385758 | 1829 | struct drm_i915_private *i915 = uncore->i915; |
2e81bc61 DCS |
1830 | enum forcewake_domains fw_domains = uncore->fw_domains; |
1831 | enum forcewake_domain_id domain_id; | |
1832 | int i; | |
f7de5027 | 1833 | |
2e81bc61 DCS |
1834 | if (!intel_uncore_has_forcewake(uncore) || INTEL_GEN(i915) < 11) |
1835 | return; | |
26376a7e | 1836 | |
2e81bc61 DCS |
1837 | for (i = 0; i < I915_MAX_VCS; i++) { |
1838 | domain_id = FW_DOMAIN_ID_MEDIA_VDBOX0 + i; | |
26376a7e | 1839 | |
2e81bc61 DCS |
1840 | if (HAS_ENGINE(i915, _VCS(i))) |
1841 | continue; | |
26376a7e | 1842 | |
2e81bc61 DCS |
1843 | if (fw_domains & BIT(domain_id)) |
1844 | fw_domain_fini(uncore, domain_id); | |
1845 | } | |
26376a7e | 1846 | |
2e81bc61 DCS |
1847 | for (i = 0; i < I915_MAX_VECS; i++) { |
1848 | domain_id = FW_DOMAIN_ID_MEDIA_VEBOX0 + i; | |
26376a7e | 1849 | |
2e81bc61 DCS |
1850 | if (HAS_ENGINE(i915, _VECS(i))) |
1851 | continue; | |
26376a7e | 1852 | |
2e81bc61 DCS |
1853 | if (fw_domains & BIT(domain_id)) |
1854 | fw_domain_fini(uncore, domain_id); | |
26376a7e OM |
1855 | } |
1856 | } | |
1857 | ||
3de6f852 | 1858 | void intel_uncore_fini_mmio(struct intel_uncore *uncore) |
0b274481 | 1859 | { |
2e81bc61 DCS |
1860 | if (intel_uncore_has_forcewake(uncore)) { |
1861 | iosf_mbi_punit_acquire(); | |
1862 | iosf_mbi_unregister_pmic_bus_access_notifier_unlocked( | |
1863 | &uncore->pmic_bus_access_nb); | |
1864 | intel_uncore_forcewake_reset(uncore); | |
f833cdb0 | 1865 | intel_uncore_fw_domains_fini(uncore); |
2e81bc61 DCS |
1866 | iosf_mbi_punit_release(); |
1867 | } | |
1868 | ||
25286aac | 1869 | uncore_mmio_cleanup(uncore); |
0b274481 BW |
1870 | } |
1871 | ||
3fd3a6ff JL |
1872 | static const struct reg_whitelist { |
1873 | i915_reg_t offset_ldw; | |
1874 | i915_reg_t offset_udw; | |
1875 | u16 gen_mask; | |
1876 | u8 size; | |
1877 | } reg_read_whitelist[] = { { | |
1878 | .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE), | |
1879 | .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE), | |
2b92a82f | 1880 | .gen_mask = INTEL_GEN_MASK(4, 12), |
3fd3a6ff JL |
1881 | .size = 8 |
1882 | } }; | |
907b28c5 CW |
1883 | |
1884 | int i915_reg_read_ioctl(struct drm_device *dev, | |
1885 | void *data, struct drm_file *file) | |
1886 | { | |
8ed3a623 TU |
1887 | struct drm_i915_private *i915 = to_i915(dev); |
1888 | struct intel_uncore *uncore = &i915->uncore; | |
907b28c5 | 1889 | struct drm_i915_reg_read *reg = data; |
3fd3a6ff | 1890 | struct reg_whitelist const *entry; |
538ef96b | 1891 | intel_wakeref_t wakeref; |
3fd3a6ff JL |
1892 | unsigned int flags; |
1893 | int remain; | |
1894 | int ret = 0; | |
1895 | ||
1896 | entry = reg_read_whitelist; | |
1897 | remain = ARRAY_SIZE(reg_read_whitelist); | |
1898 | while (remain) { | |
1899 | u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw); | |
1900 | ||
1901 | GEM_BUG_ON(!is_power_of_2(entry->size)); | |
1902 | GEM_BUG_ON(entry->size > 8); | |
1903 | GEM_BUG_ON(entry_offset & (entry->size - 1)); | |
1904 | ||
8ed3a623 | 1905 | if (INTEL_INFO(i915)->gen_mask & entry->gen_mask && |
3fd3a6ff | 1906 | entry_offset == (reg->offset & -entry->size)) |
907b28c5 | 1907 | break; |
3fd3a6ff JL |
1908 | entry++; |
1909 | remain--; | |
907b28c5 CW |
1910 | } |
1911 | ||
3fd3a6ff | 1912 | if (!remain) |
907b28c5 CW |
1913 | return -EINVAL; |
1914 | ||
3fd3a6ff | 1915 | flags = reg->offset & (entry->size - 1); |
648a9bc5 | 1916 | |
c447ff7d | 1917 | with_intel_runtime_pm(&i915->runtime_pm, wakeref) { |
d4225a53 | 1918 | if (entry->size == 8 && flags == I915_REG_READ_8B_WA) |
8ed3a623 TU |
1919 | reg->val = intel_uncore_read64_2x32(uncore, |
1920 | entry->offset_ldw, | |
1921 | entry->offset_udw); | |
d4225a53 | 1922 | else if (entry->size == 8 && flags == 0) |
8ed3a623 TU |
1923 | reg->val = intel_uncore_read64(uncore, |
1924 | entry->offset_ldw); | |
d4225a53 | 1925 | else if (entry->size == 4 && flags == 0) |
8ed3a623 | 1926 | reg->val = intel_uncore_read(uncore, entry->offset_ldw); |
d4225a53 | 1927 | else if (entry->size == 2 && flags == 0) |
8ed3a623 TU |
1928 | reg->val = intel_uncore_read16(uncore, |
1929 | entry->offset_ldw); | |
d4225a53 | 1930 | else if (entry->size == 1 && flags == 0) |
8ed3a623 TU |
1931 | reg->val = intel_uncore_read8(uncore, |
1932 | entry->offset_ldw); | |
d4225a53 CW |
1933 | else |
1934 | ret = -EINVAL; | |
1935 | } | |
3fd3a6ff | 1936 | |
cf67c70f | 1937 | return ret; |
907b28c5 CW |
1938 | } |
1939 | ||
1758b90e | 1940 | /** |
1d1a9774 | 1941 | * __intel_wait_for_register_fw - wait until register matches expected state |
d2d551c0 | 1942 | * @uncore: the struct intel_uncore |
1758b90e CW |
1943 | * @reg: the register to read |
1944 | * @mask: mask to apply to register value | |
1945 | * @value: expected value | |
1d1a9774 MW |
1946 | * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait |
1947 | * @slow_timeout_ms: slow timeout in millisecond | |
1948 | * @out_value: optional placeholder to hold registry value | |
1758b90e CW |
1949 | * |
1950 | * This routine waits until the target register @reg contains the expected | |
3d466cd6 DV |
1951 | * @value after applying the @mask, i.e. it waits until :: |
1952 | * | |
1953 | * (I915_READ_FW(reg) & mask) == value | |
1954 | * | |
1d1a9774 | 1955 | * Otherwise, the wait will timeout after @slow_timeout_ms milliseconds. |
6976e74b | 1956 | * For atomic context @slow_timeout_ms must be zero and @fast_timeout_us |
84d84cb7 | 1957 | * must be not larger than 20,0000 microseconds. |
1758b90e CW |
1958 | * |
1959 | * Note that this routine assumes the caller holds forcewake asserted, it is | |
1960 | * not suitable for very long waits. See intel_wait_for_register() if you | |
1961 | * wish to wait without holding forcewake for the duration (i.e. you expect | |
1962 | * the wait to be slow). | |
1963 | * | |
e4661f14 | 1964 | * Return: 0 if the register matches the desired condition, or -ETIMEDOUT. |
1758b90e | 1965 | */ |
d2d551c0 | 1966 | int __intel_wait_for_register_fw(struct intel_uncore *uncore, |
1d1a9774 | 1967 | i915_reg_t reg, |
3fc7d86b MW |
1968 | u32 mask, |
1969 | u32 value, | |
1970 | unsigned int fast_timeout_us, | |
1971 | unsigned int slow_timeout_ms, | |
1d1a9774 | 1972 | u32 *out_value) |
1758b90e | 1973 | { |
ff26ffa8 | 1974 | u32 uninitialized_var(reg_value); |
d2d551c0 | 1975 | #define done (((reg_value = intel_uncore_read_fw(uncore, reg)) & mask) == value) |
1d1a9774 MW |
1976 | int ret; |
1977 | ||
6976e74b | 1978 | /* Catch any overuse of this function */ |
84d84cb7 CW |
1979 | might_sleep_if(slow_timeout_ms); |
1980 | GEM_BUG_ON(fast_timeout_us > 20000); | |
6976e74b | 1981 | |
84d84cb7 CW |
1982 | ret = -ETIMEDOUT; |
1983 | if (fast_timeout_us && fast_timeout_us <= 20000) | |
1d1a9774 | 1984 | ret = _wait_for_atomic(done, fast_timeout_us, 0); |
ff26ffa8 | 1985 | if (ret && slow_timeout_ms) |
1d1a9774 | 1986 | ret = wait_for(done, slow_timeout_ms); |
84d84cb7 | 1987 | |
1d1a9774 MW |
1988 | if (out_value) |
1989 | *out_value = reg_value; | |
84d84cb7 | 1990 | |
1758b90e CW |
1991 | return ret; |
1992 | #undef done | |
1993 | } | |
1994 | ||
1995 | /** | |
23fdbdd7 | 1996 | * __intel_wait_for_register - wait until register matches expected state |
baba6e57 | 1997 | * @uncore: the struct intel_uncore |
1758b90e CW |
1998 | * @reg: the register to read |
1999 | * @mask: mask to apply to register value | |
2000 | * @value: expected value | |
23fdbdd7 SP |
2001 | * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait |
2002 | * @slow_timeout_ms: slow timeout in millisecond | |
2003 | * @out_value: optional placeholder to hold registry value | |
1758b90e CW |
2004 | * |
2005 | * This routine waits until the target register @reg contains the expected | |
3d466cd6 DV |
2006 | * @value after applying the @mask, i.e. it waits until :: |
2007 | * | |
2008 | * (I915_READ(reg) & mask) == value | |
2009 | * | |
1758b90e CW |
2010 | * Otherwise, the wait will timeout after @timeout_ms milliseconds. |
2011 | * | |
e4661f14 | 2012 | * Return: 0 if the register matches the desired condition, or -ETIMEDOUT. |
1758b90e | 2013 | */ |
97a04e0d DCS |
2014 | int __intel_wait_for_register(struct intel_uncore *uncore, |
2015 | i915_reg_t reg, | |
2016 | u32 mask, | |
2017 | u32 value, | |
2018 | unsigned int fast_timeout_us, | |
2019 | unsigned int slow_timeout_ms, | |
2020 | u32 *out_value) | |
2021 | { | |
1758b90e | 2022 | unsigned fw = |
4319382e | 2023 | intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ); |
23fdbdd7 | 2024 | u32 reg_value; |
1758b90e CW |
2025 | int ret; |
2026 | ||
3df82dd4 | 2027 | might_sleep_if(slow_timeout_ms); |
05646543 | 2028 | |
272c7e52 DCS |
2029 | spin_lock_irq(&uncore->lock); |
2030 | intel_uncore_forcewake_get__locked(uncore, fw); | |
05646543 | 2031 | |
d2d551c0 | 2032 | ret = __intel_wait_for_register_fw(uncore, |
05646543 | 2033 | reg, mask, value, |
23fdbdd7 | 2034 | fast_timeout_us, 0, ®_value); |
05646543 | 2035 | |
272c7e52 DCS |
2036 | intel_uncore_forcewake_put__locked(uncore, fw); |
2037 | spin_unlock_irq(&uncore->lock); | |
05646543 | 2038 | |
3df82dd4 | 2039 | if (ret && slow_timeout_ms) |
d2d551c0 DCS |
2040 | ret = __wait_for(reg_value = intel_uncore_read_notrace(uncore, |
2041 | reg), | |
23fdbdd7 SP |
2042 | (reg_value & mask) == value, |
2043 | slow_timeout_ms * 1000, 10, 1000); | |
2044 | ||
39806c3f VS |
2045 | /* just trace the final value */ |
2046 | trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true); | |
2047 | ||
23fdbdd7 SP |
2048 | if (out_value) |
2049 | *out_value = reg_value; | |
1758b90e CW |
2050 | |
2051 | return ret; | |
d431440c TE |
2052 | } |
2053 | ||
2cf7bf6f | 2054 | bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore) |
907b28c5 | 2055 | { |
0a9b2630 DCS |
2056 | bool ret; |
2057 | ||
2058 | spin_lock_irq(&uncore->debug->lock); | |
2059 | ret = check_for_unclaimed_mmio(uncore); | |
2060 | spin_unlock_irq(&uncore->debug->lock); | |
2061 | ||
2062 | return ret; | |
907b28c5 | 2063 | } |
75714940 | 2064 | |
bc3b9346 | 2065 | bool |
2cf7bf6f | 2066 | intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore) |
75714940 | 2067 | { |
a167b1e1 CW |
2068 | bool ret = false; |
2069 | ||
0a9b2630 | 2070 | spin_lock_irq(&uncore->debug->lock); |
a167b1e1 | 2071 | |
0a9b2630 | 2072 | if (unlikely(uncore->debug->unclaimed_mmio_check <= 0)) |
a167b1e1 | 2073 | goto out; |
75714940 | 2074 | |
0a9b2630 | 2075 | if (unlikely(check_for_unclaimed_mmio(uncore))) { |
7ef4ac6e | 2076 | if (!i915_modparams.mmio_debug) { |
d0208cfa WK |
2077 | drm_dbg(&uncore->i915->drm, |
2078 | "Unclaimed register detected, " | |
2079 | "enabling oneshot unclaimed register reporting. " | |
2080 | "Please use i915.mmio_debug=N for more information.\n"); | |
7ef4ac6e CW |
2081 | i915_modparams.mmio_debug++; |
2082 | } | |
0a9b2630 | 2083 | uncore->debug->unclaimed_mmio_check--; |
a167b1e1 | 2084 | ret = true; |
75714940 | 2085 | } |
bc3b9346 | 2086 | |
a167b1e1 | 2087 | out: |
0a9b2630 | 2088 | spin_unlock_irq(&uncore->debug->lock); |
a167b1e1 CW |
2089 | |
2090 | return ret; | |
75714940 | 2091 | } |
3756685a | 2092 | |
3756685a TU |
2093 | /** |
2094 | * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access | |
2095 | * a register | |
4319382e | 2096 | * @uncore: pointer to struct intel_uncore |
3756685a TU |
2097 | * @reg: register in question |
2098 | * @op: operation bitmask of FW_REG_READ and/or FW_REG_WRITE | |
2099 | * | |
2100 | * Returns a set of forcewake domains required to be taken with for example | |
2101 | * intel_uncore_forcewake_get for the specified register to be accessible in the | |
2102 | * specified mode (read, write or read/write) with raw mmio accessors. | |
2103 | * | |
2104 | * NOTE: On Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the | |
2105 | * callers to do FIFO management on their own or risk losing writes. | |
2106 | */ | |
2107 | enum forcewake_domains | |
4319382e | 2108 | intel_uncore_forcewake_for_reg(struct intel_uncore *uncore, |
3756685a TU |
2109 | i915_reg_t reg, unsigned int op) |
2110 | { | |
2111 | enum forcewake_domains fw_domains = 0; | |
2112 | ||
a9f236d1 | 2113 | drm_WARN_ON(&uncore->i915->drm, !op); |
3756685a | 2114 | |
4319382e | 2115 | if (!intel_uncore_has_forcewake(uncore)) |
895833bd TU |
2116 | return 0; |
2117 | ||
3756685a | 2118 | if (op & FW_REG_READ) |
ccb2acea | 2119 | fw_domains = uncore->funcs.read_fw_domains(uncore, reg); |
3756685a TU |
2120 | |
2121 | if (op & FW_REG_WRITE) | |
ccb2acea DCS |
2122 | fw_domains |= uncore->funcs.write_fw_domains(uncore, reg); |
2123 | ||
a9f236d1 | 2124 | drm_WARN_ON(&uncore->i915->drm, fw_domains & ~uncore->fw_domains); |
3756685a TU |
2125 | |
2126 | return fw_domains; | |
2127 | } | |
26e7a2a1 CW |
2128 | |
2129 | #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) | |
0757ac8f | 2130 | #include "selftests/mock_uncore.c" |
26e7a2a1 CW |
2131 | #include "selftests/intel_uncore.c" |
2132 | #endif |