Commit | Line | Data |
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907b28c5 CW |
1 | /* |
2 | * Copyright © 2013 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | */ | |
23 | ||
24 | #include "i915_drv.h" | |
25 | #include "intel_drv.h" | |
cf9d2890 | 26 | #include "i915_vgpu.h" |
907b28c5 | 27 | |
6daccb0b CW |
28 | #include <linux/pm_runtime.h> |
29 | ||
83e33372 | 30 | #define FORCEWAKE_ACK_TIMEOUT_MS 50 |
907b28c5 | 31 | |
75aa3f63 | 32 | #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32((dev_priv__), (reg__)) |
6af5d92f | 33 | |
05a2fb15 MK |
34 | static const char * const forcewake_domain_names[] = { |
35 | "render", | |
36 | "blitter", | |
37 | "media", | |
38 | }; | |
39 | ||
40 | const char * | |
48c1026a | 41 | intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id) |
05a2fb15 | 42 | { |
53abb679 | 43 | BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT); |
05a2fb15 MK |
44 | |
45 | if (id >= 0 && id < FW_DOMAIN_ID_COUNT) | |
46 | return forcewake_domain_names[id]; | |
47 | ||
48 | WARN_ON(id); | |
49 | ||
50 | return "unknown"; | |
51 | } | |
52 | ||
05a2fb15 MK |
53 | static inline void |
54 | fw_domain_reset(const struct intel_uncore_forcewake_domain *d) | |
907b28c5 | 55 | { |
f0f59a00 | 56 | WARN_ON(!i915_mmio_reg_valid(d->reg_set)); |
05a2fb15 | 57 | __raw_i915_write32(d->i915, d->reg_set, d->val_reset); |
907b28c5 CW |
58 | } |
59 | ||
05a2fb15 MK |
60 | static inline void |
61 | fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d) | |
907b28c5 | 62 | { |
a57a4a67 TU |
63 | d->wake_count++; |
64 | hrtimer_start_range_ns(&d->timer, | |
65 | ktime_set(0, NSEC_PER_MSEC), | |
66 | NSEC_PER_MSEC, | |
67 | HRTIMER_MODE_REL); | |
907b28c5 CW |
68 | } |
69 | ||
05a2fb15 MK |
70 | static inline void |
71 | fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d) | |
907b28c5 | 72 | { |
05a2fb15 MK |
73 | if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) & |
74 | FORCEWAKE_KERNEL) == 0, | |
907b28c5 | 75 | FORCEWAKE_ACK_TIMEOUT_MS)) |
05a2fb15 MK |
76 | DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n", |
77 | intel_uncore_forcewake_domain_to_str(d->id)); | |
78 | } | |
907b28c5 | 79 | |
05a2fb15 MK |
80 | static inline void |
81 | fw_domain_get(const struct intel_uncore_forcewake_domain *d) | |
82 | { | |
83 | __raw_i915_write32(d->i915, d->reg_set, d->val_set); | |
84 | } | |
907b28c5 | 85 | |
05a2fb15 MK |
86 | static inline void |
87 | fw_domain_wait_ack(const struct intel_uncore_forcewake_domain *d) | |
88 | { | |
89 | if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) & | |
90 | FORCEWAKE_KERNEL), | |
907b28c5 | 91 | FORCEWAKE_ACK_TIMEOUT_MS)) |
05a2fb15 MK |
92 | DRM_ERROR("%s: timed out waiting for forcewake ack request.\n", |
93 | intel_uncore_forcewake_domain_to_str(d->id)); | |
94 | } | |
907b28c5 | 95 | |
05a2fb15 MK |
96 | static inline void |
97 | fw_domain_put(const struct intel_uncore_forcewake_domain *d) | |
98 | { | |
99 | __raw_i915_write32(d->i915, d->reg_set, d->val_clear); | |
907b28c5 CW |
100 | } |
101 | ||
05a2fb15 MK |
102 | static inline void |
103 | fw_domain_posting_read(const struct intel_uncore_forcewake_domain *d) | |
907b28c5 | 104 | { |
05a2fb15 | 105 | /* something from same cacheline, but not from the set register */ |
f0f59a00 | 106 | if (i915_mmio_reg_valid(d->reg_post)) |
05a2fb15 | 107 | __raw_posting_read(d->i915, d->reg_post); |
907b28c5 CW |
108 | } |
109 | ||
05a2fb15 | 110 | static void |
48c1026a | 111 | fw_domains_get(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains) |
907b28c5 | 112 | { |
05a2fb15 | 113 | struct intel_uncore_forcewake_domain *d; |
907b28c5 | 114 | |
33c582c1 | 115 | for_each_fw_domain_masked(d, fw_domains, dev_priv) { |
05a2fb15 MK |
116 | fw_domain_wait_ack_clear(d); |
117 | fw_domain_get(d); | |
05a2fb15 | 118 | } |
4e1176dd TU |
119 | |
120 | for_each_fw_domain_masked(d, fw_domains, dev_priv) | |
121 | fw_domain_wait_ack(d); | |
05a2fb15 | 122 | } |
907b28c5 | 123 | |
05a2fb15 | 124 | static void |
48c1026a | 125 | fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains) |
05a2fb15 MK |
126 | { |
127 | struct intel_uncore_forcewake_domain *d; | |
907b28c5 | 128 | |
33c582c1 | 129 | for_each_fw_domain_masked(d, fw_domains, dev_priv) { |
05a2fb15 MK |
130 | fw_domain_put(d); |
131 | fw_domain_posting_read(d); | |
132 | } | |
133 | } | |
907b28c5 | 134 | |
05a2fb15 MK |
135 | static void |
136 | fw_domains_posting_read(struct drm_i915_private *dev_priv) | |
137 | { | |
138 | struct intel_uncore_forcewake_domain *d; | |
05a2fb15 MK |
139 | |
140 | /* No need to do for all, just do for first found */ | |
33c582c1 | 141 | for_each_fw_domain(d, dev_priv) { |
05a2fb15 MK |
142 | fw_domain_posting_read(d); |
143 | break; | |
144 | } | |
145 | } | |
146 | ||
147 | static void | |
48c1026a | 148 | fw_domains_reset(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains) |
05a2fb15 MK |
149 | { |
150 | struct intel_uncore_forcewake_domain *d; | |
05a2fb15 | 151 | |
3225b2f9 MK |
152 | if (dev_priv->uncore.fw_domains == 0) |
153 | return; | |
f9b3927a | 154 | |
33c582c1 | 155 | for_each_fw_domain_masked(d, fw_domains, dev_priv) |
05a2fb15 MK |
156 | fw_domain_reset(d); |
157 | ||
158 | fw_domains_posting_read(dev_priv); | |
159 | } | |
160 | ||
161 | static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) | |
162 | { | |
163 | /* w/a for a sporadic read returning 0 by waiting for the GT | |
164 | * thread to wake up. | |
165 | */ | |
166 | if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) & | |
167 | GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500)) | |
168 | DRM_ERROR("GT thread status wait timed out\n"); | |
169 | } | |
170 | ||
171 | static void fw_domains_get_with_thread_status(struct drm_i915_private *dev_priv, | |
48c1026a | 172 | enum forcewake_domains fw_domains) |
05a2fb15 MK |
173 | { |
174 | fw_domains_get(dev_priv, fw_domains); | |
907b28c5 | 175 | |
05a2fb15 | 176 | /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */ |
c549f738 | 177 | __gen6_gt_wait_for_thread_c0(dev_priv); |
907b28c5 CW |
178 | } |
179 | ||
180 | static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) | |
181 | { | |
182 | u32 gtfifodbg; | |
6af5d92f CW |
183 | |
184 | gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG); | |
90f256b5 VS |
185 | if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg)) |
186 | __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg); | |
907b28c5 CW |
187 | } |
188 | ||
05a2fb15 | 189 | static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv, |
48c1026a | 190 | enum forcewake_domains fw_domains) |
907b28c5 | 191 | { |
05a2fb15 | 192 | fw_domains_put(dev_priv, fw_domains); |
907b28c5 CW |
193 | gen6_gt_check_fifodbg(dev_priv); |
194 | } | |
195 | ||
c32e3788 DG |
196 | static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv) |
197 | { | |
198 | u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL); | |
199 | ||
200 | return count & GT_FIFO_FREE_ENTRIES_MASK; | |
201 | } | |
202 | ||
907b28c5 CW |
203 | static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) |
204 | { | |
205 | int ret = 0; | |
206 | ||
5135d64b D |
207 | /* On VLV, FIFO will be shared by both SW and HW. |
208 | * So, we need to read the FREE_ENTRIES everytime */ | |
2d1fe073 | 209 | if (IS_VALLEYVIEW(dev_priv)) |
c32e3788 | 210 | dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv); |
5135d64b | 211 | |
907b28c5 CW |
212 | if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { |
213 | int loop = 500; | |
c32e3788 DG |
214 | u32 fifo = fifo_free_entries(dev_priv); |
215 | ||
907b28c5 CW |
216 | while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { |
217 | udelay(10); | |
c32e3788 | 218 | fifo = fifo_free_entries(dev_priv); |
907b28c5 CW |
219 | } |
220 | if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) | |
221 | ++ret; | |
222 | dev_priv->uncore.fifo_count = fifo; | |
223 | } | |
224 | dev_priv->uncore.fifo_count--; | |
225 | ||
226 | return ret; | |
227 | } | |
228 | ||
a57a4a67 TU |
229 | static enum hrtimer_restart |
230 | intel_uncore_fw_release_timer(struct hrtimer *timer) | |
38cff0b1 | 231 | { |
a57a4a67 TU |
232 | struct intel_uncore_forcewake_domain *domain = |
233 | container_of(timer, struct intel_uncore_forcewake_domain, timer); | |
003342a5 | 234 | struct drm_i915_private *dev_priv = domain->i915; |
b2cff0db | 235 | unsigned long irqflags; |
38cff0b1 | 236 | |
003342a5 | 237 | assert_rpm_device_not_suspended(dev_priv); |
38cff0b1 | 238 | |
003342a5 | 239 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
b2cff0db CW |
240 | if (WARN_ON(domain->wake_count == 0)) |
241 | domain->wake_count++; | |
242 | ||
003342a5 TU |
243 | if (--domain->wake_count == 0) { |
244 | dev_priv->uncore.funcs.force_wake_put(dev_priv, domain->mask); | |
245 | dev_priv->uncore.fw_domains_active &= ~domain->mask; | |
246 | } | |
b2cff0db | 247 | |
003342a5 | 248 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
a57a4a67 TU |
249 | |
250 | return HRTIMER_NORESTART; | |
38cff0b1 ZW |
251 | } |
252 | ||
dc97997a CW |
253 | void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv, |
254 | bool restore) | |
38cff0b1 | 255 | { |
48c1026a | 256 | unsigned long irqflags; |
b2cff0db | 257 | struct intel_uncore_forcewake_domain *domain; |
48c1026a | 258 | int retry_count = 100; |
003342a5 | 259 | enum forcewake_domains fw, active_domains; |
38cff0b1 | 260 | |
b2cff0db CW |
261 | /* Hold uncore.lock across reset to prevent any register access |
262 | * with forcewake not set correctly. Wait until all pending | |
263 | * timers are run before holding. | |
264 | */ | |
265 | while (1) { | |
266 | active_domains = 0; | |
38cff0b1 | 267 | |
33c582c1 | 268 | for_each_fw_domain(domain, dev_priv) { |
a57a4a67 | 269 | if (hrtimer_cancel(&domain->timer) == 0) |
b2cff0db | 270 | continue; |
38cff0b1 | 271 | |
a57a4a67 | 272 | intel_uncore_fw_release_timer(&domain->timer); |
b2cff0db | 273 | } |
aec347ab | 274 | |
b2cff0db | 275 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
b2ec142c | 276 | |
33c582c1 | 277 | for_each_fw_domain(domain, dev_priv) { |
a57a4a67 | 278 | if (hrtimer_active(&domain->timer)) |
33c582c1 | 279 | active_domains |= domain->mask; |
b2cff0db | 280 | } |
3123fcaf | 281 | |
b2cff0db CW |
282 | if (active_domains == 0) |
283 | break; | |
aec347ab | 284 | |
b2cff0db CW |
285 | if (--retry_count == 0) { |
286 | DRM_ERROR("Timed out waiting for forcewake timers to finish\n"); | |
287 | break; | |
288 | } | |
0294ae7b | 289 | |
b2cff0db CW |
290 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
291 | cond_resched(); | |
292 | } | |
0294ae7b | 293 | |
b2cff0db CW |
294 | WARN_ON(active_domains); |
295 | ||
003342a5 | 296 | fw = dev_priv->uncore.fw_domains_active; |
b2cff0db CW |
297 | if (fw) |
298 | dev_priv->uncore.funcs.force_wake_put(dev_priv, fw); | |
ef46e0d2 | 299 | |
05a2fb15 | 300 | fw_domains_reset(dev_priv, FORCEWAKE_ALL); |
38cff0b1 | 301 | |
0294ae7b | 302 | if (restore) { /* If reset with a user forcewake, try to restore */ |
0294ae7b CW |
303 | if (fw) |
304 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fw); | |
305 | ||
dc97997a | 306 | if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) |
0294ae7b | 307 | dev_priv->uncore.fifo_count = |
c32e3788 | 308 | fifo_free_entries(dev_priv); |
0294ae7b CW |
309 | } |
310 | ||
b2cff0db | 311 | if (!restore) |
59bad947 | 312 | assert_forcewakes_inactive(dev_priv); |
b2cff0db | 313 | |
0294ae7b | 314 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
ef46e0d2 DV |
315 | } |
316 | ||
c02e85a0 MK |
317 | static u64 gen9_edram_size(struct drm_i915_private *dev_priv) |
318 | { | |
319 | const unsigned int ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 }; | |
320 | const unsigned int sets[4] = { 1, 1, 2, 2 }; | |
321 | const u32 cap = dev_priv->edram_cap; | |
322 | ||
323 | return EDRAM_NUM_BANKS(cap) * | |
324 | ways[EDRAM_WAYS_IDX(cap)] * | |
325 | sets[EDRAM_SETS_IDX(cap)] * | |
326 | 1024 * 1024; | |
327 | } | |
328 | ||
3accaf7e | 329 | u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv) |
907b28c5 | 330 | { |
3accaf7e MK |
331 | if (!HAS_EDRAM(dev_priv)) |
332 | return 0; | |
333 | ||
c02e85a0 MK |
334 | /* The needed capability bits for size calculation |
335 | * are not there with pre gen9 so return 128MB always. | |
3accaf7e | 336 | */ |
c02e85a0 MK |
337 | if (INTEL_GEN(dev_priv) < 9) |
338 | return 128 * 1024 * 1024; | |
3accaf7e | 339 | |
c02e85a0 | 340 | return gen9_edram_size(dev_priv); |
3accaf7e | 341 | } |
907b28c5 | 342 | |
3accaf7e MK |
343 | static void intel_uncore_edram_detect(struct drm_i915_private *dev_priv) |
344 | { | |
345 | if (IS_HASWELL(dev_priv) || | |
346 | IS_BROADWELL(dev_priv) || | |
347 | INTEL_GEN(dev_priv) >= 9) { | |
348 | dev_priv->edram_cap = __raw_i915_read32(dev_priv, | |
349 | HSW_EDRAM_CAP); | |
350 | ||
351 | /* NB: We can't write IDICR yet because we do not have gt funcs | |
18ce3994 | 352 | * set up */ |
3accaf7e MK |
353 | } else { |
354 | dev_priv->edram_cap = 0; | |
18ce3994 | 355 | } |
3accaf7e MK |
356 | |
357 | if (HAS_EDRAM(dev_priv)) | |
358 | DRM_INFO("Found %lluMB of eDRAM\n", | |
359 | intel_uncore_edram_size(dev_priv) / (1024 * 1024)); | |
f9b3927a MK |
360 | } |
361 | ||
8a47eb19 | 362 | static bool |
8ac3e1bb | 363 | fpga_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv) |
8a47eb19 MK |
364 | { |
365 | u32 dbg; | |
366 | ||
8a47eb19 MK |
367 | dbg = __raw_i915_read32(dev_priv, FPGA_DBG); |
368 | if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM))) | |
369 | return false; | |
370 | ||
371 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); | |
372 | ||
373 | return true; | |
374 | } | |
375 | ||
8ac3e1bb MK |
376 | static bool |
377 | vlv_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv) | |
378 | { | |
379 | u32 cer; | |
380 | ||
381 | cer = __raw_i915_read32(dev_priv, CLAIM_ER); | |
382 | if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK)))) | |
383 | return false; | |
384 | ||
385 | __raw_i915_write32(dev_priv, CLAIM_ER, CLAIM_ER_CLR); | |
386 | ||
387 | return true; | |
388 | } | |
389 | ||
390 | static bool | |
391 | check_for_unclaimed_mmio(struct drm_i915_private *dev_priv) | |
392 | { | |
393 | if (HAS_FPGA_DBG_UNCLAIMED(dev_priv)) | |
394 | return fpga_check_for_unclaimed_mmio(dev_priv); | |
395 | ||
396 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
397 | return vlv_check_for_unclaimed_mmio(dev_priv); | |
398 | ||
399 | return false; | |
400 | } | |
401 | ||
dc97997a | 402 | static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv, |
f9b3927a MK |
403 | bool restore_forcewake) |
404 | { | |
85ee17eb PP |
405 | struct intel_device_info *info = mkwrite_device_info(dev_priv); |
406 | ||
8a47eb19 MK |
407 | /* clear out unclaimed reg detection bit */ |
408 | if (check_for_unclaimed_mmio(dev_priv)) | |
409 | DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n"); | |
907b28c5 | 410 | |
97058870 | 411 | /* clear out old GT FIFO errors */ |
dc97997a | 412 | if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) |
97058870 VS |
413 | __raw_i915_write32(dev_priv, GTFIFODBG, |
414 | __raw_i915_read32(dev_priv, GTFIFODBG)); | |
415 | ||
a04f90a3 | 416 | /* WaDisableShadowRegForCpd:chv */ |
dc97997a | 417 | if (IS_CHERRYVIEW(dev_priv)) { |
a04f90a3 D |
418 | __raw_i915_write32(dev_priv, GTFIFOCTL, |
419 | __raw_i915_read32(dev_priv, GTFIFOCTL) | | |
420 | GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL | | |
421 | GT_FIFO_CTL_RC6_POLICY_STALL); | |
422 | } | |
423 | ||
a3f79ca6 | 424 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST)) |
85ee17eb PP |
425 | info->has_decoupled_mmio = false; |
426 | ||
dc97997a | 427 | intel_uncore_forcewake_reset(dev_priv, restore_forcewake); |
521198a2 MK |
428 | } |
429 | ||
dc97997a CW |
430 | void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv, |
431 | bool restore_forcewake) | |
ed493883 | 432 | { |
dc97997a CW |
433 | __intel_uncore_early_sanitize(dev_priv, restore_forcewake); |
434 | i915_check_and_clear_faults(dev_priv); | |
ed493883 ID |
435 | } |
436 | ||
dc97997a | 437 | void intel_uncore_sanitize(struct drm_i915_private *dev_priv) |
521198a2 | 438 | { |
dc97997a | 439 | i915.enable_rc6 = sanitize_rc6_option(dev_priv, i915.enable_rc6); |
274008e8 | 440 | |
907b28c5 | 441 | /* BIOS often leaves RC6 enabled, but disable it for hw init */ |
54b4f68f | 442 | intel_sanitize_gt_powersave(dev_priv); |
907b28c5 CW |
443 | } |
444 | ||
a6111f7b CW |
445 | static void __intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, |
446 | enum forcewake_domains fw_domains) | |
447 | { | |
448 | struct intel_uncore_forcewake_domain *domain; | |
a6111f7b | 449 | |
a6111f7b CW |
450 | fw_domains &= dev_priv->uncore.fw_domains; |
451 | ||
33c582c1 | 452 | for_each_fw_domain_masked(domain, fw_domains, dev_priv) { |
a6111f7b | 453 | if (domain->wake_count++) |
33c582c1 | 454 | fw_domains &= ~domain->mask; |
a6111f7b CW |
455 | } |
456 | ||
003342a5 | 457 | if (fw_domains) { |
a6111f7b | 458 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains); |
003342a5 TU |
459 | dev_priv->uncore.fw_domains_active |= fw_domains; |
460 | } | |
a6111f7b CW |
461 | } |
462 | ||
59bad947 MK |
463 | /** |
464 | * intel_uncore_forcewake_get - grab forcewake domain references | |
465 | * @dev_priv: i915 device instance | |
466 | * @fw_domains: forcewake domains to get reference on | |
467 | * | |
468 | * This function can be used get GT's forcewake domain references. | |
469 | * Normal register access will handle the forcewake domains automatically. | |
470 | * However if some sequence requires the GT to not power down a particular | |
471 | * forcewake domains this function should be called at the beginning of the | |
472 | * sequence. And subsequently the reference should be dropped by symmetric | |
473 | * call to intel_unforce_forcewake_put(). Usually caller wants all the domains | |
474 | * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL. | |
907b28c5 | 475 | */ |
59bad947 | 476 | void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, |
48c1026a | 477 | enum forcewake_domains fw_domains) |
907b28c5 CW |
478 | { |
479 | unsigned long irqflags; | |
480 | ||
ab484f8f BW |
481 | if (!dev_priv->uncore.funcs.force_wake_get) |
482 | return; | |
483 | ||
c9b8846a | 484 | assert_rpm_wakelock_held(dev_priv); |
c8c8fb33 | 485 | |
6daccb0b | 486 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
a6111f7b | 487 | __intel_uncore_forcewake_get(dev_priv, fw_domains); |
907b28c5 CW |
488 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
489 | } | |
490 | ||
59bad947 | 491 | /** |
a6111f7b | 492 | * intel_uncore_forcewake_get__locked - grab forcewake domain references |
59bad947 | 493 | * @dev_priv: i915 device instance |
a6111f7b | 494 | * @fw_domains: forcewake domains to get reference on |
59bad947 | 495 | * |
a6111f7b CW |
496 | * See intel_uncore_forcewake_get(). This variant places the onus |
497 | * on the caller to explicitly handle the dev_priv->uncore.lock spinlock. | |
907b28c5 | 498 | */ |
a6111f7b CW |
499 | void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv, |
500 | enum forcewake_domains fw_domains) | |
501 | { | |
502 | assert_spin_locked(&dev_priv->uncore.lock); | |
503 | ||
504 | if (!dev_priv->uncore.funcs.force_wake_get) | |
505 | return; | |
506 | ||
507 | __intel_uncore_forcewake_get(dev_priv, fw_domains); | |
508 | } | |
509 | ||
510 | static void __intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, | |
511 | enum forcewake_domains fw_domains) | |
907b28c5 | 512 | { |
b2cff0db | 513 | struct intel_uncore_forcewake_domain *domain; |
907b28c5 | 514 | |
b2cff0db CW |
515 | fw_domains &= dev_priv->uncore.fw_domains; |
516 | ||
33c582c1 | 517 | for_each_fw_domain_masked(domain, fw_domains, dev_priv) { |
b2cff0db CW |
518 | if (WARN_ON(domain->wake_count == 0)) |
519 | continue; | |
520 | ||
521 | if (--domain->wake_count) | |
522 | continue; | |
523 | ||
05a2fb15 | 524 | fw_domain_arm_timer(domain); |
aec347ab | 525 | } |
a6111f7b | 526 | } |
dc9fb09c | 527 | |
a6111f7b CW |
528 | /** |
529 | * intel_uncore_forcewake_put - release a forcewake domain reference | |
530 | * @dev_priv: i915 device instance | |
531 | * @fw_domains: forcewake domains to put references | |
532 | * | |
533 | * This function drops the device-level forcewakes for specified | |
534 | * domains obtained by intel_uncore_forcewake_get(). | |
535 | */ | |
536 | void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, | |
537 | enum forcewake_domains fw_domains) | |
538 | { | |
539 | unsigned long irqflags; | |
540 | ||
541 | if (!dev_priv->uncore.funcs.force_wake_put) | |
542 | return; | |
543 | ||
544 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
545 | __intel_uncore_forcewake_put(dev_priv, fw_domains); | |
907b28c5 CW |
546 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
547 | } | |
548 | ||
a6111f7b CW |
549 | /** |
550 | * intel_uncore_forcewake_put__locked - grab forcewake domain references | |
551 | * @dev_priv: i915 device instance | |
552 | * @fw_domains: forcewake domains to get reference on | |
553 | * | |
554 | * See intel_uncore_forcewake_put(). This variant places the onus | |
555 | * on the caller to explicitly handle the dev_priv->uncore.lock spinlock. | |
556 | */ | |
557 | void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv, | |
558 | enum forcewake_domains fw_domains) | |
559 | { | |
560 | assert_spin_locked(&dev_priv->uncore.lock); | |
561 | ||
562 | if (!dev_priv->uncore.funcs.force_wake_put) | |
563 | return; | |
564 | ||
565 | __intel_uncore_forcewake_put(dev_priv, fw_domains); | |
566 | } | |
567 | ||
59bad947 | 568 | void assert_forcewakes_inactive(struct drm_i915_private *dev_priv) |
e998c40f PZ |
569 | { |
570 | if (!dev_priv->uncore.funcs.force_wake_get) | |
571 | return; | |
572 | ||
003342a5 | 573 | WARN_ON(dev_priv->uncore.fw_domains_active); |
e998c40f PZ |
574 | } |
575 | ||
907b28c5 | 576 | /* We give fast paths for the really cool registers */ |
40181697 | 577 | #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000) |
907b28c5 | 578 | |
6863b76c TU |
579 | #define __gen6_reg_read_fw_domains(offset) \ |
580 | ({ \ | |
581 | enum forcewake_domains __fwd; \ | |
582 | if (NEEDS_FORCE_WAKE(offset)) \ | |
583 | __fwd = FORCEWAKE_RENDER; \ | |
584 | else \ | |
585 | __fwd = 0; \ | |
586 | __fwd; \ | |
587 | }) | |
588 | ||
9480dbf0 | 589 | static int fw_range_cmp(u32 offset, const struct intel_forcewake_range *entry) |
91e630b9 | 590 | { |
91e630b9 TU |
591 | if (offset < entry->start) |
592 | return -1; | |
593 | else if (offset > entry->end) | |
594 | return 1; | |
595 | else | |
596 | return 0; | |
597 | } | |
598 | ||
9480dbf0 TU |
599 | /* Copied and "macroized" from lib/bsearch.c */ |
600 | #define BSEARCH(key, base, num, cmp) ({ \ | |
601 | unsigned int start__ = 0, end__ = (num); \ | |
602 | typeof(base) result__ = NULL; \ | |
603 | while (start__ < end__) { \ | |
604 | unsigned int mid__ = start__ + (end__ - start__) / 2; \ | |
605 | int ret__ = (cmp)((key), (base) + mid__); \ | |
606 | if (ret__ < 0) { \ | |
607 | end__ = mid__; \ | |
608 | } else if (ret__ > 0) { \ | |
609 | start__ = mid__ + 1; \ | |
610 | } else { \ | |
611 | result__ = (base) + mid__; \ | |
612 | break; \ | |
613 | } \ | |
614 | } \ | |
615 | result__; \ | |
616 | }) | |
617 | ||
9fc1117c | 618 | static enum forcewake_domains |
15157970 | 619 | find_fw_domain(struct drm_i915_private *dev_priv, u32 offset) |
9fc1117c | 620 | { |
9480dbf0 | 621 | const struct intel_forcewake_range *entry; |
9fc1117c | 622 | |
9480dbf0 TU |
623 | entry = BSEARCH(offset, |
624 | dev_priv->uncore.fw_domains_table, | |
625 | dev_priv->uncore.fw_domains_table_entries, | |
91e630b9 | 626 | fw_range_cmp); |
38fb6a40 | 627 | |
0dd356bb | 628 | return entry ? entry->domains : 0; |
9fc1117c TU |
629 | } |
630 | ||
b0081239 | 631 | static void |
15157970 | 632 | intel_fw_table_check(struct drm_i915_private *dev_priv) |
b0081239 | 633 | { |
15157970 TU |
634 | const struct intel_forcewake_range *ranges; |
635 | unsigned int num_ranges; | |
b0081239 TU |
636 | s32 prev; |
637 | unsigned int i; | |
638 | ||
639 | if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG)) | |
640 | return; | |
641 | ||
15157970 TU |
642 | ranges = dev_priv->uncore.fw_domains_table; |
643 | if (!ranges) | |
644 | return; | |
645 | ||
646 | num_ranges = dev_priv->uncore.fw_domains_table_entries; | |
647 | ||
b0081239 | 648 | for (i = 0, prev = -1; i < num_ranges; i++, ranges++) { |
a194b8cb TU |
649 | WARN_ON_ONCE(IS_GEN9(dev_priv) && |
650 | (prev + 1) != (s32)ranges->start); | |
b0081239 TU |
651 | WARN_ON_ONCE(prev >= (s32)ranges->start); |
652 | prev = ranges->start; | |
653 | WARN_ON_ONCE(prev >= (s32)ranges->end); | |
654 | prev = ranges->end; | |
655 | } | |
656 | } | |
657 | ||
9fc1117c TU |
658 | #define GEN_FW_RANGE(s, e, d) \ |
659 | { .start = (s), .end = (e), .domains = (d) } | |
1938e59a | 660 | |
895833bd TU |
661 | #define HAS_FWTABLE(dev_priv) \ |
662 | (IS_GEN9(dev_priv) || \ | |
663 | IS_CHERRYVIEW(dev_priv) || \ | |
664 | IS_VALLEYVIEW(dev_priv)) | |
665 | ||
b0081239 | 666 | /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */ |
9fc1117c TU |
667 | static const struct intel_forcewake_range __vlv_fw_ranges[] = { |
668 | GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER), | |
669 | GEN_FW_RANGE(0x5000, 0x7fff, FORCEWAKE_RENDER), | |
670 | GEN_FW_RANGE(0xb000, 0x11fff, FORCEWAKE_RENDER), | |
9fc1117c TU |
671 | GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA), |
672 | GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_MEDIA), | |
b0081239 | 673 | GEN_FW_RANGE(0x2e000, 0x2ffff, FORCEWAKE_RENDER), |
9fc1117c TU |
674 | GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA), |
675 | }; | |
1938e59a | 676 | |
895833bd | 677 | #define __fwtable_reg_read_fw_domains(offset) \ |
6863b76c TU |
678 | ({ \ |
679 | enum forcewake_domains __fwd = 0; \ | |
0dd356bb | 680 | if (NEEDS_FORCE_WAKE((offset))) \ |
15157970 | 681 | __fwd = find_fw_domain(dev_priv, offset); \ |
6863b76c TU |
682 | __fwd; \ |
683 | }) | |
684 | ||
47188574 | 685 | /* *Must* be sorted by offset! See intel_shadow_table_check(). */ |
6863b76c | 686 | static const i915_reg_t gen8_shadowed_regs[] = { |
47188574 TU |
687 | RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */ |
688 | GEN6_RPNSWREQ, /* 0xA008 */ | |
689 | GEN6_RC_VIDEO_FREQ, /* 0xA00C */ | |
690 | RING_TAIL(GEN6_BSD_RING_BASE), /* 0x12000 (base) */ | |
691 | RING_TAIL(VEBOX_RING_BASE), /* 0x1a000 (base) */ | |
692 | RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */ | |
6863b76c TU |
693 | /* TODO: Other registers are not yet used */ |
694 | }; | |
695 | ||
47188574 TU |
696 | static void intel_shadow_table_check(void) |
697 | { | |
698 | const i915_reg_t *reg = gen8_shadowed_regs; | |
699 | s32 prev; | |
700 | u32 offset; | |
701 | unsigned int i; | |
702 | ||
703 | if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG)) | |
704 | return; | |
705 | ||
706 | for (i = 0, prev = -1; i < ARRAY_SIZE(gen8_shadowed_regs); i++, reg++) { | |
707 | offset = i915_mmio_reg_offset(*reg); | |
708 | WARN_ON_ONCE(prev >= (s32)offset); | |
709 | prev = offset; | |
710 | } | |
711 | } | |
712 | ||
9480dbf0 | 713 | static int mmio_reg_cmp(u32 key, const i915_reg_t *reg) |
5a659383 | 714 | { |
9480dbf0 | 715 | u32 offset = i915_mmio_reg_offset(*reg); |
5a659383 | 716 | |
9480dbf0 | 717 | if (key < offset) |
5a659383 | 718 | return -1; |
9480dbf0 | 719 | else if (key > offset) |
5a659383 TU |
720 | return 1; |
721 | else | |
722 | return 0; | |
723 | } | |
724 | ||
6863b76c TU |
725 | static bool is_gen8_shadowed(u32 offset) |
726 | { | |
9480dbf0 | 727 | const i915_reg_t *regs = gen8_shadowed_regs; |
5a659383 | 728 | |
9480dbf0 TU |
729 | return BSEARCH(offset, regs, ARRAY_SIZE(gen8_shadowed_regs), |
730 | mmio_reg_cmp); | |
6863b76c TU |
731 | } |
732 | ||
733 | #define __gen8_reg_write_fw_domains(offset) \ | |
734 | ({ \ | |
735 | enum forcewake_domains __fwd; \ | |
736 | if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(offset)) \ | |
737 | __fwd = FORCEWAKE_RENDER; \ | |
738 | else \ | |
739 | __fwd = 0; \ | |
740 | __fwd; \ | |
741 | }) | |
742 | ||
b0081239 | 743 | /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */ |
9fc1117c TU |
744 | static const struct intel_forcewake_range __chv_fw_ranges[] = { |
745 | GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER), | |
b0081239 | 746 | GEN_FW_RANGE(0x4000, 0x4fff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), |
9fc1117c | 747 | GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), |
b0081239 | 748 | GEN_FW_RANGE(0x8000, 0x82ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), |
9fc1117c | 749 | GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), |
b0081239 | 750 | GEN_FW_RANGE(0x8500, 0x85ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), |
9fc1117c | 751 | GEN_FW_RANGE(0x8800, 0x88ff, FORCEWAKE_MEDIA), |
b0081239 TU |
752 | GEN_FW_RANGE(0x9000, 0xafff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), |
753 | GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER), | |
9fc1117c | 754 | GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA), |
b0081239 TU |
755 | GEN_FW_RANGE(0xe000, 0xe7ff, FORCEWAKE_RENDER), |
756 | GEN_FW_RANGE(0xf000, 0xffff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), | |
9fc1117c TU |
757 | GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA), |
758 | GEN_FW_RANGE(0x1a000, 0x1bfff, FORCEWAKE_MEDIA), | |
759 | GEN_FW_RANGE(0x1e800, 0x1e9ff, FORCEWAKE_MEDIA), | |
760 | GEN_FW_RANGE(0x30000, 0x37fff, FORCEWAKE_MEDIA), | |
9fc1117c | 761 | }; |
38fb6a40 | 762 | |
22d48c55 | 763 | #define __fwtable_reg_write_fw_domains(offset) \ |
6863b76c TU |
764 | ({ \ |
765 | enum forcewake_domains __fwd = 0; \ | |
0dd356bb | 766 | if (NEEDS_FORCE_WAKE((offset)) && !is_gen8_shadowed(offset)) \ |
15157970 | 767 | __fwd = find_fw_domain(dev_priv, offset); \ |
6863b76c TU |
768 | __fwd; \ |
769 | }) | |
770 | ||
b0081239 | 771 | /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */ |
9fc1117c | 772 | static const struct intel_forcewake_range __gen9_fw_ranges[] = { |
0dd356bb | 773 | GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER), |
9fc1117c TU |
774 | GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */ |
775 | GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), | |
0dd356bb | 776 | GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER), |
9fc1117c | 777 | GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER), |
0dd356bb | 778 | GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER), |
9fc1117c | 779 | GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), |
0dd356bb | 780 | GEN_FW_RANGE(0x8000, 0x812f, FORCEWAKE_BLITTER), |
b0081239 | 781 | GEN_FW_RANGE(0x8130, 0x813f, FORCEWAKE_MEDIA), |
9fc1117c | 782 | GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER), |
0dd356bb | 783 | GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER), |
9fc1117c | 784 | GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), |
0dd356bb | 785 | GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_BLITTER), |
b0081239 | 786 | GEN_FW_RANGE(0x8800, 0x89ff, FORCEWAKE_MEDIA), |
0dd356bb | 787 | GEN_FW_RANGE(0x8a00, 0x8bff, FORCEWAKE_BLITTER), |
9fc1117c | 788 | GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER), |
0dd356bb | 789 | GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER), |
9fc1117c | 790 | GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), |
0dd356bb | 791 | GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER), |
b0081239 | 792 | GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER), |
78424c92 | 793 | GEN_FW_RANGE(0xb480, 0xcfff, FORCEWAKE_BLITTER), |
9fc1117c | 794 | GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA), |
0dd356bb | 795 | GEN_FW_RANGE(0xd800, 0xdfff, FORCEWAKE_BLITTER), |
b0081239 | 796 | GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER), |
0dd356bb | 797 | GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_BLITTER), |
9fc1117c | 798 | GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA), |
0dd356bb | 799 | GEN_FW_RANGE(0x14000, 0x19fff, FORCEWAKE_BLITTER), |
9fc1117c | 800 | GEN_FW_RANGE(0x1a000, 0x1e9ff, FORCEWAKE_MEDIA), |
0dd356bb | 801 | GEN_FW_RANGE(0x1ea00, 0x243ff, FORCEWAKE_BLITTER), |
b0081239 | 802 | GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER), |
0dd356bb | 803 | GEN_FW_RANGE(0x24800, 0x2ffff, FORCEWAKE_BLITTER), |
9fc1117c TU |
804 | GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA), |
805 | }; | |
6863b76c | 806 | |
907b28c5 CW |
807 | static void |
808 | ilk_dummy_write(struct drm_i915_private *dev_priv) | |
809 | { | |
810 | /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up | |
811 | * the chip from rc6 before touching it for real. MI_MODE is masked, | |
812 | * hence harmless to write 0 into. */ | |
6af5d92f | 813 | __raw_i915_write32(dev_priv, MI_MODE, 0); |
907b28c5 CW |
814 | } |
815 | ||
816 | static void | |
9c053501 MK |
817 | __unclaimed_reg_debug(struct drm_i915_private *dev_priv, |
818 | const i915_reg_t reg, | |
819 | const bool read, | |
820 | const bool before) | |
907b28c5 | 821 | { |
dda96033 CW |
822 | if (WARN(check_for_unclaimed_mmio(dev_priv) && !before, |
823 | "Unclaimed %s register 0x%x\n", | |
824 | read ? "read from" : "write to", | |
4bd0a25d | 825 | i915_mmio_reg_offset(reg))) |
48572edd | 826 | i915.mmio_debug--; /* Only report the first N failures */ |
907b28c5 CW |
827 | } |
828 | ||
9c053501 MK |
829 | static inline void |
830 | unclaimed_reg_debug(struct drm_i915_private *dev_priv, | |
831 | const i915_reg_t reg, | |
832 | const bool read, | |
833 | const bool before) | |
834 | { | |
835 | if (likely(!i915.mmio_debug)) | |
836 | return; | |
837 | ||
838 | __unclaimed_reg_debug(dev_priv, reg, read, before); | |
839 | } | |
840 | ||
85ee17eb PP |
841 | static const enum decoupled_power_domain fw2dpd_domain[] = { |
842 | GEN9_DECOUPLED_PD_RENDER, | |
843 | GEN9_DECOUPLED_PD_BLITTER, | |
844 | GEN9_DECOUPLED_PD_ALL, | |
845 | GEN9_DECOUPLED_PD_MEDIA, | |
846 | GEN9_DECOUPLED_PD_ALL, | |
847 | GEN9_DECOUPLED_PD_ALL, | |
848 | GEN9_DECOUPLED_PD_ALL | |
849 | }; | |
850 | ||
851 | /* | |
852 | * Decoupled MMIO access for only 1 DWORD | |
853 | */ | |
854 | static void __gen9_decoupled_mmio_access(struct drm_i915_private *dev_priv, | |
855 | u32 reg, | |
856 | enum forcewake_domains fw_domain, | |
857 | enum decoupled_ops operation) | |
858 | { | |
859 | enum decoupled_power_domain dp_domain; | |
860 | u32 ctrl_reg_data = 0; | |
861 | ||
862 | dp_domain = fw2dpd_domain[fw_domain - 1]; | |
863 | ||
864 | ctrl_reg_data |= reg; | |
865 | ctrl_reg_data |= (operation << GEN9_DECOUPLED_OP_SHIFT); | |
866 | ctrl_reg_data |= (dp_domain << GEN9_DECOUPLED_PD_SHIFT); | |
867 | ctrl_reg_data |= GEN9_DECOUPLED_DW1_GO; | |
868 | __raw_i915_write32(dev_priv, GEN9_DECOUPLED_REG0_DW1, ctrl_reg_data); | |
869 | ||
870 | if (wait_for_atomic((__raw_i915_read32(dev_priv, | |
871 | GEN9_DECOUPLED_REG0_DW1) & | |
872 | GEN9_DECOUPLED_DW1_GO) == 0, | |
873 | FORCEWAKE_ACK_TIMEOUT_MS)) | |
874 | DRM_ERROR("Decoupled MMIO wait timed out\n"); | |
875 | } | |
876 | ||
877 | static inline u32 | |
878 | __gen9_decoupled_mmio_read32(struct drm_i915_private *dev_priv, | |
879 | u32 reg, | |
880 | enum forcewake_domains fw_domain) | |
881 | { | |
882 | __gen9_decoupled_mmio_access(dev_priv, reg, fw_domain, | |
883 | GEN9_DECOUPLED_OP_READ); | |
884 | ||
885 | return __raw_i915_read32(dev_priv, GEN9_DECOUPLED_REG0_DW0); | |
886 | } | |
887 | ||
888 | static inline void | |
889 | __gen9_decoupled_mmio_write(struct drm_i915_private *dev_priv, | |
890 | u32 reg, u32 data, | |
891 | enum forcewake_domains fw_domain) | |
892 | { | |
893 | ||
894 | __raw_i915_write32(dev_priv, GEN9_DECOUPLED_REG0_DW0, data); | |
895 | ||
896 | __gen9_decoupled_mmio_access(dev_priv, reg, fw_domain, | |
897 | GEN9_DECOUPLED_OP_WRITE); | |
898 | } | |
899 | ||
900 | ||
51f67885 | 901 | #define GEN2_READ_HEADER(x) \ |
5d738795 | 902 | u##x val = 0; \ |
da5827c3 | 903 | assert_rpm_wakelock_held(dev_priv); |
5d738795 | 904 | |
51f67885 | 905 | #define GEN2_READ_FOOTER \ |
5d738795 BW |
906 | trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ |
907 | return val | |
908 | ||
51f67885 | 909 | #define __gen2_read(x) \ |
0b274481 | 910 | static u##x \ |
f0f59a00 | 911 | gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ |
51f67885 | 912 | GEN2_READ_HEADER(x); \ |
3967018e | 913 | val = __raw_i915_read##x(dev_priv, reg); \ |
51f67885 | 914 | GEN2_READ_FOOTER; \ |
3967018e BW |
915 | } |
916 | ||
917 | #define __gen5_read(x) \ | |
918 | static u##x \ | |
f0f59a00 | 919 | gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ |
51f67885 | 920 | GEN2_READ_HEADER(x); \ |
3967018e BW |
921 | ilk_dummy_write(dev_priv); \ |
922 | val = __raw_i915_read##x(dev_priv, reg); \ | |
51f67885 | 923 | GEN2_READ_FOOTER; \ |
3967018e BW |
924 | } |
925 | ||
51f67885 CW |
926 | __gen5_read(8) |
927 | __gen5_read(16) | |
928 | __gen5_read(32) | |
929 | __gen5_read(64) | |
930 | __gen2_read(8) | |
931 | __gen2_read(16) | |
932 | __gen2_read(32) | |
933 | __gen2_read(64) | |
934 | ||
935 | #undef __gen5_read | |
936 | #undef __gen2_read | |
937 | ||
938 | #undef GEN2_READ_FOOTER | |
939 | #undef GEN2_READ_HEADER | |
940 | ||
941 | #define GEN6_READ_HEADER(x) \ | |
f0f59a00 | 942 | u32 offset = i915_mmio_reg_offset(reg); \ |
51f67885 CW |
943 | unsigned long irqflags; \ |
944 | u##x val = 0; \ | |
da5827c3 | 945 | assert_rpm_wakelock_held(dev_priv); \ |
9c053501 MK |
946 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \ |
947 | unclaimed_reg_debug(dev_priv, reg, true, true) | |
51f67885 CW |
948 | |
949 | #define GEN6_READ_FOOTER \ | |
9c053501 | 950 | unclaimed_reg_debug(dev_priv, reg, true, false); \ |
51f67885 CW |
951 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ |
952 | trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ | |
953 | return val | |
954 | ||
c521b0c8 TU |
955 | static noinline void ___force_wake_auto(struct drm_i915_private *dev_priv, |
956 | enum forcewake_domains fw_domains) | |
b2cff0db CW |
957 | { |
958 | struct intel_uncore_forcewake_domain *domain; | |
b2cff0db | 959 | |
c521b0c8 TU |
960 | for_each_fw_domain_masked(domain, fw_domains, dev_priv) |
961 | fw_domain_arm_timer(domain); | |
962 | ||
963 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains); | |
964 | dev_priv->uncore.fw_domains_active |= fw_domains; | |
965 | } | |
966 | ||
967 | static inline void __force_wake_auto(struct drm_i915_private *dev_priv, | |
968 | enum forcewake_domains fw_domains) | |
969 | { | |
b2cff0db CW |
970 | if (WARN_ON(!fw_domains)) |
971 | return; | |
972 | ||
003342a5 TU |
973 | /* Turn on all requested but inactive supported forcewake domains. */ |
974 | fw_domains &= dev_priv->uncore.fw_domains; | |
975 | fw_domains &= ~dev_priv->uncore.fw_domains_active; | |
b2cff0db | 976 | |
c521b0c8 TU |
977 | if (fw_domains) |
978 | ___force_wake_auto(dev_priv, fw_domains); | |
b2cff0db CW |
979 | } |
980 | ||
3967018e BW |
981 | #define __gen6_read(x) \ |
982 | static u##x \ | |
f0f59a00 | 983 | gen6_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ |
6863b76c | 984 | enum forcewake_domains fw_engine; \ |
51f67885 | 985 | GEN6_READ_HEADER(x); \ |
6863b76c TU |
986 | fw_engine = __gen6_reg_read_fw_domains(offset); \ |
987 | if (fw_engine) \ | |
988 | __force_wake_auto(dev_priv, fw_engine); \ | |
dc9fb09c | 989 | val = __raw_i915_read##x(dev_priv, reg); \ |
51f67885 | 990 | GEN6_READ_FOOTER; \ |
907b28c5 CW |
991 | } |
992 | ||
6044c4a3 | 993 | #define __fwtable_read(x) \ |
940aece4 | 994 | static u##x \ |
6044c4a3 | 995 | fwtable_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ |
6863b76c | 996 | enum forcewake_domains fw_engine; \ |
51f67885 | 997 | GEN6_READ_HEADER(x); \ |
895833bd | 998 | fw_engine = __fwtable_reg_read_fw_domains(offset); \ |
6a42d0f4 | 999 | if (fw_engine) \ |
b208ba8e | 1000 | __force_wake_auto(dev_priv, fw_engine); \ |
6fe72865 | 1001 | val = __raw_i915_read##x(dev_priv, reg); \ |
51f67885 | 1002 | GEN6_READ_FOOTER; \ |
940aece4 D |
1003 | } |
1004 | ||
85ee17eb PP |
1005 | #define __gen9_decoupled_read(x) \ |
1006 | static u##x \ | |
1007 | gen9_decoupled_read##x(struct drm_i915_private *dev_priv, \ | |
1008 | i915_reg_t reg, bool trace) { \ | |
1009 | enum forcewake_domains fw_engine; \ | |
1010 | GEN6_READ_HEADER(x); \ | |
1011 | fw_engine = __fwtable_reg_read_fw_domains(offset); \ | |
1012 | if (fw_engine & ~dev_priv->uncore.fw_domains_active) { \ | |
1013 | unsigned i; \ | |
1014 | u32 *ptr_data = (u32 *) &val; \ | |
1015 | for (i = 0; i < x/32; i++, offset += sizeof(u32), ptr_data++) \ | |
1016 | *ptr_data = __gen9_decoupled_mmio_read32(dev_priv, \ | |
1017 | offset, \ | |
1018 | fw_engine); \ | |
1019 | } else { \ | |
1020 | val = __raw_i915_read##x(dev_priv, reg); \ | |
1021 | } \ | |
1022 | GEN6_READ_FOOTER; \ | |
1023 | } | |
1024 | ||
1025 | __gen9_decoupled_read(32) | |
1026 | __gen9_decoupled_read(64) | |
6044c4a3 TU |
1027 | __fwtable_read(8) |
1028 | __fwtable_read(16) | |
1029 | __fwtable_read(32) | |
1030 | __fwtable_read(64) | |
3967018e BW |
1031 | __gen6_read(8) |
1032 | __gen6_read(16) | |
1033 | __gen6_read(32) | |
1034 | __gen6_read(64) | |
3967018e | 1035 | |
6044c4a3 | 1036 | #undef __fwtable_read |
3967018e | 1037 | #undef __gen6_read |
51f67885 CW |
1038 | #undef GEN6_READ_FOOTER |
1039 | #undef GEN6_READ_HEADER | |
5d738795 | 1040 | |
8a74db7a VS |
1041 | #define VGPU_READ_HEADER(x) \ |
1042 | unsigned long irqflags; \ | |
1043 | u##x val = 0; \ | |
da5827c3 | 1044 | assert_rpm_device_not_suspended(dev_priv); \ |
8a74db7a VS |
1045 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags) |
1046 | ||
1047 | #define VGPU_READ_FOOTER \ | |
1048 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ | |
1049 | trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ | |
1050 | return val | |
1051 | ||
1052 | #define __vgpu_read(x) \ | |
1053 | static u##x \ | |
f0f59a00 | 1054 | vgpu_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ |
8a74db7a VS |
1055 | VGPU_READ_HEADER(x); \ |
1056 | val = __raw_i915_read##x(dev_priv, reg); \ | |
1057 | VGPU_READ_FOOTER; \ | |
1058 | } | |
1059 | ||
1060 | __vgpu_read(8) | |
1061 | __vgpu_read(16) | |
1062 | __vgpu_read(32) | |
1063 | __vgpu_read(64) | |
1064 | ||
1065 | #undef __vgpu_read | |
1066 | #undef VGPU_READ_FOOTER | |
1067 | #undef VGPU_READ_HEADER | |
1068 | ||
51f67885 | 1069 | #define GEN2_WRITE_HEADER \ |
5d738795 | 1070 | trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ |
da5827c3 | 1071 | assert_rpm_wakelock_held(dev_priv); \ |
907b28c5 | 1072 | |
51f67885 | 1073 | #define GEN2_WRITE_FOOTER |
0d965301 | 1074 | |
51f67885 | 1075 | #define __gen2_write(x) \ |
0b274481 | 1076 | static void \ |
f0f59a00 | 1077 | gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \ |
51f67885 | 1078 | GEN2_WRITE_HEADER; \ |
4032ef43 | 1079 | __raw_i915_write##x(dev_priv, reg, val); \ |
51f67885 | 1080 | GEN2_WRITE_FOOTER; \ |
4032ef43 BW |
1081 | } |
1082 | ||
1083 | #define __gen5_write(x) \ | |
1084 | static void \ | |
f0f59a00 | 1085 | gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \ |
51f67885 | 1086 | GEN2_WRITE_HEADER; \ |
4032ef43 BW |
1087 | ilk_dummy_write(dev_priv); \ |
1088 | __raw_i915_write##x(dev_priv, reg, val); \ | |
51f67885 | 1089 | GEN2_WRITE_FOOTER; \ |
4032ef43 BW |
1090 | } |
1091 | ||
51f67885 CW |
1092 | __gen5_write(8) |
1093 | __gen5_write(16) | |
1094 | __gen5_write(32) | |
51f67885 CW |
1095 | __gen2_write(8) |
1096 | __gen2_write(16) | |
1097 | __gen2_write(32) | |
51f67885 CW |
1098 | |
1099 | #undef __gen5_write | |
1100 | #undef __gen2_write | |
1101 | ||
1102 | #undef GEN2_WRITE_FOOTER | |
1103 | #undef GEN2_WRITE_HEADER | |
1104 | ||
1105 | #define GEN6_WRITE_HEADER \ | |
f0f59a00 | 1106 | u32 offset = i915_mmio_reg_offset(reg); \ |
51f67885 CW |
1107 | unsigned long irqflags; \ |
1108 | trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ | |
da5827c3 | 1109 | assert_rpm_wakelock_held(dev_priv); \ |
9c053501 MK |
1110 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \ |
1111 | unclaimed_reg_debug(dev_priv, reg, false, true) | |
51f67885 CW |
1112 | |
1113 | #define GEN6_WRITE_FOOTER \ | |
9c053501 | 1114 | unclaimed_reg_debug(dev_priv, reg, false, false); \ |
51f67885 CW |
1115 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags) |
1116 | ||
4032ef43 BW |
1117 | #define __gen6_write(x) \ |
1118 | static void \ | |
f0f59a00 | 1119 | gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \ |
4032ef43 | 1120 | u32 __fifo_ret = 0; \ |
51f67885 | 1121 | GEN6_WRITE_HEADER; \ |
0670c5a6 | 1122 | if (NEEDS_FORCE_WAKE(offset)) { \ |
4032ef43 BW |
1123 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ |
1124 | } \ | |
1125 | __raw_i915_write##x(dev_priv, reg, val); \ | |
1126 | if (unlikely(__fifo_ret)) { \ | |
1127 | gen6_gt_check_fifodbg(dev_priv); \ | |
1128 | } \ | |
51f67885 | 1129 | GEN6_WRITE_FOOTER; \ |
4032ef43 BW |
1130 | } |
1131 | ||
ab2aa47e BW |
1132 | #define __gen8_write(x) \ |
1133 | static void \ | |
f0f59a00 | 1134 | gen8_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \ |
6863b76c | 1135 | enum forcewake_domains fw_engine; \ |
51f67885 | 1136 | GEN6_WRITE_HEADER; \ |
6863b76c TU |
1137 | fw_engine = __gen8_reg_write_fw_domains(offset); \ |
1138 | if (fw_engine) \ | |
1139 | __force_wake_auto(dev_priv, fw_engine); \ | |
b2cff0db | 1140 | __raw_i915_write##x(dev_priv, reg, val); \ |
51f67885 | 1141 | GEN6_WRITE_FOOTER; \ |
ab2aa47e BW |
1142 | } |
1143 | ||
22d48c55 | 1144 | #define __fwtable_write(x) \ |
1938e59a | 1145 | static void \ |
22d48c55 | 1146 | fwtable_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \ |
6863b76c | 1147 | enum forcewake_domains fw_engine; \ |
51f67885 | 1148 | GEN6_WRITE_HEADER; \ |
22d48c55 | 1149 | fw_engine = __fwtable_reg_write_fw_domains(offset); \ |
6a42d0f4 | 1150 | if (fw_engine) \ |
b208ba8e | 1151 | __force_wake_auto(dev_priv, fw_engine); \ |
1938e59a | 1152 | __raw_i915_write##x(dev_priv, reg, val); \ |
51f67885 | 1153 | GEN6_WRITE_FOOTER; \ |
1938e59a D |
1154 | } |
1155 | ||
85ee17eb PP |
1156 | #define __gen9_decoupled_write(x) \ |
1157 | static void \ | |
1158 | gen9_decoupled_write##x(struct drm_i915_private *dev_priv, \ | |
1159 | i915_reg_t reg, u##x val, \ | |
1160 | bool trace) { \ | |
1161 | enum forcewake_domains fw_engine; \ | |
1162 | GEN6_WRITE_HEADER; \ | |
1163 | fw_engine = __fwtable_reg_write_fw_domains(offset); \ | |
1164 | if (fw_engine & ~dev_priv->uncore.fw_domains_active) \ | |
1165 | __gen9_decoupled_mmio_write(dev_priv, \ | |
1166 | offset, \ | |
1167 | val, \ | |
1168 | fw_engine); \ | |
1169 | else \ | |
1170 | __raw_i915_write##x(dev_priv, reg, val); \ | |
1171 | GEN6_WRITE_FOOTER; \ | |
1172 | } | |
1173 | ||
1174 | __gen9_decoupled_write(32) | |
22d48c55 TU |
1175 | __fwtable_write(8) |
1176 | __fwtable_write(16) | |
1177 | __fwtable_write(32) | |
ab2aa47e BW |
1178 | __gen8_write(8) |
1179 | __gen8_write(16) | |
1180 | __gen8_write(32) | |
4032ef43 BW |
1181 | __gen6_write(8) |
1182 | __gen6_write(16) | |
1183 | __gen6_write(32) | |
4032ef43 | 1184 | |
22d48c55 | 1185 | #undef __fwtable_write |
ab2aa47e | 1186 | #undef __gen8_write |
4032ef43 | 1187 | #undef __gen6_write |
51f67885 CW |
1188 | #undef GEN6_WRITE_FOOTER |
1189 | #undef GEN6_WRITE_HEADER | |
907b28c5 | 1190 | |
8a74db7a VS |
1191 | #define VGPU_WRITE_HEADER \ |
1192 | unsigned long irqflags; \ | |
1193 | trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ | |
da5827c3 | 1194 | assert_rpm_device_not_suspended(dev_priv); \ |
8a74db7a VS |
1195 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags) |
1196 | ||
1197 | #define VGPU_WRITE_FOOTER \ | |
1198 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags) | |
1199 | ||
1200 | #define __vgpu_write(x) \ | |
1201 | static void vgpu_write##x(struct drm_i915_private *dev_priv, \ | |
f0f59a00 | 1202 | i915_reg_t reg, u##x val, bool trace) { \ |
8a74db7a VS |
1203 | VGPU_WRITE_HEADER; \ |
1204 | __raw_i915_write##x(dev_priv, reg, val); \ | |
1205 | VGPU_WRITE_FOOTER; \ | |
1206 | } | |
1207 | ||
1208 | __vgpu_write(8) | |
1209 | __vgpu_write(16) | |
1210 | __vgpu_write(32) | |
8a74db7a VS |
1211 | |
1212 | #undef __vgpu_write | |
1213 | #undef VGPU_WRITE_FOOTER | |
1214 | #undef VGPU_WRITE_HEADER | |
1215 | ||
43d942a7 YZ |
1216 | #define ASSIGN_WRITE_MMIO_VFUNCS(x) \ |
1217 | do { \ | |
1218 | dev_priv->uncore.funcs.mmio_writeb = x##_write8; \ | |
1219 | dev_priv->uncore.funcs.mmio_writew = x##_write16; \ | |
1220 | dev_priv->uncore.funcs.mmio_writel = x##_write32; \ | |
43d942a7 YZ |
1221 | } while (0) |
1222 | ||
1223 | #define ASSIGN_READ_MMIO_VFUNCS(x) \ | |
1224 | do { \ | |
1225 | dev_priv->uncore.funcs.mmio_readb = x##_read8; \ | |
1226 | dev_priv->uncore.funcs.mmio_readw = x##_read16; \ | |
1227 | dev_priv->uncore.funcs.mmio_readl = x##_read32; \ | |
1228 | dev_priv->uncore.funcs.mmio_readq = x##_read64; \ | |
1229 | } while (0) | |
1230 | ||
05a2fb15 MK |
1231 | |
1232 | static void fw_domain_init(struct drm_i915_private *dev_priv, | |
48c1026a | 1233 | enum forcewake_domain_id domain_id, |
f0f59a00 VS |
1234 | i915_reg_t reg_set, |
1235 | i915_reg_t reg_ack) | |
05a2fb15 MK |
1236 | { |
1237 | struct intel_uncore_forcewake_domain *d; | |
1238 | ||
1239 | if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT)) | |
1240 | return; | |
1241 | ||
1242 | d = &dev_priv->uncore.fw_domain[domain_id]; | |
1243 | ||
1244 | WARN_ON(d->wake_count); | |
1245 | ||
1246 | d->wake_count = 0; | |
1247 | d->reg_set = reg_set; | |
1248 | d->reg_ack = reg_ack; | |
1249 | ||
1250 | if (IS_GEN6(dev_priv)) { | |
1251 | d->val_reset = 0; | |
1252 | d->val_set = FORCEWAKE_KERNEL; | |
1253 | d->val_clear = 0; | |
1254 | } else { | |
8543747c | 1255 | /* WaRsClearFWBitsAtReset:bdw,skl */ |
05a2fb15 MK |
1256 | d->val_reset = _MASKED_BIT_DISABLE(0xffff); |
1257 | d->val_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL); | |
1258 | d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL); | |
1259 | } | |
1260 | ||
666a4537 | 1261 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
05a2fb15 MK |
1262 | d->reg_post = FORCEWAKE_ACK_VLV; |
1263 | else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) | |
1264 | d->reg_post = ECOBUS; | |
05a2fb15 MK |
1265 | |
1266 | d->i915 = dev_priv; | |
1267 | d->id = domain_id; | |
1268 | ||
33c582c1 TU |
1269 | BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER)); |
1270 | BUILD_BUG_ON(FORCEWAKE_BLITTER != (1 << FW_DOMAIN_ID_BLITTER)); | |
1271 | BUILD_BUG_ON(FORCEWAKE_MEDIA != (1 << FW_DOMAIN_ID_MEDIA)); | |
1272 | ||
1273 | d->mask = 1 << domain_id; | |
1274 | ||
a57a4a67 TU |
1275 | hrtimer_init(&d->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); |
1276 | d->timer.function = intel_uncore_fw_release_timer; | |
05a2fb15 MK |
1277 | |
1278 | dev_priv->uncore.fw_domains |= (1 << domain_id); | |
f9b3927a MK |
1279 | |
1280 | fw_domain_reset(d); | |
05a2fb15 MK |
1281 | } |
1282 | ||
dc97997a | 1283 | static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv) |
0b274481 | 1284 | { |
2d1fe073 | 1285 | if (INTEL_INFO(dev_priv)->gen <= 5) |
3225b2f9 MK |
1286 | return; |
1287 | ||
dc97997a | 1288 | if (IS_GEN9(dev_priv)) { |
05a2fb15 MK |
1289 | dev_priv->uncore.funcs.force_wake_get = fw_domains_get; |
1290 | dev_priv->uncore.funcs.force_wake_put = fw_domains_put; | |
1291 | fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, | |
1292 | FORCEWAKE_RENDER_GEN9, | |
1293 | FORCEWAKE_ACK_RENDER_GEN9); | |
1294 | fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER, | |
1295 | FORCEWAKE_BLITTER_GEN9, | |
1296 | FORCEWAKE_ACK_BLITTER_GEN9); | |
1297 | fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA, | |
1298 | FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9); | |
dc97997a | 1299 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
05a2fb15 | 1300 | dev_priv->uncore.funcs.force_wake_get = fw_domains_get; |
dc97997a | 1301 | if (!IS_CHERRYVIEW(dev_priv)) |
756c349d MK |
1302 | dev_priv->uncore.funcs.force_wake_put = |
1303 | fw_domains_put_with_fifo; | |
1304 | else | |
1305 | dev_priv->uncore.funcs.force_wake_put = fw_domains_put; | |
05a2fb15 MK |
1306 | fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, |
1307 | FORCEWAKE_VLV, FORCEWAKE_ACK_VLV); | |
1308 | fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA, | |
1309 | FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV); | |
dc97997a | 1310 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
05a2fb15 MK |
1311 | dev_priv->uncore.funcs.force_wake_get = |
1312 | fw_domains_get_with_thread_status; | |
dc97997a | 1313 | if (IS_HASWELL(dev_priv)) |
3d7d0c85 VS |
1314 | dev_priv->uncore.funcs.force_wake_put = |
1315 | fw_domains_put_with_fifo; | |
1316 | else | |
1317 | dev_priv->uncore.funcs.force_wake_put = fw_domains_put; | |
05a2fb15 MK |
1318 | fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, |
1319 | FORCEWAKE_MT, FORCEWAKE_ACK_HSW); | |
dc97997a | 1320 | } else if (IS_IVYBRIDGE(dev_priv)) { |
0b274481 BW |
1321 | u32 ecobus; |
1322 | ||
1323 | /* IVB configs may use multi-threaded forcewake */ | |
1324 | ||
1325 | /* A small trick here - if the bios hasn't configured | |
1326 | * MT forcewake, and if the device is in RC6, then | |
1327 | * force_wake_mt_get will not wake the device and the | |
1328 | * ECOBUS read will return zero. Which will be | |
1329 | * (correctly) interpreted by the test below as MT | |
1330 | * forcewake being disabled. | |
1331 | */ | |
05a2fb15 MK |
1332 | dev_priv->uncore.funcs.force_wake_get = |
1333 | fw_domains_get_with_thread_status; | |
1334 | dev_priv->uncore.funcs.force_wake_put = | |
1335 | fw_domains_put_with_fifo; | |
1336 | ||
f9b3927a MK |
1337 | /* We need to init first for ECOBUS access and then |
1338 | * determine later if we want to reinit, in case of MT access is | |
6ea2556f MK |
1339 | * not working. In this stage we don't know which flavour this |
1340 | * ivb is, so it is better to reset also the gen6 fw registers | |
1341 | * before the ecobus check. | |
f9b3927a | 1342 | */ |
6ea2556f MK |
1343 | |
1344 | __raw_i915_write32(dev_priv, FORCEWAKE, 0); | |
1345 | __raw_posting_read(dev_priv, ECOBUS); | |
1346 | ||
05a2fb15 MK |
1347 | fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, |
1348 | FORCEWAKE_MT, FORCEWAKE_MT_ACK); | |
f9b3927a | 1349 | |
556ab7a6 | 1350 | spin_lock_irq(&dev_priv->uncore.lock); |
05a2fb15 | 1351 | fw_domains_get_with_thread_status(dev_priv, FORCEWAKE_ALL); |
0b274481 | 1352 | ecobus = __raw_i915_read32(dev_priv, ECOBUS); |
05a2fb15 | 1353 | fw_domains_put_with_fifo(dev_priv, FORCEWAKE_ALL); |
556ab7a6 | 1354 | spin_unlock_irq(&dev_priv->uncore.lock); |
0b274481 | 1355 | |
05a2fb15 | 1356 | if (!(ecobus & FORCEWAKE_MT_ENABLE)) { |
0b274481 BW |
1357 | DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n"); |
1358 | DRM_INFO("when using vblank-synced partial screen updates.\n"); | |
05a2fb15 MK |
1359 | fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, |
1360 | FORCEWAKE, FORCEWAKE_ACK); | |
0b274481 | 1361 | } |
dc97997a | 1362 | } else if (IS_GEN6(dev_priv)) { |
0b274481 | 1363 | dev_priv->uncore.funcs.force_wake_get = |
05a2fb15 | 1364 | fw_domains_get_with_thread_status; |
0b274481 | 1365 | dev_priv->uncore.funcs.force_wake_put = |
05a2fb15 MK |
1366 | fw_domains_put_with_fifo; |
1367 | fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, | |
1368 | FORCEWAKE, FORCEWAKE_ACK); | |
0b274481 | 1369 | } |
3225b2f9 MK |
1370 | |
1371 | /* All future platforms are expected to require complex power gating */ | |
1372 | WARN_ON(dev_priv->uncore.fw_domains == 0); | |
f9b3927a MK |
1373 | } |
1374 | ||
15157970 TU |
1375 | #define ASSIGN_FW_DOMAINS_TABLE(d) \ |
1376 | { \ | |
1377 | dev_priv->uncore.fw_domains_table = \ | |
1378 | (struct intel_forcewake_range *)(d); \ | |
1379 | dev_priv->uncore.fw_domains_table_entries = ARRAY_SIZE((d)); \ | |
1380 | } | |
1381 | ||
dc97997a | 1382 | void intel_uncore_init(struct drm_i915_private *dev_priv) |
f9b3927a | 1383 | { |
dc97997a | 1384 | i915_check_vgpu(dev_priv); |
cf9d2890 | 1385 | |
3accaf7e | 1386 | intel_uncore_edram_detect(dev_priv); |
dc97997a CW |
1387 | intel_uncore_fw_domains_init(dev_priv); |
1388 | __intel_uncore_early_sanitize(dev_priv, false); | |
0b274481 | 1389 | |
75714940 MK |
1390 | dev_priv->uncore.unclaimed_mmio_check = 1; |
1391 | ||
dc97997a | 1392 | switch (INTEL_INFO(dev_priv)->gen) { |
ab2aa47e | 1393 | default: |
4597a88a | 1394 | case 9: |
15157970 | 1395 | ASSIGN_FW_DOMAINS_TABLE(__gen9_fw_ranges); |
22d48c55 | 1396 | ASSIGN_WRITE_MMIO_VFUNCS(fwtable); |
6044c4a3 | 1397 | ASSIGN_READ_MMIO_VFUNCS(fwtable); |
85ee17eb PP |
1398 | if (HAS_DECOUPLED_MMIO(dev_priv)) { |
1399 | dev_priv->uncore.funcs.mmio_readl = | |
1400 | gen9_decoupled_read32; | |
1401 | dev_priv->uncore.funcs.mmio_readq = | |
1402 | gen9_decoupled_read64; | |
1403 | dev_priv->uncore.funcs.mmio_writel = | |
1404 | gen9_decoupled_write32; | |
1405 | } | |
4597a88a ZW |
1406 | break; |
1407 | case 8: | |
dc97997a | 1408 | if (IS_CHERRYVIEW(dev_priv)) { |
15157970 | 1409 | ASSIGN_FW_DOMAINS_TABLE(__chv_fw_ranges); |
22d48c55 | 1410 | ASSIGN_WRITE_MMIO_VFUNCS(fwtable); |
6044c4a3 | 1411 | ASSIGN_READ_MMIO_VFUNCS(fwtable); |
1938e59a D |
1412 | |
1413 | } else { | |
43d942a7 YZ |
1414 | ASSIGN_WRITE_MMIO_VFUNCS(gen8); |
1415 | ASSIGN_READ_MMIO_VFUNCS(gen6); | |
1938e59a | 1416 | } |
ab2aa47e | 1417 | break; |
3967018e BW |
1418 | case 7: |
1419 | case 6: | |
e9b825f4 | 1420 | ASSIGN_WRITE_MMIO_VFUNCS(gen6); |
940aece4 | 1421 | |
dc97997a | 1422 | if (IS_VALLEYVIEW(dev_priv)) { |
15157970 | 1423 | ASSIGN_FW_DOMAINS_TABLE(__vlv_fw_ranges); |
6044c4a3 | 1424 | ASSIGN_READ_MMIO_VFUNCS(fwtable); |
940aece4 | 1425 | } else { |
43d942a7 | 1426 | ASSIGN_READ_MMIO_VFUNCS(gen6); |
940aece4 | 1427 | } |
3967018e BW |
1428 | break; |
1429 | case 5: | |
43d942a7 YZ |
1430 | ASSIGN_WRITE_MMIO_VFUNCS(gen5); |
1431 | ASSIGN_READ_MMIO_VFUNCS(gen5); | |
3967018e BW |
1432 | break; |
1433 | case 4: | |
1434 | case 3: | |
1435 | case 2: | |
51f67885 CW |
1436 | ASSIGN_WRITE_MMIO_VFUNCS(gen2); |
1437 | ASSIGN_READ_MMIO_VFUNCS(gen2); | |
3967018e BW |
1438 | break; |
1439 | } | |
ed493883 | 1440 | |
15157970 | 1441 | intel_fw_table_check(dev_priv); |
47188574 TU |
1442 | if (INTEL_GEN(dev_priv) >= 8) |
1443 | intel_shadow_table_check(); | |
15157970 | 1444 | |
c033666a | 1445 | if (intel_vgpu_active(dev_priv)) { |
3be0bf5a YZ |
1446 | ASSIGN_WRITE_MMIO_VFUNCS(vgpu); |
1447 | ASSIGN_READ_MMIO_VFUNCS(vgpu); | |
1448 | } | |
1449 | ||
dc97997a | 1450 | i915_check_and_clear_faults(dev_priv); |
0b274481 | 1451 | } |
43d942a7 YZ |
1452 | #undef ASSIGN_WRITE_MMIO_VFUNCS |
1453 | #undef ASSIGN_READ_MMIO_VFUNCS | |
0b274481 | 1454 | |
dc97997a | 1455 | void intel_uncore_fini(struct drm_i915_private *dev_priv) |
0b274481 | 1456 | { |
0b274481 | 1457 | /* Paranoia: make sure we have disabled everything before we exit. */ |
dc97997a CW |
1458 | intel_uncore_sanitize(dev_priv); |
1459 | intel_uncore_forcewake_reset(dev_priv, false); | |
0b274481 BW |
1460 | } |
1461 | ||
ae5702d2 | 1462 | #define GEN_RANGE(l, h) GENMASK((h) - 1, (l) - 1) |
af76ae44 | 1463 | |
907b28c5 | 1464 | static const struct register_whitelist { |
f0f59a00 | 1465 | i915_reg_t offset_ldw, offset_udw; |
907b28c5 | 1466 | uint32_t size; |
af76ae44 DL |
1467 | /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */ |
1468 | uint32_t gen_bitmask; | |
907b28c5 | 1469 | } whitelist[] = { |
8697600b VS |
1470 | { .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE), |
1471 | .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE), | |
1472 | .size = 8, .gen_bitmask = GEN_RANGE(4, 9) }, | |
907b28c5 CW |
1473 | }; |
1474 | ||
1475 | int i915_reg_read_ioctl(struct drm_device *dev, | |
1476 | void *data, struct drm_file *file) | |
1477 | { | |
fac5e23e | 1478 | struct drm_i915_private *dev_priv = to_i915(dev); |
907b28c5 CW |
1479 | struct drm_i915_reg_read *reg = data; |
1480 | struct register_whitelist const *entry = whitelist; | |
648a9bc5 | 1481 | unsigned size; |
f0f59a00 | 1482 | i915_reg_t offset_ldw, offset_udw; |
cf67c70f | 1483 | int i, ret = 0; |
907b28c5 CW |
1484 | |
1485 | for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) { | |
f0f59a00 | 1486 | if (i915_mmio_reg_offset(entry->offset_ldw) == (reg->offset & -entry->size) && |
66478475 | 1487 | (INTEL_INFO(dev_priv)->gen_mask & entry->gen_bitmask)) |
907b28c5 CW |
1488 | break; |
1489 | } | |
1490 | ||
1491 | if (i == ARRAY_SIZE(whitelist)) | |
1492 | return -EINVAL; | |
1493 | ||
648a9bc5 CW |
1494 | /* We use the low bits to encode extra flags as the register should |
1495 | * be naturally aligned (and those that are not so aligned merely | |
1496 | * limit the available flags for that register). | |
1497 | */ | |
8697600b VS |
1498 | offset_ldw = entry->offset_ldw; |
1499 | offset_udw = entry->offset_udw; | |
648a9bc5 | 1500 | size = entry->size; |
f0f59a00 | 1501 | size |= reg->offset ^ i915_mmio_reg_offset(offset_ldw); |
648a9bc5 | 1502 | |
cf67c70f PZ |
1503 | intel_runtime_pm_get(dev_priv); |
1504 | ||
648a9bc5 CW |
1505 | switch (size) { |
1506 | case 8 | 1: | |
8697600b | 1507 | reg->val = I915_READ64_2x32(offset_ldw, offset_udw); |
648a9bc5 | 1508 | break; |
907b28c5 | 1509 | case 8: |
8697600b | 1510 | reg->val = I915_READ64(offset_ldw); |
907b28c5 CW |
1511 | break; |
1512 | case 4: | |
8697600b | 1513 | reg->val = I915_READ(offset_ldw); |
907b28c5 CW |
1514 | break; |
1515 | case 2: | |
8697600b | 1516 | reg->val = I915_READ16(offset_ldw); |
907b28c5 CW |
1517 | break; |
1518 | case 1: | |
8697600b | 1519 | reg->val = I915_READ8(offset_ldw); |
907b28c5 CW |
1520 | break; |
1521 | default: | |
cf67c70f PZ |
1522 | ret = -EINVAL; |
1523 | goto out; | |
907b28c5 CW |
1524 | } |
1525 | ||
cf67c70f PZ |
1526 | out: |
1527 | intel_runtime_pm_put(dev_priv); | |
1528 | return ret; | |
907b28c5 CW |
1529 | } |
1530 | ||
dc97997a | 1531 | static int i915_reset_complete(struct pci_dev *pdev) |
907b28c5 CW |
1532 | { |
1533 | u8 gdrst; | |
dc97997a | 1534 | pci_read_config_byte(pdev, I915_GDRST, &gdrst); |
73bbf6bd | 1535 | return (gdrst & GRDOM_RESET_STATUS) == 0; |
907b28c5 CW |
1536 | } |
1537 | ||
dc97997a | 1538 | static int i915_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask) |
907b28c5 | 1539 | { |
91c8a326 | 1540 | struct pci_dev *pdev = dev_priv->drm.pdev; |
dc97997a | 1541 | |
73bbf6bd | 1542 | /* assert reset for at least 20 usec */ |
dc97997a | 1543 | pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE); |
73bbf6bd | 1544 | udelay(20); |
dc97997a | 1545 | pci_write_config_byte(pdev, I915_GDRST, 0); |
907b28c5 | 1546 | |
dc97997a | 1547 | return wait_for(i915_reset_complete(pdev), 500); |
73bbf6bd VS |
1548 | } |
1549 | ||
dc97997a | 1550 | static int g4x_reset_complete(struct pci_dev *pdev) |
73bbf6bd VS |
1551 | { |
1552 | u8 gdrst; | |
dc97997a | 1553 | pci_read_config_byte(pdev, I915_GDRST, &gdrst); |
73bbf6bd | 1554 | return (gdrst & GRDOM_RESET_ENABLE) == 0; |
907b28c5 CW |
1555 | } |
1556 | ||
dc97997a | 1557 | static int g33_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask) |
408d4b9e | 1558 | { |
91c8a326 | 1559 | struct pci_dev *pdev = dev_priv->drm.pdev; |
dc97997a CW |
1560 | pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE); |
1561 | return wait_for(g4x_reset_complete(pdev), 500); | |
408d4b9e VS |
1562 | } |
1563 | ||
dc97997a | 1564 | static int g4x_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask) |
fa4f53c4 | 1565 | { |
91c8a326 | 1566 | struct pci_dev *pdev = dev_priv->drm.pdev; |
fa4f53c4 VS |
1567 | int ret; |
1568 | ||
dc97997a | 1569 | pci_write_config_byte(pdev, I915_GDRST, |
fa4f53c4 | 1570 | GRDOM_RENDER | GRDOM_RESET_ENABLE); |
dc97997a | 1571 | ret = wait_for(g4x_reset_complete(pdev), 500); |
fa4f53c4 VS |
1572 | if (ret) |
1573 | return ret; | |
1574 | ||
1575 | /* WaVcpClkGateDisableForMediaReset:ctg,elk */ | |
1576 | I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE); | |
1577 | POSTING_READ(VDECCLK_GATE_D); | |
1578 | ||
dc97997a | 1579 | pci_write_config_byte(pdev, I915_GDRST, |
fa4f53c4 | 1580 | GRDOM_MEDIA | GRDOM_RESET_ENABLE); |
dc97997a | 1581 | ret = wait_for(g4x_reset_complete(pdev), 500); |
fa4f53c4 VS |
1582 | if (ret) |
1583 | return ret; | |
1584 | ||
1585 | /* WaVcpClkGateDisableForMediaReset:ctg,elk */ | |
1586 | I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE); | |
1587 | POSTING_READ(VDECCLK_GATE_D); | |
1588 | ||
dc97997a | 1589 | pci_write_config_byte(pdev, I915_GDRST, 0); |
fa4f53c4 VS |
1590 | |
1591 | return 0; | |
1592 | } | |
1593 | ||
dc97997a CW |
1594 | static int ironlake_do_reset(struct drm_i915_private *dev_priv, |
1595 | unsigned engine_mask) | |
907b28c5 | 1596 | { |
907b28c5 CW |
1597 | int ret; |
1598 | ||
c039b7f2 | 1599 | I915_WRITE(ILK_GDSR, |
0f08ffd6 | 1600 | ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE); |
87273b71 CW |
1601 | ret = intel_wait_for_register(dev_priv, |
1602 | ILK_GDSR, ILK_GRDOM_RESET_ENABLE, 0, | |
1603 | 500); | |
907b28c5 CW |
1604 | if (ret) |
1605 | return ret; | |
1606 | ||
c039b7f2 | 1607 | I915_WRITE(ILK_GDSR, |
0f08ffd6 | 1608 | ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE); |
87273b71 CW |
1609 | ret = intel_wait_for_register(dev_priv, |
1610 | ILK_GDSR, ILK_GRDOM_RESET_ENABLE, 0, | |
1611 | 500); | |
9aa7250f VS |
1612 | if (ret) |
1613 | return ret; | |
1614 | ||
c039b7f2 | 1615 | I915_WRITE(ILK_GDSR, 0); |
9aa7250f VS |
1616 | |
1617 | return 0; | |
907b28c5 CW |
1618 | } |
1619 | ||
ee4b6faf MK |
1620 | /* Reset the hardware domains (GENX_GRDOM_*) specified by mask */ |
1621 | static int gen6_hw_domain_reset(struct drm_i915_private *dev_priv, | |
1622 | u32 hw_domain_mask) | |
907b28c5 | 1623 | { |
907b28c5 CW |
1624 | /* GEN6_GDRST is not in the gt power well, no need to check |
1625 | * for fifo space for the write or forcewake the chip for | |
1626 | * the read | |
1627 | */ | |
ee4b6faf | 1628 | __raw_i915_write32(dev_priv, GEN6_GDRST, hw_domain_mask); |
907b28c5 | 1629 | |
ee4b6faf | 1630 | /* Spin waiting for the device to ack the reset requests */ |
4a17fe13 CW |
1631 | return intel_wait_for_register_fw(dev_priv, |
1632 | GEN6_GDRST, hw_domain_mask, 0, | |
1633 | 500); | |
ee4b6faf MK |
1634 | } |
1635 | ||
1636 | /** | |
1637 | * gen6_reset_engines - reset individual engines | |
dc97997a | 1638 | * @dev_priv: i915 device |
ee4b6faf MK |
1639 | * @engine_mask: mask of intel_ring_flag() engines or ALL_ENGINES for full reset |
1640 | * | |
1641 | * This function will reset the individual engines that are set in engine_mask. | |
1642 | * If you provide ALL_ENGINES as mask, full global domain reset will be issued. | |
1643 | * | |
1644 | * Note: It is responsibility of the caller to handle the difference between | |
1645 | * asking full domain reset versus reset for all available individual engines. | |
1646 | * | |
1647 | * Returns 0 on success, nonzero on error. | |
1648 | */ | |
dc97997a CW |
1649 | static int gen6_reset_engines(struct drm_i915_private *dev_priv, |
1650 | unsigned engine_mask) | |
ee4b6faf | 1651 | { |
ee4b6faf MK |
1652 | struct intel_engine_cs *engine; |
1653 | const u32 hw_engine_mask[I915_NUM_ENGINES] = { | |
1654 | [RCS] = GEN6_GRDOM_RENDER, | |
1655 | [BCS] = GEN6_GRDOM_BLT, | |
1656 | [VCS] = GEN6_GRDOM_MEDIA, | |
1657 | [VCS2] = GEN8_GRDOM_MEDIA2, | |
1658 | [VECS] = GEN6_GRDOM_VECS, | |
1659 | }; | |
1660 | u32 hw_mask; | |
1661 | int ret; | |
1662 | ||
1663 | if (engine_mask == ALL_ENGINES) { | |
1664 | hw_mask = GEN6_GRDOM_FULL; | |
1665 | } else { | |
bafb0fce CW |
1666 | unsigned int tmp; |
1667 | ||
ee4b6faf | 1668 | hw_mask = 0; |
bafb0fce | 1669 | for_each_engine_masked(engine, dev_priv, engine_mask, tmp) |
ee4b6faf MK |
1670 | hw_mask |= hw_engine_mask[engine->id]; |
1671 | } | |
1672 | ||
1673 | ret = gen6_hw_domain_reset(dev_priv, hw_mask); | |
907b28c5 | 1674 | |
dc97997a | 1675 | intel_uncore_forcewake_reset(dev_priv, true); |
5babf0fc | 1676 | |
907b28c5 CW |
1677 | return ret; |
1678 | } | |
1679 | ||
1758b90e CW |
1680 | /** |
1681 | * intel_wait_for_register_fw - wait until register matches expected state | |
1682 | * @dev_priv: the i915 device | |
1683 | * @reg: the register to read | |
1684 | * @mask: mask to apply to register value | |
1685 | * @value: expected value | |
1686 | * @timeout_ms: timeout in millisecond | |
1687 | * | |
1688 | * This routine waits until the target register @reg contains the expected | |
3d466cd6 DV |
1689 | * @value after applying the @mask, i.e. it waits until :: |
1690 | * | |
1691 | * (I915_READ_FW(reg) & mask) == value | |
1692 | * | |
1758b90e CW |
1693 | * Otherwise, the wait will timeout after @timeout_ms milliseconds. |
1694 | * | |
1695 | * Note that this routine assumes the caller holds forcewake asserted, it is | |
1696 | * not suitable for very long waits. See intel_wait_for_register() if you | |
1697 | * wish to wait without holding forcewake for the duration (i.e. you expect | |
1698 | * the wait to be slow). | |
1699 | * | |
1700 | * Returns 0 if the register matches the desired condition, or -ETIMEOUT. | |
1701 | */ | |
1702 | int intel_wait_for_register_fw(struct drm_i915_private *dev_priv, | |
1703 | i915_reg_t reg, | |
1704 | const u32 mask, | |
1705 | const u32 value, | |
1706 | const unsigned long timeout_ms) | |
1707 | { | |
1708 | #define done ((I915_READ_FW(reg) & mask) == value) | |
1709 | int ret = wait_for_us(done, 2); | |
1710 | if (ret) | |
1711 | ret = wait_for(done, timeout_ms); | |
1712 | return ret; | |
1713 | #undef done | |
1714 | } | |
1715 | ||
1716 | /** | |
1717 | * intel_wait_for_register - wait until register matches expected state | |
1718 | * @dev_priv: the i915 device | |
1719 | * @reg: the register to read | |
1720 | * @mask: mask to apply to register value | |
1721 | * @value: expected value | |
1722 | * @timeout_ms: timeout in millisecond | |
1723 | * | |
1724 | * This routine waits until the target register @reg contains the expected | |
3d466cd6 DV |
1725 | * @value after applying the @mask, i.e. it waits until :: |
1726 | * | |
1727 | * (I915_READ(reg) & mask) == value | |
1728 | * | |
1758b90e CW |
1729 | * Otherwise, the wait will timeout after @timeout_ms milliseconds. |
1730 | * | |
1731 | * Returns 0 if the register matches the desired condition, or -ETIMEOUT. | |
1732 | */ | |
1733 | int intel_wait_for_register(struct drm_i915_private *dev_priv, | |
1734 | i915_reg_t reg, | |
1735 | const u32 mask, | |
1736 | const u32 value, | |
1737 | const unsigned long timeout_ms) | |
7fd2d269 | 1738 | { |
1758b90e CW |
1739 | |
1740 | unsigned fw = | |
1741 | intel_uncore_forcewake_for_reg(dev_priv, reg, FW_REG_READ); | |
1742 | int ret; | |
1743 | ||
1744 | intel_uncore_forcewake_get(dev_priv, fw); | |
1745 | ret = wait_for_us((I915_READ_FW(reg) & mask) == value, 2); | |
1746 | intel_uncore_forcewake_put(dev_priv, fw); | |
1747 | if (ret) | |
1748 | ret = wait_for((I915_READ_NOTRACE(reg) & mask) == value, | |
1749 | timeout_ms); | |
1750 | ||
1751 | return ret; | |
d431440c TE |
1752 | } |
1753 | ||
1754 | static int gen8_request_engine_reset(struct intel_engine_cs *engine) | |
1755 | { | |
c033666a | 1756 | struct drm_i915_private *dev_priv = engine->i915; |
d431440c | 1757 | int ret; |
d431440c TE |
1758 | |
1759 | I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base), | |
1760 | _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET)); | |
1761 | ||
1758b90e CW |
1762 | ret = intel_wait_for_register_fw(dev_priv, |
1763 | RING_RESET_CTL(engine->mmio_base), | |
1764 | RESET_CTL_READY_TO_RESET, | |
1765 | RESET_CTL_READY_TO_RESET, | |
1766 | 700); | |
d431440c TE |
1767 | if (ret) |
1768 | DRM_ERROR("%s: reset request timeout\n", engine->name); | |
1769 | ||
1770 | return ret; | |
1771 | } | |
1772 | ||
1773 | static void gen8_unrequest_engine_reset(struct intel_engine_cs *engine) | |
1774 | { | |
c033666a | 1775 | struct drm_i915_private *dev_priv = engine->i915; |
d431440c TE |
1776 | |
1777 | I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base), | |
1778 | _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET)); | |
7fd2d269 MK |
1779 | } |
1780 | ||
dc97997a CW |
1781 | static int gen8_reset_engines(struct drm_i915_private *dev_priv, |
1782 | unsigned engine_mask) | |
7fd2d269 | 1783 | { |
7fd2d269 | 1784 | struct intel_engine_cs *engine; |
bafb0fce | 1785 | unsigned int tmp; |
7fd2d269 | 1786 | |
bafb0fce | 1787 | for_each_engine_masked(engine, dev_priv, engine_mask, tmp) |
d431440c | 1788 | if (gen8_request_engine_reset(engine)) |
7fd2d269 | 1789 | goto not_ready; |
7fd2d269 | 1790 | |
dc97997a | 1791 | return gen6_reset_engines(dev_priv, engine_mask); |
7fd2d269 MK |
1792 | |
1793 | not_ready: | |
bafb0fce | 1794 | for_each_engine_masked(engine, dev_priv, engine_mask, tmp) |
d431440c | 1795 | gen8_unrequest_engine_reset(engine); |
7fd2d269 MK |
1796 | |
1797 | return -EIO; | |
1798 | } | |
1799 | ||
dc97997a CW |
1800 | typedef int (*reset_func)(struct drm_i915_private *, unsigned engine_mask); |
1801 | ||
1802 | static reset_func intel_get_gpu_reset(struct drm_i915_private *dev_priv) | |
907b28c5 | 1803 | { |
b1330fbb CW |
1804 | if (!i915.reset) |
1805 | return NULL; | |
1806 | ||
dc97997a | 1807 | if (INTEL_INFO(dev_priv)->gen >= 8) |
ee4b6faf | 1808 | return gen8_reset_engines; |
dc97997a | 1809 | else if (INTEL_INFO(dev_priv)->gen >= 6) |
ee4b6faf | 1810 | return gen6_reset_engines; |
dc97997a | 1811 | else if (IS_GEN5(dev_priv)) |
49e4d842 | 1812 | return ironlake_do_reset; |
dc97997a | 1813 | else if (IS_G4X(dev_priv)) |
49e4d842 | 1814 | return g4x_do_reset; |
73f67aa8 | 1815 | else if (IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) |
49e4d842 | 1816 | return g33_do_reset; |
dc97997a | 1817 | else if (INTEL_INFO(dev_priv)->gen >= 3) |
49e4d842 | 1818 | return i915_do_reset; |
542c184f | 1819 | else |
49e4d842 CW |
1820 | return NULL; |
1821 | } | |
1822 | ||
dc97997a | 1823 | int intel_gpu_reset(struct drm_i915_private *dev_priv, unsigned engine_mask) |
49e4d842 | 1824 | { |
dc97997a | 1825 | reset_func reset; |
99106bc1 | 1826 | int ret; |
49e4d842 | 1827 | |
dc97997a | 1828 | reset = intel_get_gpu_reset(dev_priv); |
49e4d842 | 1829 | if (reset == NULL) |
542c184f | 1830 | return -ENODEV; |
49e4d842 | 1831 | |
99106bc1 MK |
1832 | /* If the power well sleeps during the reset, the reset |
1833 | * request may be dropped and never completes (causing -EIO). | |
1834 | */ | |
1835 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
dc97997a | 1836 | ret = reset(dev_priv, engine_mask); |
99106bc1 MK |
1837 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
1838 | ||
1839 | return ret; | |
49e4d842 CW |
1840 | } |
1841 | ||
dc97997a | 1842 | bool intel_has_gpu_reset(struct drm_i915_private *dev_priv) |
49e4d842 | 1843 | { |
dc97997a | 1844 | return intel_get_gpu_reset(dev_priv) != NULL; |
907b28c5 CW |
1845 | } |
1846 | ||
6b332fa2 AS |
1847 | int intel_guc_reset(struct drm_i915_private *dev_priv) |
1848 | { | |
1849 | int ret; | |
1850 | unsigned long irqflags; | |
1851 | ||
1a3d1898 | 1852 | if (!HAS_GUC(dev_priv)) |
6b332fa2 AS |
1853 | return -EINVAL; |
1854 | ||
1855 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
1856 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
1857 | ||
1858 | ret = gen6_hw_domain_reset(dev_priv, GEN9_GRDOM_GUC); | |
1859 | ||
1860 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
1861 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
1862 | ||
1863 | return ret; | |
1864 | } | |
1865 | ||
fc97618b | 1866 | bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv) |
907b28c5 | 1867 | { |
fc97618b | 1868 | return check_for_unclaimed_mmio(dev_priv); |
907b28c5 | 1869 | } |
75714940 | 1870 | |
bc3b9346 | 1871 | bool |
75714940 MK |
1872 | intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv) |
1873 | { | |
1874 | if (unlikely(i915.mmio_debug || | |
1875 | dev_priv->uncore.unclaimed_mmio_check <= 0)) | |
bc3b9346 | 1876 | return false; |
75714940 MK |
1877 | |
1878 | if (unlikely(intel_uncore_unclaimed_mmio(dev_priv))) { | |
1879 | DRM_DEBUG("Unclaimed register detected, " | |
1880 | "enabling oneshot unclaimed register reporting. " | |
1881 | "Please use i915.mmio_debug=N for more information.\n"); | |
1882 | i915.mmio_debug++; | |
1883 | dev_priv->uncore.unclaimed_mmio_check--; | |
bc3b9346 | 1884 | return true; |
75714940 | 1885 | } |
bc3b9346 MK |
1886 | |
1887 | return false; | |
75714940 | 1888 | } |
3756685a TU |
1889 | |
1890 | static enum forcewake_domains | |
1891 | intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv, | |
1892 | i915_reg_t reg) | |
1893 | { | |
895833bd | 1894 | u32 offset = i915_mmio_reg_offset(reg); |
3756685a TU |
1895 | enum forcewake_domains fw_domains; |
1896 | ||
895833bd TU |
1897 | if (HAS_FWTABLE(dev_priv)) { |
1898 | fw_domains = __fwtable_reg_read_fw_domains(offset); | |
1899 | } else if (INTEL_GEN(dev_priv) >= 6) { | |
1900 | fw_domains = __gen6_reg_read_fw_domains(offset); | |
1901 | } else { | |
1902 | WARN_ON(!IS_GEN(dev_priv, 2, 5)); | |
1903 | fw_domains = 0; | |
3756685a TU |
1904 | } |
1905 | ||
1906 | WARN_ON(fw_domains & ~dev_priv->uncore.fw_domains); | |
1907 | ||
1908 | return fw_domains; | |
1909 | } | |
1910 | ||
1911 | static enum forcewake_domains | |
1912 | intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv, | |
1913 | i915_reg_t reg) | |
1914 | { | |
22d48c55 | 1915 | u32 offset = i915_mmio_reg_offset(reg); |
3756685a TU |
1916 | enum forcewake_domains fw_domains; |
1917 | ||
22d48c55 TU |
1918 | if (HAS_FWTABLE(dev_priv) && !IS_VALLEYVIEW(dev_priv)) { |
1919 | fw_domains = __fwtable_reg_write_fw_domains(offset); | |
1920 | } else if (IS_GEN8(dev_priv)) { | |
1921 | fw_domains = __gen8_reg_write_fw_domains(offset); | |
1922 | } else if (IS_GEN(dev_priv, 6, 7)) { | |
3756685a | 1923 | fw_domains = FORCEWAKE_RENDER; |
22d48c55 TU |
1924 | } else { |
1925 | WARN_ON(!IS_GEN(dev_priv, 2, 5)); | |
1926 | fw_domains = 0; | |
3756685a TU |
1927 | } |
1928 | ||
1929 | WARN_ON(fw_domains & ~dev_priv->uncore.fw_domains); | |
1930 | ||
1931 | return fw_domains; | |
1932 | } | |
1933 | ||
1934 | /** | |
1935 | * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access | |
1936 | * a register | |
1937 | * @dev_priv: pointer to struct drm_i915_private | |
1938 | * @reg: register in question | |
1939 | * @op: operation bitmask of FW_REG_READ and/or FW_REG_WRITE | |
1940 | * | |
1941 | * Returns a set of forcewake domains required to be taken with for example | |
1942 | * intel_uncore_forcewake_get for the specified register to be accessible in the | |
1943 | * specified mode (read, write or read/write) with raw mmio accessors. | |
1944 | * | |
1945 | * NOTE: On Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the | |
1946 | * callers to do FIFO management on their own or risk losing writes. | |
1947 | */ | |
1948 | enum forcewake_domains | |
1949 | intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv, | |
1950 | i915_reg_t reg, unsigned int op) | |
1951 | { | |
1952 | enum forcewake_domains fw_domains = 0; | |
1953 | ||
1954 | WARN_ON(!op); | |
1955 | ||
895833bd TU |
1956 | if (intel_vgpu_active(dev_priv)) |
1957 | return 0; | |
1958 | ||
3756685a TU |
1959 | if (op & FW_REG_READ) |
1960 | fw_domains = intel_uncore_forcewake_for_read(dev_priv, reg); | |
1961 | ||
1962 | if (op & FW_REG_WRITE) | |
1963 | fw_domains |= intel_uncore_forcewake_for_write(dev_priv, reg); | |
1964 | ||
1965 | return fw_domains; | |
1966 | } |