Commit | Line | Data |
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907b28c5 CW |
1 | /* |
2 | * Copyright © 2013 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | */ | |
23 | ||
24 | #include "i915_drv.h" | |
25 | #include "intel_drv.h" | |
cf9d2890 | 26 | #include "i915_vgpu.h" |
907b28c5 | 27 | |
6daccb0b CW |
28 | #include <linux/pm_runtime.h> |
29 | ||
83e33372 | 30 | #define FORCEWAKE_ACK_TIMEOUT_MS 50 |
907b28c5 | 31 | |
75aa3f63 | 32 | #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32((dev_priv__), (reg__)) |
6af5d92f | 33 | |
05a2fb15 MK |
34 | static const char * const forcewake_domain_names[] = { |
35 | "render", | |
36 | "blitter", | |
37 | "media", | |
38 | }; | |
39 | ||
40 | const char * | |
48c1026a | 41 | intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id) |
05a2fb15 | 42 | { |
53abb679 | 43 | BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT); |
05a2fb15 MK |
44 | |
45 | if (id >= 0 && id < FW_DOMAIN_ID_COUNT) | |
46 | return forcewake_domain_names[id]; | |
47 | ||
48 | WARN_ON(id); | |
49 | ||
50 | return "unknown"; | |
51 | } | |
52 | ||
05a2fb15 MK |
53 | static inline void |
54 | fw_domain_reset(const struct intel_uncore_forcewake_domain *d) | |
907b28c5 | 55 | { |
f0f59a00 | 56 | WARN_ON(!i915_mmio_reg_valid(d->reg_set)); |
05a2fb15 | 57 | __raw_i915_write32(d->i915, d->reg_set, d->val_reset); |
907b28c5 CW |
58 | } |
59 | ||
05a2fb15 MK |
60 | static inline void |
61 | fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d) | |
907b28c5 | 62 | { |
05a2fb15 | 63 | mod_timer_pinned(&d->timer, jiffies + 1); |
907b28c5 CW |
64 | } |
65 | ||
05a2fb15 MK |
66 | static inline void |
67 | fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d) | |
907b28c5 | 68 | { |
05a2fb15 MK |
69 | if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) & |
70 | FORCEWAKE_KERNEL) == 0, | |
907b28c5 | 71 | FORCEWAKE_ACK_TIMEOUT_MS)) |
05a2fb15 MK |
72 | DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n", |
73 | intel_uncore_forcewake_domain_to_str(d->id)); | |
74 | } | |
907b28c5 | 75 | |
05a2fb15 MK |
76 | static inline void |
77 | fw_domain_get(const struct intel_uncore_forcewake_domain *d) | |
78 | { | |
79 | __raw_i915_write32(d->i915, d->reg_set, d->val_set); | |
80 | } | |
907b28c5 | 81 | |
05a2fb15 MK |
82 | static inline void |
83 | fw_domain_wait_ack(const struct intel_uncore_forcewake_domain *d) | |
84 | { | |
85 | if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) & | |
86 | FORCEWAKE_KERNEL), | |
907b28c5 | 87 | FORCEWAKE_ACK_TIMEOUT_MS)) |
05a2fb15 MK |
88 | DRM_ERROR("%s: timed out waiting for forcewake ack request.\n", |
89 | intel_uncore_forcewake_domain_to_str(d->id)); | |
90 | } | |
907b28c5 | 91 | |
05a2fb15 MK |
92 | static inline void |
93 | fw_domain_put(const struct intel_uncore_forcewake_domain *d) | |
94 | { | |
95 | __raw_i915_write32(d->i915, d->reg_set, d->val_clear); | |
907b28c5 CW |
96 | } |
97 | ||
05a2fb15 MK |
98 | static inline void |
99 | fw_domain_posting_read(const struct intel_uncore_forcewake_domain *d) | |
907b28c5 | 100 | { |
05a2fb15 | 101 | /* something from same cacheline, but not from the set register */ |
f0f59a00 | 102 | if (i915_mmio_reg_valid(d->reg_post)) |
05a2fb15 | 103 | __raw_posting_read(d->i915, d->reg_post); |
907b28c5 CW |
104 | } |
105 | ||
05a2fb15 | 106 | static void |
48c1026a | 107 | fw_domains_get(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains) |
907b28c5 | 108 | { |
05a2fb15 | 109 | struct intel_uncore_forcewake_domain *d; |
48c1026a | 110 | enum forcewake_domain_id id; |
907b28c5 | 111 | |
05a2fb15 MK |
112 | for_each_fw_domain_mask(d, fw_domains, dev_priv, id) { |
113 | fw_domain_wait_ack_clear(d); | |
114 | fw_domain_get(d); | |
05a2fb15 MK |
115 | fw_domain_wait_ack(d); |
116 | } | |
117 | } | |
907b28c5 | 118 | |
05a2fb15 | 119 | static void |
48c1026a | 120 | fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains) |
05a2fb15 MK |
121 | { |
122 | struct intel_uncore_forcewake_domain *d; | |
48c1026a | 123 | enum forcewake_domain_id id; |
907b28c5 | 124 | |
05a2fb15 MK |
125 | for_each_fw_domain_mask(d, fw_domains, dev_priv, id) { |
126 | fw_domain_put(d); | |
127 | fw_domain_posting_read(d); | |
128 | } | |
129 | } | |
907b28c5 | 130 | |
05a2fb15 MK |
131 | static void |
132 | fw_domains_posting_read(struct drm_i915_private *dev_priv) | |
133 | { | |
134 | struct intel_uncore_forcewake_domain *d; | |
48c1026a | 135 | enum forcewake_domain_id id; |
05a2fb15 MK |
136 | |
137 | /* No need to do for all, just do for first found */ | |
138 | for_each_fw_domain(d, dev_priv, id) { | |
139 | fw_domain_posting_read(d); | |
140 | break; | |
141 | } | |
142 | } | |
143 | ||
144 | static void | |
48c1026a | 145 | fw_domains_reset(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains) |
05a2fb15 MK |
146 | { |
147 | struct intel_uncore_forcewake_domain *d; | |
48c1026a | 148 | enum forcewake_domain_id id; |
05a2fb15 | 149 | |
3225b2f9 MK |
150 | if (dev_priv->uncore.fw_domains == 0) |
151 | return; | |
f9b3927a | 152 | |
05a2fb15 MK |
153 | for_each_fw_domain_mask(d, fw_domains, dev_priv, id) |
154 | fw_domain_reset(d); | |
155 | ||
156 | fw_domains_posting_read(dev_priv); | |
157 | } | |
158 | ||
159 | static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) | |
160 | { | |
161 | /* w/a for a sporadic read returning 0 by waiting for the GT | |
162 | * thread to wake up. | |
163 | */ | |
164 | if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) & | |
165 | GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500)) | |
166 | DRM_ERROR("GT thread status wait timed out\n"); | |
167 | } | |
168 | ||
169 | static void fw_domains_get_with_thread_status(struct drm_i915_private *dev_priv, | |
48c1026a | 170 | enum forcewake_domains fw_domains) |
05a2fb15 MK |
171 | { |
172 | fw_domains_get(dev_priv, fw_domains); | |
907b28c5 | 173 | |
05a2fb15 | 174 | /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */ |
c549f738 | 175 | __gen6_gt_wait_for_thread_c0(dev_priv); |
907b28c5 CW |
176 | } |
177 | ||
178 | static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) | |
179 | { | |
180 | u32 gtfifodbg; | |
6af5d92f CW |
181 | |
182 | gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG); | |
90f256b5 VS |
183 | if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg)) |
184 | __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg); | |
907b28c5 CW |
185 | } |
186 | ||
05a2fb15 | 187 | static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv, |
48c1026a | 188 | enum forcewake_domains fw_domains) |
907b28c5 | 189 | { |
05a2fb15 | 190 | fw_domains_put(dev_priv, fw_domains); |
907b28c5 CW |
191 | gen6_gt_check_fifodbg(dev_priv); |
192 | } | |
193 | ||
c32e3788 DG |
194 | static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv) |
195 | { | |
196 | u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL); | |
197 | ||
198 | return count & GT_FIFO_FREE_ENTRIES_MASK; | |
199 | } | |
200 | ||
907b28c5 CW |
201 | static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) |
202 | { | |
203 | int ret = 0; | |
204 | ||
5135d64b D |
205 | /* On VLV, FIFO will be shared by both SW and HW. |
206 | * So, we need to read the FREE_ENTRIES everytime */ | |
207 | if (IS_VALLEYVIEW(dev_priv->dev)) | |
c32e3788 | 208 | dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv); |
5135d64b | 209 | |
907b28c5 CW |
210 | if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { |
211 | int loop = 500; | |
c32e3788 DG |
212 | u32 fifo = fifo_free_entries(dev_priv); |
213 | ||
907b28c5 CW |
214 | while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { |
215 | udelay(10); | |
c32e3788 | 216 | fifo = fifo_free_entries(dev_priv); |
907b28c5 CW |
217 | } |
218 | if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) | |
219 | ++ret; | |
220 | dev_priv->uncore.fifo_count = fifo; | |
221 | } | |
222 | dev_priv->uncore.fifo_count--; | |
223 | ||
224 | return ret; | |
225 | } | |
226 | ||
59bad947 | 227 | static void intel_uncore_fw_release_timer(unsigned long arg) |
38cff0b1 | 228 | { |
b2cff0db CW |
229 | struct intel_uncore_forcewake_domain *domain = (void *)arg; |
230 | unsigned long irqflags; | |
38cff0b1 | 231 | |
da5827c3 | 232 | assert_rpm_device_not_suspended(domain->i915); |
38cff0b1 | 233 | |
b2cff0db CW |
234 | spin_lock_irqsave(&domain->i915->uncore.lock, irqflags); |
235 | if (WARN_ON(domain->wake_count == 0)) | |
236 | domain->wake_count++; | |
237 | ||
238 | if (--domain->wake_count == 0) | |
239 | domain->i915->uncore.funcs.force_wake_put(domain->i915, | |
240 | 1 << domain->id); | |
241 | ||
242 | spin_unlock_irqrestore(&domain->i915->uncore.lock, irqflags); | |
38cff0b1 ZW |
243 | } |
244 | ||
b2cff0db | 245 | void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore) |
38cff0b1 | 246 | { |
b2cff0db | 247 | struct drm_i915_private *dev_priv = dev->dev_private; |
48c1026a | 248 | unsigned long irqflags; |
b2cff0db | 249 | struct intel_uncore_forcewake_domain *domain; |
48c1026a MK |
250 | int retry_count = 100; |
251 | enum forcewake_domain_id id; | |
252 | enum forcewake_domains fw = 0, active_domains; | |
38cff0b1 | 253 | |
b2cff0db CW |
254 | /* Hold uncore.lock across reset to prevent any register access |
255 | * with forcewake not set correctly. Wait until all pending | |
256 | * timers are run before holding. | |
257 | */ | |
258 | while (1) { | |
259 | active_domains = 0; | |
38cff0b1 | 260 | |
b2cff0db CW |
261 | for_each_fw_domain(domain, dev_priv, id) { |
262 | if (del_timer_sync(&domain->timer) == 0) | |
263 | continue; | |
38cff0b1 | 264 | |
59bad947 | 265 | intel_uncore_fw_release_timer((unsigned long)domain); |
b2cff0db | 266 | } |
aec347ab | 267 | |
b2cff0db | 268 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
b2ec142c | 269 | |
b2cff0db CW |
270 | for_each_fw_domain(domain, dev_priv, id) { |
271 | if (timer_pending(&domain->timer)) | |
272 | active_domains |= (1 << id); | |
273 | } | |
3123fcaf | 274 | |
b2cff0db CW |
275 | if (active_domains == 0) |
276 | break; | |
aec347ab | 277 | |
b2cff0db CW |
278 | if (--retry_count == 0) { |
279 | DRM_ERROR("Timed out waiting for forcewake timers to finish\n"); | |
280 | break; | |
281 | } | |
0294ae7b | 282 | |
b2cff0db CW |
283 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
284 | cond_resched(); | |
285 | } | |
0294ae7b | 286 | |
b2cff0db CW |
287 | WARN_ON(active_domains); |
288 | ||
289 | for_each_fw_domain(domain, dev_priv, id) | |
290 | if (domain->wake_count) | |
291 | fw |= 1 << id; | |
292 | ||
293 | if (fw) | |
294 | dev_priv->uncore.funcs.force_wake_put(dev_priv, fw); | |
ef46e0d2 | 295 | |
05a2fb15 | 296 | fw_domains_reset(dev_priv, FORCEWAKE_ALL); |
38cff0b1 | 297 | |
0294ae7b | 298 | if (restore) { /* If reset with a user forcewake, try to restore */ |
0294ae7b CW |
299 | if (fw) |
300 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fw); | |
301 | ||
302 | if (IS_GEN6(dev) || IS_GEN7(dev)) | |
303 | dev_priv->uncore.fifo_count = | |
c32e3788 | 304 | fifo_free_entries(dev_priv); |
0294ae7b CW |
305 | } |
306 | ||
b2cff0db | 307 | if (!restore) |
59bad947 | 308 | assert_forcewakes_inactive(dev_priv); |
b2cff0db | 309 | |
0294ae7b | 310 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
ef46e0d2 DV |
311 | } |
312 | ||
f9b3927a | 313 | static void intel_uncore_ellc_detect(struct drm_device *dev) |
907b28c5 CW |
314 | { |
315 | struct drm_i915_private *dev_priv = dev->dev_private; | |
316 | ||
e25dca86 DL |
317 | if ((IS_HASWELL(dev) || IS_BROADWELL(dev) || |
318 | INTEL_INFO(dev)->gen >= 9) && | |
2db59d53 | 319 | (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) & EDRAM_ENABLED)) { |
18ce3994 BW |
320 | /* The docs do not explain exactly how the calculation can be |
321 | * made. It is somewhat guessable, but for now, it's always | |
322 | * 128MB. | |
323 | * NB: We can't write IDICR yet because we do not have gt funcs | |
324 | * set up */ | |
325 | dev_priv->ellc_size = 128; | |
326 | DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size); | |
327 | } | |
f9b3927a MK |
328 | } |
329 | ||
8a47eb19 MK |
330 | static bool |
331 | check_for_unclaimed_mmio(struct drm_i915_private *dev_priv) | |
332 | { | |
333 | u32 dbg; | |
334 | ||
335 | if (!HAS_FPGA_DBG_UNCLAIMED(dev_priv)) | |
336 | return false; | |
337 | ||
338 | dbg = __raw_i915_read32(dev_priv, FPGA_DBG); | |
339 | if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM))) | |
340 | return false; | |
341 | ||
342 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); | |
343 | ||
344 | return true; | |
345 | } | |
346 | ||
f9b3927a MK |
347 | static void __intel_uncore_early_sanitize(struct drm_device *dev, |
348 | bool restore_forcewake) | |
349 | { | |
350 | struct drm_i915_private *dev_priv = dev->dev_private; | |
351 | ||
8a47eb19 MK |
352 | /* clear out unclaimed reg detection bit */ |
353 | if (check_for_unclaimed_mmio(dev_priv)) | |
354 | DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n"); | |
907b28c5 | 355 | |
97058870 VS |
356 | /* clear out old GT FIFO errors */ |
357 | if (IS_GEN6(dev) || IS_GEN7(dev)) | |
358 | __raw_i915_write32(dev_priv, GTFIFODBG, | |
359 | __raw_i915_read32(dev_priv, GTFIFODBG)); | |
360 | ||
a04f90a3 D |
361 | /* WaDisableShadowRegForCpd:chv */ |
362 | if (IS_CHERRYVIEW(dev)) { | |
363 | __raw_i915_write32(dev_priv, GTFIFOCTL, | |
364 | __raw_i915_read32(dev_priv, GTFIFOCTL) | | |
365 | GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL | | |
366 | GT_FIFO_CTL_RC6_POLICY_STALL); | |
367 | } | |
368 | ||
10018603 | 369 | intel_uncore_forcewake_reset(dev, restore_forcewake); |
521198a2 MK |
370 | } |
371 | ||
ed493883 ID |
372 | void intel_uncore_early_sanitize(struct drm_device *dev, bool restore_forcewake) |
373 | { | |
374 | __intel_uncore_early_sanitize(dev, restore_forcewake); | |
375 | i915_check_and_clear_faults(dev); | |
376 | } | |
377 | ||
521198a2 MK |
378 | void intel_uncore_sanitize(struct drm_device *dev) |
379 | { | |
907b28c5 CW |
380 | /* BIOS often leaves RC6 enabled, but disable it for hw init */ |
381 | intel_disable_gt_powersave(dev); | |
382 | } | |
383 | ||
a6111f7b CW |
384 | static void __intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, |
385 | enum forcewake_domains fw_domains) | |
386 | { | |
387 | struct intel_uncore_forcewake_domain *domain; | |
388 | enum forcewake_domain_id id; | |
389 | ||
390 | if (!dev_priv->uncore.funcs.force_wake_get) | |
391 | return; | |
392 | ||
393 | fw_domains &= dev_priv->uncore.fw_domains; | |
394 | ||
395 | for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) { | |
396 | if (domain->wake_count++) | |
397 | fw_domains &= ~(1 << id); | |
398 | } | |
399 | ||
400 | if (fw_domains) | |
401 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains); | |
402 | } | |
403 | ||
59bad947 MK |
404 | /** |
405 | * intel_uncore_forcewake_get - grab forcewake domain references | |
406 | * @dev_priv: i915 device instance | |
407 | * @fw_domains: forcewake domains to get reference on | |
408 | * | |
409 | * This function can be used get GT's forcewake domain references. | |
410 | * Normal register access will handle the forcewake domains automatically. | |
411 | * However if some sequence requires the GT to not power down a particular | |
412 | * forcewake domains this function should be called at the beginning of the | |
413 | * sequence. And subsequently the reference should be dropped by symmetric | |
414 | * call to intel_unforce_forcewake_put(). Usually caller wants all the domains | |
415 | * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL. | |
907b28c5 | 416 | */ |
59bad947 | 417 | void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, |
48c1026a | 418 | enum forcewake_domains fw_domains) |
907b28c5 CW |
419 | { |
420 | unsigned long irqflags; | |
421 | ||
ab484f8f BW |
422 | if (!dev_priv->uncore.funcs.force_wake_get) |
423 | return; | |
424 | ||
c9b8846a | 425 | assert_rpm_wakelock_held(dev_priv); |
c8c8fb33 | 426 | |
6daccb0b | 427 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
a6111f7b | 428 | __intel_uncore_forcewake_get(dev_priv, fw_domains); |
907b28c5 CW |
429 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
430 | } | |
431 | ||
59bad947 | 432 | /** |
a6111f7b | 433 | * intel_uncore_forcewake_get__locked - grab forcewake domain references |
59bad947 | 434 | * @dev_priv: i915 device instance |
a6111f7b | 435 | * @fw_domains: forcewake domains to get reference on |
59bad947 | 436 | * |
a6111f7b CW |
437 | * See intel_uncore_forcewake_get(). This variant places the onus |
438 | * on the caller to explicitly handle the dev_priv->uncore.lock spinlock. | |
907b28c5 | 439 | */ |
a6111f7b CW |
440 | void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv, |
441 | enum forcewake_domains fw_domains) | |
442 | { | |
443 | assert_spin_locked(&dev_priv->uncore.lock); | |
444 | ||
445 | if (!dev_priv->uncore.funcs.force_wake_get) | |
446 | return; | |
447 | ||
448 | __intel_uncore_forcewake_get(dev_priv, fw_domains); | |
449 | } | |
450 | ||
451 | static void __intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, | |
452 | enum forcewake_domains fw_domains) | |
907b28c5 | 453 | { |
b2cff0db | 454 | struct intel_uncore_forcewake_domain *domain; |
48c1026a | 455 | enum forcewake_domain_id id; |
907b28c5 | 456 | |
ab484f8f BW |
457 | if (!dev_priv->uncore.funcs.force_wake_put) |
458 | return; | |
459 | ||
b2cff0db CW |
460 | fw_domains &= dev_priv->uncore.fw_domains; |
461 | ||
b2cff0db CW |
462 | for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) { |
463 | if (WARN_ON(domain->wake_count == 0)) | |
464 | continue; | |
465 | ||
466 | if (--domain->wake_count) | |
467 | continue; | |
468 | ||
469 | domain->wake_count++; | |
05a2fb15 | 470 | fw_domain_arm_timer(domain); |
aec347ab | 471 | } |
a6111f7b | 472 | } |
dc9fb09c | 473 | |
a6111f7b CW |
474 | /** |
475 | * intel_uncore_forcewake_put - release a forcewake domain reference | |
476 | * @dev_priv: i915 device instance | |
477 | * @fw_domains: forcewake domains to put references | |
478 | * | |
479 | * This function drops the device-level forcewakes for specified | |
480 | * domains obtained by intel_uncore_forcewake_get(). | |
481 | */ | |
482 | void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, | |
483 | enum forcewake_domains fw_domains) | |
484 | { | |
485 | unsigned long irqflags; | |
486 | ||
487 | if (!dev_priv->uncore.funcs.force_wake_put) | |
488 | return; | |
489 | ||
490 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
491 | __intel_uncore_forcewake_put(dev_priv, fw_domains); | |
907b28c5 CW |
492 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
493 | } | |
494 | ||
a6111f7b CW |
495 | /** |
496 | * intel_uncore_forcewake_put__locked - grab forcewake domain references | |
497 | * @dev_priv: i915 device instance | |
498 | * @fw_domains: forcewake domains to get reference on | |
499 | * | |
500 | * See intel_uncore_forcewake_put(). This variant places the onus | |
501 | * on the caller to explicitly handle the dev_priv->uncore.lock spinlock. | |
502 | */ | |
503 | void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv, | |
504 | enum forcewake_domains fw_domains) | |
505 | { | |
506 | assert_spin_locked(&dev_priv->uncore.lock); | |
507 | ||
508 | if (!dev_priv->uncore.funcs.force_wake_put) | |
509 | return; | |
510 | ||
511 | __intel_uncore_forcewake_put(dev_priv, fw_domains); | |
512 | } | |
513 | ||
59bad947 | 514 | void assert_forcewakes_inactive(struct drm_i915_private *dev_priv) |
e998c40f | 515 | { |
b2cff0db | 516 | struct intel_uncore_forcewake_domain *domain; |
48c1026a | 517 | enum forcewake_domain_id id; |
b2cff0db | 518 | |
e998c40f PZ |
519 | if (!dev_priv->uncore.funcs.force_wake_get) |
520 | return; | |
521 | ||
05a2fb15 | 522 | for_each_fw_domain(domain, dev_priv, id) |
b2cff0db | 523 | WARN_ON(domain->wake_count); |
e998c40f PZ |
524 | } |
525 | ||
907b28c5 | 526 | /* We give fast paths for the really cool registers */ |
40181697 | 527 | #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000) |
907b28c5 | 528 | |
1938e59a | 529 | #define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end)) |
38fb6a40 | 530 | |
1938e59a D |
531 | #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \ |
532 | (REG_RANGE((reg), 0x2000, 0x4000) || \ | |
533 | REG_RANGE((reg), 0x5000, 0x8000) || \ | |
534 | REG_RANGE((reg), 0xB000, 0x12000) || \ | |
535 | REG_RANGE((reg), 0x2E000, 0x30000)) | |
536 | ||
537 | #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \ | |
538 | (REG_RANGE((reg), 0x12000, 0x14000) || \ | |
539 | REG_RANGE((reg), 0x22000, 0x24000) || \ | |
540 | REG_RANGE((reg), 0x30000, 0x40000)) | |
541 | ||
542 | #define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \ | |
543 | (REG_RANGE((reg), 0x2000, 0x4000) || \ | |
db5ff4ac | 544 | REG_RANGE((reg), 0x5200, 0x8000) || \ |
1938e59a | 545 | REG_RANGE((reg), 0x8300, 0x8500) || \ |
db5ff4ac | 546 | REG_RANGE((reg), 0xB000, 0xB480) || \ |
1938e59a D |
547 | REG_RANGE((reg), 0xE000, 0xE800)) |
548 | ||
549 | #define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \ | |
550 | (REG_RANGE((reg), 0x8800, 0x8900) || \ | |
551 | REG_RANGE((reg), 0xD000, 0xD800) || \ | |
552 | REG_RANGE((reg), 0x12000, 0x14000) || \ | |
553 | REG_RANGE((reg), 0x1A000, 0x1C000) || \ | |
554 | REG_RANGE((reg), 0x1E800, 0x1EA00) || \ | |
db5ff4ac | 555 | REG_RANGE((reg), 0x30000, 0x38000)) |
1938e59a D |
556 | |
557 | #define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \ | |
558 | (REG_RANGE((reg), 0x4000, 0x5000) || \ | |
559 | REG_RANGE((reg), 0x8000, 0x8300) || \ | |
560 | REG_RANGE((reg), 0x8500, 0x8600) || \ | |
561 | REG_RANGE((reg), 0x9000, 0xB000) || \ | |
db5ff4ac | 562 | REG_RANGE((reg), 0xF000, 0x10000)) |
38fb6a40 | 563 | |
4597a88a | 564 | #define FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) \ |
8ee558d8 | 565 | REG_RANGE((reg), 0xB00, 0x2000) |
4597a88a ZW |
566 | |
567 | #define FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) \ | |
8ee558d8 AG |
568 | (REG_RANGE((reg), 0x2000, 0x2700) || \ |
569 | REG_RANGE((reg), 0x3000, 0x4000) || \ | |
4597a88a | 570 | REG_RANGE((reg), 0x5200, 0x8000) || \ |
8ee558d8 | 571 | REG_RANGE((reg), 0x8140, 0x8160) || \ |
4597a88a ZW |
572 | REG_RANGE((reg), 0x8300, 0x8500) || \ |
573 | REG_RANGE((reg), 0x8C00, 0x8D00) || \ | |
574 | REG_RANGE((reg), 0xB000, 0xB480) || \ | |
8ee558d8 AG |
575 | REG_RANGE((reg), 0xE000, 0xE900) || \ |
576 | REG_RANGE((reg), 0x24400, 0x24800)) | |
4597a88a ZW |
577 | |
578 | #define FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) \ | |
8ee558d8 AG |
579 | (REG_RANGE((reg), 0x8130, 0x8140) || \ |
580 | REG_RANGE((reg), 0x8800, 0x8A00) || \ | |
4597a88a ZW |
581 | REG_RANGE((reg), 0xD000, 0xD800) || \ |
582 | REG_RANGE((reg), 0x12000, 0x14000) || \ | |
583 | REG_RANGE((reg), 0x1A000, 0x1EA00) || \ | |
584 | REG_RANGE((reg), 0x30000, 0x40000)) | |
585 | ||
586 | #define FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg) \ | |
587 | REG_RANGE((reg), 0x9400, 0x9800) | |
588 | ||
589 | #define FORCEWAKE_GEN9_BLITTER_RANGE_OFFSET(reg) \ | |
0c8bfe52 | 590 | ((reg) < 0x40000 && \ |
4597a88a ZW |
591 | !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) && \ |
592 | !FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) && \ | |
593 | !FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) && \ | |
594 | !FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) | |
595 | ||
907b28c5 CW |
596 | static void |
597 | ilk_dummy_write(struct drm_i915_private *dev_priv) | |
598 | { | |
599 | /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up | |
600 | * the chip from rc6 before touching it for real. MI_MODE is masked, | |
601 | * hence harmless to write 0 into. */ | |
6af5d92f | 602 | __raw_i915_write32(dev_priv, MI_MODE, 0); |
907b28c5 CW |
603 | } |
604 | ||
605 | static void | |
f0f59a00 | 606 | hsw_unclaimed_reg_debug(struct drm_i915_private *dev_priv, |
4bd0a25d MK |
607 | const i915_reg_t reg, |
608 | const bool read, | |
609 | const bool before) | |
907b28c5 | 610 | { |
4bd0a25d | 611 | if (likely(!i915.mmio_debug)) |
5978118c PZ |
612 | return; |
613 | ||
4bd0a25d MK |
614 | if (WARN(check_for_unclaimed_mmio(dev_priv), |
615 | "Unclaimed register detected %s %s register 0x%x\n", | |
616 | before ? "before" : "after", | |
617 | read ? "reading" : "writing to", | |
618 | i915_mmio_reg_offset(reg))) | |
48572edd | 619 | i915.mmio_debug--; /* Only report the first N failures */ |
907b28c5 CW |
620 | } |
621 | ||
51f67885 | 622 | #define GEN2_READ_HEADER(x) \ |
5d738795 | 623 | u##x val = 0; \ |
da5827c3 | 624 | assert_rpm_wakelock_held(dev_priv); |
5d738795 | 625 | |
51f67885 | 626 | #define GEN2_READ_FOOTER \ |
5d738795 BW |
627 | trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ |
628 | return val | |
629 | ||
51f67885 | 630 | #define __gen2_read(x) \ |
0b274481 | 631 | static u##x \ |
f0f59a00 | 632 | gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ |
51f67885 | 633 | GEN2_READ_HEADER(x); \ |
3967018e | 634 | val = __raw_i915_read##x(dev_priv, reg); \ |
51f67885 | 635 | GEN2_READ_FOOTER; \ |
3967018e BW |
636 | } |
637 | ||
638 | #define __gen5_read(x) \ | |
639 | static u##x \ | |
f0f59a00 | 640 | gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ |
51f67885 | 641 | GEN2_READ_HEADER(x); \ |
3967018e BW |
642 | ilk_dummy_write(dev_priv); \ |
643 | val = __raw_i915_read##x(dev_priv, reg); \ | |
51f67885 | 644 | GEN2_READ_FOOTER; \ |
3967018e BW |
645 | } |
646 | ||
51f67885 CW |
647 | __gen5_read(8) |
648 | __gen5_read(16) | |
649 | __gen5_read(32) | |
650 | __gen5_read(64) | |
651 | __gen2_read(8) | |
652 | __gen2_read(16) | |
653 | __gen2_read(32) | |
654 | __gen2_read(64) | |
655 | ||
656 | #undef __gen5_read | |
657 | #undef __gen2_read | |
658 | ||
659 | #undef GEN2_READ_FOOTER | |
660 | #undef GEN2_READ_HEADER | |
661 | ||
662 | #define GEN6_READ_HEADER(x) \ | |
f0f59a00 | 663 | u32 offset = i915_mmio_reg_offset(reg); \ |
51f67885 CW |
664 | unsigned long irqflags; \ |
665 | u##x val = 0; \ | |
da5827c3 | 666 | assert_rpm_wakelock_held(dev_priv); \ |
51f67885 CW |
667 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags) |
668 | ||
669 | #define GEN6_READ_FOOTER \ | |
670 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ | |
671 | trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ | |
672 | return val | |
673 | ||
b2cff0db | 674 | static inline void __force_wake_get(struct drm_i915_private *dev_priv, |
48c1026a | 675 | enum forcewake_domains fw_domains) |
b2cff0db CW |
676 | { |
677 | struct intel_uncore_forcewake_domain *domain; | |
48c1026a | 678 | enum forcewake_domain_id id; |
b2cff0db CW |
679 | |
680 | if (WARN_ON(!fw_domains)) | |
681 | return; | |
682 | ||
683 | /* Ideally GCC would be constant-fold and eliminate this loop */ | |
05a2fb15 | 684 | for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) { |
b2cff0db | 685 | if (domain->wake_count) { |
05a2fb15 | 686 | fw_domains &= ~(1 << id); |
b2cff0db CW |
687 | continue; |
688 | } | |
689 | ||
690 | domain->wake_count++; | |
05a2fb15 | 691 | fw_domain_arm_timer(domain); |
b2cff0db CW |
692 | } |
693 | ||
694 | if (fw_domains) | |
695 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains); | |
696 | } | |
697 | ||
3967018e BW |
698 | #define __gen6_read(x) \ |
699 | static u##x \ | |
f0f59a00 | 700 | gen6_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ |
51f67885 | 701 | GEN6_READ_HEADER(x); \ |
5978118c | 702 | hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \ |
0670c5a6 | 703 | if (NEEDS_FORCE_WAKE(offset)) \ |
b2cff0db | 704 | __force_wake_get(dev_priv, FORCEWAKE_RENDER); \ |
dc9fb09c | 705 | val = __raw_i915_read##x(dev_priv, reg); \ |
5978118c | 706 | hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \ |
51f67885 | 707 | GEN6_READ_FOOTER; \ |
907b28c5 CW |
708 | } |
709 | ||
940aece4 D |
710 | #define __vlv_read(x) \ |
711 | static u##x \ | |
f0f59a00 | 712 | vlv_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ |
6a42d0f4 | 713 | enum forcewake_domains fw_engine = 0; \ |
51f67885 | 714 | GEN6_READ_HEADER(x); \ |
0670c5a6 | 715 | if (!NEEDS_FORCE_WAKE(offset)) \ |
e97d8fbe | 716 | fw_engine = 0; \ |
0670c5a6 | 717 | else if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(offset)) \ |
6a42d0f4 | 718 | fw_engine = FORCEWAKE_RENDER; \ |
0670c5a6 | 719 | else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(offset)) \ |
6a42d0f4 VS |
720 | fw_engine = FORCEWAKE_MEDIA; \ |
721 | if (fw_engine) \ | |
722 | __force_wake_get(dev_priv, fw_engine); \ | |
6fe72865 | 723 | val = __raw_i915_read##x(dev_priv, reg); \ |
51f67885 | 724 | GEN6_READ_FOOTER; \ |
940aece4 D |
725 | } |
726 | ||
1938e59a D |
727 | #define __chv_read(x) \ |
728 | static u##x \ | |
f0f59a00 | 729 | chv_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ |
6a42d0f4 | 730 | enum forcewake_domains fw_engine = 0; \ |
51f67885 | 731 | GEN6_READ_HEADER(x); \ |
0670c5a6 | 732 | if (!NEEDS_FORCE_WAKE(offset)) \ |
e97d8fbe | 733 | fw_engine = 0; \ |
0670c5a6 | 734 | else if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(offset)) \ |
6a42d0f4 | 735 | fw_engine = FORCEWAKE_RENDER; \ |
0670c5a6 | 736 | else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(offset)) \ |
6a42d0f4 | 737 | fw_engine = FORCEWAKE_MEDIA; \ |
0670c5a6 | 738 | else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(offset)) \ |
6a42d0f4 VS |
739 | fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \ |
740 | if (fw_engine) \ | |
741 | __force_wake_get(dev_priv, fw_engine); \ | |
1938e59a | 742 | val = __raw_i915_read##x(dev_priv, reg); \ |
51f67885 | 743 | GEN6_READ_FOOTER; \ |
1938e59a | 744 | } |
940aece4 | 745 | |
ded17493 | 746 | #define SKL_NEEDS_FORCE_WAKE(reg) \ |
0c8bfe52 | 747 | ((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg)) |
4597a88a ZW |
748 | |
749 | #define __gen9_read(x) \ | |
750 | static u##x \ | |
f0f59a00 | 751 | gen9_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ |
48c1026a | 752 | enum forcewake_domains fw_engine; \ |
51f67885 | 753 | GEN6_READ_HEADER(x); \ |
6c908bf4 | 754 | hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \ |
0670c5a6 | 755 | if (!SKL_NEEDS_FORCE_WAKE(offset)) \ |
b2cff0db | 756 | fw_engine = 0; \ |
0670c5a6 | 757 | else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(offset)) \ |
b2cff0db | 758 | fw_engine = FORCEWAKE_RENDER; \ |
0670c5a6 | 759 | else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(offset)) \ |
b2cff0db | 760 | fw_engine = FORCEWAKE_MEDIA; \ |
0670c5a6 | 761 | else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(offset)) \ |
b2cff0db CW |
762 | fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \ |
763 | else \ | |
764 | fw_engine = FORCEWAKE_BLITTER; \ | |
765 | if (fw_engine) \ | |
766 | __force_wake_get(dev_priv, fw_engine); \ | |
767 | val = __raw_i915_read##x(dev_priv, reg); \ | |
6c908bf4 | 768 | hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \ |
51f67885 | 769 | GEN6_READ_FOOTER; \ |
4597a88a ZW |
770 | } |
771 | ||
772 | __gen9_read(8) | |
773 | __gen9_read(16) | |
774 | __gen9_read(32) | |
775 | __gen9_read(64) | |
1938e59a D |
776 | __chv_read(8) |
777 | __chv_read(16) | |
778 | __chv_read(32) | |
779 | __chv_read(64) | |
940aece4 D |
780 | __vlv_read(8) |
781 | __vlv_read(16) | |
782 | __vlv_read(32) | |
783 | __vlv_read(64) | |
3967018e BW |
784 | __gen6_read(8) |
785 | __gen6_read(16) | |
786 | __gen6_read(32) | |
787 | __gen6_read(64) | |
3967018e | 788 | |
4597a88a | 789 | #undef __gen9_read |
1938e59a | 790 | #undef __chv_read |
940aece4 | 791 | #undef __vlv_read |
3967018e | 792 | #undef __gen6_read |
51f67885 CW |
793 | #undef GEN6_READ_FOOTER |
794 | #undef GEN6_READ_HEADER | |
5d738795 | 795 | |
8a74db7a VS |
796 | #define VGPU_READ_HEADER(x) \ |
797 | unsigned long irqflags; \ | |
798 | u##x val = 0; \ | |
da5827c3 | 799 | assert_rpm_device_not_suspended(dev_priv); \ |
8a74db7a VS |
800 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags) |
801 | ||
802 | #define VGPU_READ_FOOTER \ | |
803 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ | |
804 | trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ | |
805 | return val | |
806 | ||
807 | #define __vgpu_read(x) \ | |
808 | static u##x \ | |
f0f59a00 | 809 | vgpu_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ |
8a74db7a VS |
810 | VGPU_READ_HEADER(x); \ |
811 | val = __raw_i915_read##x(dev_priv, reg); \ | |
812 | VGPU_READ_FOOTER; \ | |
813 | } | |
814 | ||
815 | __vgpu_read(8) | |
816 | __vgpu_read(16) | |
817 | __vgpu_read(32) | |
818 | __vgpu_read(64) | |
819 | ||
820 | #undef __vgpu_read | |
821 | #undef VGPU_READ_FOOTER | |
822 | #undef VGPU_READ_HEADER | |
823 | ||
51f67885 | 824 | #define GEN2_WRITE_HEADER \ |
5d738795 | 825 | trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ |
da5827c3 | 826 | assert_rpm_wakelock_held(dev_priv); \ |
907b28c5 | 827 | |
51f67885 | 828 | #define GEN2_WRITE_FOOTER |
0d965301 | 829 | |
51f67885 | 830 | #define __gen2_write(x) \ |
0b274481 | 831 | static void \ |
f0f59a00 | 832 | gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \ |
51f67885 | 833 | GEN2_WRITE_HEADER; \ |
4032ef43 | 834 | __raw_i915_write##x(dev_priv, reg, val); \ |
51f67885 | 835 | GEN2_WRITE_FOOTER; \ |
4032ef43 BW |
836 | } |
837 | ||
838 | #define __gen5_write(x) \ | |
839 | static void \ | |
f0f59a00 | 840 | gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \ |
51f67885 | 841 | GEN2_WRITE_HEADER; \ |
4032ef43 BW |
842 | ilk_dummy_write(dev_priv); \ |
843 | __raw_i915_write##x(dev_priv, reg, val); \ | |
51f67885 | 844 | GEN2_WRITE_FOOTER; \ |
4032ef43 BW |
845 | } |
846 | ||
51f67885 CW |
847 | __gen5_write(8) |
848 | __gen5_write(16) | |
849 | __gen5_write(32) | |
850 | __gen5_write(64) | |
851 | __gen2_write(8) | |
852 | __gen2_write(16) | |
853 | __gen2_write(32) | |
854 | __gen2_write(64) | |
855 | ||
856 | #undef __gen5_write | |
857 | #undef __gen2_write | |
858 | ||
859 | #undef GEN2_WRITE_FOOTER | |
860 | #undef GEN2_WRITE_HEADER | |
861 | ||
862 | #define GEN6_WRITE_HEADER \ | |
f0f59a00 | 863 | u32 offset = i915_mmio_reg_offset(reg); \ |
51f67885 CW |
864 | unsigned long irqflags; \ |
865 | trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ | |
da5827c3 | 866 | assert_rpm_wakelock_held(dev_priv); \ |
51f67885 CW |
867 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags) |
868 | ||
869 | #define GEN6_WRITE_FOOTER \ | |
870 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags) | |
871 | ||
4032ef43 BW |
872 | #define __gen6_write(x) \ |
873 | static void \ | |
f0f59a00 | 874 | gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \ |
4032ef43 | 875 | u32 __fifo_ret = 0; \ |
51f67885 | 876 | GEN6_WRITE_HEADER; \ |
0670c5a6 | 877 | if (NEEDS_FORCE_WAKE(offset)) { \ |
4032ef43 BW |
878 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ |
879 | } \ | |
880 | __raw_i915_write##x(dev_priv, reg, val); \ | |
881 | if (unlikely(__fifo_ret)) { \ | |
882 | gen6_gt_check_fifodbg(dev_priv); \ | |
883 | } \ | |
51f67885 | 884 | GEN6_WRITE_FOOTER; \ |
4032ef43 BW |
885 | } |
886 | ||
887 | #define __hsw_write(x) \ | |
888 | static void \ | |
f0f59a00 | 889 | hsw_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \ |
907b28c5 | 890 | u32 __fifo_ret = 0; \ |
51f67885 | 891 | GEN6_WRITE_HEADER; \ |
0670c5a6 | 892 | if (NEEDS_FORCE_WAKE(offset)) { \ |
907b28c5 CW |
893 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ |
894 | } \ | |
5978118c | 895 | hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \ |
6af5d92f | 896 | __raw_i915_write##x(dev_priv, reg, val); \ |
907b28c5 CW |
897 | if (unlikely(__fifo_ret)) { \ |
898 | gen6_gt_check_fifodbg(dev_priv); \ | |
899 | } \ | |
5978118c | 900 | hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \ |
51f67885 | 901 | GEN6_WRITE_FOOTER; \ |
907b28c5 | 902 | } |
3967018e | 903 | |
f0f59a00 | 904 | static const i915_reg_t gen8_shadowed_regs[] = { |
ab2aa47e BW |
905 | FORCEWAKE_MT, |
906 | GEN6_RPNSWREQ, | |
907 | GEN6_RC_VIDEO_FREQ, | |
908 | RING_TAIL(RENDER_RING_BASE), | |
909 | RING_TAIL(GEN6_BSD_RING_BASE), | |
910 | RING_TAIL(VEBOX_RING_BASE), | |
911 | RING_TAIL(BLT_RING_BASE), | |
912 | /* TODO: Other registers are not yet used */ | |
913 | }; | |
914 | ||
f0f59a00 VS |
915 | static bool is_gen8_shadowed(struct drm_i915_private *dev_priv, |
916 | i915_reg_t reg) | |
ab2aa47e BW |
917 | { |
918 | int i; | |
919 | for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++) | |
f0f59a00 | 920 | if (i915_mmio_reg_equal(reg, gen8_shadowed_regs[i])) |
ab2aa47e BW |
921 | return true; |
922 | ||
923 | return false; | |
924 | } | |
925 | ||
926 | #define __gen8_write(x) \ | |
927 | static void \ | |
f0f59a00 | 928 | gen8_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \ |
51f67885 | 929 | GEN6_WRITE_HEADER; \ |
66bc2cab | 930 | hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \ |
0670c5a6 | 931 | if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(dev_priv, reg)) \ |
b2cff0db CW |
932 | __force_wake_get(dev_priv, FORCEWAKE_RENDER); \ |
933 | __raw_i915_write##x(dev_priv, reg, val); \ | |
66bc2cab | 934 | hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \ |
51f67885 | 935 | GEN6_WRITE_FOOTER; \ |
ab2aa47e BW |
936 | } |
937 | ||
1938e59a D |
938 | #define __chv_write(x) \ |
939 | static void \ | |
f0f59a00 | 940 | chv_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \ |
6a42d0f4 | 941 | enum forcewake_domains fw_engine = 0; \ |
51f67885 | 942 | GEN6_WRITE_HEADER; \ |
0670c5a6 | 943 | if (!NEEDS_FORCE_WAKE(offset) || \ |
e97d8fbe | 944 | is_gen8_shadowed(dev_priv, reg)) \ |
6a42d0f4 | 945 | fw_engine = 0; \ |
0670c5a6 | 946 | else if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(offset)) \ |
6a42d0f4 | 947 | fw_engine = FORCEWAKE_RENDER; \ |
0670c5a6 | 948 | else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(offset)) \ |
6a42d0f4 | 949 | fw_engine = FORCEWAKE_MEDIA; \ |
0670c5a6 | 950 | else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(offset)) \ |
6a42d0f4 VS |
951 | fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \ |
952 | if (fw_engine) \ | |
953 | __force_wake_get(dev_priv, fw_engine); \ | |
1938e59a | 954 | __raw_i915_write##x(dev_priv, reg, val); \ |
51f67885 | 955 | GEN6_WRITE_FOOTER; \ |
1938e59a D |
956 | } |
957 | ||
f0f59a00 | 958 | static const i915_reg_t gen9_shadowed_regs[] = { |
7c859007 ZW |
959 | RING_TAIL(RENDER_RING_BASE), |
960 | RING_TAIL(GEN6_BSD_RING_BASE), | |
961 | RING_TAIL(VEBOX_RING_BASE), | |
962 | RING_TAIL(BLT_RING_BASE), | |
963 | FORCEWAKE_BLITTER_GEN9, | |
964 | FORCEWAKE_RENDER_GEN9, | |
965 | FORCEWAKE_MEDIA_GEN9, | |
966 | GEN6_RPNSWREQ, | |
967 | GEN6_RC_VIDEO_FREQ, | |
968 | /* TODO: Other registers are not yet used */ | |
969 | }; | |
970 | ||
f0f59a00 VS |
971 | static bool is_gen9_shadowed(struct drm_i915_private *dev_priv, |
972 | i915_reg_t reg) | |
7c859007 ZW |
973 | { |
974 | int i; | |
975 | for (i = 0; i < ARRAY_SIZE(gen9_shadowed_regs); i++) | |
f0f59a00 | 976 | if (i915_mmio_reg_equal(reg, gen9_shadowed_regs[i])) |
7c859007 ZW |
977 | return true; |
978 | ||
979 | return false; | |
980 | } | |
981 | ||
4597a88a ZW |
982 | #define __gen9_write(x) \ |
983 | static void \ | |
f0f59a00 | 984 | gen9_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, \ |
4597a88a | 985 | bool trace) { \ |
48c1026a | 986 | enum forcewake_domains fw_engine; \ |
51f67885 | 987 | GEN6_WRITE_HEADER; \ |
6c908bf4 | 988 | hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \ |
0670c5a6 | 989 | if (!SKL_NEEDS_FORCE_WAKE(offset) || \ |
b2cff0db CW |
990 | is_gen9_shadowed(dev_priv, reg)) \ |
991 | fw_engine = 0; \ | |
0670c5a6 | 992 | else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(offset)) \ |
b2cff0db | 993 | fw_engine = FORCEWAKE_RENDER; \ |
0670c5a6 | 994 | else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(offset)) \ |
b2cff0db | 995 | fw_engine = FORCEWAKE_MEDIA; \ |
0670c5a6 | 996 | else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(offset)) \ |
b2cff0db CW |
997 | fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \ |
998 | else \ | |
999 | fw_engine = FORCEWAKE_BLITTER; \ | |
1000 | if (fw_engine) \ | |
1001 | __force_wake_get(dev_priv, fw_engine); \ | |
1002 | __raw_i915_write##x(dev_priv, reg, val); \ | |
6c908bf4 | 1003 | hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \ |
51f67885 | 1004 | GEN6_WRITE_FOOTER; \ |
4597a88a ZW |
1005 | } |
1006 | ||
1007 | __gen9_write(8) | |
1008 | __gen9_write(16) | |
1009 | __gen9_write(32) | |
1010 | __gen9_write(64) | |
1938e59a D |
1011 | __chv_write(8) |
1012 | __chv_write(16) | |
1013 | __chv_write(32) | |
1014 | __chv_write(64) | |
ab2aa47e BW |
1015 | __gen8_write(8) |
1016 | __gen8_write(16) | |
1017 | __gen8_write(32) | |
1018 | __gen8_write(64) | |
4032ef43 BW |
1019 | __hsw_write(8) |
1020 | __hsw_write(16) | |
1021 | __hsw_write(32) | |
1022 | __hsw_write(64) | |
1023 | __gen6_write(8) | |
1024 | __gen6_write(16) | |
1025 | __gen6_write(32) | |
1026 | __gen6_write(64) | |
4032ef43 | 1027 | |
4597a88a | 1028 | #undef __gen9_write |
1938e59a | 1029 | #undef __chv_write |
ab2aa47e | 1030 | #undef __gen8_write |
4032ef43 BW |
1031 | #undef __hsw_write |
1032 | #undef __gen6_write | |
51f67885 CW |
1033 | #undef GEN6_WRITE_FOOTER |
1034 | #undef GEN6_WRITE_HEADER | |
907b28c5 | 1035 | |
8a74db7a VS |
1036 | #define VGPU_WRITE_HEADER \ |
1037 | unsigned long irqflags; \ | |
1038 | trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ | |
da5827c3 | 1039 | assert_rpm_device_not_suspended(dev_priv); \ |
8a74db7a VS |
1040 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags) |
1041 | ||
1042 | #define VGPU_WRITE_FOOTER \ | |
1043 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags) | |
1044 | ||
1045 | #define __vgpu_write(x) \ | |
1046 | static void vgpu_write##x(struct drm_i915_private *dev_priv, \ | |
f0f59a00 | 1047 | i915_reg_t reg, u##x val, bool trace) { \ |
8a74db7a VS |
1048 | VGPU_WRITE_HEADER; \ |
1049 | __raw_i915_write##x(dev_priv, reg, val); \ | |
1050 | VGPU_WRITE_FOOTER; \ | |
1051 | } | |
1052 | ||
1053 | __vgpu_write(8) | |
1054 | __vgpu_write(16) | |
1055 | __vgpu_write(32) | |
1056 | __vgpu_write(64) | |
1057 | ||
1058 | #undef __vgpu_write | |
1059 | #undef VGPU_WRITE_FOOTER | |
1060 | #undef VGPU_WRITE_HEADER | |
1061 | ||
43d942a7 YZ |
1062 | #define ASSIGN_WRITE_MMIO_VFUNCS(x) \ |
1063 | do { \ | |
1064 | dev_priv->uncore.funcs.mmio_writeb = x##_write8; \ | |
1065 | dev_priv->uncore.funcs.mmio_writew = x##_write16; \ | |
1066 | dev_priv->uncore.funcs.mmio_writel = x##_write32; \ | |
1067 | dev_priv->uncore.funcs.mmio_writeq = x##_write64; \ | |
1068 | } while (0) | |
1069 | ||
1070 | #define ASSIGN_READ_MMIO_VFUNCS(x) \ | |
1071 | do { \ | |
1072 | dev_priv->uncore.funcs.mmio_readb = x##_read8; \ | |
1073 | dev_priv->uncore.funcs.mmio_readw = x##_read16; \ | |
1074 | dev_priv->uncore.funcs.mmio_readl = x##_read32; \ | |
1075 | dev_priv->uncore.funcs.mmio_readq = x##_read64; \ | |
1076 | } while (0) | |
1077 | ||
05a2fb15 MK |
1078 | |
1079 | static void fw_domain_init(struct drm_i915_private *dev_priv, | |
48c1026a | 1080 | enum forcewake_domain_id domain_id, |
f0f59a00 VS |
1081 | i915_reg_t reg_set, |
1082 | i915_reg_t reg_ack) | |
05a2fb15 MK |
1083 | { |
1084 | struct intel_uncore_forcewake_domain *d; | |
1085 | ||
1086 | if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT)) | |
1087 | return; | |
1088 | ||
1089 | d = &dev_priv->uncore.fw_domain[domain_id]; | |
1090 | ||
1091 | WARN_ON(d->wake_count); | |
1092 | ||
1093 | d->wake_count = 0; | |
1094 | d->reg_set = reg_set; | |
1095 | d->reg_ack = reg_ack; | |
1096 | ||
1097 | if (IS_GEN6(dev_priv)) { | |
1098 | d->val_reset = 0; | |
1099 | d->val_set = FORCEWAKE_KERNEL; | |
1100 | d->val_clear = 0; | |
1101 | } else { | |
8543747c | 1102 | /* WaRsClearFWBitsAtReset:bdw,skl */ |
05a2fb15 MK |
1103 | d->val_reset = _MASKED_BIT_DISABLE(0xffff); |
1104 | d->val_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL); | |
1105 | d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL); | |
1106 | } | |
1107 | ||
666a4537 | 1108 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
05a2fb15 MK |
1109 | d->reg_post = FORCEWAKE_ACK_VLV; |
1110 | else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) | |
1111 | d->reg_post = ECOBUS; | |
05a2fb15 MK |
1112 | |
1113 | d->i915 = dev_priv; | |
1114 | d->id = domain_id; | |
1115 | ||
59bad947 | 1116 | setup_timer(&d->timer, intel_uncore_fw_release_timer, (unsigned long)d); |
05a2fb15 MK |
1117 | |
1118 | dev_priv->uncore.fw_domains |= (1 << domain_id); | |
f9b3927a MK |
1119 | |
1120 | fw_domain_reset(d); | |
05a2fb15 MK |
1121 | } |
1122 | ||
f9b3927a | 1123 | static void intel_uncore_fw_domains_init(struct drm_device *dev) |
0b274481 BW |
1124 | { |
1125 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0b274481 | 1126 | |
3225b2f9 MK |
1127 | if (INTEL_INFO(dev_priv->dev)->gen <= 5) |
1128 | return; | |
1129 | ||
38cff0b1 | 1130 | if (IS_GEN9(dev)) { |
05a2fb15 MK |
1131 | dev_priv->uncore.funcs.force_wake_get = fw_domains_get; |
1132 | dev_priv->uncore.funcs.force_wake_put = fw_domains_put; | |
1133 | fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, | |
1134 | FORCEWAKE_RENDER_GEN9, | |
1135 | FORCEWAKE_ACK_RENDER_GEN9); | |
1136 | fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER, | |
1137 | FORCEWAKE_BLITTER_GEN9, | |
1138 | FORCEWAKE_ACK_BLITTER_GEN9); | |
1139 | fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA, | |
1140 | FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9); | |
666a4537 | 1141 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
05a2fb15 | 1142 | dev_priv->uncore.funcs.force_wake_get = fw_domains_get; |
756c349d MK |
1143 | if (!IS_CHERRYVIEW(dev)) |
1144 | dev_priv->uncore.funcs.force_wake_put = | |
1145 | fw_domains_put_with_fifo; | |
1146 | else | |
1147 | dev_priv->uncore.funcs.force_wake_put = fw_domains_put; | |
05a2fb15 MK |
1148 | fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, |
1149 | FORCEWAKE_VLV, FORCEWAKE_ACK_VLV); | |
1150 | fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA, | |
1151 | FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV); | |
f98cd096 | 1152 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
05a2fb15 MK |
1153 | dev_priv->uncore.funcs.force_wake_get = |
1154 | fw_domains_get_with_thread_status; | |
1155 | dev_priv->uncore.funcs.force_wake_put = fw_domains_put; | |
1156 | fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, | |
1157 | FORCEWAKE_MT, FORCEWAKE_ACK_HSW); | |
0b274481 BW |
1158 | } else if (IS_IVYBRIDGE(dev)) { |
1159 | u32 ecobus; | |
1160 | ||
1161 | /* IVB configs may use multi-threaded forcewake */ | |
1162 | ||
1163 | /* A small trick here - if the bios hasn't configured | |
1164 | * MT forcewake, and if the device is in RC6, then | |
1165 | * force_wake_mt_get will not wake the device and the | |
1166 | * ECOBUS read will return zero. Which will be | |
1167 | * (correctly) interpreted by the test below as MT | |
1168 | * forcewake being disabled. | |
1169 | */ | |
05a2fb15 MK |
1170 | dev_priv->uncore.funcs.force_wake_get = |
1171 | fw_domains_get_with_thread_status; | |
1172 | dev_priv->uncore.funcs.force_wake_put = | |
1173 | fw_domains_put_with_fifo; | |
1174 | ||
f9b3927a MK |
1175 | /* We need to init first for ECOBUS access and then |
1176 | * determine later if we want to reinit, in case of MT access is | |
6ea2556f MK |
1177 | * not working. In this stage we don't know which flavour this |
1178 | * ivb is, so it is better to reset also the gen6 fw registers | |
1179 | * before the ecobus check. | |
f9b3927a | 1180 | */ |
6ea2556f MK |
1181 | |
1182 | __raw_i915_write32(dev_priv, FORCEWAKE, 0); | |
1183 | __raw_posting_read(dev_priv, ECOBUS); | |
1184 | ||
05a2fb15 MK |
1185 | fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, |
1186 | FORCEWAKE_MT, FORCEWAKE_MT_ACK); | |
f9b3927a | 1187 | |
0b274481 | 1188 | mutex_lock(&dev->struct_mutex); |
05a2fb15 | 1189 | fw_domains_get_with_thread_status(dev_priv, FORCEWAKE_ALL); |
0b274481 | 1190 | ecobus = __raw_i915_read32(dev_priv, ECOBUS); |
05a2fb15 | 1191 | fw_domains_put_with_fifo(dev_priv, FORCEWAKE_ALL); |
0b274481 BW |
1192 | mutex_unlock(&dev->struct_mutex); |
1193 | ||
05a2fb15 | 1194 | if (!(ecobus & FORCEWAKE_MT_ENABLE)) { |
0b274481 BW |
1195 | DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n"); |
1196 | DRM_INFO("when using vblank-synced partial screen updates.\n"); | |
05a2fb15 MK |
1197 | fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, |
1198 | FORCEWAKE, FORCEWAKE_ACK); | |
0b274481 BW |
1199 | } |
1200 | } else if (IS_GEN6(dev)) { | |
1201 | dev_priv->uncore.funcs.force_wake_get = | |
05a2fb15 | 1202 | fw_domains_get_with_thread_status; |
0b274481 | 1203 | dev_priv->uncore.funcs.force_wake_put = |
05a2fb15 MK |
1204 | fw_domains_put_with_fifo; |
1205 | fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, | |
1206 | FORCEWAKE, FORCEWAKE_ACK); | |
0b274481 | 1207 | } |
3225b2f9 MK |
1208 | |
1209 | /* All future platforms are expected to require complex power gating */ | |
1210 | WARN_ON(dev_priv->uncore.fw_domains == 0); | |
f9b3927a MK |
1211 | } |
1212 | ||
1213 | void intel_uncore_init(struct drm_device *dev) | |
1214 | { | |
1215 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1216 | ||
cf9d2890 YZ |
1217 | i915_check_vgpu(dev); |
1218 | ||
f9b3927a MK |
1219 | intel_uncore_ellc_detect(dev); |
1220 | intel_uncore_fw_domains_init(dev); | |
1221 | __intel_uncore_early_sanitize(dev, false); | |
0b274481 | 1222 | |
75714940 MK |
1223 | dev_priv->uncore.unclaimed_mmio_check = 1; |
1224 | ||
3967018e | 1225 | switch (INTEL_INFO(dev)->gen) { |
ab2aa47e | 1226 | default: |
4597a88a ZW |
1227 | case 9: |
1228 | ASSIGN_WRITE_MMIO_VFUNCS(gen9); | |
1229 | ASSIGN_READ_MMIO_VFUNCS(gen9); | |
1230 | break; | |
1231 | case 8: | |
1938e59a | 1232 | if (IS_CHERRYVIEW(dev)) { |
43d942a7 YZ |
1233 | ASSIGN_WRITE_MMIO_VFUNCS(chv); |
1234 | ASSIGN_READ_MMIO_VFUNCS(chv); | |
1938e59a D |
1235 | |
1236 | } else { | |
43d942a7 YZ |
1237 | ASSIGN_WRITE_MMIO_VFUNCS(gen8); |
1238 | ASSIGN_READ_MMIO_VFUNCS(gen6); | |
1938e59a | 1239 | } |
ab2aa47e | 1240 | break; |
3967018e BW |
1241 | case 7: |
1242 | case 6: | |
4032ef43 | 1243 | if (IS_HASWELL(dev)) { |
43d942a7 | 1244 | ASSIGN_WRITE_MMIO_VFUNCS(hsw); |
4032ef43 | 1245 | } else { |
43d942a7 | 1246 | ASSIGN_WRITE_MMIO_VFUNCS(gen6); |
4032ef43 | 1247 | } |
940aece4 D |
1248 | |
1249 | if (IS_VALLEYVIEW(dev)) { | |
43d942a7 | 1250 | ASSIGN_READ_MMIO_VFUNCS(vlv); |
940aece4 | 1251 | } else { |
43d942a7 | 1252 | ASSIGN_READ_MMIO_VFUNCS(gen6); |
940aece4 | 1253 | } |
3967018e BW |
1254 | break; |
1255 | case 5: | |
43d942a7 YZ |
1256 | ASSIGN_WRITE_MMIO_VFUNCS(gen5); |
1257 | ASSIGN_READ_MMIO_VFUNCS(gen5); | |
3967018e BW |
1258 | break; |
1259 | case 4: | |
1260 | case 3: | |
1261 | case 2: | |
51f67885 CW |
1262 | ASSIGN_WRITE_MMIO_VFUNCS(gen2); |
1263 | ASSIGN_READ_MMIO_VFUNCS(gen2); | |
3967018e BW |
1264 | break; |
1265 | } | |
ed493883 | 1266 | |
3be0bf5a YZ |
1267 | if (intel_vgpu_active(dev)) { |
1268 | ASSIGN_WRITE_MMIO_VFUNCS(vgpu); | |
1269 | ASSIGN_READ_MMIO_VFUNCS(vgpu); | |
1270 | } | |
1271 | ||
ed493883 | 1272 | i915_check_and_clear_faults(dev); |
0b274481 | 1273 | } |
43d942a7 YZ |
1274 | #undef ASSIGN_WRITE_MMIO_VFUNCS |
1275 | #undef ASSIGN_READ_MMIO_VFUNCS | |
0b274481 BW |
1276 | |
1277 | void intel_uncore_fini(struct drm_device *dev) | |
1278 | { | |
0b274481 BW |
1279 | /* Paranoia: make sure we have disabled everything before we exit. */ |
1280 | intel_uncore_sanitize(dev); | |
0294ae7b | 1281 | intel_uncore_forcewake_reset(dev, false); |
0b274481 BW |
1282 | } |
1283 | ||
af76ae44 DL |
1284 | #define GEN_RANGE(l, h) GENMASK(h, l) |
1285 | ||
907b28c5 | 1286 | static const struct register_whitelist { |
f0f59a00 | 1287 | i915_reg_t offset_ldw, offset_udw; |
907b28c5 | 1288 | uint32_t size; |
af76ae44 DL |
1289 | /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */ |
1290 | uint32_t gen_bitmask; | |
907b28c5 | 1291 | } whitelist[] = { |
8697600b VS |
1292 | { .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE), |
1293 | .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE), | |
1294 | .size = 8, .gen_bitmask = GEN_RANGE(4, 9) }, | |
907b28c5 CW |
1295 | }; |
1296 | ||
1297 | int i915_reg_read_ioctl(struct drm_device *dev, | |
1298 | void *data, struct drm_file *file) | |
1299 | { | |
1300 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1301 | struct drm_i915_reg_read *reg = data; | |
1302 | struct register_whitelist const *entry = whitelist; | |
648a9bc5 | 1303 | unsigned size; |
f0f59a00 | 1304 | i915_reg_t offset_ldw, offset_udw; |
cf67c70f | 1305 | int i, ret = 0; |
907b28c5 CW |
1306 | |
1307 | for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) { | |
f0f59a00 | 1308 | if (i915_mmio_reg_offset(entry->offset_ldw) == (reg->offset & -entry->size) && |
907b28c5 CW |
1309 | (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask)) |
1310 | break; | |
1311 | } | |
1312 | ||
1313 | if (i == ARRAY_SIZE(whitelist)) | |
1314 | return -EINVAL; | |
1315 | ||
648a9bc5 CW |
1316 | /* We use the low bits to encode extra flags as the register should |
1317 | * be naturally aligned (and those that are not so aligned merely | |
1318 | * limit the available flags for that register). | |
1319 | */ | |
8697600b VS |
1320 | offset_ldw = entry->offset_ldw; |
1321 | offset_udw = entry->offset_udw; | |
648a9bc5 | 1322 | size = entry->size; |
f0f59a00 | 1323 | size |= reg->offset ^ i915_mmio_reg_offset(offset_ldw); |
648a9bc5 | 1324 | |
cf67c70f PZ |
1325 | intel_runtime_pm_get(dev_priv); |
1326 | ||
648a9bc5 CW |
1327 | switch (size) { |
1328 | case 8 | 1: | |
8697600b | 1329 | reg->val = I915_READ64_2x32(offset_ldw, offset_udw); |
648a9bc5 | 1330 | break; |
907b28c5 | 1331 | case 8: |
8697600b | 1332 | reg->val = I915_READ64(offset_ldw); |
907b28c5 CW |
1333 | break; |
1334 | case 4: | |
8697600b | 1335 | reg->val = I915_READ(offset_ldw); |
907b28c5 CW |
1336 | break; |
1337 | case 2: | |
8697600b | 1338 | reg->val = I915_READ16(offset_ldw); |
907b28c5 CW |
1339 | break; |
1340 | case 1: | |
8697600b | 1341 | reg->val = I915_READ8(offset_ldw); |
907b28c5 CW |
1342 | break; |
1343 | default: | |
cf67c70f PZ |
1344 | ret = -EINVAL; |
1345 | goto out; | |
907b28c5 CW |
1346 | } |
1347 | ||
cf67c70f PZ |
1348 | out: |
1349 | intel_runtime_pm_put(dev_priv); | |
1350 | return ret; | |
907b28c5 CW |
1351 | } |
1352 | ||
b6359918 MK |
1353 | int i915_get_reset_stats_ioctl(struct drm_device *dev, |
1354 | void *data, struct drm_file *file) | |
1355 | { | |
1356 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1357 | struct drm_i915_reset_stats *args = data; | |
1358 | struct i915_ctx_hang_stats *hs; | |
273497e5 | 1359 | struct intel_context *ctx; |
b6359918 MK |
1360 | int ret; |
1361 | ||
661df041 MK |
1362 | if (args->flags || args->pad) |
1363 | return -EINVAL; | |
1364 | ||
821d66dd | 1365 | if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN)) |
b6359918 MK |
1366 | return -EPERM; |
1367 | ||
1368 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1369 | if (ret) | |
1370 | return ret; | |
1371 | ||
41bde553 BW |
1372 | ctx = i915_gem_context_get(file->driver_priv, args->ctx_id); |
1373 | if (IS_ERR(ctx)) { | |
b6359918 | 1374 | mutex_unlock(&dev->struct_mutex); |
41bde553 | 1375 | return PTR_ERR(ctx); |
b6359918 | 1376 | } |
41bde553 | 1377 | hs = &ctx->hang_stats; |
b6359918 MK |
1378 | |
1379 | if (capable(CAP_SYS_ADMIN)) | |
1380 | args->reset_count = i915_reset_count(&dev_priv->gpu_error); | |
1381 | else | |
1382 | args->reset_count = 0; | |
1383 | ||
1384 | args->batch_active = hs->batch_active; | |
1385 | args->batch_pending = hs->batch_pending; | |
1386 | ||
1387 | mutex_unlock(&dev->struct_mutex); | |
1388 | ||
1389 | return 0; | |
1390 | } | |
1391 | ||
59ea9054 | 1392 | static int i915_reset_complete(struct drm_device *dev) |
907b28c5 CW |
1393 | { |
1394 | u8 gdrst; | |
59ea9054 | 1395 | pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst); |
73bbf6bd | 1396 | return (gdrst & GRDOM_RESET_STATUS) == 0; |
907b28c5 CW |
1397 | } |
1398 | ||
59ea9054 | 1399 | static int i915_do_reset(struct drm_device *dev) |
907b28c5 | 1400 | { |
73bbf6bd | 1401 | /* assert reset for at least 20 usec */ |
59ea9054 | 1402 | pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE); |
73bbf6bd | 1403 | udelay(20); |
59ea9054 | 1404 | pci_write_config_byte(dev->pdev, I915_GDRST, 0); |
907b28c5 | 1405 | |
59ea9054 | 1406 | return wait_for(i915_reset_complete(dev), 500); |
73bbf6bd VS |
1407 | } |
1408 | ||
1409 | static int g4x_reset_complete(struct drm_device *dev) | |
1410 | { | |
1411 | u8 gdrst; | |
59ea9054 | 1412 | pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst); |
73bbf6bd | 1413 | return (gdrst & GRDOM_RESET_ENABLE) == 0; |
907b28c5 CW |
1414 | } |
1415 | ||
408d4b9e VS |
1416 | static int g33_do_reset(struct drm_device *dev) |
1417 | { | |
408d4b9e VS |
1418 | pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE); |
1419 | return wait_for(g4x_reset_complete(dev), 500); | |
1420 | } | |
1421 | ||
fa4f53c4 VS |
1422 | static int g4x_do_reset(struct drm_device *dev) |
1423 | { | |
1424 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1425 | int ret; | |
1426 | ||
59ea9054 | 1427 | pci_write_config_byte(dev->pdev, I915_GDRST, |
fa4f53c4 | 1428 | GRDOM_RENDER | GRDOM_RESET_ENABLE); |
73bbf6bd | 1429 | ret = wait_for(g4x_reset_complete(dev), 500); |
fa4f53c4 VS |
1430 | if (ret) |
1431 | return ret; | |
1432 | ||
1433 | /* WaVcpClkGateDisableForMediaReset:ctg,elk */ | |
1434 | I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE); | |
1435 | POSTING_READ(VDECCLK_GATE_D); | |
1436 | ||
59ea9054 | 1437 | pci_write_config_byte(dev->pdev, I915_GDRST, |
fa4f53c4 | 1438 | GRDOM_MEDIA | GRDOM_RESET_ENABLE); |
73bbf6bd | 1439 | ret = wait_for(g4x_reset_complete(dev), 500); |
fa4f53c4 VS |
1440 | if (ret) |
1441 | return ret; | |
1442 | ||
1443 | /* WaVcpClkGateDisableForMediaReset:ctg,elk */ | |
1444 | I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE); | |
1445 | POSTING_READ(VDECCLK_GATE_D); | |
1446 | ||
59ea9054 | 1447 | pci_write_config_byte(dev->pdev, I915_GDRST, 0); |
fa4f53c4 VS |
1448 | |
1449 | return 0; | |
1450 | } | |
1451 | ||
907b28c5 CW |
1452 | static int ironlake_do_reset(struct drm_device *dev) |
1453 | { | |
1454 | struct drm_i915_private *dev_priv = dev->dev_private; | |
907b28c5 CW |
1455 | int ret; |
1456 | ||
c039b7f2 | 1457 | I915_WRITE(ILK_GDSR, |
0f08ffd6 | 1458 | ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE); |
c039b7f2 | 1459 | ret = wait_for((I915_READ(ILK_GDSR) & |
b3a3f03d | 1460 | ILK_GRDOM_RESET_ENABLE) == 0, 500); |
907b28c5 CW |
1461 | if (ret) |
1462 | return ret; | |
1463 | ||
c039b7f2 | 1464 | I915_WRITE(ILK_GDSR, |
0f08ffd6 | 1465 | ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE); |
c039b7f2 | 1466 | ret = wait_for((I915_READ(ILK_GDSR) & |
9aa7250f VS |
1467 | ILK_GRDOM_RESET_ENABLE) == 0, 500); |
1468 | if (ret) | |
1469 | return ret; | |
1470 | ||
c039b7f2 | 1471 | I915_WRITE(ILK_GDSR, 0); |
9aa7250f VS |
1472 | |
1473 | return 0; | |
907b28c5 CW |
1474 | } |
1475 | ||
1476 | static int gen6_do_reset(struct drm_device *dev) | |
1477 | { | |
1478 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1479 | int ret; | |
907b28c5 CW |
1480 | |
1481 | /* Reset the chip */ | |
1482 | ||
1483 | /* GEN6_GDRST is not in the gt power well, no need to check | |
1484 | * for fifo space for the write or forcewake the chip for | |
1485 | * the read | |
1486 | */ | |
6af5d92f | 1487 | __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL); |
907b28c5 CW |
1488 | |
1489 | /* Spin waiting for the device to ack the reset request */ | |
6af5d92f | 1490 | ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500); |
907b28c5 | 1491 | |
0294ae7b | 1492 | intel_uncore_forcewake_reset(dev, true); |
5babf0fc | 1493 | |
907b28c5 CW |
1494 | return ret; |
1495 | } | |
1496 | ||
7fd2d269 | 1497 | static int wait_for_register(struct drm_i915_private *dev_priv, |
f0f59a00 | 1498 | i915_reg_t reg, |
7fd2d269 MK |
1499 | const u32 mask, |
1500 | const u32 value, | |
1501 | const unsigned long timeout_ms) | |
1502 | { | |
1503 | return wait_for((I915_READ(reg) & mask) == value, timeout_ms); | |
1504 | } | |
1505 | ||
1506 | static int gen8_do_reset(struct drm_device *dev) | |
1507 | { | |
1508 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1509 | struct intel_engine_cs *engine; | |
1510 | int i; | |
1511 | ||
1512 | for_each_ring(engine, dev_priv, i) { | |
1513 | I915_WRITE(RING_RESET_CTL(engine->mmio_base), | |
1514 | _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET)); | |
1515 | ||
1516 | if (wait_for_register(dev_priv, | |
1517 | RING_RESET_CTL(engine->mmio_base), | |
1518 | RESET_CTL_READY_TO_RESET, | |
1519 | RESET_CTL_READY_TO_RESET, | |
1520 | 700)) { | |
1521 | DRM_ERROR("%s: reset request timeout\n", engine->name); | |
1522 | goto not_ready; | |
1523 | } | |
1524 | } | |
1525 | ||
1526 | return gen6_do_reset(dev); | |
1527 | ||
1528 | not_ready: | |
1529 | for_each_ring(engine, dev_priv, i) | |
1530 | I915_WRITE(RING_RESET_CTL(engine->mmio_base), | |
1531 | _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET)); | |
1532 | ||
1533 | return -EIO; | |
1534 | } | |
1535 | ||
49e4d842 | 1536 | static int (*intel_get_gpu_reset(struct drm_device *dev))(struct drm_device *) |
907b28c5 | 1537 | { |
b1330fbb CW |
1538 | if (!i915.reset) |
1539 | return NULL; | |
1540 | ||
7fd2d269 MK |
1541 | if (INTEL_INFO(dev)->gen >= 8) |
1542 | return gen8_do_reset; | |
1543 | else if (INTEL_INFO(dev)->gen >= 6) | |
49e4d842 | 1544 | return gen6_do_reset; |
542c184f | 1545 | else if (IS_GEN5(dev)) |
49e4d842 | 1546 | return ironlake_do_reset; |
542c184f | 1547 | else if (IS_G4X(dev)) |
49e4d842 | 1548 | return g4x_do_reset; |
408d4b9e | 1549 | else if (IS_G33(dev)) |
49e4d842 | 1550 | return g33_do_reset; |
408d4b9e | 1551 | else if (INTEL_INFO(dev)->gen >= 3) |
49e4d842 | 1552 | return i915_do_reset; |
542c184f | 1553 | else |
49e4d842 CW |
1554 | return NULL; |
1555 | } | |
1556 | ||
1557 | int intel_gpu_reset(struct drm_device *dev) | |
1558 | { | |
99106bc1 | 1559 | struct drm_i915_private *dev_priv = to_i915(dev); |
49e4d842 | 1560 | int (*reset)(struct drm_device *); |
99106bc1 | 1561 | int ret; |
49e4d842 CW |
1562 | |
1563 | reset = intel_get_gpu_reset(dev); | |
1564 | if (reset == NULL) | |
542c184f | 1565 | return -ENODEV; |
49e4d842 | 1566 | |
99106bc1 MK |
1567 | /* If the power well sleeps during the reset, the reset |
1568 | * request may be dropped and never completes (causing -EIO). | |
1569 | */ | |
1570 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
1571 | ret = reset(dev); | |
1572 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
1573 | ||
1574 | return ret; | |
49e4d842 CW |
1575 | } |
1576 | ||
1577 | bool intel_has_gpu_reset(struct drm_device *dev) | |
1578 | { | |
1579 | return intel_get_gpu_reset(dev) != NULL; | |
907b28c5 CW |
1580 | } |
1581 | ||
fc97618b | 1582 | bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv) |
907b28c5 | 1583 | { |
fc97618b | 1584 | return check_for_unclaimed_mmio(dev_priv); |
907b28c5 | 1585 | } |
75714940 MK |
1586 | |
1587 | void | |
1588 | intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv) | |
1589 | { | |
1590 | if (unlikely(i915.mmio_debug || | |
1591 | dev_priv->uncore.unclaimed_mmio_check <= 0)) | |
1592 | return; | |
1593 | ||
1594 | if (unlikely(intel_uncore_unclaimed_mmio(dev_priv))) { | |
1595 | DRM_DEBUG("Unclaimed register detected, " | |
1596 | "enabling oneshot unclaimed register reporting. " | |
1597 | "Please use i915.mmio_debug=N for more information.\n"); | |
1598 | i915.mmio_debug++; | |
1599 | dev_priv->uncore.unclaimed_mmio_check--; | |
1600 | } | |
1601 | } |