Commit | Line | Data |
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907b28c5 CW |
1 | /* |
2 | * Copyright © 2013 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | */ | |
23 | ||
24 | #include "i915_drv.h" | |
25 | #include "intel_drv.h" | |
cf9d2890 | 26 | #include "i915_vgpu.h" |
907b28c5 | 27 | |
6daccb0b CW |
28 | #include <linux/pm_runtime.h> |
29 | ||
83e33372 | 30 | #define FORCEWAKE_ACK_TIMEOUT_MS 50 |
907b28c5 | 31 | |
75aa3f63 | 32 | #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32((dev_priv__), (reg__)) |
6af5d92f | 33 | |
05a2fb15 MK |
34 | static const char * const forcewake_domain_names[] = { |
35 | "render", | |
36 | "blitter", | |
37 | "media", | |
38 | }; | |
39 | ||
40 | const char * | |
48c1026a | 41 | intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id) |
05a2fb15 | 42 | { |
53abb679 | 43 | BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT); |
05a2fb15 MK |
44 | |
45 | if (id >= 0 && id < FW_DOMAIN_ID_COUNT) | |
46 | return forcewake_domain_names[id]; | |
47 | ||
48 | WARN_ON(id); | |
49 | ||
50 | return "unknown"; | |
51 | } | |
52 | ||
05a2fb15 MK |
53 | static inline void |
54 | fw_domain_reset(const struct intel_uncore_forcewake_domain *d) | |
907b28c5 | 55 | { |
f0f59a00 | 56 | WARN_ON(!i915_mmio_reg_valid(d->reg_set)); |
05a2fb15 | 57 | __raw_i915_write32(d->i915, d->reg_set, d->val_reset); |
907b28c5 CW |
58 | } |
59 | ||
05a2fb15 MK |
60 | static inline void |
61 | fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d) | |
907b28c5 | 62 | { |
a57a4a67 TU |
63 | d->wake_count++; |
64 | hrtimer_start_range_ns(&d->timer, | |
8b0e1953 | 65 | NSEC_PER_MSEC, |
a57a4a67 TU |
66 | NSEC_PER_MSEC, |
67 | HRTIMER_MODE_REL); | |
907b28c5 CW |
68 | } |
69 | ||
05a2fb15 MK |
70 | static inline void |
71 | fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d) | |
907b28c5 | 72 | { |
05a2fb15 MK |
73 | if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) & |
74 | FORCEWAKE_KERNEL) == 0, | |
907b28c5 | 75 | FORCEWAKE_ACK_TIMEOUT_MS)) |
05a2fb15 MK |
76 | DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n", |
77 | intel_uncore_forcewake_domain_to_str(d->id)); | |
78 | } | |
907b28c5 | 79 | |
05a2fb15 MK |
80 | static inline void |
81 | fw_domain_get(const struct intel_uncore_forcewake_domain *d) | |
82 | { | |
83 | __raw_i915_write32(d->i915, d->reg_set, d->val_set); | |
84 | } | |
907b28c5 | 85 | |
05a2fb15 MK |
86 | static inline void |
87 | fw_domain_wait_ack(const struct intel_uncore_forcewake_domain *d) | |
88 | { | |
89 | if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) & | |
90 | FORCEWAKE_KERNEL), | |
907b28c5 | 91 | FORCEWAKE_ACK_TIMEOUT_MS)) |
05a2fb15 MK |
92 | DRM_ERROR("%s: timed out waiting for forcewake ack request.\n", |
93 | intel_uncore_forcewake_domain_to_str(d->id)); | |
94 | } | |
907b28c5 | 95 | |
05a2fb15 MK |
96 | static inline void |
97 | fw_domain_put(const struct intel_uncore_forcewake_domain *d) | |
98 | { | |
99 | __raw_i915_write32(d->i915, d->reg_set, d->val_clear); | |
907b28c5 CW |
100 | } |
101 | ||
05a2fb15 MK |
102 | static inline void |
103 | fw_domain_posting_read(const struct intel_uncore_forcewake_domain *d) | |
907b28c5 | 104 | { |
05a2fb15 | 105 | /* something from same cacheline, but not from the set register */ |
f0f59a00 | 106 | if (i915_mmio_reg_valid(d->reg_post)) |
05a2fb15 | 107 | __raw_posting_read(d->i915, d->reg_post); |
907b28c5 CW |
108 | } |
109 | ||
05a2fb15 | 110 | static void |
48c1026a | 111 | fw_domains_get(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains) |
907b28c5 | 112 | { |
05a2fb15 | 113 | struct intel_uncore_forcewake_domain *d; |
907b28c5 | 114 | |
33c582c1 | 115 | for_each_fw_domain_masked(d, fw_domains, dev_priv) { |
05a2fb15 MK |
116 | fw_domain_wait_ack_clear(d); |
117 | fw_domain_get(d); | |
05a2fb15 | 118 | } |
4e1176dd TU |
119 | |
120 | for_each_fw_domain_masked(d, fw_domains, dev_priv) | |
121 | fw_domain_wait_ack(d); | |
05a2fb15 | 122 | } |
907b28c5 | 123 | |
05a2fb15 | 124 | static void |
48c1026a | 125 | fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains) |
05a2fb15 MK |
126 | { |
127 | struct intel_uncore_forcewake_domain *d; | |
907b28c5 | 128 | |
33c582c1 | 129 | for_each_fw_domain_masked(d, fw_domains, dev_priv) { |
05a2fb15 MK |
130 | fw_domain_put(d); |
131 | fw_domain_posting_read(d); | |
132 | } | |
133 | } | |
907b28c5 | 134 | |
517f188c WL |
135 | static void |
136 | vgpu_fw_domains_nop(struct drm_i915_private *dev_priv, | |
137 | enum forcewake_domains fw_domains) | |
138 | { | |
139 | /* Guest driver doesn't need to takes care forcewake. */ | |
140 | } | |
141 | ||
05a2fb15 MK |
142 | static void |
143 | fw_domains_posting_read(struct drm_i915_private *dev_priv) | |
144 | { | |
145 | struct intel_uncore_forcewake_domain *d; | |
05a2fb15 MK |
146 | |
147 | /* No need to do for all, just do for first found */ | |
33c582c1 | 148 | for_each_fw_domain(d, dev_priv) { |
05a2fb15 MK |
149 | fw_domain_posting_read(d); |
150 | break; | |
151 | } | |
152 | } | |
153 | ||
154 | static void | |
48c1026a | 155 | fw_domains_reset(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains) |
05a2fb15 MK |
156 | { |
157 | struct intel_uncore_forcewake_domain *d; | |
05a2fb15 | 158 | |
3225b2f9 MK |
159 | if (dev_priv->uncore.fw_domains == 0) |
160 | return; | |
f9b3927a | 161 | |
33c582c1 | 162 | for_each_fw_domain_masked(d, fw_domains, dev_priv) |
05a2fb15 MK |
163 | fw_domain_reset(d); |
164 | ||
165 | fw_domains_posting_read(dev_priv); | |
166 | } | |
167 | ||
168 | static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) | |
169 | { | |
170 | /* w/a for a sporadic read returning 0 by waiting for the GT | |
171 | * thread to wake up. | |
172 | */ | |
173 | if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) & | |
174 | GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500)) | |
175 | DRM_ERROR("GT thread status wait timed out\n"); | |
176 | } | |
177 | ||
178 | static void fw_domains_get_with_thread_status(struct drm_i915_private *dev_priv, | |
48c1026a | 179 | enum forcewake_domains fw_domains) |
05a2fb15 MK |
180 | { |
181 | fw_domains_get(dev_priv, fw_domains); | |
907b28c5 | 182 | |
05a2fb15 | 183 | /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */ |
c549f738 | 184 | __gen6_gt_wait_for_thread_c0(dev_priv); |
907b28c5 CW |
185 | } |
186 | ||
187 | static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) | |
188 | { | |
189 | u32 gtfifodbg; | |
6af5d92f CW |
190 | |
191 | gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG); | |
90f256b5 VS |
192 | if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg)) |
193 | __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg); | |
907b28c5 CW |
194 | } |
195 | ||
05a2fb15 | 196 | static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv, |
48c1026a | 197 | enum forcewake_domains fw_domains) |
907b28c5 | 198 | { |
05a2fb15 | 199 | fw_domains_put(dev_priv, fw_domains); |
907b28c5 CW |
200 | gen6_gt_check_fifodbg(dev_priv); |
201 | } | |
202 | ||
c32e3788 DG |
203 | static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv) |
204 | { | |
205 | u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL); | |
206 | ||
207 | return count & GT_FIFO_FREE_ENTRIES_MASK; | |
208 | } | |
209 | ||
907b28c5 CW |
210 | static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) |
211 | { | |
212 | int ret = 0; | |
213 | ||
5135d64b D |
214 | /* On VLV, FIFO will be shared by both SW and HW. |
215 | * So, we need to read the FREE_ENTRIES everytime */ | |
2d1fe073 | 216 | if (IS_VALLEYVIEW(dev_priv)) |
c32e3788 | 217 | dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv); |
5135d64b | 218 | |
907b28c5 CW |
219 | if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { |
220 | int loop = 500; | |
c32e3788 DG |
221 | u32 fifo = fifo_free_entries(dev_priv); |
222 | ||
907b28c5 CW |
223 | while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { |
224 | udelay(10); | |
c32e3788 | 225 | fifo = fifo_free_entries(dev_priv); |
907b28c5 CW |
226 | } |
227 | if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) | |
228 | ++ret; | |
229 | dev_priv->uncore.fifo_count = fifo; | |
230 | } | |
231 | dev_priv->uncore.fifo_count--; | |
232 | ||
233 | return ret; | |
234 | } | |
235 | ||
a57a4a67 TU |
236 | static enum hrtimer_restart |
237 | intel_uncore_fw_release_timer(struct hrtimer *timer) | |
38cff0b1 | 238 | { |
a57a4a67 TU |
239 | struct intel_uncore_forcewake_domain *domain = |
240 | container_of(timer, struct intel_uncore_forcewake_domain, timer); | |
003342a5 | 241 | struct drm_i915_private *dev_priv = domain->i915; |
b2cff0db | 242 | unsigned long irqflags; |
38cff0b1 | 243 | |
003342a5 | 244 | assert_rpm_device_not_suspended(dev_priv); |
38cff0b1 | 245 | |
003342a5 | 246 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
b2cff0db CW |
247 | if (WARN_ON(domain->wake_count == 0)) |
248 | domain->wake_count++; | |
249 | ||
003342a5 TU |
250 | if (--domain->wake_count == 0) { |
251 | dev_priv->uncore.funcs.force_wake_put(dev_priv, domain->mask); | |
252 | dev_priv->uncore.fw_domains_active &= ~domain->mask; | |
253 | } | |
b2cff0db | 254 | |
003342a5 | 255 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
a57a4a67 TU |
256 | |
257 | return HRTIMER_NORESTART; | |
38cff0b1 ZW |
258 | } |
259 | ||
dc97997a CW |
260 | void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv, |
261 | bool restore) | |
38cff0b1 | 262 | { |
48c1026a | 263 | unsigned long irqflags; |
b2cff0db | 264 | struct intel_uncore_forcewake_domain *domain; |
48c1026a | 265 | int retry_count = 100; |
003342a5 | 266 | enum forcewake_domains fw, active_domains; |
38cff0b1 | 267 | |
b2cff0db CW |
268 | /* Hold uncore.lock across reset to prevent any register access |
269 | * with forcewake not set correctly. Wait until all pending | |
270 | * timers are run before holding. | |
271 | */ | |
272 | while (1) { | |
273 | active_domains = 0; | |
38cff0b1 | 274 | |
33c582c1 | 275 | for_each_fw_domain(domain, dev_priv) { |
a57a4a67 | 276 | if (hrtimer_cancel(&domain->timer) == 0) |
b2cff0db | 277 | continue; |
38cff0b1 | 278 | |
a57a4a67 | 279 | intel_uncore_fw_release_timer(&domain->timer); |
b2cff0db | 280 | } |
aec347ab | 281 | |
b2cff0db | 282 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
b2ec142c | 283 | |
33c582c1 | 284 | for_each_fw_domain(domain, dev_priv) { |
a57a4a67 | 285 | if (hrtimer_active(&domain->timer)) |
33c582c1 | 286 | active_domains |= domain->mask; |
b2cff0db | 287 | } |
3123fcaf | 288 | |
b2cff0db CW |
289 | if (active_domains == 0) |
290 | break; | |
aec347ab | 291 | |
b2cff0db CW |
292 | if (--retry_count == 0) { |
293 | DRM_ERROR("Timed out waiting for forcewake timers to finish\n"); | |
294 | break; | |
295 | } | |
0294ae7b | 296 | |
b2cff0db CW |
297 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
298 | cond_resched(); | |
299 | } | |
0294ae7b | 300 | |
b2cff0db CW |
301 | WARN_ON(active_domains); |
302 | ||
003342a5 | 303 | fw = dev_priv->uncore.fw_domains_active; |
b2cff0db CW |
304 | if (fw) |
305 | dev_priv->uncore.funcs.force_wake_put(dev_priv, fw); | |
ef46e0d2 | 306 | |
05a2fb15 | 307 | fw_domains_reset(dev_priv, FORCEWAKE_ALL); |
38cff0b1 | 308 | |
0294ae7b | 309 | if (restore) { /* If reset with a user forcewake, try to restore */ |
0294ae7b CW |
310 | if (fw) |
311 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fw); | |
312 | ||
dc97997a | 313 | if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) |
0294ae7b | 314 | dev_priv->uncore.fifo_count = |
c32e3788 | 315 | fifo_free_entries(dev_priv); |
0294ae7b CW |
316 | } |
317 | ||
b2cff0db | 318 | if (!restore) |
59bad947 | 319 | assert_forcewakes_inactive(dev_priv); |
b2cff0db | 320 | |
0294ae7b | 321 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
ef46e0d2 DV |
322 | } |
323 | ||
c02e85a0 MK |
324 | static u64 gen9_edram_size(struct drm_i915_private *dev_priv) |
325 | { | |
326 | const unsigned int ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 }; | |
327 | const unsigned int sets[4] = { 1, 1, 2, 2 }; | |
328 | const u32 cap = dev_priv->edram_cap; | |
329 | ||
330 | return EDRAM_NUM_BANKS(cap) * | |
331 | ways[EDRAM_WAYS_IDX(cap)] * | |
332 | sets[EDRAM_SETS_IDX(cap)] * | |
333 | 1024 * 1024; | |
334 | } | |
335 | ||
3accaf7e | 336 | u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv) |
907b28c5 | 337 | { |
3accaf7e MK |
338 | if (!HAS_EDRAM(dev_priv)) |
339 | return 0; | |
340 | ||
c02e85a0 MK |
341 | /* The needed capability bits for size calculation |
342 | * are not there with pre gen9 so return 128MB always. | |
3accaf7e | 343 | */ |
c02e85a0 MK |
344 | if (INTEL_GEN(dev_priv) < 9) |
345 | return 128 * 1024 * 1024; | |
3accaf7e | 346 | |
c02e85a0 | 347 | return gen9_edram_size(dev_priv); |
3accaf7e | 348 | } |
907b28c5 | 349 | |
3accaf7e MK |
350 | static void intel_uncore_edram_detect(struct drm_i915_private *dev_priv) |
351 | { | |
352 | if (IS_HASWELL(dev_priv) || | |
353 | IS_BROADWELL(dev_priv) || | |
354 | INTEL_GEN(dev_priv) >= 9) { | |
355 | dev_priv->edram_cap = __raw_i915_read32(dev_priv, | |
356 | HSW_EDRAM_CAP); | |
357 | ||
358 | /* NB: We can't write IDICR yet because we do not have gt funcs | |
18ce3994 | 359 | * set up */ |
3accaf7e MK |
360 | } else { |
361 | dev_priv->edram_cap = 0; | |
18ce3994 | 362 | } |
3accaf7e MK |
363 | |
364 | if (HAS_EDRAM(dev_priv)) | |
365 | DRM_INFO("Found %lluMB of eDRAM\n", | |
366 | intel_uncore_edram_size(dev_priv) / (1024 * 1024)); | |
f9b3927a MK |
367 | } |
368 | ||
8a47eb19 | 369 | static bool |
8ac3e1bb | 370 | fpga_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv) |
8a47eb19 MK |
371 | { |
372 | u32 dbg; | |
373 | ||
8a47eb19 MK |
374 | dbg = __raw_i915_read32(dev_priv, FPGA_DBG); |
375 | if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM))) | |
376 | return false; | |
377 | ||
378 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); | |
379 | ||
380 | return true; | |
381 | } | |
382 | ||
8ac3e1bb MK |
383 | static bool |
384 | vlv_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv) | |
385 | { | |
386 | u32 cer; | |
387 | ||
388 | cer = __raw_i915_read32(dev_priv, CLAIM_ER); | |
389 | if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK)))) | |
390 | return false; | |
391 | ||
392 | __raw_i915_write32(dev_priv, CLAIM_ER, CLAIM_ER_CLR); | |
393 | ||
394 | return true; | |
395 | } | |
396 | ||
397 | static bool | |
398 | check_for_unclaimed_mmio(struct drm_i915_private *dev_priv) | |
399 | { | |
400 | if (HAS_FPGA_DBG_UNCLAIMED(dev_priv)) | |
401 | return fpga_check_for_unclaimed_mmio(dev_priv); | |
402 | ||
403 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
404 | return vlv_check_for_unclaimed_mmio(dev_priv); | |
405 | ||
406 | return false; | |
407 | } | |
408 | ||
dc97997a | 409 | static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv, |
f9b3927a MK |
410 | bool restore_forcewake) |
411 | { | |
85ee17eb PP |
412 | struct intel_device_info *info = mkwrite_device_info(dev_priv); |
413 | ||
8a47eb19 MK |
414 | /* clear out unclaimed reg detection bit */ |
415 | if (check_for_unclaimed_mmio(dev_priv)) | |
416 | DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n"); | |
907b28c5 | 417 | |
97058870 | 418 | /* clear out old GT FIFO errors */ |
dc97997a | 419 | if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) |
97058870 VS |
420 | __raw_i915_write32(dev_priv, GTFIFODBG, |
421 | __raw_i915_read32(dev_priv, GTFIFODBG)); | |
422 | ||
a04f90a3 | 423 | /* WaDisableShadowRegForCpd:chv */ |
dc97997a | 424 | if (IS_CHERRYVIEW(dev_priv)) { |
a04f90a3 D |
425 | __raw_i915_write32(dev_priv, GTFIFOCTL, |
426 | __raw_i915_read32(dev_priv, GTFIFOCTL) | | |
427 | GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL | | |
428 | GT_FIFO_CTL_RC6_POLICY_STALL); | |
429 | } | |
430 | ||
a3f79ca6 | 431 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST)) |
85ee17eb PP |
432 | info->has_decoupled_mmio = false; |
433 | ||
dc97997a | 434 | intel_uncore_forcewake_reset(dev_priv, restore_forcewake); |
521198a2 MK |
435 | } |
436 | ||
dc97997a CW |
437 | void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv, |
438 | bool restore_forcewake) | |
ed493883 | 439 | { |
dc97997a CW |
440 | __intel_uncore_early_sanitize(dev_priv, restore_forcewake); |
441 | i915_check_and_clear_faults(dev_priv); | |
ed493883 ID |
442 | } |
443 | ||
dc97997a | 444 | void intel_uncore_sanitize(struct drm_i915_private *dev_priv) |
521198a2 | 445 | { |
dc97997a | 446 | i915.enable_rc6 = sanitize_rc6_option(dev_priv, i915.enable_rc6); |
274008e8 | 447 | |
907b28c5 | 448 | /* BIOS often leaves RC6 enabled, but disable it for hw init */ |
54b4f68f | 449 | intel_sanitize_gt_powersave(dev_priv); |
907b28c5 CW |
450 | } |
451 | ||
a6111f7b CW |
452 | static void __intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, |
453 | enum forcewake_domains fw_domains) | |
454 | { | |
455 | struct intel_uncore_forcewake_domain *domain; | |
a6111f7b | 456 | |
a6111f7b CW |
457 | fw_domains &= dev_priv->uncore.fw_domains; |
458 | ||
33c582c1 | 459 | for_each_fw_domain_masked(domain, fw_domains, dev_priv) { |
a6111f7b | 460 | if (domain->wake_count++) |
33c582c1 | 461 | fw_domains &= ~domain->mask; |
a6111f7b CW |
462 | } |
463 | ||
003342a5 | 464 | if (fw_domains) { |
a6111f7b | 465 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains); |
003342a5 TU |
466 | dev_priv->uncore.fw_domains_active |= fw_domains; |
467 | } | |
a6111f7b CW |
468 | } |
469 | ||
59bad947 MK |
470 | /** |
471 | * intel_uncore_forcewake_get - grab forcewake domain references | |
472 | * @dev_priv: i915 device instance | |
473 | * @fw_domains: forcewake domains to get reference on | |
474 | * | |
475 | * This function can be used get GT's forcewake domain references. | |
476 | * Normal register access will handle the forcewake domains automatically. | |
477 | * However if some sequence requires the GT to not power down a particular | |
478 | * forcewake domains this function should be called at the beginning of the | |
479 | * sequence. And subsequently the reference should be dropped by symmetric | |
480 | * call to intel_unforce_forcewake_put(). Usually caller wants all the domains | |
481 | * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL. | |
907b28c5 | 482 | */ |
59bad947 | 483 | void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, |
48c1026a | 484 | enum forcewake_domains fw_domains) |
907b28c5 CW |
485 | { |
486 | unsigned long irqflags; | |
487 | ||
ab484f8f BW |
488 | if (!dev_priv->uncore.funcs.force_wake_get) |
489 | return; | |
490 | ||
c9b8846a | 491 | assert_rpm_wakelock_held(dev_priv); |
c8c8fb33 | 492 | |
6daccb0b | 493 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
a6111f7b | 494 | __intel_uncore_forcewake_get(dev_priv, fw_domains); |
907b28c5 CW |
495 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
496 | } | |
497 | ||
59bad947 | 498 | /** |
a6111f7b | 499 | * intel_uncore_forcewake_get__locked - grab forcewake domain references |
59bad947 | 500 | * @dev_priv: i915 device instance |
a6111f7b | 501 | * @fw_domains: forcewake domains to get reference on |
59bad947 | 502 | * |
a6111f7b CW |
503 | * See intel_uncore_forcewake_get(). This variant places the onus |
504 | * on the caller to explicitly handle the dev_priv->uncore.lock spinlock. | |
907b28c5 | 505 | */ |
a6111f7b CW |
506 | void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv, |
507 | enum forcewake_domains fw_domains) | |
508 | { | |
509 | assert_spin_locked(&dev_priv->uncore.lock); | |
510 | ||
511 | if (!dev_priv->uncore.funcs.force_wake_get) | |
512 | return; | |
513 | ||
514 | __intel_uncore_forcewake_get(dev_priv, fw_domains); | |
515 | } | |
516 | ||
517 | static void __intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, | |
518 | enum forcewake_domains fw_domains) | |
907b28c5 | 519 | { |
b2cff0db | 520 | struct intel_uncore_forcewake_domain *domain; |
907b28c5 | 521 | |
b2cff0db CW |
522 | fw_domains &= dev_priv->uncore.fw_domains; |
523 | ||
33c582c1 | 524 | for_each_fw_domain_masked(domain, fw_domains, dev_priv) { |
b2cff0db CW |
525 | if (WARN_ON(domain->wake_count == 0)) |
526 | continue; | |
527 | ||
528 | if (--domain->wake_count) | |
529 | continue; | |
530 | ||
05a2fb15 | 531 | fw_domain_arm_timer(domain); |
aec347ab | 532 | } |
a6111f7b | 533 | } |
dc9fb09c | 534 | |
a6111f7b CW |
535 | /** |
536 | * intel_uncore_forcewake_put - release a forcewake domain reference | |
537 | * @dev_priv: i915 device instance | |
538 | * @fw_domains: forcewake domains to put references | |
539 | * | |
540 | * This function drops the device-level forcewakes for specified | |
541 | * domains obtained by intel_uncore_forcewake_get(). | |
542 | */ | |
543 | void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, | |
544 | enum forcewake_domains fw_domains) | |
545 | { | |
546 | unsigned long irqflags; | |
547 | ||
548 | if (!dev_priv->uncore.funcs.force_wake_put) | |
549 | return; | |
550 | ||
551 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
552 | __intel_uncore_forcewake_put(dev_priv, fw_domains); | |
907b28c5 CW |
553 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
554 | } | |
555 | ||
a6111f7b CW |
556 | /** |
557 | * intel_uncore_forcewake_put__locked - grab forcewake domain references | |
558 | * @dev_priv: i915 device instance | |
559 | * @fw_domains: forcewake domains to get reference on | |
560 | * | |
561 | * See intel_uncore_forcewake_put(). This variant places the onus | |
562 | * on the caller to explicitly handle the dev_priv->uncore.lock spinlock. | |
563 | */ | |
564 | void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv, | |
565 | enum forcewake_domains fw_domains) | |
566 | { | |
567 | assert_spin_locked(&dev_priv->uncore.lock); | |
568 | ||
569 | if (!dev_priv->uncore.funcs.force_wake_put) | |
570 | return; | |
571 | ||
572 | __intel_uncore_forcewake_put(dev_priv, fw_domains); | |
573 | } | |
574 | ||
59bad947 | 575 | void assert_forcewakes_inactive(struct drm_i915_private *dev_priv) |
e998c40f PZ |
576 | { |
577 | if (!dev_priv->uncore.funcs.force_wake_get) | |
578 | return; | |
579 | ||
003342a5 | 580 | WARN_ON(dev_priv->uncore.fw_domains_active); |
e998c40f PZ |
581 | } |
582 | ||
907b28c5 | 583 | /* We give fast paths for the really cool registers */ |
40181697 | 584 | #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000) |
907b28c5 | 585 | |
6863b76c TU |
586 | #define __gen6_reg_read_fw_domains(offset) \ |
587 | ({ \ | |
588 | enum forcewake_domains __fwd; \ | |
589 | if (NEEDS_FORCE_WAKE(offset)) \ | |
590 | __fwd = FORCEWAKE_RENDER; \ | |
591 | else \ | |
592 | __fwd = 0; \ | |
593 | __fwd; \ | |
594 | }) | |
595 | ||
9480dbf0 | 596 | static int fw_range_cmp(u32 offset, const struct intel_forcewake_range *entry) |
91e630b9 | 597 | { |
91e630b9 TU |
598 | if (offset < entry->start) |
599 | return -1; | |
600 | else if (offset > entry->end) | |
601 | return 1; | |
602 | else | |
603 | return 0; | |
604 | } | |
605 | ||
9480dbf0 TU |
606 | /* Copied and "macroized" from lib/bsearch.c */ |
607 | #define BSEARCH(key, base, num, cmp) ({ \ | |
608 | unsigned int start__ = 0, end__ = (num); \ | |
609 | typeof(base) result__ = NULL; \ | |
610 | while (start__ < end__) { \ | |
611 | unsigned int mid__ = start__ + (end__ - start__) / 2; \ | |
612 | int ret__ = (cmp)((key), (base) + mid__); \ | |
613 | if (ret__ < 0) { \ | |
614 | end__ = mid__; \ | |
615 | } else if (ret__ > 0) { \ | |
616 | start__ = mid__ + 1; \ | |
617 | } else { \ | |
618 | result__ = (base) + mid__; \ | |
619 | break; \ | |
620 | } \ | |
621 | } \ | |
622 | result__; \ | |
623 | }) | |
624 | ||
9fc1117c | 625 | static enum forcewake_domains |
15157970 | 626 | find_fw_domain(struct drm_i915_private *dev_priv, u32 offset) |
9fc1117c | 627 | { |
9480dbf0 | 628 | const struct intel_forcewake_range *entry; |
9fc1117c | 629 | |
9480dbf0 TU |
630 | entry = BSEARCH(offset, |
631 | dev_priv->uncore.fw_domains_table, | |
632 | dev_priv->uncore.fw_domains_table_entries, | |
91e630b9 | 633 | fw_range_cmp); |
38fb6a40 | 634 | |
99191427 JL |
635 | if (!entry) |
636 | return 0; | |
637 | ||
638 | WARN(entry->domains & ~dev_priv->uncore.fw_domains, | |
639 | "Uninitialized forcewake domain(s) 0x%x accessed at 0x%x\n", | |
640 | entry->domains & ~dev_priv->uncore.fw_domains, offset); | |
641 | ||
642 | return entry->domains; | |
9fc1117c TU |
643 | } |
644 | ||
b0081239 | 645 | static void |
15157970 | 646 | intel_fw_table_check(struct drm_i915_private *dev_priv) |
b0081239 | 647 | { |
15157970 TU |
648 | const struct intel_forcewake_range *ranges; |
649 | unsigned int num_ranges; | |
b0081239 TU |
650 | s32 prev; |
651 | unsigned int i; | |
652 | ||
653 | if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG)) | |
654 | return; | |
655 | ||
15157970 TU |
656 | ranges = dev_priv->uncore.fw_domains_table; |
657 | if (!ranges) | |
658 | return; | |
659 | ||
660 | num_ranges = dev_priv->uncore.fw_domains_table_entries; | |
661 | ||
b0081239 | 662 | for (i = 0, prev = -1; i < num_ranges; i++, ranges++) { |
a194b8cb TU |
663 | WARN_ON_ONCE(IS_GEN9(dev_priv) && |
664 | (prev + 1) != (s32)ranges->start); | |
b0081239 TU |
665 | WARN_ON_ONCE(prev >= (s32)ranges->start); |
666 | prev = ranges->start; | |
667 | WARN_ON_ONCE(prev >= (s32)ranges->end); | |
668 | prev = ranges->end; | |
669 | } | |
670 | } | |
671 | ||
9fc1117c TU |
672 | #define GEN_FW_RANGE(s, e, d) \ |
673 | { .start = (s), .end = (e), .domains = (d) } | |
1938e59a | 674 | |
895833bd TU |
675 | #define HAS_FWTABLE(dev_priv) \ |
676 | (IS_GEN9(dev_priv) || \ | |
677 | IS_CHERRYVIEW(dev_priv) || \ | |
678 | IS_VALLEYVIEW(dev_priv)) | |
679 | ||
b0081239 | 680 | /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */ |
9fc1117c TU |
681 | static const struct intel_forcewake_range __vlv_fw_ranges[] = { |
682 | GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER), | |
683 | GEN_FW_RANGE(0x5000, 0x7fff, FORCEWAKE_RENDER), | |
684 | GEN_FW_RANGE(0xb000, 0x11fff, FORCEWAKE_RENDER), | |
9fc1117c TU |
685 | GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA), |
686 | GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_MEDIA), | |
b0081239 | 687 | GEN_FW_RANGE(0x2e000, 0x2ffff, FORCEWAKE_RENDER), |
9fc1117c TU |
688 | GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA), |
689 | }; | |
1938e59a | 690 | |
895833bd | 691 | #define __fwtable_reg_read_fw_domains(offset) \ |
6863b76c TU |
692 | ({ \ |
693 | enum forcewake_domains __fwd = 0; \ | |
0dd356bb | 694 | if (NEEDS_FORCE_WAKE((offset))) \ |
15157970 | 695 | __fwd = find_fw_domain(dev_priv, offset); \ |
6863b76c TU |
696 | __fwd; \ |
697 | }) | |
698 | ||
47188574 | 699 | /* *Must* be sorted by offset! See intel_shadow_table_check(). */ |
6863b76c | 700 | static const i915_reg_t gen8_shadowed_regs[] = { |
47188574 TU |
701 | RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */ |
702 | GEN6_RPNSWREQ, /* 0xA008 */ | |
703 | GEN6_RC_VIDEO_FREQ, /* 0xA00C */ | |
704 | RING_TAIL(GEN6_BSD_RING_BASE), /* 0x12000 (base) */ | |
705 | RING_TAIL(VEBOX_RING_BASE), /* 0x1a000 (base) */ | |
706 | RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */ | |
6863b76c TU |
707 | /* TODO: Other registers are not yet used */ |
708 | }; | |
709 | ||
47188574 TU |
710 | static void intel_shadow_table_check(void) |
711 | { | |
712 | const i915_reg_t *reg = gen8_shadowed_regs; | |
713 | s32 prev; | |
714 | u32 offset; | |
715 | unsigned int i; | |
716 | ||
717 | if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG)) | |
718 | return; | |
719 | ||
720 | for (i = 0, prev = -1; i < ARRAY_SIZE(gen8_shadowed_regs); i++, reg++) { | |
721 | offset = i915_mmio_reg_offset(*reg); | |
722 | WARN_ON_ONCE(prev >= (s32)offset); | |
723 | prev = offset; | |
724 | } | |
725 | } | |
726 | ||
9480dbf0 | 727 | static int mmio_reg_cmp(u32 key, const i915_reg_t *reg) |
5a659383 | 728 | { |
9480dbf0 | 729 | u32 offset = i915_mmio_reg_offset(*reg); |
5a659383 | 730 | |
9480dbf0 | 731 | if (key < offset) |
5a659383 | 732 | return -1; |
9480dbf0 | 733 | else if (key > offset) |
5a659383 TU |
734 | return 1; |
735 | else | |
736 | return 0; | |
737 | } | |
738 | ||
6863b76c TU |
739 | static bool is_gen8_shadowed(u32 offset) |
740 | { | |
9480dbf0 | 741 | const i915_reg_t *regs = gen8_shadowed_regs; |
5a659383 | 742 | |
9480dbf0 TU |
743 | return BSEARCH(offset, regs, ARRAY_SIZE(gen8_shadowed_regs), |
744 | mmio_reg_cmp); | |
6863b76c TU |
745 | } |
746 | ||
747 | #define __gen8_reg_write_fw_domains(offset) \ | |
748 | ({ \ | |
749 | enum forcewake_domains __fwd; \ | |
750 | if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(offset)) \ | |
751 | __fwd = FORCEWAKE_RENDER; \ | |
752 | else \ | |
753 | __fwd = 0; \ | |
754 | __fwd; \ | |
755 | }) | |
756 | ||
b0081239 | 757 | /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */ |
9fc1117c TU |
758 | static const struct intel_forcewake_range __chv_fw_ranges[] = { |
759 | GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER), | |
b0081239 | 760 | GEN_FW_RANGE(0x4000, 0x4fff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), |
9fc1117c | 761 | GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), |
b0081239 | 762 | GEN_FW_RANGE(0x8000, 0x82ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), |
9fc1117c | 763 | GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), |
b0081239 | 764 | GEN_FW_RANGE(0x8500, 0x85ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), |
9fc1117c | 765 | GEN_FW_RANGE(0x8800, 0x88ff, FORCEWAKE_MEDIA), |
b0081239 TU |
766 | GEN_FW_RANGE(0x9000, 0xafff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), |
767 | GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER), | |
9fc1117c | 768 | GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA), |
b0081239 TU |
769 | GEN_FW_RANGE(0xe000, 0xe7ff, FORCEWAKE_RENDER), |
770 | GEN_FW_RANGE(0xf000, 0xffff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), | |
9fc1117c TU |
771 | GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA), |
772 | GEN_FW_RANGE(0x1a000, 0x1bfff, FORCEWAKE_MEDIA), | |
773 | GEN_FW_RANGE(0x1e800, 0x1e9ff, FORCEWAKE_MEDIA), | |
774 | GEN_FW_RANGE(0x30000, 0x37fff, FORCEWAKE_MEDIA), | |
9fc1117c | 775 | }; |
38fb6a40 | 776 | |
22d48c55 | 777 | #define __fwtable_reg_write_fw_domains(offset) \ |
6863b76c TU |
778 | ({ \ |
779 | enum forcewake_domains __fwd = 0; \ | |
0dd356bb | 780 | if (NEEDS_FORCE_WAKE((offset)) && !is_gen8_shadowed(offset)) \ |
15157970 | 781 | __fwd = find_fw_domain(dev_priv, offset); \ |
6863b76c TU |
782 | __fwd; \ |
783 | }) | |
784 | ||
b0081239 | 785 | /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */ |
9fc1117c | 786 | static const struct intel_forcewake_range __gen9_fw_ranges[] = { |
0dd356bb | 787 | GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER), |
9fc1117c TU |
788 | GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */ |
789 | GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), | |
0dd356bb | 790 | GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER), |
9fc1117c | 791 | GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER), |
0dd356bb | 792 | GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER), |
9fc1117c | 793 | GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), |
0dd356bb | 794 | GEN_FW_RANGE(0x8000, 0x812f, FORCEWAKE_BLITTER), |
b0081239 | 795 | GEN_FW_RANGE(0x8130, 0x813f, FORCEWAKE_MEDIA), |
9fc1117c | 796 | GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER), |
0dd356bb | 797 | GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER), |
9fc1117c | 798 | GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), |
0dd356bb | 799 | GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_BLITTER), |
b0081239 | 800 | GEN_FW_RANGE(0x8800, 0x89ff, FORCEWAKE_MEDIA), |
0dd356bb | 801 | GEN_FW_RANGE(0x8a00, 0x8bff, FORCEWAKE_BLITTER), |
9fc1117c | 802 | GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER), |
0dd356bb | 803 | GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER), |
9fc1117c | 804 | GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), |
0dd356bb | 805 | GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER), |
b0081239 | 806 | GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER), |
78424c92 | 807 | GEN_FW_RANGE(0xb480, 0xcfff, FORCEWAKE_BLITTER), |
9fc1117c | 808 | GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA), |
0dd356bb | 809 | GEN_FW_RANGE(0xd800, 0xdfff, FORCEWAKE_BLITTER), |
b0081239 | 810 | GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER), |
0dd356bb | 811 | GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_BLITTER), |
9fc1117c | 812 | GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA), |
0dd356bb | 813 | GEN_FW_RANGE(0x14000, 0x19fff, FORCEWAKE_BLITTER), |
9fc1117c | 814 | GEN_FW_RANGE(0x1a000, 0x1e9ff, FORCEWAKE_MEDIA), |
0dd356bb | 815 | GEN_FW_RANGE(0x1ea00, 0x243ff, FORCEWAKE_BLITTER), |
b0081239 | 816 | GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER), |
0dd356bb | 817 | GEN_FW_RANGE(0x24800, 0x2ffff, FORCEWAKE_BLITTER), |
9fc1117c TU |
818 | GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA), |
819 | }; | |
6863b76c | 820 | |
907b28c5 CW |
821 | static void |
822 | ilk_dummy_write(struct drm_i915_private *dev_priv) | |
823 | { | |
824 | /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up | |
825 | * the chip from rc6 before touching it for real. MI_MODE is masked, | |
826 | * hence harmless to write 0 into. */ | |
6af5d92f | 827 | __raw_i915_write32(dev_priv, MI_MODE, 0); |
907b28c5 CW |
828 | } |
829 | ||
830 | static void | |
9c053501 MK |
831 | __unclaimed_reg_debug(struct drm_i915_private *dev_priv, |
832 | const i915_reg_t reg, | |
833 | const bool read, | |
834 | const bool before) | |
907b28c5 | 835 | { |
dda96033 CW |
836 | if (WARN(check_for_unclaimed_mmio(dev_priv) && !before, |
837 | "Unclaimed %s register 0x%x\n", | |
838 | read ? "read from" : "write to", | |
4bd0a25d | 839 | i915_mmio_reg_offset(reg))) |
48572edd | 840 | i915.mmio_debug--; /* Only report the first N failures */ |
907b28c5 CW |
841 | } |
842 | ||
9c053501 MK |
843 | static inline void |
844 | unclaimed_reg_debug(struct drm_i915_private *dev_priv, | |
845 | const i915_reg_t reg, | |
846 | const bool read, | |
847 | const bool before) | |
848 | { | |
849 | if (likely(!i915.mmio_debug)) | |
850 | return; | |
851 | ||
852 | __unclaimed_reg_debug(dev_priv, reg, read, before); | |
853 | } | |
854 | ||
85ee17eb PP |
855 | static const enum decoupled_power_domain fw2dpd_domain[] = { |
856 | GEN9_DECOUPLED_PD_RENDER, | |
857 | GEN9_DECOUPLED_PD_BLITTER, | |
858 | GEN9_DECOUPLED_PD_ALL, | |
859 | GEN9_DECOUPLED_PD_MEDIA, | |
860 | GEN9_DECOUPLED_PD_ALL, | |
861 | GEN9_DECOUPLED_PD_ALL, | |
862 | GEN9_DECOUPLED_PD_ALL | |
863 | }; | |
864 | ||
865 | /* | |
866 | * Decoupled MMIO access for only 1 DWORD | |
867 | */ | |
868 | static void __gen9_decoupled_mmio_access(struct drm_i915_private *dev_priv, | |
869 | u32 reg, | |
870 | enum forcewake_domains fw_domain, | |
871 | enum decoupled_ops operation) | |
872 | { | |
873 | enum decoupled_power_domain dp_domain; | |
874 | u32 ctrl_reg_data = 0; | |
875 | ||
876 | dp_domain = fw2dpd_domain[fw_domain - 1]; | |
877 | ||
878 | ctrl_reg_data |= reg; | |
879 | ctrl_reg_data |= (operation << GEN9_DECOUPLED_OP_SHIFT); | |
880 | ctrl_reg_data |= (dp_domain << GEN9_DECOUPLED_PD_SHIFT); | |
881 | ctrl_reg_data |= GEN9_DECOUPLED_DW1_GO; | |
882 | __raw_i915_write32(dev_priv, GEN9_DECOUPLED_REG0_DW1, ctrl_reg_data); | |
883 | ||
884 | if (wait_for_atomic((__raw_i915_read32(dev_priv, | |
885 | GEN9_DECOUPLED_REG0_DW1) & | |
886 | GEN9_DECOUPLED_DW1_GO) == 0, | |
887 | FORCEWAKE_ACK_TIMEOUT_MS)) | |
888 | DRM_ERROR("Decoupled MMIO wait timed out\n"); | |
889 | } | |
890 | ||
891 | static inline u32 | |
892 | __gen9_decoupled_mmio_read32(struct drm_i915_private *dev_priv, | |
893 | u32 reg, | |
894 | enum forcewake_domains fw_domain) | |
895 | { | |
896 | __gen9_decoupled_mmio_access(dev_priv, reg, fw_domain, | |
897 | GEN9_DECOUPLED_OP_READ); | |
898 | ||
899 | return __raw_i915_read32(dev_priv, GEN9_DECOUPLED_REG0_DW0); | |
900 | } | |
901 | ||
902 | static inline void | |
903 | __gen9_decoupled_mmio_write(struct drm_i915_private *dev_priv, | |
904 | u32 reg, u32 data, | |
905 | enum forcewake_domains fw_domain) | |
906 | { | |
907 | ||
908 | __raw_i915_write32(dev_priv, GEN9_DECOUPLED_REG0_DW0, data); | |
909 | ||
910 | __gen9_decoupled_mmio_access(dev_priv, reg, fw_domain, | |
911 | GEN9_DECOUPLED_OP_WRITE); | |
912 | } | |
913 | ||
914 | ||
51f67885 | 915 | #define GEN2_READ_HEADER(x) \ |
5d738795 | 916 | u##x val = 0; \ |
da5827c3 | 917 | assert_rpm_wakelock_held(dev_priv); |
5d738795 | 918 | |
51f67885 | 919 | #define GEN2_READ_FOOTER \ |
5d738795 BW |
920 | trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ |
921 | return val | |
922 | ||
51f67885 | 923 | #define __gen2_read(x) \ |
0b274481 | 924 | static u##x \ |
f0f59a00 | 925 | gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ |
51f67885 | 926 | GEN2_READ_HEADER(x); \ |
3967018e | 927 | val = __raw_i915_read##x(dev_priv, reg); \ |
51f67885 | 928 | GEN2_READ_FOOTER; \ |
3967018e BW |
929 | } |
930 | ||
931 | #define __gen5_read(x) \ | |
932 | static u##x \ | |
f0f59a00 | 933 | gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ |
51f67885 | 934 | GEN2_READ_HEADER(x); \ |
3967018e BW |
935 | ilk_dummy_write(dev_priv); \ |
936 | val = __raw_i915_read##x(dev_priv, reg); \ | |
51f67885 | 937 | GEN2_READ_FOOTER; \ |
3967018e BW |
938 | } |
939 | ||
51f67885 CW |
940 | __gen5_read(8) |
941 | __gen5_read(16) | |
942 | __gen5_read(32) | |
943 | __gen5_read(64) | |
944 | __gen2_read(8) | |
945 | __gen2_read(16) | |
946 | __gen2_read(32) | |
947 | __gen2_read(64) | |
948 | ||
949 | #undef __gen5_read | |
950 | #undef __gen2_read | |
951 | ||
952 | #undef GEN2_READ_FOOTER | |
953 | #undef GEN2_READ_HEADER | |
954 | ||
955 | #define GEN6_READ_HEADER(x) \ | |
f0f59a00 | 956 | u32 offset = i915_mmio_reg_offset(reg); \ |
51f67885 CW |
957 | unsigned long irqflags; \ |
958 | u##x val = 0; \ | |
da5827c3 | 959 | assert_rpm_wakelock_held(dev_priv); \ |
9c053501 MK |
960 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \ |
961 | unclaimed_reg_debug(dev_priv, reg, true, true) | |
51f67885 CW |
962 | |
963 | #define GEN6_READ_FOOTER \ | |
9c053501 | 964 | unclaimed_reg_debug(dev_priv, reg, true, false); \ |
51f67885 CW |
965 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ |
966 | trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ | |
967 | return val | |
968 | ||
c521b0c8 TU |
969 | static noinline void ___force_wake_auto(struct drm_i915_private *dev_priv, |
970 | enum forcewake_domains fw_domains) | |
b2cff0db CW |
971 | { |
972 | struct intel_uncore_forcewake_domain *domain; | |
b2cff0db | 973 | |
c521b0c8 TU |
974 | for_each_fw_domain_masked(domain, fw_domains, dev_priv) |
975 | fw_domain_arm_timer(domain); | |
976 | ||
977 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains); | |
978 | dev_priv->uncore.fw_domains_active |= fw_domains; | |
979 | } | |
980 | ||
981 | static inline void __force_wake_auto(struct drm_i915_private *dev_priv, | |
982 | enum forcewake_domains fw_domains) | |
983 | { | |
b2cff0db CW |
984 | if (WARN_ON(!fw_domains)) |
985 | return; | |
986 | ||
003342a5 TU |
987 | /* Turn on all requested but inactive supported forcewake domains. */ |
988 | fw_domains &= dev_priv->uncore.fw_domains; | |
989 | fw_domains &= ~dev_priv->uncore.fw_domains_active; | |
b2cff0db | 990 | |
c521b0c8 TU |
991 | if (fw_domains) |
992 | ___force_wake_auto(dev_priv, fw_domains); | |
b2cff0db CW |
993 | } |
994 | ||
3967018e BW |
995 | #define __gen6_read(x) \ |
996 | static u##x \ | |
f0f59a00 | 997 | gen6_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ |
6863b76c | 998 | enum forcewake_domains fw_engine; \ |
51f67885 | 999 | GEN6_READ_HEADER(x); \ |
6863b76c TU |
1000 | fw_engine = __gen6_reg_read_fw_domains(offset); \ |
1001 | if (fw_engine) \ | |
1002 | __force_wake_auto(dev_priv, fw_engine); \ | |
dc9fb09c | 1003 | val = __raw_i915_read##x(dev_priv, reg); \ |
51f67885 | 1004 | GEN6_READ_FOOTER; \ |
907b28c5 CW |
1005 | } |
1006 | ||
6044c4a3 | 1007 | #define __fwtable_read(x) \ |
940aece4 | 1008 | static u##x \ |
6044c4a3 | 1009 | fwtable_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ |
6863b76c | 1010 | enum forcewake_domains fw_engine; \ |
51f67885 | 1011 | GEN6_READ_HEADER(x); \ |
895833bd | 1012 | fw_engine = __fwtable_reg_read_fw_domains(offset); \ |
6a42d0f4 | 1013 | if (fw_engine) \ |
b208ba8e | 1014 | __force_wake_auto(dev_priv, fw_engine); \ |
6fe72865 | 1015 | val = __raw_i915_read##x(dev_priv, reg); \ |
51f67885 | 1016 | GEN6_READ_FOOTER; \ |
940aece4 D |
1017 | } |
1018 | ||
85ee17eb PP |
1019 | #define __gen9_decoupled_read(x) \ |
1020 | static u##x \ | |
1021 | gen9_decoupled_read##x(struct drm_i915_private *dev_priv, \ | |
1022 | i915_reg_t reg, bool trace) { \ | |
1023 | enum forcewake_domains fw_engine; \ | |
1024 | GEN6_READ_HEADER(x); \ | |
1025 | fw_engine = __fwtable_reg_read_fw_domains(offset); \ | |
1026 | if (fw_engine & ~dev_priv->uncore.fw_domains_active) { \ | |
1027 | unsigned i; \ | |
1028 | u32 *ptr_data = (u32 *) &val; \ | |
1029 | for (i = 0; i < x/32; i++, offset += sizeof(u32), ptr_data++) \ | |
1030 | *ptr_data = __gen9_decoupled_mmio_read32(dev_priv, \ | |
1031 | offset, \ | |
1032 | fw_engine); \ | |
1033 | } else { \ | |
1034 | val = __raw_i915_read##x(dev_priv, reg); \ | |
1035 | } \ | |
1036 | GEN6_READ_FOOTER; \ | |
1037 | } | |
1038 | ||
1039 | __gen9_decoupled_read(32) | |
1040 | __gen9_decoupled_read(64) | |
6044c4a3 TU |
1041 | __fwtable_read(8) |
1042 | __fwtable_read(16) | |
1043 | __fwtable_read(32) | |
1044 | __fwtable_read(64) | |
3967018e BW |
1045 | __gen6_read(8) |
1046 | __gen6_read(16) | |
1047 | __gen6_read(32) | |
1048 | __gen6_read(64) | |
3967018e | 1049 | |
6044c4a3 | 1050 | #undef __fwtable_read |
3967018e | 1051 | #undef __gen6_read |
51f67885 CW |
1052 | #undef GEN6_READ_FOOTER |
1053 | #undef GEN6_READ_HEADER | |
5d738795 | 1054 | |
51f67885 | 1055 | #define GEN2_WRITE_HEADER \ |
5d738795 | 1056 | trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ |
da5827c3 | 1057 | assert_rpm_wakelock_held(dev_priv); \ |
907b28c5 | 1058 | |
51f67885 | 1059 | #define GEN2_WRITE_FOOTER |
0d965301 | 1060 | |
51f67885 | 1061 | #define __gen2_write(x) \ |
0b274481 | 1062 | static void \ |
f0f59a00 | 1063 | gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \ |
51f67885 | 1064 | GEN2_WRITE_HEADER; \ |
4032ef43 | 1065 | __raw_i915_write##x(dev_priv, reg, val); \ |
51f67885 | 1066 | GEN2_WRITE_FOOTER; \ |
4032ef43 BW |
1067 | } |
1068 | ||
1069 | #define __gen5_write(x) \ | |
1070 | static void \ | |
f0f59a00 | 1071 | gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \ |
51f67885 | 1072 | GEN2_WRITE_HEADER; \ |
4032ef43 BW |
1073 | ilk_dummy_write(dev_priv); \ |
1074 | __raw_i915_write##x(dev_priv, reg, val); \ | |
51f67885 | 1075 | GEN2_WRITE_FOOTER; \ |
4032ef43 BW |
1076 | } |
1077 | ||
51f67885 CW |
1078 | __gen5_write(8) |
1079 | __gen5_write(16) | |
1080 | __gen5_write(32) | |
51f67885 CW |
1081 | __gen2_write(8) |
1082 | __gen2_write(16) | |
1083 | __gen2_write(32) | |
51f67885 CW |
1084 | |
1085 | #undef __gen5_write | |
1086 | #undef __gen2_write | |
1087 | ||
1088 | #undef GEN2_WRITE_FOOTER | |
1089 | #undef GEN2_WRITE_HEADER | |
1090 | ||
1091 | #define GEN6_WRITE_HEADER \ | |
f0f59a00 | 1092 | u32 offset = i915_mmio_reg_offset(reg); \ |
51f67885 CW |
1093 | unsigned long irqflags; \ |
1094 | trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ | |
da5827c3 | 1095 | assert_rpm_wakelock_held(dev_priv); \ |
9c053501 MK |
1096 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \ |
1097 | unclaimed_reg_debug(dev_priv, reg, false, true) | |
51f67885 CW |
1098 | |
1099 | #define GEN6_WRITE_FOOTER \ | |
9c053501 | 1100 | unclaimed_reg_debug(dev_priv, reg, false, false); \ |
51f67885 CW |
1101 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags) |
1102 | ||
4032ef43 BW |
1103 | #define __gen6_write(x) \ |
1104 | static void \ | |
f0f59a00 | 1105 | gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \ |
4032ef43 | 1106 | u32 __fifo_ret = 0; \ |
51f67885 | 1107 | GEN6_WRITE_HEADER; \ |
0670c5a6 | 1108 | if (NEEDS_FORCE_WAKE(offset)) { \ |
4032ef43 BW |
1109 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ |
1110 | } \ | |
1111 | __raw_i915_write##x(dev_priv, reg, val); \ | |
1112 | if (unlikely(__fifo_ret)) { \ | |
1113 | gen6_gt_check_fifodbg(dev_priv); \ | |
1114 | } \ | |
51f67885 | 1115 | GEN6_WRITE_FOOTER; \ |
4032ef43 BW |
1116 | } |
1117 | ||
ab2aa47e BW |
1118 | #define __gen8_write(x) \ |
1119 | static void \ | |
f0f59a00 | 1120 | gen8_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \ |
6863b76c | 1121 | enum forcewake_domains fw_engine; \ |
51f67885 | 1122 | GEN6_WRITE_HEADER; \ |
6863b76c TU |
1123 | fw_engine = __gen8_reg_write_fw_domains(offset); \ |
1124 | if (fw_engine) \ | |
1125 | __force_wake_auto(dev_priv, fw_engine); \ | |
b2cff0db | 1126 | __raw_i915_write##x(dev_priv, reg, val); \ |
51f67885 | 1127 | GEN6_WRITE_FOOTER; \ |
ab2aa47e BW |
1128 | } |
1129 | ||
22d48c55 | 1130 | #define __fwtable_write(x) \ |
1938e59a | 1131 | static void \ |
22d48c55 | 1132 | fwtable_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \ |
6863b76c | 1133 | enum forcewake_domains fw_engine; \ |
51f67885 | 1134 | GEN6_WRITE_HEADER; \ |
22d48c55 | 1135 | fw_engine = __fwtable_reg_write_fw_domains(offset); \ |
6a42d0f4 | 1136 | if (fw_engine) \ |
b208ba8e | 1137 | __force_wake_auto(dev_priv, fw_engine); \ |
1938e59a | 1138 | __raw_i915_write##x(dev_priv, reg, val); \ |
51f67885 | 1139 | GEN6_WRITE_FOOTER; \ |
1938e59a D |
1140 | } |
1141 | ||
85ee17eb PP |
1142 | #define __gen9_decoupled_write(x) \ |
1143 | static void \ | |
1144 | gen9_decoupled_write##x(struct drm_i915_private *dev_priv, \ | |
1145 | i915_reg_t reg, u##x val, \ | |
1146 | bool trace) { \ | |
1147 | enum forcewake_domains fw_engine; \ | |
1148 | GEN6_WRITE_HEADER; \ | |
1149 | fw_engine = __fwtable_reg_write_fw_domains(offset); \ | |
1150 | if (fw_engine & ~dev_priv->uncore.fw_domains_active) \ | |
1151 | __gen9_decoupled_mmio_write(dev_priv, \ | |
1152 | offset, \ | |
1153 | val, \ | |
1154 | fw_engine); \ | |
1155 | else \ | |
1156 | __raw_i915_write##x(dev_priv, reg, val); \ | |
1157 | GEN6_WRITE_FOOTER; \ | |
1158 | } | |
1159 | ||
1160 | __gen9_decoupled_write(32) | |
22d48c55 TU |
1161 | __fwtable_write(8) |
1162 | __fwtable_write(16) | |
1163 | __fwtable_write(32) | |
ab2aa47e BW |
1164 | __gen8_write(8) |
1165 | __gen8_write(16) | |
1166 | __gen8_write(32) | |
4032ef43 BW |
1167 | __gen6_write(8) |
1168 | __gen6_write(16) | |
1169 | __gen6_write(32) | |
4032ef43 | 1170 | |
22d48c55 | 1171 | #undef __fwtable_write |
ab2aa47e | 1172 | #undef __gen8_write |
4032ef43 | 1173 | #undef __gen6_write |
51f67885 CW |
1174 | #undef GEN6_WRITE_FOOTER |
1175 | #undef GEN6_WRITE_HEADER | |
907b28c5 | 1176 | |
43d942a7 YZ |
1177 | #define ASSIGN_WRITE_MMIO_VFUNCS(x) \ |
1178 | do { \ | |
1179 | dev_priv->uncore.funcs.mmio_writeb = x##_write8; \ | |
1180 | dev_priv->uncore.funcs.mmio_writew = x##_write16; \ | |
1181 | dev_priv->uncore.funcs.mmio_writel = x##_write32; \ | |
43d942a7 YZ |
1182 | } while (0) |
1183 | ||
1184 | #define ASSIGN_READ_MMIO_VFUNCS(x) \ | |
1185 | do { \ | |
1186 | dev_priv->uncore.funcs.mmio_readb = x##_read8; \ | |
1187 | dev_priv->uncore.funcs.mmio_readw = x##_read16; \ | |
1188 | dev_priv->uncore.funcs.mmio_readl = x##_read32; \ | |
1189 | dev_priv->uncore.funcs.mmio_readq = x##_read64; \ | |
1190 | } while (0) | |
1191 | ||
05a2fb15 MK |
1192 | |
1193 | static void fw_domain_init(struct drm_i915_private *dev_priv, | |
48c1026a | 1194 | enum forcewake_domain_id domain_id, |
f0f59a00 VS |
1195 | i915_reg_t reg_set, |
1196 | i915_reg_t reg_ack) | |
05a2fb15 MK |
1197 | { |
1198 | struct intel_uncore_forcewake_domain *d; | |
1199 | ||
1200 | if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT)) | |
1201 | return; | |
1202 | ||
1203 | d = &dev_priv->uncore.fw_domain[domain_id]; | |
1204 | ||
1205 | WARN_ON(d->wake_count); | |
1206 | ||
1207 | d->wake_count = 0; | |
1208 | d->reg_set = reg_set; | |
1209 | d->reg_ack = reg_ack; | |
1210 | ||
1211 | if (IS_GEN6(dev_priv)) { | |
1212 | d->val_reset = 0; | |
1213 | d->val_set = FORCEWAKE_KERNEL; | |
1214 | d->val_clear = 0; | |
1215 | } else { | |
8543747c | 1216 | /* WaRsClearFWBitsAtReset:bdw,skl */ |
05a2fb15 MK |
1217 | d->val_reset = _MASKED_BIT_DISABLE(0xffff); |
1218 | d->val_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL); | |
1219 | d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL); | |
1220 | } | |
1221 | ||
666a4537 | 1222 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
05a2fb15 MK |
1223 | d->reg_post = FORCEWAKE_ACK_VLV; |
1224 | else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) | |
1225 | d->reg_post = ECOBUS; | |
05a2fb15 MK |
1226 | |
1227 | d->i915 = dev_priv; | |
1228 | d->id = domain_id; | |
1229 | ||
33c582c1 TU |
1230 | BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER)); |
1231 | BUILD_BUG_ON(FORCEWAKE_BLITTER != (1 << FW_DOMAIN_ID_BLITTER)); | |
1232 | BUILD_BUG_ON(FORCEWAKE_MEDIA != (1 << FW_DOMAIN_ID_MEDIA)); | |
1233 | ||
1234 | d->mask = 1 << domain_id; | |
1235 | ||
a57a4a67 TU |
1236 | hrtimer_init(&d->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); |
1237 | d->timer.function = intel_uncore_fw_release_timer; | |
05a2fb15 MK |
1238 | |
1239 | dev_priv->uncore.fw_domains |= (1 << domain_id); | |
f9b3927a MK |
1240 | |
1241 | fw_domain_reset(d); | |
05a2fb15 MK |
1242 | } |
1243 | ||
dc97997a | 1244 | static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv) |
0b274481 | 1245 | { |
2d1fe073 | 1246 | if (INTEL_INFO(dev_priv)->gen <= 5) |
3225b2f9 MK |
1247 | return; |
1248 | ||
dc97997a | 1249 | if (IS_GEN9(dev_priv)) { |
05a2fb15 MK |
1250 | dev_priv->uncore.funcs.force_wake_get = fw_domains_get; |
1251 | dev_priv->uncore.funcs.force_wake_put = fw_domains_put; | |
1252 | fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, | |
1253 | FORCEWAKE_RENDER_GEN9, | |
1254 | FORCEWAKE_ACK_RENDER_GEN9); | |
1255 | fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER, | |
1256 | FORCEWAKE_BLITTER_GEN9, | |
1257 | FORCEWAKE_ACK_BLITTER_GEN9); | |
1258 | fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA, | |
1259 | FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9); | |
dc97997a | 1260 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
05a2fb15 | 1261 | dev_priv->uncore.funcs.force_wake_get = fw_domains_get; |
dc97997a | 1262 | if (!IS_CHERRYVIEW(dev_priv)) |
756c349d MK |
1263 | dev_priv->uncore.funcs.force_wake_put = |
1264 | fw_domains_put_with_fifo; | |
1265 | else | |
1266 | dev_priv->uncore.funcs.force_wake_put = fw_domains_put; | |
05a2fb15 MK |
1267 | fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, |
1268 | FORCEWAKE_VLV, FORCEWAKE_ACK_VLV); | |
1269 | fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA, | |
1270 | FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV); | |
dc97997a | 1271 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
05a2fb15 MK |
1272 | dev_priv->uncore.funcs.force_wake_get = |
1273 | fw_domains_get_with_thread_status; | |
dc97997a | 1274 | if (IS_HASWELL(dev_priv)) |
3d7d0c85 VS |
1275 | dev_priv->uncore.funcs.force_wake_put = |
1276 | fw_domains_put_with_fifo; | |
1277 | else | |
1278 | dev_priv->uncore.funcs.force_wake_put = fw_domains_put; | |
05a2fb15 MK |
1279 | fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, |
1280 | FORCEWAKE_MT, FORCEWAKE_ACK_HSW); | |
dc97997a | 1281 | } else if (IS_IVYBRIDGE(dev_priv)) { |
0b274481 BW |
1282 | u32 ecobus; |
1283 | ||
1284 | /* IVB configs may use multi-threaded forcewake */ | |
1285 | ||
1286 | /* A small trick here - if the bios hasn't configured | |
1287 | * MT forcewake, and if the device is in RC6, then | |
1288 | * force_wake_mt_get will not wake the device and the | |
1289 | * ECOBUS read will return zero. Which will be | |
1290 | * (correctly) interpreted by the test below as MT | |
1291 | * forcewake being disabled. | |
1292 | */ | |
05a2fb15 MK |
1293 | dev_priv->uncore.funcs.force_wake_get = |
1294 | fw_domains_get_with_thread_status; | |
1295 | dev_priv->uncore.funcs.force_wake_put = | |
1296 | fw_domains_put_with_fifo; | |
1297 | ||
f9b3927a MK |
1298 | /* We need to init first for ECOBUS access and then |
1299 | * determine later if we want to reinit, in case of MT access is | |
6ea2556f MK |
1300 | * not working. In this stage we don't know which flavour this |
1301 | * ivb is, so it is better to reset also the gen6 fw registers | |
1302 | * before the ecobus check. | |
f9b3927a | 1303 | */ |
6ea2556f MK |
1304 | |
1305 | __raw_i915_write32(dev_priv, FORCEWAKE, 0); | |
1306 | __raw_posting_read(dev_priv, ECOBUS); | |
1307 | ||
05a2fb15 MK |
1308 | fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, |
1309 | FORCEWAKE_MT, FORCEWAKE_MT_ACK); | |
f9b3927a | 1310 | |
556ab7a6 | 1311 | spin_lock_irq(&dev_priv->uncore.lock); |
05a2fb15 | 1312 | fw_domains_get_with_thread_status(dev_priv, FORCEWAKE_ALL); |
0b274481 | 1313 | ecobus = __raw_i915_read32(dev_priv, ECOBUS); |
05a2fb15 | 1314 | fw_domains_put_with_fifo(dev_priv, FORCEWAKE_ALL); |
556ab7a6 | 1315 | spin_unlock_irq(&dev_priv->uncore.lock); |
0b274481 | 1316 | |
05a2fb15 | 1317 | if (!(ecobus & FORCEWAKE_MT_ENABLE)) { |
0b274481 BW |
1318 | DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n"); |
1319 | DRM_INFO("when using vblank-synced partial screen updates.\n"); | |
05a2fb15 MK |
1320 | fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, |
1321 | FORCEWAKE, FORCEWAKE_ACK); | |
0b274481 | 1322 | } |
dc97997a | 1323 | } else if (IS_GEN6(dev_priv)) { |
0b274481 | 1324 | dev_priv->uncore.funcs.force_wake_get = |
05a2fb15 | 1325 | fw_domains_get_with_thread_status; |
0b274481 | 1326 | dev_priv->uncore.funcs.force_wake_put = |
05a2fb15 MK |
1327 | fw_domains_put_with_fifo; |
1328 | fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, | |
1329 | FORCEWAKE, FORCEWAKE_ACK); | |
0b274481 | 1330 | } |
3225b2f9 | 1331 | |
517f188c WL |
1332 | if (intel_vgpu_active(dev_priv)) { |
1333 | dev_priv->uncore.funcs.force_wake_get = vgpu_fw_domains_nop; | |
1334 | dev_priv->uncore.funcs.force_wake_put = vgpu_fw_domains_nop; | |
1335 | } | |
1336 | ||
3225b2f9 MK |
1337 | /* All future platforms are expected to require complex power gating */ |
1338 | WARN_ON(dev_priv->uncore.fw_domains == 0); | |
f9b3927a MK |
1339 | } |
1340 | ||
15157970 TU |
1341 | #define ASSIGN_FW_DOMAINS_TABLE(d) \ |
1342 | { \ | |
1343 | dev_priv->uncore.fw_domains_table = \ | |
1344 | (struct intel_forcewake_range *)(d); \ | |
1345 | dev_priv->uncore.fw_domains_table_entries = ARRAY_SIZE((d)); \ | |
1346 | } | |
1347 | ||
dc97997a | 1348 | void intel_uncore_init(struct drm_i915_private *dev_priv) |
f9b3927a | 1349 | { |
dc97997a | 1350 | i915_check_vgpu(dev_priv); |
cf9d2890 | 1351 | |
3accaf7e | 1352 | intel_uncore_edram_detect(dev_priv); |
dc97997a CW |
1353 | intel_uncore_fw_domains_init(dev_priv); |
1354 | __intel_uncore_early_sanitize(dev_priv, false); | |
0b274481 | 1355 | |
75714940 MK |
1356 | dev_priv->uncore.unclaimed_mmio_check = 1; |
1357 | ||
dc97997a | 1358 | switch (INTEL_INFO(dev_priv)->gen) { |
ab2aa47e | 1359 | default: |
4597a88a | 1360 | case 9: |
15157970 | 1361 | ASSIGN_FW_DOMAINS_TABLE(__gen9_fw_ranges); |
22d48c55 | 1362 | ASSIGN_WRITE_MMIO_VFUNCS(fwtable); |
6044c4a3 | 1363 | ASSIGN_READ_MMIO_VFUNCS(fwtable); |
85ee17eb PP |
1364 | if (HAS_DECOUPLED_MMIO(dev_priv)) { |
1365 | dev_priv->uncore.funcs.mmio_readl = | |
1366 | gen9_decoupled_read32; | |
1367 | dev_priv->uncore.funcs.mmio_readq = | |
1368 | gen9_decoupled_read64; | |
1369 | dev_priv->uncore.funcs.mmio_writel = | |
1370 | gen9_decoupled_write32; | |
1371 | } | |
4597a88a ZW |
1372 | break; |
1373 | case 8: | |
dc97997a | 1374 | if (IS_CHERRYVIEW(dev_priv)) { |
15157970 | 1375 | ASSIGN_FW_DOMAINS_TABLE(__chv_fw_ranges); |
22d48c55 | 1376 | ASSIGN_WRITE_MMIO_VFUNCS(fwtable); |
6044c4a3 | 1377 | ASSIGN_READ_MMIO_VFUNCS(fwtable); |
1938e59a D |
1378 | |
1379 | } else { | |
43d942a7 YZ |
1380 | ASSIGN_WRITE_MMIO_VFUNCS(gen8); |
1381 | ASSIGN_READ_MMIO_VFUNCS(gen6); | |
1938e59a | 1382 | } |
ab2aa47e | 1383 | break; |
3967018e BW |
1384 | case 7: |
1385 | case 6: | |
e9b825f4 | 1386 | ASSIGN_WRITE_MMIO_VFUNCS(gen6); |
940aece4 | 1387 | |
dc97997a | 1388 | if (IS_VALLEYVIEW(dev_priv)) { |
15157970 | 1389 | ASSIGN_FW_DOMAINS_TABLE(__vlv_fw_ranges); |
6044c4a3 | 1390 | ASSIGN_READ_MMIO_VFUNCS(fwtable); |
940aece4 | 1391 | } else { |
43d942a7 | 1392 | ASSIGN_READ_MMIO_VFUNCS(gen6); |
940aece4 | 1393 | } |
3967018e BW |
1394 | break; |
1395 | case 5: | |
43d942a7 YZ |
1396 | ASSIGN_WRITE_MMIO_VFUNCS(gen5); |
1397 | ASSIGN_READ_MMIO_VFUNCS(gen5); | |
3967018e BW |
1398 | break; |
1399 | case 4: | |
1400 | case 3: | |
1401 | case 2: | |
51f67885 CW |
1402 | ASSIGN_WRITE_MMIO_VFUNCS(gen2); |
1403 | ASSIGN_READ_MMIO_VFUNCS(gen2); | |
3967018e BW |
1404 | break; |
1405 | } | |
ed493883 | 1406 | |
15157970 | 1407 | intel_fw_table_check(dev_priv); |
47188574 TU |
1408 | if (INTEL_GEN(dev_priv) >= 8) |
1409 | intel_shadow_table_check(); | |
15157970 | 1410 | |
dc97997a | 1411 | i915_check_and_clear_faults(dev_priv); |
0b274481 | 1412 | } |
43d942a7 YZ |
1413 | #undef ASSIGN_WRITE_MMIO_VFUNCS |
1414 | #undef ASSIGN_READ_MMIO_VFUNCS | |
0b274481 | 1415 | |
dc97997a | 1416 | void intel_uncore_fini(struct drm_i915_private *dev_priv) |
0b274481 | 1417 | { |
0b274481 | 1418 | /* Paranoia: make sure we have disabled everything before we exit. */ |
dc97997a CW |
1419 | intel_uncore_sanitize(dev_priv); |
1420 | intel_uncore_forcewake_reset(dev_priv, false); | |
0b274481 BW |
1421 | } |
1422 | ||
ae5702d2 | 1423 | #define GEN_RANGE(l, h) GENMASK((h) - 1, (l) - 1) |
af76ae44 | 1424 | |
907b28c5 | 1425 | static const struct register_whitelist { |
f0f59a00 | 1426 | i915_reg_t offset_ldw, offset_udw; |
907b28c5 | 1427 | uint32_t size; |
af76ae44 DL |
1428 | /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */ |
1429 | uint32_t gen_bitmask; | |
907b28c5 | 1430 | } whitelist[] = { |
8697600b VS |
1431 | { .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE), |
1432 | .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE), | |
1433 | .size = 8, .gen_bitmask = GEN_RANGE(4, 9) }, | |
907b28c5 CW |
1434 | }; |
1435 | ||
1436 | int i915_reg_read_ioctl(struct drm_device *dev, | |
1437 | void *data, struct drm_file *file) | |
1438 | { | |
fac5e23e | 1439 | struct drm_i915_private *dev_priv = to_i915(dev); |
907b28c5 CW |
1440 | struct drm_i915_reg_read *reg = data; |
1441 | struct register_whitelist const *entry = whitelist; | |
648a9bc5 | 1442 | unsigned size; |
f0f59a00 | 1443 | i915_reg_t offset_ldw, offset_udw; |
cf67c70f | 1444 | int i, ret = 0; |
907b28c5 CW |
1445 | |
1446 | for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) { | |
f0f59a00 | 1447 | if (i915_mmio_reg_offset(entry->offset_ldw) == (reg->offset & -entry->size) && |
66478475 | 1448 | (INTEL_INFO(dev_priv)->gen_mask & entry->gen_bitmask)) |
907b28c5 CW |
1449 | break; |
1450 | } | |
1451 | ||
1452 | if (i == ARRAY_SIZE(whitelist)) | |
1453 | return -EINVAL; | |
1454 | ||
648a9bc5 CW |
1455 | /* We use the low bits to encode extra flags as the register should |
1456 | * be naturally aligned (and those that are not so aligned merely | |
1457 | * limit the available flags for that register). | |
1458 | */ | |
8697600b VS |
1459 | offset_ldw = entry->offset_ldw; |
1460 | offset_udw = entry->offset_udw; | |
648a9bc5 | 1461 | size = entry->size; |
f0f59a00 | 1462 | size |= reg->offset ^ i915_mmio_reg_offset(offset_ldw); |
648a9bc5 | 1463 | |
cf67c70f PZ |
1464 | intel_runtime_pm_get(dev_priv); |
1465 | ||
648a9bc5 CW |
1466 | switch (size) { |
1467 | case 8 | 1: | |
8697600b | 1468 | reg->val = I915_READ64_2x32(offset_ldw, offset_udw); |
648a9bc5 | 1469 | break; |
907b28c5 | 1470 | case 8: |
8697600b | 1471 | reg->val = I915_READ64(offset_ldw); |
907b28c5 CW |
1472 | break; |
1473 | case 4: | |
8697600b | 1474 | reg->val = I915_READ(offset_ldw); |
907b28c5 CW |
1475 | break; |
1476 | case 2: | |
8697600b | 1477 | reg->val = I915_READ16(offset_ldw); |
907b28c5 CW |
1478 | break; |
1479 | case 1: | |
8697600b | 1480 | reg->val = I915_READ8(offset_ldw); |
907b28c5 CW |
1481 | break; |
1482 | default: | |
cf67c70f PZ |
1483 | ret = -EINVAL; |
1484 | goto out; | |
907b28c5 CW |
1485 | } |
1486 | ||
cf67c70f PZ |
1487 | out: |
1488 | intel_runtime_pm_put(dev_priv); | |
1489 | return ret; | |
907b28c5 CW |
1490 | } |
1491 | ||
dc97997a | 1492 | static int i915_reset_complete(struct pci_dev *pdev) |
907b28c5 CW |
1493 | { |
1494 | u8 gdrst; | |
dc97997a | 1495 | pci_read_config_byte(pdev, I915_GDRST, &gdrst); |
73bbf6bd | 1496 | return (gdrst & GRDOM_RESET_STATUS) == 0; |
907b28c5 CW |
1497 | } |
1498 | ||
dc97997a | 1499 | static int i915_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask) |
907b28c5 | 1500 | { |
91c8a326 | 1501 | struct pci_dev *pdev = dev_priv->drm.pdev; |
dc97997a | 1502 | |
73bbf6bd | 1503 | /* assert reset for at least 20 usec */ |
dc97997a | 1504 | pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE); |
73bbf6bd | 1505 | udelay(20); |
dc97997a | 1506 | pci_write_config_byte(pdev, I915_GDRST, 0); |
907b28c5 | 1507 | |
dc97997a | 1508 | return wait_for(i915_reset_complete(pdev), 500); |
73bbf6bd VS |
1509 | } |
1510 | ||
dc97997a | 1511 | static int g4x_reset_complete(struct pci_dev *pdev) |
73bbf6bd VS |
1512 | { |
1513 | u8 gdrst; | |
dc97997a | 1514 | pci_read_config_byte(pdev, I915_GDRST, &gdrst); |
73bbf6bd | 1515 | return (gdrst & GRDOM_RESET_ENABLE) == 0; |
907b28c5 CW |
1516 | } |
1517 | ||
dc97997a | 1518 | static int g33_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask) |
408d4b9e | 1519 | { |
91c8a326 | 1520 | struct pci_dev *pdev = dev_priv->drm.pdev; |
dc97997a CW |
1521 | pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE); |
1522 | return wait_for(g4x_reset_complete(pdev), 500); | |
408d4b9e VS |
1523 | } |
1524 | ||
dc97997a | 1525 | static int g4x_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask) |
fa4f53c4 | 1526 | { |
91c8a326 | 1527 | struct pci_dev *pdev = dev_priv->drm.pdev; |
fa4f53c4 VS |
1528 | int ret; |
1529 | ||
dc97997a | 1530 | pci_write_config_byte(pdev, I915_GDRST, |
fa4f53c4 | 1531 | GRDOM_RENDER | GRDOM_RESET_ENABLE); |
dc97997a | 1532 | ret = wait_for(g4x_reset_complete(pdev), 500); |
fa4f53c4 VS |
1533 | if (ret) |
1534 | return ret; | |
1535 | ||
1536 | /* WaVcpClkGateDisableForMediaReset:ctg,elk */ | |
1537 | I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE); | |
1538 | POSTING_READ(VDECCLK_GATE_D); | |
1539 | ||
dc97997a | 1540 | pci_write_config_byte(pdev, I915_GDRST, |
fa4f53c4 | 1541 | GRDOM_MEDIA | GRDOM_RESET_ENABLE); |
dc97997a | 1542 | ret = wait_for(g4x_reset_complete(pdev), 500); |
fa4f53c4 VS |
1543 | if (ret) |
1544 | return ret; | |
1545 | ||
1546 | /* WaVcpClkGateDisableForMediaReset:ctg,elk */ | |
1547 | I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE); | |
1548 | POSTING_READ(VDECCLK_GATE_D); | |
1549 | ||
dc97997a | 1550 | pci_write_config_byte(pdev, I915_GDRST, 0); |
fa4f53c4 VS |
1551 | |
1552 | return 0; | |
1553 | } | |
1554 | ||
dc97997a CW |
1555 | static int ironlake_do_reset(struct drm_i915_private *dev_priv, |
1556 | unsigned engine_mask) | |
907b28c5 | 1557 | { |
907b28c5 CW |
1558 | int ret; |
1559 | ||
c039b7f2 | 1560 | I915_WRITE(ILK_GDSR, |
0f08ffd6 | 1561 | ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE); |
87273b71 CW |
1562 | ret = intel_wait_for_register(dev_priv, |
1563 | ILK_GDSR, ILK_GRDOM_RESET_ENABLE, 0, | |
1564 | 500); | |
907b28c5 CW |
1565 | if (ret) |
1566 | return ret; | |
1567 | ||
c039b7f2 | 1568 | I915_WRITE(ILK_GDSR, |
0f08ffd6 | 1569 | ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE); |
87273b71 CW |
1570 | ret = intel_wait_for_register(dev_priv, |
1571 | ILK_GDSR, ILK_GRDOM_RESET_ENABLE, 0, | |
1572 | 500); | |
9aa7250f VS |
1573 | if (ret) |
1574 | return ret; | |
1575 | ||
c039b7f2 | 1576 | I915_WRITE(ILK_GDSR, 0); |
9aa7250f VS |
1577 | |
1578 | return 0; | |
907b28c5 CW |
1579 | } |
1580 | ||
ee4b6faf MK |
1581 | /* Reset the hardware domains (GENX_GRDOM_*) specified by mask */ |
1582 | static int gen6_hw_domain_reset(struct drm_i915_private *dev_priv, | |
1583 | u32 hw_domain_mask) | |
907b28c5 | 1584 | { |
907b28c5 CW |
1585 | /* GEN6_GDRST is not in the gt power well, no need to check |
1586 | * for fifo space for the write or forcewake the chip for | |
1587 | * the read | |
1588 | */ | |
ee4b6faf | 1589 | __raw_i915_write32(dev_priv, GEN6_GDRST, hw_domain_mask); |
907b28c5 | 1590 | |
ee4b6faf | 1591 | /* Spin waiting for the device to ack the reset requests */ |
4a17fe13 CW |
1592 | return intel_wait_for_register_fw(dev_priv, |
1593 | GEN6_GDRST, hw_domain_mask, 0, | |
1594 | 500); | |
ee4b6faf MK |
1595 | } |
1596 | ||
1597 | /** | |
1598 | * gen6_reset_engines - reset individual engines | |
dc97997a | 1599 | * @dev_priv: i915 device |
ee4b6faf MK |
1600 | * @engine_mask: mask of intel_ring_flag() engines or ALL_ENGINES for full reset |
1601 | * | |
1602 | * This function will reset the individual engines that are set in engine_mask. | |
1603 | * If you provide ALL_ENGINES as mask, full global domain reset will be issued. | |
1604 | * | |
1605 | * Note: It is responsibility of the caller to handle the difference between | |
1606 | * asking full domain reset versus reset for all available individual engines. | |
1607 | * | |
1608 | * Returns 0 on success, nonzero on error. | |
1609 | */ | |
dc97997a CW |
1610 | static int gen6_reset_engines(struct drm_i915_private *dev_priv, |
1611 | unsigned engine_mask) | |
ee4b6faf | 1612 | { |
ee4b6faf MK |
1613 | struct intel_engine_cs *engine; |
1614 | const u32 hw_engine_mask[I915_NUM_ENGINES] = { | |
1615 | [RCS] = GEN6_GRDOM_RENDER, | |
1616 | [BCS] = GEN6_GRDOM_BLT, | |
1617 | [VCS] = GEN6_GRDOM_MEDIA, | |
1618 | [VCS2] = GEN8_GRDOM_MEDIA2, | |
1619 | [VECS] = GEN6_GRDOM_VECS, | |
1620 | }; | |
1621 | u32 hw_mask; | |
1622 | int ret; | |
1623 | ||
1624 | if (engine_mask == ALL_ENGINES) { | |
1625 | hw_mask = GEN6_GRDOM_FULL; | |
1626 | } else { | |
bafb0fce CW |
1627 | unsigned int tmp; |
1628 | ||
ee4b6faf | 1629 | hw_mask = 0; |
bafb0fce | 1630 | for_each_engine_masked(engine, dev_priv, engine_mask, tmp) |
ee4b6faf MK |
1631 | hw_mask |= hw_engine_mask[engine->id]; |
1632 | } | |
1633 | ||
1634 | ret = gen6_hw_domain_reset(dev_priv, hw_mask); | |
907b28c5 | 1635 | |
dc97997a | 1636 | intel_uncore_forcewake_reset(dev_priv, true); |
5babf0fc | 1637 | |
907b28c5 CW |
1638 | return ret; |
1639 | } | |
1640 | ||
1758b90e CW |
1641 | /** |
1642 | * intel_wait_for_register_fw - wait until register matches expected state | |
1643 | * @dev_priv: the i915 device | |
1644 | * @reg: the register to read | |
1645 | * @mask: mask to apply to register value | |
1646 | * @value: expected value | |
1647 | * @timeout_ms: timeout in millisecond | |
1648 | * | |
1649 | * This routine waits until the target register @reg contains the expected | |
3d466cd6 DV |
1650 | * @value after applying the @mask, i.e. it waits until :: |
1651 | * | |
1652 | * (I915_READ_FW(reg) & mask) == value | |
1653 | * | |
1758b90e CW |
1654 | * Otherwise, the wait will timeout after @timeout_ms milliseconds. |
1655 | * | |
1656 | * Note that this routine assumes the caller holds forcewake asserted, it is | |
1657 | * not suitable for very long waits. See intel_wait_for_register() if you | |
1658 | * wish to wait without holding forcewake for the duration (i.e. you expect | |
1659 | * the wait to be slow). | |
1660 | * | |
1661 | * Returns 0 if the register matches the desired condition, or -ETIMEOUT. | |
1662 | */ | |
1663 | int intel_wait_for_register_fw(struct drm_i915_private *dev_priv, | |
1664 | i915_reg_t reg, | |
1665 | const u32 mask, | |
1666 | const u32 value, | |
1667 | const unsigned long timeout_ms) | |
1668 | { | |
1669 | #define done ((I915_READ_FW(reg) & mask) == value) | |
1670 | int ret = wait_for_us(done, 2); | |
1671 | if (ret) | |
1672 | ret = wait_for(done, timeout_ms); | |
1673 | return ret; | |
1674 | #undef done | |
1675 | } | |
1676 | ||
1677 | /** | |
1678 | * intel_wait_for_register - wait until register matches expected state | |
1679 | * @dev_priv: the i915 device | |
1680 | * @reg: the register to read | |
1681 | * @mask: mask to apply to register value | |
1682 | * @value: expected value | |
1683 | * @timeout_ms: timeout in millisecond | |
1684 | * | |
1685 | * This routine waits until the target register @reg contains the expected | |
3d466cd6 DV |
1686 | * @value after applying the @mask, i.e. it waits until :: |
1687 | * | |
1688 | * (I915_READ(reg) & mask) == value | |
1689 | * | |
1758b90e CW |
1690 | * Otherwise, the wait will timeout after @timeout_ms milliseconds. |
1691 | * | |
1692 | * Returns 0 if the register matches the desired condition, or -ETIMEOUT. | |
1693 | */ | |
1694 | int intel_wait_for_register(struct drm_i915_private *dev_priv, | |
1695 | i915_reg_t reg, | |
1696 | const u32 mask, | |
1697 | const u32 value, | |
1698 | const unsigned long timeout_ms) | |
7fd2d269 | 1699 | { |
1758b90e CW |
1700 | |
1701 | unsigned fw = | |
1702 | intel_uncore_forcewake_for_reg(dev_priv, reg, FW_REG_READ); | |
1703 | int ret; | |
1704 | ||
1705 | intel_uncore_forcewake_get(dev_priv, fw); | |
1706 | ret = wait_for_us((I915_READ_FW(reg) & mask) == value, 2); | |
1707 | intel_uncore_forcewake_put(dev_priv, fw); | |
1708 | if (ret) | |
1709 | ret = wait_for((I915_READ_NOTRACE(reg) & mask) == value, | |
1710 | timeout_ms); | |
1711 | ||
1712 | return ret; | |
d431440c TE |
1713 | } |
1714 | ||
1715 | static int gen8_request_engine_reset(struct intel_engine_cs *engine) | |
1716 | { | |
c033666a | 1717 | struct drm_i915_private *dev_priv = engine->i915; |
d431440c | 1718 | int ret; |
d431440c TE |
1719 | |
1720 | I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base), | |
1721 | _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET)); | |
1722 | ||
1758b90e CW |
1723 | ret = intel_wait_for_register_fw(dev_priv, |
1724 | RING_RESET_CTL(engine->mmio_base), | |
1725 | RESET_CTL_READY_TO_RESET, | |
1726 | RESET_CTL_READY_TO_RESET, | |
1727 | 700); | |
d431440c TE |
1728 | if (ret) |
1729 | DRM_ERROR("%s: reset request timeout\n", engine->name); | |
1730 | ||
1731 | return ret; | |
1732 | } | |
1733 | ||
1734 | static void gen8_unrequest_engine_reset(struct intel_engine_cs *engine) | |
1735 | { | |
c033666a | 1736 | struct drm_i915_private *dev_priv = engine->i915; |
d431440c TE |
1737 | |
1738 | I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base), | |
1739 | _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET)); | |
7fd2d269 MK |
1740 | } |
1741 | ||
dc97997a CW |
1742 | static int gen8_reset_engines(struct drm_i915_private *dev_priv, |
1743 | unsigned engine_mask) | |
7fd2d269 | 1744 | { |
7fd2d269 | 1745 | struct intel_engine_cs *engine; |
bafb0fce | 1746 | unsigned int tmp; |
7fd2d269 | 1747 | |
bafb0fce | 1748 | for_each_engine_masked(engine, dev_priv, engine_mask, tmp) |
d431440c | 1749 | if (gen8_request_engine_reset(engine)) |
7fd2d269 | 1750 | goto not_ready; |
7fd2d269 | 1751 | |
dc97997a | 1752 | return gen6_reset_engines(dev_priv, engine_mask); |
7fd2d269 MK |
1753 | |
1754 | not_ready: | |
bafb0fce | 1755 | for_each_engine_masked(engine, dev_priv, engine_mask, tmp) |
d431440c | 1756 | gen8_unrequest_engine_reset(engine); |
7fd2d269 MK |
1757 | |
1758 | return -EIO; | |
1759 | } | |
1760 | ||
dc97997a CW |
1761 | typedef int (*reset_func)(struct drm_i915_private *, unsigned engine_mask); |
1762 | ||
1763 | static reset_func intel_get_gpu_reset(struct drm_i915_private *dev_priv) | |
907b28c5 | 1764 | { |
b1330fbb CW |
1765 | if (!i915.reset) |
1766 | return NULL; | |
1767 | ||
dc97997a | 1768 | if (INTEL_INFO(dev_priv)->gen >= 8) |
ee4b6faf | 1769 | return gen8_reset_engines; |
dc97997a | 1770 | else if (INTEL_INFO(dev_priv)->gen >= 6) |
ee4b6faf | 1771 | return gen6_reset_engines; |
dc97997a | 1772 | else if (IS_GEN5(dev_priv)) |
49e4d842 | 1773 | return ironlake_do_reset; |
dc97997a | 1774 | else if (IS_G4X(dev_priv)) |
49e4d842 | 1775 | return g4x_do_reset; |
73f67aa8 | 1776 | else if (IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) |
49e4d842 | 1777 | return g33_do_reset; |
dc97997a | 1778 | else if (INTEL_INFO(dev_priv)->gen >= 3) |
49e4d842 | 1779 | return i915_do_reset; |
542c184f | 1780 | else |
49e4d842 CW |
1781 | return NULL; |
1782 | } | |
1783 | ||
dc97997a | 1784 | int intel_gpu_reset(struct drm_i915_private *dev_priv, unsigned engine_mask) |
49e4d842 | 1785 | { |
dc97997a | 1786 | reset_func reset; |
99106bc1 | 1787 | int ret; |
49e4d842 | 1788 | |
dc97997a | 1789 | reset = intel_get_gpu_reset(dev_priv); |
49e4d842 | 1790 | if (reset == NULL) |
542c184f | 1791 | return -ENODEV; |
49e4d842 | 1792 | |
99106bc1 MK |
1793 | /* If the power well sleeps during the reset, the reset |
1794 | * request may be dropped and never completes (causing -EIO). | |
1795 | */ | |
1796 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
dc97997a | 1797 | ret = reset(dev_priv, engine_mask); |
99106bc1 MK |
1798 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
1799 | ||
1800 | return ret; | |
49e4d842 CW |
1801 | } |
1802 | ||
dc97997a | 1803 | bool intel_has_gpu_reset(struct drm_i915_private *dev_priv) |
49e4d842 | 1804 | { |
dc97997a | 1805 | return intel_get_gpu_reset(dev_priv) != NULL; |
907b28c5 CW |
1806 | } |
1807 | ||
6b332fa2 AS |
1808 | int intel_guc_reset(struct drm_i915_private *dev_priv) |
1809 | { | |
1810 | int ret; | |
1811 | unsigned long irqflags; | |
1812 | ||
1a3d1898 | 1813 | if (!HAS_GUC(dev_priv)) |
6b332fa2 AS |
1814 | return -EINVAL; |
1815 | ||
1816 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
1817 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
1818 | ||
1819 | ret = gen6_hw_domain_reset(dev_priv, GEN9_GRDOM_GUC); | |
1820 | ||
1821 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
1822 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
1823 | ||
1824 | return ret; | |
1825 | } | |
1826 | ||
fc97618b | 1827 | bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv) |
907b28c5 | 1828 | { |
fc97618b | 1829 | return check_for_unclaimed_mmio(dev_priv); |
907b28c5 | 1830 | } |
75714940 | 1831 | |
bc3b9346 | 1832 | bool |
75714940 MK |
1833 | intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv) |
1834 | { | |
1835 | if (unlikely(i915.mmio_debug || | |
1836 | dev_priv->uncore.unclaimed_mmio_check <= 0)) | |
bc3b9346 | 1837 | return false; |
75714940 MK |
1838 | |
1839 | if (unlikely(intel_uncore_unclaimed_mmio(dev_priv))) { | |
1840 | DRM_DEBUG("Unclaimed register detected, " | |
1841 | "enabling oneshot unclaimed register reporting. " | |
1842 | "Please use i915.mmio_debug=N for more information.\n"); | |
1843 | i915.mmio_debug++; | |
1844 | dev_priv->uncore.unclaimed_mmio_check--; | |
bc3b9346 | 1845 | return true; |
75714940 | 1846 | } |
bc3b9346 MK |
1847 | |
1848 | return false; | |
75714940 | 1849 | } |
3756685a TU |
1850 | |
1851 | static enum forcewake_domains | |
1852 | intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv, | |
1853 | i915_reg_t reg) | |
1854 | { | |
895833bd | 1855 | u32 offset = i915_mmio_reg_offset(reg); |
3756685a TU |
1856 | enum forcewake_domains fw_domains; |
1857 | ||
895833bd TU |
1858 | if (HAS_FWTABLE(dev_priv)) { |
1859 | fw_domains = __fwtable_reg_read_fw_domains(offset); | |
1860 | } else if (INTEL_GEN(dev_priv) >= 6) { | |
1861 | fw_domains = __gen6_reg_read_fw_domains(offset); | |
1862 | } else { | |
1863 | WARN_ON(!IS_GEN(dev_priv, 2, 5)); | |
1864 | fw_domains = 0; | |
3756685a TU |
1865 | } |
1866 | ||
1867 | WARN_ON(fw_domains & ~dev_priv->uncore.fw_domains); | |
1868 | ||
1869 | return fw_domains; | |
1870 | } | |
1871 | ||
1872 | static enum forcewake_domains | |
1873 | intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv, | |
1874 | i915_reg_t reg) | |
1875 | { | |
22d48c55 | 1876 | u32 offset = i915_mmio_reg_offset(reg); |
3756685a TU |
1877 | enum forcewake_domains fw_domains; |
1878 | ||
22d48c55 TU |
1879 | if (HAS_FWTABLE(dev_priv) && !IS_VALLEYVIEW(dev_priv)) { |
1880 | fw_domains = __fwtable_reg_write_fw_domains(offset); | |
1881 | } else if (IS_GEN8(dev_priv)) { | |
1882 | fw_domains = __gen8_reg_write_fw_domains(offset); | |
1883 | } else if (IS_GEN(dev_priv, 6, 7)) { | |
3756685a | 1884 | fw_domains = FORCEWAKE_RENDER; |
22d48c55 TU |
1885 | } else { |
1886 | WARN_ON(!IS_GEN(dev_priv, 2, 5)); | |
1887 | fw_domains = 0; | |
3756685a TU |
1888 | } |
1889 | ||
1890 | WARN_ON(fw_domains & ~dev_priv->uncore.fw_domains); | |
1891 | ||
1892 | return fw_domains; | |
1893 | } | |
1894 | ||
1895 | /** | |
1896 | * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access | |
1897 | * a register | |
1898 | * @dev_priv: pointer to struct drm_i915_private | |
1899 | * @reg: register in question | |
1900 | * @op: operation bitmask of FW_REG_READ and/or FW_REG_WRITE | |
1901 | * | |
1902 | * Returns a set of forcewake domains required to be taken with for example | |
1903 | * intel_uncore_forcewake_get for the specified register to be accessible in the | |
1904 | * specified mode (read, write or read/write) with raw mmio accessors. | |
1905 | * | |
1906 | * NOTE: On Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the | |
1907 | * callers to do FIFO management on their own or risk losing writes. | |
1908 | */ | |
1909 | enum forcewake_domains | |
1910 | intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv, | |
1911 | i915_reg_t reg, unsigned int op) | |
1912 | { | |
1913 | enum forcewake_domains fw_domains = 0; | |
1914 | ||
1915 | WARN_ON(!op); | |
1916 | ||
895833bd TU |
1917 | if (intel_vgpu_active(dev_priv)) |
1918 | return 0; | |
1919 | ||
3756685a TU |
1920 | if (op & FW_REG_READ) |
1921 | fw_domains = intel_uncore_forcewake_for_read(dev_priv, reg); | |
1922 | ||
1923 | if (op & FW_REG_WRITE) | |
1924 | fw_domains |= intel_uncore_forcewake_for_write(dev_priv, reg); | |
1925 | ||
1926 | return fw_domains; | |
1927 | } |