Commit | Line | Data |
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907b28c5 CW |
1 | /* |
2 | * Copyright © 2013 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | */ | |
23 | ||
24 | #include "i915_drv.h" | |
25 | #include "intel_drv.h" | |
cf9d2890 | 26 | #include "i915_vgpu.h" |
907b28c5 | 27 | |
264ec1a8 | 28 | #include <asm/iosf_mbi.h> |
6daccb0b CW |
29 | #include <linux/pm_runtime.h> |
30 | ||
83e33372 | 31 | #define FORCEWAKE_ACK_TIMEOUT_MS 50 |
6b07b6d2 | 32 | #define GT_FIFO_TIMEOUT_MS 10 |
907b28c5 | 33 | |
6cc5ca76 | 34 | #define __raw_posting_read(...) ((void)__raw_uncore_read32(__VA_ARGS__)) |
6af5d92f | 35 | |
05a2fb15 MK |
36 | static const char * const forcewake_domain_names[] = { |
37 | "render", | |
38 | "blitter", | |
39 | "media", | |
a89a70a8 DCS |
40 | "vdbox0", |
41 | "vdbox1", | |
42 | "vdbox2", | |
43 | "vdbox3", | |
44 | "vebox0", | |
45 | "vebox1", | |
05a2fb15 MK |
46 | }; |
47 | ||
48 | const char * | |
48c1026a | 49 | intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id) |
05a2fb15 | 50 | { |
53abb679 | 51 | BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT); |
05a2fb15 MK |
52 | |
53 | if (id >= 0 && id < FW_DOMAIN_ID_COUNT) | |
54 | return forcewake_domain_names[id]; | |
55 | ||
56 | WARN_ON(id); | |
57 | ||
58 | return "unknown"; | |
59 | } | |
60 | ||
535d8d27 | 61 | #define fw_ack(d) readl((d)->reg_ack) |
159367bb DCS |
62 | #define fw_set(d, val) writel(_MASKED_BIT_ENABLE((val)), (d)->reg_set) |
63 | #define fw_clear(d, val) writel(_MASKED_BIT_DISABLE((val)), (d)->reg_set) | |
535d8d27 | 64 | |
05a2fb15 | 65 | static inline void |
159367bb | 66 | fw_domain_reset(const struct intel_uncore_forcewake_domain *d) |
907b28c5 | 67 | { |
26376a7e OM |
68 | /* |
69 | * We don't really know if the powerwell for the forcewake domain we are | |
70 | * trying to reset here does exist at this point (engines could be fused | |
71 | * off in ICL+), so no waiting for acks | |
72 | */ | |
159367bb DCS |
73 | /* WaRsClearFWBitsAtReset:bdw,skl */ |
74 | fw_clear(d, 0xffff); | |
907b28c5 CW |
75 | } |
76 | ||
05a2fb15 MK |
77 | static inline void |
78 | fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d) | |
907b28c5 | 79 | { |
a57a4a67 TU |
80 | d->wake_count++; |
81 | hrtimer_start_range_ns(&d->timer, | |
8b0e1953 | 82 | NSEC_PER_MSEC, |
a57a4a67 TU |
83 | NSEC_PER_MSEC, |
84 | HRTIMER_MODE_REL); | |
907b28c5 CW |
85 | } |
86 | ||
71306303 | 87 | static inline int |
535d8d27 | 88 | __wait_for_ack(const struct intel_uncore_forcewake_domain *d, |
71306303 MK |
89 | const u32 ack, |
90 | const u32 value) | |
91 | { | |
535d8d27 | 92 | return wait_for_atomic((fw_ack(d) & ack) == value, |
71306303 MK |
93 | FORCEWAKE_ACK_TIMEOUT_MS); |
94 | } | |
95 | ||
96 | static inline int | |
535d8d27 | 97 | wait_ack_clear(const struct intel_uncore_forcewake_domain *d, |
71306303 MK |
98 | const u32 ack) |
99 | { | |
535d8d27 | 100 | return __wait_for_ack(d, ack, 0); |
71306303 MK |
101 | } |
102 | ||
103 | static inline int | |
535d8d27 | 104 | wait_ack_set(const struct intel_uncore_forcewake_domain *d, |
71306303 MK |
105 | const u32 ack) |
106 | { | |
535d8d27 | 107 | return __wait_for_ack(d, ack, ack); |
71306303 MK |
108 | } |
109 | ||
05a2fb15 | 110 | static inline void |
535d8d27 | 111 | fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d) |
907b28c5 | 112 | { |
535d8d27 | 113 | if (wait_ack_clear(d, FORCEWAKE_KERNEL)) |
05a2fb15 MK |
114 | DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n", |
115 | intel_uncore_forcewake_domain_to_str(d->id)); | |
116 | } | |
907b28c5 | 117 | |
71306303 MK |
118 | enum ack_type { |
119 | ACK_CLEAR = 0, | |
120 | ACK_SET | |
121 | }; | |
122 | ||
123 | static int | |
535d8d27 | 124 | fw_domain_wait_ack_with_fallback(const struct intel_uncore_forcewake_domain *d, |
71306303 MK |
125 | const enum ack_type type) |
126 | { | |
127 | const u32 ack_bit = FORCEWAKE_KERNEL; | |
128 | const u32 value = type == ACK_SET ? ack_bit : 0; | |
129 | unsigned int pass; | |
130 | bool ack_detected; | |
131 | ||
132 | /* | |
133 | * There is a possibility of driver's wake request colliding | |
134 | * with hardware's own wake requests and that can cause | |
135 | * hardware to not deliver the driver's ack message. | |
136 | * | |
137 | * Use a fallback bit toggle to kick the gpu state machine | |
138 | * in the hope that the original ack will be delivered along with | |
139 | * the fallback ack. | |
140 | * | |
cc38cae7 OM |
141 | * This workaround is described in HSDES #1604254524 and it's known as: |
142 | * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl | |
143 | * although the name is a bit misleading. | |
71306303 MK |
144 | */ |
145 | ||
146 | pass = 1; | |
147 | do { | |
535d8d27 | 148 | wait_ack_clear(d, FORCEWAKE_KERNEL_FALLBACK); |
71306303 | 149 | |
159367bb | 150 | fw_set(d, FORCEWAKE_KERNEL_FALLBACK); |
71306303 MK |
151 | /* Give gt some time to relax before the polling frenzy */ |
152 | udelay(10 * pass); | |
535d8d27 | 153 | wait_ack_set(d, FORCEWAKE_KERNEL_FALLBACK); |
71306303 | 154 | |
535d8d27 | 155 | ack_detected = (fw_ack(d) & ack_bit) == value; |
71306303 | 156 | |
159367bb | 157 | fw_clear(d, FORCEWAKE_KERNEL_FALLBACK); |
71306303 MK |
158 | } while (!ack_detected && pass++ < 10); |
159 | ||
160 | DRM_DEBUG_DRIVER("%s had to use fallback to %s ack, 0x%x (passes %u)\n", | |
161 | intel_uncore_forcewake_domain_to_str(d->id), | |
162 | type == ACK_SET ? "set" : "clear", | |
535d8d27 | 163 | fw_ack(d), |
71306303 MK |
164 | pass); |
165 | ||
166 | return ack_detected ? 0 : -ETIMEDOUT; | |
167 | } | |
168 | ||
169 | static inline void | |
535d8d27 | 170 | fw_domain_wait_ack_clear_fallback(const struct intel_uncore_forcewake_domain *d) |
71306303 | 171 | { |
535d8d27 | 172 | if (likely(!wait_ack_clear(d, FORCEWAKE_KERNEL))) |
71306303 MK |
173 | return; |
174 | ||
535d8d27 DCS |
175 | if (fw_domain_wait_ack_with_fallback(d, ACK_CLEAR)) |
176 | fw_domain_wait_ack_clear(d); | |
71306303 MK |
177 | } |
178 | ||
05a2fb15 | 179 | static inline void |
159367bb | 180 | fw_domain_get(const struct intel_uncore_forcewake_domain *d) |
05a2fb15 | 181 | { |
159367bb | 182 | fw_set(d, FORCEWAKE_KERNEL); |
05a2fb15 | 183 | } |
907b28c5 | 184 | |
05a2fb15 | 185 | static inline void |
535d8d27 | 186 | fw_domain_wait_ack_set(const struct intel_uncore_forcewake_domain *d) |
05a2fb15 | 187 | { |
535d8d27 | 188 | if (wait_ack_set(d, FORCEWAKE_KERNEL)) |
05a2fb15 MK |
189 | DRM_ERROR("%s: timed out waiting for forcewake ack request.\n", |
190 | intel_uncore_forcewake_domain_to_str(d->id)); | |
191 | } | |
907b28c5 | 192 | |
71306303 | 193 | static inline void |
535d8d27 | 194 | fw_domain_wait_ack_set_fallback(const struct intel_uncore_forcewake_domain *d) |
71306303 | 195 | { |
535d8d27 | 196 | if (likely(!wait_ack_set(d, FORCEWAKE_KERNEL))) |
71306303 MK |
197 | return; |
198 | ||
535d8d27 DCS |
199 | if (fw_domain_wait_ack_with_fallback(d, ACK_SET)) |
200 | fw_domain_wait_ack_set(d); | |
71306303 MK |
201 | } |
202 | ||
05a2fb15 | 203 | static inline void |
159367bb | 204 | fw_domain_put(const struct intel_uncore_forcewake_domain *d) |
05a2fb15 | 205 | { |
159367bb | 206 | fw_clear(d, FORCEWAKE_KERNEL); |
907b28c5 CW |
207 | } |
208 | ||
05a2fb15 | 209 | static void |
f568eeee | 210 | fw_domains_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains) |
907b28c5 | 211 | { |
05a2fb15 | 212 | struct intel_uncore_forcewake_domain *d; |
d2dc94bc | 213 | unsigned int tmp; |
907b28c5 | 214 | |
535d8d27 | 215 | GEM_BUG_ON(fw_domains & ~uncore->fw_domains); |
d2dc94bc | 216 | |
f568eeee | 217 | for_each_fw_domain_masked(d, fw_domains, uncore, tmp) { |
535d8d27 | 218 | fw_domain_wait_ack_clear(d); |
159367bb | 219 | fw_domain_get(d); |
05a2fb15 | 220 | } |
4e1176dd | 221 | |
f568eeee | 222 | for_each_fw_domain_masked(d, fw_domains, uncore, tmp) |
535d8d27 | 223 | fw_domain_wait_ack_set(d); |
71306303 | 224 | |
535d8d27 | 225 | uncore->fw_domains_active |= fw_domains; |
71306303 MK |
226 | } |
227 | ||
228 | static void | |
f568eeee | 229 | fw_domains_get_with_fallback(struct intel_uncore *uncore, |
71306303 MK |
230 | enum forcewake_domains fw_domains) |
231 | { | |
232 | struct intel_uncore_forcewake_domain *d; | |
233 | unsigned int tmp; | |
234 | ||
535d8d27 | 235 | GEM_BUG_ON(fw_domains & ~uncore->fw_domains); |
71306303 | 236 | |
f568eeee | 237 | for_each_fw_domain_masked(d, fw_domains, uncore, tmp) { |
535d8d27 | 238 | fw_domain_wait_ack_clear_fallback(d); |
159367bb | 239 | fw_domain_get(d); |
71306303 MK |
240 | } |
241 | ||
f568eeee | 242 | for_each_fw_domain_masked(d, fw_domains, uncore, tmp) |
535d8d27 | 243 | fw_domain_wait_ack_set_fallback(d); |
b8473050 | 244 | |
535d8d27 | 245 | uncore->fw_domains_active |= fw_domains; |
05a2fb15 | 246 | } |
907b28c5 | 247 | |
05a2fb15 | 248 | static void |
f568eeee | 249 | fw_domains_put(struct intel_uncore *uncore, enum forcewake_domains fw_domains) |
05a2fb15 MK |
250 | { |
251 | struct intel_uncore_forcewake_domain *d; | |
d2dc94bc CW |
252 | unsigned int tmp; |
253 | ||
535d8d27 | 254 | GEM_BUG_ON(fw_domains & ~uncore->fw_domains); |
907b28c5 | 255 | |
f568eeee | 256 | for_each_fw_domain_masked(d, fw_domains, uncore, tmp) |
159367bb | 257 | fw_domain_put(d); |
b8473050 | 258 | |
535d8d27 | 259 | uncore->fw_domains_active &= ~fw_domains; |
05a2fb15 | 260 | } |
907b28c5 | 261 | |
05a2fb15 | 262 | static void |
f568eeee | 263 | fw_domains_reset(struct intel_uncore *uncore, |
577ac4bd | 264 | enum forcewake_domains fw_domains) |
05a2fb15 MK |
265 | { |
266 | struct intel_uncore_forcewake_domain *d; | |
d2dc94bc | 267 | unsigned int tmp; |
05a2fb15 | 268 | |
d2dc94bc | 269 | if (!fw_domains) |
3225b2f9 | 270 | return; |
f9b3927a | 271 | |
535d8d27 | 272 | GEM_BUG_ON(fw_domains & ~uncore->fw_domains); |
d2dc94bc | 273 | |
f568eeee | 274 | for_each_fw_domain_masked(d, fw_domains, uncore, tmp) |
159367bb | 275 | fw_domain_reset(d); |
05a2fb15 MK |
276 | } |
277 | ||
6ebc9692 | 278 | static inline u32 gt_thread_status(struct intel_uncore *uncore) |
a5b22b5e CW |
279 | { |
280 | u32 val; | |
281 | ||
6cc5ca76 | 282 | val = __raw_uncore_read32(uncore, GEN6_GT_THREAD_STATUS_REG); |
a5b22b5e CW |
283 | val &= GEN6_GT_THREAD_STATUS_CORE_MASK; |
284 | ||
285 | return val; | |
286 | } | |
287 | ||
6ebc9692 | 288 | static void __gen6_gt_wait_for_thread_c0(struct intel_uncore *uncore) |
05a2fb15 | 289 | { |
a5b22b5e CW |
290 | /* |
291 | * w/a for a sporadic read returning 0 by waiting for the GT | |
05a2fb15 MK |
292 | * thread to wake up. |
293 | */ | |
6ebc9692 | 294 | WARN_ONCE(wait_for_atomic_us(gt_thread_status(uncore) == 0, 5000), |
a5b22b5e | 295 | "GT thread status wait timed out\n"); |
05a2fb15 MK |
296 | } |
297 | ||
f568eeee | 298 | static void fw_domains_get_with_thread_status(struct intel_uncore *uncore, |
48c1026a | 299 | enum forcewake_domains fw_domains) |
05a2fb15 | 300 | { |
f568eeee | 301 | fw_domains_get(uncore, fw_domains); |
907b28c5 | 302 | |
05a2fb15 | 303 | /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */ |
6ebc9692 | 304 | __gen6_gt_wait_for_thread_c0(uncore); |
907b28c5 CW |
305 | } |
306 | ||
6ebc9692 | 307 | static inline u32 fifo_free_entries(struct intel_uncore *uncore) |
c32e3788 | 308 | { |
6cc5ca76 | 309 | u32 count = __raw_uncore_read32(uncore, GTFIFOCTL); |
c32e3788 DG |
310 | |
311 | return count & GT_FIFO_FREE_ENTRIES_MASK; | |
312 | } | |
313 | ||
6ebc9692 | 314 | static void __gen6_gt_wait_for_fifo(struct intel_uncore *uncore) |
907b28c5 | 315 | { |
6b07b6d2 | 316 | u32 n; |
907b28c5 | 317 | |
5135d64b D |
318 | /* On VLV, FIFO will be shared by both SW and HW. |
319 | * So, we need to read the FREE_ENTRIES everytime */ | |
6ebc9692 DCS |
320 | if (IS_VALLEYVIEW(uncore_to_i915(uncore))) |
321 | n = fifo_free_entries(uncore); | |
6b07b6d2 | 322 | else |
272c7e52 | 323 | n = uncore->fifo_count; |
6b07b6d2 MK |
324 | |
325 | if (n <= GT_FIFO_NUM_RESERVED_ENTRIES) { | |
6ebc9692 | 326 | if (wait_for_atomic((n = fifo_free_entries(uncore)) > |
6b07b6d2 MK |
327 | GT_FIFO_NUM_RESERVED_ENTRIES, |
328 | GT_FIFO_TIMEOUT_MS)) { | |
329 | DRM_DEBUG("GT_FIFO timeout, entries: %u\n", n); | |
330 | return; | |
907b28c5 | 331 | } |
907b28c5 | 332 | } |
907b28c5 | 333 | |
272c7e52 | 334 | uncore->fifo_count = n - 1; |
907b28c5 CW |
335 | } |
336 | ||
a57a4a67 TU |
337 | static enum hrtimer_restart |
338 | intel_uncore_fw_release_timer(struct hrtimer *timer) | |
38cff0b1 | 339 | { |
a57a4a67 TU |
340 | struct intel_uncore_forcewake_domain *domain = |
341 | container_of(timer, struct intel_uncore_forcewake_domain, timer); | |
f568eeee | 342 | struct intel_uncore *uncore = forcewake_domain_to_uncore(domain); |
b2cff0db | 343 | unsigned long irqflags; |
38cff0b1 | 344 | |
eb17af67 | 345 | assert_rpm_device_not_suspended(uncore->rpm); |
38cff0b1 | 346 | |
c9e0c6da CW |
347 | if (xchg(&domain->active, false)) |
348 | return HRTIMER_RESTART; | |
349 | ||
f568eeee | 350 | spin_lock_irqsave(&uncore->lock, irqflags); |
b2cff0db CW |
351 | if (WARN_ON(domain->wake_count == 0)) |
352 | domain->wake_count++; | |
353 | ||
b8473050 | 354 | if (--domain->wake_count == 0) |
f568eeee | 355 | uncore->funcs.force_wake_put(uncore, domain->mask); |
b2cff0db | 356 | |
f568eeee | 357 | spin_unlock_irqrestore(&uncore->lock, irqflags); |
a57a4a67 TU |
358 | |
359 | return HRTIMER_NORESTART; | |
38cff0b1 ZW |
360 | } |
361 | ||
a5266db4 | 362 | /* Note callers must have acquired the PUNIT->PMIC bus, before calling this. */ |
d60996ab | 363 | static unsigned int |
f568eeee | 364 | intel_uncore_forcewake_reset(struct intel_uncore *uncore) |
38cff0b1 | 365 | { |
48c1026a | 366 | unsigned long irqflags; |
b2cff0db | 367 | struct intel_uncore_forcewake_domain *domain; |
48c1026a | 368 | int retry_count = 100; |
003342a5 | 369 | enum forcewake_domains fw, active_domains; |
38cff0b1 | 370 | |
a5266db4 HG |
371 | iosf_mbi_assert_punit_acquired(); |
372 | ||
b2cff0db CW |
373 | /* Hold uncore.lock across reset to prevent any register access |
374 | * with forcewake not set correctly. Wait until all pending | |
375 | * timers are run before holding. | |
376 | */ | |
377 | while (1) { | |
d2dc94bc CW |
378 | unsigned int tmp; |
379 | ||
b2cff0db | 380 | active_domains = 0; |
38cff0b1 | 381 | |
f568eeee | 382 | for_each_fw_domain(domain, uncore, tmp) { |
c9e0c6da | 383 | smp_store_mb(domain->active, false); |
a57a4a67 | 384 | if (hrtimer_cancel(&domain->timer) == 0) |
b2cff0db | 385 | continue; |
38cff0b1 | 386 | |
a57a4a67 | 387 | intel_uncore_fw_release_timer(&domain->timer); |
b2cff0db | 388 | } |
aec347ab | 389 | |
f568eeee | 390 | spin_lock_irqsave(&uncore->lock, irqflags); |
b2ec142c | 391 | |
f568eeee | 392 | for_each_fw_domain(domain, uncore, tmp) { |
a57a4a67 | 393 | if (hrtimer_active(&domain->timer)) |
33c582c1 | 394 | active_domains |= domain->mask; |
b2cff0db | 395 | } |
3123fcaf | 396 | |
b2cff0db CW |
397 | if (active_domains == 0) |
398 | break; | |
aec347ab | 399 | |
b2cff0db CW |
400 | if (--retry_count == 0) { |
401 | DRM_ERROR("Timed out waiting for forcewake timers to finish\n"); | |
402 | break; | |
403 | } | |
0294ae7b | 404 | |
f568eeee | 405 | spin_unlock_irqrestore(&uncore->lock, irqflags); |
b2cff0db CW |
406 | cond_resched(); |
407 | } | |
0294ae7b | 408 | |
b2cff0db CW |
409 | WARN_ON(active_domains); |
410 | ||
f568eeee | 411 | fw = uncore->fw_domains_active; |
b2cff0db | 412 | if (fw) |
f568eeee | 413 | uncore->funcs.force_wake_put(uncore, fw); |
ef46e0d2 | 414 | |
f568eeee DCS |
415 | fw_domains_reset(uncore, uncore->fw_domains); |
416 | assert_forcewakes_inactive(uncore); | |
b2cff0db | 417 | |
f568eeee | 418 | spin_unlock_irqrestore(&uncore->lock, irqflags); |
d60996ab CW |
419 | |
420 | return fw; /* track the lost user forcewake domains */ | |
ef46e0d2 DV |
421 | } |
422 | ||
8a47eb19 | 423 | static bool |
6ebc9692 | 424 | fpga_check_for_unclaimed_mmio(struct intel_uncore *uncore) |
8a47eb19 MK |
425 | { |
426 | u32 dbg; | |
427 | ||
6cc5ca76 | 428 | dbg = __raw_uncore_read32(uncore, FPGA_DBG); |
8a47eb19 MK |
429 | if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM))) |
430 | return false; | |
431 | ||
6cc5ca76 | 432 | __raw_uncore_write32(uncore, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
8a47eb19 MK |
433 | |
434 | return true; | |
435 | } | |
436 | ||
8ac3e1bb | 437 | static bool |
6ebc9692 | 438 | vlv_check_for_unclaimed_mmio(struct intel_uncore *uncore) |
8ac3e1bb MK |
439 | { |
440 | u32 cer; | |
441 | ||
6cc5ca76 | 442 | cer = __raw_uncore_read32(uncore, CLAIM_ER); |
8ac3e1bb MK |
443 | if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK)))) |
444 | return false; | |
445 | ||
6cc5ca76 | 446 | __raw_uncore_write32(uncore, CLAIM_ER, CLAIM_ER_CLR); |
8ac3e1bb MK |
447 | |
448 | return true; | |
449 | } | |
450 | ||
a338908c | 451 | static bool |
6ebc9692 | 452 | gen6_check_for_fifo_debug(struct intel_uncore *uncore) |
a338908c MK |
453 | { |
454 | u32 fifodbg; | |
455 | ||
6cc5ca76 | 456 | fifodbg = __raw_uncore_read32(uncore, GTFIFODBG); |
a338908c MK |
457 | |
458 | if (unlikely(fifodbg)) { | |
459 | DRM_DEBUG_DRIVER("GTFIFODBG = 0x08%x\n", fifodbg); | |
6cc5ca76 | 460 | __raw_uncore_write32(uncore, GTFIFODBG, fifodbg); |
a338908c MK |
461 | } |
462 | ||
463 | return fifodbg; | |
464 | } | |
465 | ||
8ac3e1bb | 466 | static bool |
2cf7bf6f | 467 | check_for_unclaimed_mmio(struct intel_uncore *uncore) |
8ac3e1bb | 468 | { |
a338908c MK |
469 | bool ret = false; |
470 | ||
2cf7bf6f | 471 | if (intel_uncore_has_fpga_dbg_unclaimed(uncore)) |
6ebc9692 | 472 | ret |= fpga_check_for_unclaimed_mmio(uncore); |
8ac3e1bb | 473 | |
2cf7bf6f | 474 | if (intel_uncore_has_dbg_unclaimed(uncore)) |
6ebc9692 | 475 | ret |= vlv_check_for_unclaimed_mmio(uncore); |
a338908c | 476 | |
2cf7bf6f | 477 | if (intel_uncore_has_fifo(uncore)) |
6ebc9692 | 478 | ret |= gen6_check_for_fifo_debug(uncore); |
8ac3e1bb | 479 | |
a338908c | 480 | return ret; |
8ac3e1bb MK |
481 | } |
482 | ||
f7de5027 | 483 | static void __intel_uncore_early_sanitize(struct intel_uncore *uncore, |
d60996ab | 484 | unsigned int restore_forcewake) |
f9b3927a | 485 | { |
8a47eb19 | 486 | /* clear out unclaimed reg detection bit */ |
2cf7bf6f | 487 | if (check_for_unclaimed_mmio(uncore)) |
8a47eb19 | 488 | DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n"); |
907b28c5 | 489 | |
a04f90a3 | 490 | /* WaDisableShadowRegForCpd:chv */ |
2cf7bf6f | 491 | if (IS_CHERRYVIEW(uncore_to_i915(uncore))) { |
6cc5ca76 DCS |
492 | __raw_uncore_write32(uncore, GTFIFOCTL, |
493 | __raw_uncore_read32(uncore, GTFIFOCTL) | | |
494 | GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL | | |
495 | GT_FIFO_CTL_RC6_POLICY_STALL); | |
a04f90a3 D |
496 | } |
497 | ||
a5266db4 | 498 | iosf_mbi_punit_acquire(); |
f7de5027 | 499 | intel_uncore_forcewake_reset(uncore); |
d60996ab | 500 | if (restore_forcewake) { |
f7de5027 DCS |
501 | spin_lock_irq(&uncore->lock); |
502 | uncore->funcs.force_wake_get(uncore, restore_forcewake); | |
503 | ||
2cf7bf6f | 504 | if (intel_uncore_has_fifo(uncore)) |
6ebc9692 | 505 | uncore->fifo_count = fifo_free_entries(uncore); |
f7de5027 | 506 | spin_unlock_irq(&uncore->lock); |
d60996ab | 507 | } |
a5266db4 | 508 | iosf_mbi_punit_release(); |
521198a2 MK |
509 | } |
510 | ||
f7de5027 | 511 | void intel_uncore_suspend(struct intel_uncore *uncore) |
ed493883 | 512 | { |
a5266db4 HG |
513 | iosf_mbi_punit_acquire(); |
514 | iosf_mbi_unregister_pmic_bus_access_notifier_unlocked( | |
f7de5027 DCS |
515 | &uncore->pmic_bus_access_nb); |
516 | uncore->fw_domains_saved = intel_uncore_forcewake_reset(uncore); | |
a5266db4 | 517 | iosf_mbi_punit_release(); |
68f60946 HG |
518 | } |
519 | ||
f7de5027 | 520 | void intel_uncore_resume_early(struct intel_uncore *uncore) |
68f60946 | 521 | { |
d60996ab CW |
522 | unsigned int restore_forcewake; |
523 | ||
f7de5027 DCS |
524 | restore_forcewake = fetch_and_zero(&uncore->fw_domains_saved); |
525 | __intel_uncore_early_sanitize(uncore, restore_forcewake); | |
d60996ab | 526 | |
f7de5027 | 527 | iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb); |
ed493883 ID |
528 | } |
529 | ||
f7de5027 | 530 | void intel_uncore_runtime_resume(struct intel_uncore *uncore) |
bedf4d79 | 531 | { |
f7de5027 | 532 | iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb); |
bedf4d79 HG |
533 | } |
534 | ||
dc97997a | 535 | void intel_uncore_sanitize(struct drm_i915_private *dev_priv) |
521198a2 | 536 | { |
907b28c5 | 537 | /* BIOS often leaves RC6 enabled, but disable it for hw init */ |
54b4f68f | 538 | intel_sanitize_gt_powersave(dev_priv); |
907b28c5 CW |
539 | } |
540 | ||
f568eeee | 541 | static void __intel_uncore_forcewake_get(struct intel_uncore *uncore, |
a6111f7b CW |
542 | enum forcewake_domains fw_domains) |
543 | { | |
544 | struct intel_uncore_forcewake_domain *domain; | |
d2dc94bc | 545 | unsigned int tmp; |
a6111f7b | 546 | |
f568eeee | 547 | fw_domains &= uncore->fw_domains; |
a6111f7b | 548 | |
f568eeee | 549 | for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) { |
c9e0c6da | 550 | if (domain->wake_count++) { |
33c582c1 | 551 | fw_domains &= ~domain->mask; |
c9e0c6da CW |
552 | domain->active = true; |
553 | } | |
554 | } | |
a6111f7b | 555 | |
b8473050 | 556 | if (fw_domains) |
f568eeee | 557 | uncore->funcs.force_wake_get(uncore, fw_domains); |
a6111f7b CW |
558 | } |
559 | ||
59bad947 MK |
560 | /** |
561 | * intel_uncore_forcewake_get - grab forcewake domain references | |
3ceea6a1 | 562 | * @uncore: the intel_uncore structure |
59bad947 MK |
563 | * @fw_domains: forcewake domains to get reference on |
564 | * | |
565 | * This function can be used get GT's forcewake domain references. | |
566 | * Normal register access will handle the forcewake domains automatically. | |
567 | * However if some sequence requires the GT to not power down a particular | |
568 | * forcewake domains this function should be called at the beginning of the | |
569 | * sequence. And subsequently the reference should be dropped by symmetric | |
570 | * call to intel_unforce_forcewake_put(). Usually caller wants all the domains | |
571 | * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL. | |
907b28c5 | 572 | */ |
3ceea6a1 | 573 | void intel_uncore_forcewake_get(struct intel_uncore *uncore, |
48c1026a | 574 | enum forcewake_domains fw_domains) |
907b28c5 CW |
575 | { |
576 | unsigned long irqflags; | |
577 | ||
f568eeee | 578 | if (!uncore->funcs.force_wake_get) |
ab484f8f BW |
579 | return; |
580 | ||
eb17af67 | 581 | __assert_rpm_wakelock_held(uncore->rpm); |
c8c8fb33 | 582 | |
f568eeee DCS |
583 | spin_lock_irqsave(&uncore->lock, irqflags); |
584 | __intel_uncore_forcewake_get(uncore, fw_domains); | |
585 | spin_unlock_irqrestore(&uncore->lock, irqflags); | |
907b28c5 CW |
586 | } |
587 | ||
d7a133d8 CW |
588 | /** |
589 | * intel_uncore_forcewake_user_get - claim forcewake on behalf of userspace | |
3ceea6a1 | 590 | * @uncore: the intel_uncore structure |
d7a133d8 CW |
591 | * |
592 | * This function is a wrapper around intel_uncore_forcewake_get() to acquire | |
593 | * the GT powerwell and in the process disable our debugging for the | |
594 | * duration of userspace's bypass. | |
595 | */ | |
3ceea6a1 | 596 | void intel_uncore_forcewake_user_get(struct intel_uncore *uncore) |
d7a133d8 | 597 | { |
f568eeee DCS |
598 | spin_lock_irq(&uncore->lock); |
599 | if (!uncore->user_forcewake.count++) { | |
3ceea6a1 | 600 | intel_uncore_forcewake_get__locked(uncore, FORCEWAKE_ALL); |
d7a133d8 CW |
601 | |
602 | /* Save and disable mmio debugging for the user bypass */ | |
f568eeee DCS |
603 | uncore->user_forcewake.saved_mmio_check = |
604 | uncore->unclaimed_mmio_check; | |
605 | uncore->user_forcewake.saved_mmio_debug = | |
4f044a88 | 606 | i915_modparams.mmio_debug; |
d7a133d8 | 607 | |
f568eeee | 608 | uncore->unclaimed_mmio_check = 0; |
4f044a88 | 609 | i915_modparams.mmio_debug = 0; |
d7a133d8 | 610 | } |
f568eeee | 611 | spin_unlock_irq(&uncore->lock); |
d7a133d8 CW |
612 | } |
613 | ||
614 | /** | |
615 | * intel_uncore_forcewake_user_put - release forcewake on behalf of userspace | |
3ceea6a1 | 616 | * @uncore: the intel_uncore structure |
d7a133d8 CW |
617 | * |
618 | * This function complements intel_uncore_forcewake_user_get() and releases | |
619 | * the GT powerwell taken on behalf of the userspace bypass. | |
620 | */ | |
3ceea6a1 | 621 | void intel_uncore_forcewake_user_put(struct intel_uncore *uncore) |
d7a133d8 | 622 | { |
f568eeee DCS |
623 | spin_lock_irq(&uncore->lock); |
624 | if (!--uncore->user_forcewake.count) { | |
2cf7bf6f DCS |
625 | if (intel_uncore_unclaimed_mmio(uncore)) |
626 | dev_info(uncore_to_i915(uncore)->drm.dev, | |
d7a133d8 CW |
627 | "Invalid mmio detected during user access\n"); |
628 | ||
f568eeee DCS |
629 | uncore->unclaimed_mmio_check = |
630 | uncore->user_forcewake.saved_mmio_check; | |
4f044a88 | 631 | i915_modparams.mmio_debug = |
f568eeee | 632 | uncore->user_forcewake.saved_mmio_debug; |
d7a133d8 | 633 | |
3ceea6a1 | 634 | intel_uncore_forcewake_put__locked(uncore, FORCEWAKE_ALL); |
d7a133d8 | 635 | } |
f568eeee | 636 | spin_unlock_irq(&uncore->lock); |
d7a133d8 CW |
637 | } |
638 | ||
59bad947 | 639 | /** |
a6111f7b | 640 | * intel_uncore_forcewake_get__locked - grab forcewake domain references |
3ceea6a1 | 641 | * @uncore: the intel_uncore structure |
a6111f7b | 642 | * @fw_domains: forcewake domains to get reference on |
59bad947 | 643 | * |
a6111f7b CW |
644 | * See intel_uncore_forcewake_get(). This variant places the onus |
645 | * on the caller to explicitly handle the dev_priv->uncore.lock spinlock. | |
907b28c5 | 646 | */ |
3ceea6a1 | 647 | void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore, |
a6111f7b CW |
648 | enum forcewake_domains fw_domains) |
649 | { | |
f568eeee DCS |
650 | lockdep_assert_held(&uncore->lock); |
651 | ||
652 | if (!uncore->funcs.force_wake_get) | |
a6111f7b CW |
653 | return; |
654 | ||
f568eeee | 655 | __intel_uncore_forcewake_get(uncore, fw_domains); |
a6111f7b CW |
656 | } |
657 | ||
f568eeee | 658 | static void __intel_uncore_forcewake_put(struct intel_uncore *uncore, |
a6111f7b | 659 | enum forcewake_domains fw_domains) |
907b28c5 | 660 | { |
b2cff0db | 661 | struct intel_uncore_forcewake_domain *domain; |
d2dc94bc | 662 | unsigned int tmp; |
907b28c5 | 663 | |
f568eeee | 664 | fw_domains &= uncore->fw_domains; |
b2cff0db | 665 | |
f568eeee | 666 | for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) { |
b2cff0db CW |
667 | if (WARN_ON(domain->wake_count == 0)) |
668 | continue; | |
669 | ||
c9e0c6da CW |
670 | if (--domain->wake_count) { |
671 | domain->active = true; | |
b2cff0db | 672 | continue; |
c9e0c6da | 673 | } |
b2cff0db | 674 | |
05a2fb15 | 675 | fw_domain_arm_timer(domain); |
aec347ab | 676 | } |
a6111f7b | 677 | } |
dc9fb09c | 678 | |
a6111f7b CW |
679 | /** |
680 | * intel_uncore_forcewake_put - release a forcewake domain reference | |
3ceea6a1 | 681 | * @uncore: the intel_uncore structure |
a6111f7b CW |
682 | * @fw_domains: forcewake domains to put references |
683 | * | |
684 | * This function drops the device-level forcewakes for specified | |
685 | * domains obtained by intel_uncore_forcewake_get(). | |
686 | */ | |
3ceea6a1 | 687 | void intel_uncore_forcewake_put(struct intel_uncore *uncore, |
a6111f7b CW |
688 | enum forcewake_domains fw_domains) |
689 | { | |
690 | unsigned long irqflags; | |
691 | ||
f568eeee | 692 | if (!uncore->funcs.force_wake_put) |
a6111f7b CW |
693 | return; |
694 | ||
f568eeee DCS |
695 | spin_lock_irqsave(&uncore->lock, irqflags); |
696 | __intel_uncore_forcewake_put(uncore, fw_domains); | |
697 | spin_unlock_irqrestore(&uncore->lock, irqflags); | |
907b28c5 CW |
698 | } |
699 | ||
a6111f7b CW |
700 | /** |
701 | * intel_uncore_forcewake_put__locked - grab forcewake domain references | |
3ceea6a1 | 702 | * @uncore: the intel_uncore structure |
a6111f7b CW |
703 | * @fw_domains: forcewake domains to get reference on |
704 | * | |
705 | * See intel_uncore_forcewake_put(). This variant places the onus | |
706 | * on the caller to explicitly handle the dev_priv->uncore.lock spinlock. | |
707 | */ | |
3ceea6a1 | 708 | void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore, |
a6111f7b CW |
709 | enum forcewake_domains fw_domains) |
710 | { | |
f568eeee DCS |
711 | lockdep_assert_held(&uncore->lock); |
712 | ||
713 | if (!uncore->funcs.force_wake_put) | |
a6111f7b CW |
714 | return; |
715 | ||
f568eeee | 716 | __intel_uncore_forcewake_put(uncore, fw_domains); |
a6111f7b CW |
717 | } |
718 | ||
f568eeee | 719 | void assert_forcewakes_inactive(struct intel_uncore *uncore) |
e998c40f | 720 | { |
f568eeee | 721 | if (!uncore->funcs.force_wake_get) |
e998c40f PZ |
722 | return; |
723 | ||
f568eeee | 724 | WARN(uncore->fw_domains_active, |
67e64564 | 725 | "Expected all fw_domains to be inactive, but %08x are still on\n", |
f568eeee | 726 | uncore->fw_domains_active); |
67e64564 CW |
727 | } |
728 | ||
f568eeee | 729 | void assert_forcewakes_active(struct intel_uncore *uncore, |
67e64564 CW |
730 | enum forcewake_domains fw_domains) |
731 | { | |
f568eeee | 732 | if (!uncore->funcs.force_wake_get) |
67e64564 CW |
733 | return; |
734 | ||
eb17af67 | 735 | __assert_rpm_wakelock_held(uncore->rpm); |
67e64564 | 736 | |
f568eeee DCS |
737 | fw_domains &= uncore->fw_domains; |
738 | WARN(fw_domains & ~uncore->fw_domains_active, | |
67e64564 | 739 | "Expected %08x fw_domains to be active, but %08x are off\n", |
f568eeee | 740 | fw_domains, fw_domains & ~uncore->fw_domains_active); |
e998c40f PZ |
741 | } |
742 | ||
907b28c5 | 743 | /* We give fast paths for the really cool registers */ |
40181697 | 744 | #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000) |
907b28c5 | 745 | |
a89a70a8 DCS |
746 | #define GEN11_NEEDS_FORCE_WAKE(reg) \ |
747 | ((reg) < 0x40000 || ((reg) >= 0x1c0000 && (reg) < 0x1dc000)) | |
748 | ||
272c7e52 | 749 | #define __gen6_reg_read_fw_domains(uncore, offset) \ |
6863b76c TU |
750 | ({ \ |
751 | enum forcewake_domains __fwd; \ | |
752 | if (NEEDS_FORCE_WAKE(offset)) \ | |
753 | __fwd = FORCEWAKE_RENDER; \ | |
754 | else \ | |
755 | __fwd = 0; \ | |
756 | __fwd; \ | |
757 | }) | |
758 | ||
9480dbf0 | 759 | static int fw_range_cmp(u32 offset, const struct intel_forcewake_range *entry) |
91e630b9 | 760 | { |
91e630b9 TU |
761 | if (offset < entry->start) |
762 | return -1; | |
763 | else if (offset > entry->end) | |
764 | return 1; | |
765 | else | |
766 | return 0; | |
767 | } | |
768 | ||
9480dbf0 TU |
769 | /* Copied and "macroized" from lib/bsearch.c */ |
770 | #define BSEARCH(key, base, num, cmp) ({ \ | |
771 | unsigned int start__ = 0, end__ = (num); \ | |
772 | typeof(base) result__ = NULL; \ | |
773 | while (start__ < end__) { \ | |
774 | unsigned int mid__ = start__ + (end__ - start__) / 2; \ | |
775 | int ret__ = (cmp)((key), (base) + mid__); \ | |
776 | if (ret__ < 0) { \ | |
777 | end__ = mid__; \ | |
778 | } else if (ret__ > 0) { \ | |
779 | start__ = mid__ + 1; \ | |
780 | } else { \ | |
781 | result__ = (base) + mid__; \ | |
782 | break; \ | |
783 | } \ | |
784 | } \ | |
785 | result__; \ | |
786 | }) | |
787 | ||
9fc1117c | 788 | static enum forcewake_domains |
cb7ee690 | 789 | find_fw_domain(struct intel_uncore *uncore, u32 offset) |
9fc1117c | 790 | { |
9480dbf0 | 791 | const struct intel_forcewake_range *entry; |
9fc1117c | 792 | |
9480dbf0 | 793 | entry = BSEARCH(offset, |
cb7ee690 DCS |
794 | uncore->fw_domains_table, |
795 | uncore->fw_domains_table_entries, | |
91e630b9 | 796 | fw_range_cmp); |
38fb6a40 | 797 | |
99191427 JL |
798 | if (!entry) |
799 | return 0; | |
800 | ||
a89a70a8 DCS |
801 | /* |
802 | * The list of FW domains depends on the SKU in gen11+ so we | |
803 | * can't determine it statically. We use FORCEWAKE_ALL and | |
804 | * translate it here to the list of available domains. | |
805 | */ | |
806 | if (entry->domains == FORCEWAKE_ALL) | |
cb7ee690 | 807 | return uncore->fw_domains; |
a89a70a8 | 808 | |
cb7ee690 | 809 | WARN(entry->domains & ~uncore->fw_domains, |
99191427 | 810 | "Uninitialized forcewake domain(s) 0x%x accessed at 0x%x\n", |
cb7ee690 | 811 | entry->domains & ~uncore->fw_domains, offset); |
99191427 JL |
812 | |
813 | return entry->domains; | |
9fc1117c TU |
814 | } |
815 | ||
816 | #define GEN_FW_RANGE(s, e, d) \ | |
817 | { .start = (s), .end = (e), .domains = (d) } | |
1938e59a | 818 | |
895833bd | 819 | #define HAS_FWTABLE(dev_priv) \ |
3d16ca58 | 820 | (INTEL_GEN(dev_priv) >= 9 || \ |
895833bd TU |
821 | IS_CHERRYVIEW(dev_priv) || \ |
822 | IS_VALLEYVIEW(dev_priv)) | |
823 | ||
b0081239 | 824 | /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */ |
9fc1117c TU |
825 | static const struct intel_forcewake_range __vlv_fw_ranges[] = { |
826 | GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER), | |
827 | GEN_FW_RANGE(0x5000, 0x7fff, FORCEWAKE_RENDER), | |
828 | GEN_FW_RANGE(0xb000, 0x11fff, FORCEWAKE_RENDER), | |
9fc1117c TU |
829 | GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA), |
830 | GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_MEDIA), | |
b0081239 | 831 | GEN_FW_RANGE(0x2e000, 0x2ffff, FORCEWAKE_RENDER), |
9fc1117c TU |
832 | GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA), |
833 | }; | |
1938e59a | 834 | |
272c7e52 | 835 | #define __fwtable_reg_read_fw_domains(uncore, offset) \ |
6863b76c TU |
836 | ({ \ |
837 | enum forcewake_domains __fwd = 0; \ | |
0dd356bb | 838 | if (NEEDS_FORCE_WAKE((offset))) \ |
272c7e52 | 839 | __fwd = find_fw_domain(uncore, offset); \ |
6863b76c TU |
840 | __fwd; \ |
841 | }) | |
842 | ||
272c7e52 | 843 | #define __gen11_fwtable_reg_read_fw_domains(uncore, offset) \ |
a89a70a8 DCS |
844 | ({ \ |
845 | enum forcewake_domains __fwd = 0; \ | |
846 | if (GEN11_NEEDS_FORCE_WAKE((offset))) \ | |
272c7e52 | 847 | __fwd = find_fw_domain(uncore, offset); \ |
a89a70a8 DCS |
848 | __fwd; \ |
849 | }) | |
850 | ||
47188574 | 851 | /* *Must* be sorted by offset! See intel_shadow_table_check(). */ |
6863b76c | 852 | static const i915_reg_t gen8_shadowed_regs[] = { |
47188574 TU |
853 | RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */ |
854 | GEN6_RPNSWREQ, /* 0xA008 */ | |
855 | GEN6_RC_VIDEO_FREQ, /* 0xA00C */ | |
856 | RING_TAIL(GEN6_BSD_RING_BASE), /* 0x12000 (base) */ | |
857 | RING_TAIL(VEBOX_RING_BASE), /* 0x1a000 (base) */ | |
858 | RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */ | |
6863b76c TU |
859 | /* TODO: Other registers are not yet used */ |
860 | }; | |
861 | ||
a89a70a8 DCS |
862 | static const i915_reg_t gen11_shadowed_regs[] = { |
863 | RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */ | |
864 | GEN6_RPNSWREQ, /* 0xA008 */ | |
865 | GEN6_RC_VIDEO_FREQ, /* 0xA00C */ | |
866 | RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */ | |
867 | RING_TAIL(GEN11_BSD_RING_BASE), /* 0x1C0000 (base) */ | |
868 | RING_TAIL(GEN11_BSD2_RING_BASE), /* 0x1C4000 (base) */ | |
869 | RING_TAIL(GEN11_VEBOX_RING_BASE), /* 0x1C8000 (base) */ | |
870 | RING_TAIL(GEN11_BSD3_RING_BASE), /* 0x1D0000 (base) */ | |
871 | RING_TAIL(GEN11_BSD4_RING_BASE), /* 0x1D4000 (base) */ | |
872 | RING_TAIL(GEN11_VEBOX2_RING_BASE), /* 0x1D8000 (base) */ | |
873 | /* TODO: Other registers are not yet used */ | |
874 | }; | |
875 | ||
9480dbf0 | 876 | static int mmio_reg_cmp(u32 key, const i915_reg_t *reg) |
5a659383 | 877 | { |
9480dbf0 | 878 | u32 offset = i915_mmio_reg_offset(*reg); |
5a659383 | 879 | |
9480dbf0 | 880 | if (key < offset) |
5a659383 | 881 | return -1; |
9480dbf0 | 882 | else if (key > offset) |
5a659383 TU |
883 | return 1; |
884 | else | |
885 | return 0; | |
886 | } | |
887 | ||
a89a70a8 DCS |
888 | #define __is_genX_shadowed(x) \ |
889 | static bool is_gen##x##_shadowed(u32 offset) \ | |
890 | { \ | |
891 | const i915_reg_t *regs = gen##x##_shadowed_regs; \ | |
892 | return BSEARCH(offset, regs, ARRAY_SIZE(gen##x##_shadowed_regs), \ | |
893 | mmio_reg_cmp); \ | |
6863b76c TU |
894 | } |
895 | ||
a89a70a8 DCS |
896 | __is_genX_shadowed(8) |
897 | __is_genX_shadowed(11) | |
898 | ||
272c7e52 | 899 | #define __gen8_reg_write_fw_domains(uncore, offset) \ |
6863b76c TU |
900 | ({ \ |
901 | enum forcewake_domains __fwd; \ | |
902 | if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(offset)) \ | |
903 | __fwd = FORCEWAKE_RENDER; \ | |
904 | else \ | |
905 | __fwd = 0; \ | |
906 | __fwd; \ | |
907 | }) | |
908 | ||
b0081239 | 909 | /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */ |
9fc1117c TU |
910 | static const struct intel_forcewake_range __chv_fw_ranges[] = { |
911 | GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER), | |
b0081239 | 912 | GEN_FW_RANGE(0x4000, 0x4fff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), |
9fc1117c | 913 | GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), |
b0081239 | 914 | GEN_FW_RANGE(0x8000, 0x82ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), |
9fc1117c | 915 | GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), |
b0081239 | 916 | GEN_FW_RANGE(0x8500, 0x85ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), |
9fc1117c | 917 | GEN_FW_RANGE(0x8800, 0x88ff, FORCEWAKE_MEDIA), |
b0081239 TU |
918 | GEN_FW_RANGE(0x9000, 0xafff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), |
919 | GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER), | |
9fc1117c | 920 | GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA), |
b0081239 TU |
921 | GEN_FW_RANGE(0xe000, 0xe7ff, FORCEWAKE_RENDER), |
922 | GEN_FW_RANGE(0xf000, 0xffff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), | |
9fc1117c TU |
923 | GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA), |
924 | GEN_FW_RANGE(0x1a000, 0x1bfff, FORCEWAKE_MEDIA), | |
925 | GEN_FW_RANGE(0x1e800, 0x1e9ff, FORCEWAKE_MEDIA), | |
926 | GEN_FW_RANGE(0x30000, 0x37fff, FORCEWAKE_MEDIA), | |
9fc1117c | 927 | }; |
38fb6a40 | 928 | |
272c7e52 | 929 | #define __fwtable_reg_write_fw_domains(uncore, offset) \ |
6863b76c TU |
930 | ({ \ |
931 | enum forcewake_domains __fwd = 0; \ | |
0dd356bb | 932 | if (NEEDS_FORCE_WAKE((offset)) && !is_gen8_shadowed(offset)) \ |
272c7e52 | 933 | __fwd = find_fw_domain(uncore, offset); \ |
6863b76c TU |
934 | __fwd; \ |
935 | }) | |
936 | ||
272c7e52 | 937 | #define __gen11_fwtable_reg_write_fw_domains(uncore, offset) \ |
a89a70a8 DCS |
938 | ({ \ |
939 | enum forcewake_domains __fwd = 0; \ | |
940 | if (GEN11_NEEDS_FORCE_WAKE((offset)) && !is_gen11_shadowed(offset)) \ | |
272c7e52 | 941 | __fwd = find_fw_domain(uncore, offset); \ |
a89a70a8 DCS |
942 | __fwd; \ |
943 | }) | |
944 | ||
b0081239 | 945 | /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */ |
9fc1117c | 946 | static const struct intel_forcewake_range __gen9_fw_ranges[] = { |
0dd356bb | 947 | GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER), |
9fc1117c TU |
948 | GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */ |
949 | GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), | |
0dd356bb | 950 | GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER), |
9fc1117c | 951 | GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER), |
0dd356bb | 952 | GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER), |
9fc1117c | 953 | GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), |
0dd356bb | 954 | GEN_FW_RANGE(0x8000, 0x812f, FORCEWAKE_BLITTER), |
b0081239 | 955 | GEN_FW_RANGE(0x8130, 0x813f, FORCEWAKE_MEDIA), |
9fc1117c | 956 | GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER), |
0dd356bb | 957 | GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER), |
9fc1117c | 958 | GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), |
0dd356bb | 959 | GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_BLITTER), |
b0081239 | 960 | GEN_FW_RANGE(0x8800, 0x89ff, FORCEWAKE_MEDIA), |
0dd356bb | 961 | GEN_FW_RANGE(0x8a00, 0x8bff, FORCEWAKE_BLITTER), |
9fc1117c | 962 | GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER), |
0dd356bb | 963 | GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER), |
9fc1117c | 964 | GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), |
0dd356bb | 965 | GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER), |
b0081239 | 966 | GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER), |
78424c92 | 967 | GEN_FW_RANGE(0xb480, 0xcfff, FORCEWAKE_BLITTER), |
9fc1117c | 968 | GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA), |
0dd356bb | 969 | GEN_FW_RANGE(0xd800, 0xdfff, FORCEWAKE_BLITTER), |
b0081239 | 970 | GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER), |
0dd356bb | 971 | GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_BLITTER), |
9fc1117c | 972 | GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA), |
0dd356bb | 973 | GEN_FW_RANGE(0x14000, 0x19fff, FORCEWAKE_BLITTER), |
9fc1117c | 974 | GEN_FW_RANGE(0x1a000, 0x1e9ff, FORCEWAKE_MEDIA), |
0dd356bb | 975 | GEN_FW_RANGE(0x1ea00, 0x243ff, FORCEWAKE_BLITTER), |
b0081239 | 976 | GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER), |
0dd356bb | 977 | GEN_FW_RANGE(0x24800, 0x2ffff, FORCEWAKE_BLITTER), |
9fc1117c TU |
978 | GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA), |
979 | }; | |
6863b76c | 980 | |
a89a70a8 DCS |
981 | /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */ |
982 | static const struct intel_forcewake_range __gen11_fw_ranges[] = { | |
983 | GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER), | |
984 | GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */ | |
985 | GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), | |
986 | GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER), | |
987 | GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER), | |
988 | GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER), | |
989 | GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), | |
990 | GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_BLITTER), | |
991 | GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER), | |
992 | GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER), | |
993 | GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), | |
994 | GEN_FW_RANGE(0x8500, 0x8bff, FORCEWAKE_BLITTER), | |
995 | GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER), | |
996 | GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER), | |
997 | GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_ALL), | |
998 | GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER), | |
999 | GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER), | |
1000 | GEN_FW_RANGE(0xb480, 0xdfff, FORCEWAKE_BLITTER), | |
1001 | GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER), | |
1002 | GEN_FW_RANGE(0xe900, 0x243ff, FORCEWAKE_BLITTER), | |
1003 | GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER), | |
1004 | GEN_FW_RANGE(0x24800, 0x3ffff, FORCEWAKE_BLITTER), | |
1005 | GEN_FW_RANGE(0x40000, 0x1bffff, 0), | |
1006 | GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), | |
1007 | GEN_FW_RANGE(0x1c4000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX1), | |
1008 | GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0), | |
1009 | GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_BLITTER), | |
1010 | GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2), | |
1011 | GEN_FW_RANGE(0x1d4000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX3), | |
1012 | GEN_FW_RANGE(0x1d8000, 0x1dbfff, FORCEWAKE_MEDIA_VEBOX1) | |
1013 | }; | |
1014 | ||
907b28c5 | 1015 | static void |
6ebc9692 | 1016 | ilk_dummy_write(struct intel_uncore *uncore) |
907b28c5 CW |
1017 | { |
1018 | /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up | |
1019 | * the chip from rc6 before touching it for real. MI_MODE is masked, | |
1020 | * hence harmless to write 0 into. */ | |
6cc5ca76 | 1021 | __raw_uncore_write32(uncore, MI_MODE, 0); |
907b28c5 CW |
1022 | } |
1023 | ||
1024 | static void | |
2cf7bf6f | 1025 | __unclaimed_reg_debug(struct intel_uncore *uncore, |
9c053501 MK |
1026 | const i915_reg_t reg, |
1027 | const bool read, | |
1028 | const bool before) | |
907b28c5 | 1029 | { |
2cf7bf6f | 1030 | if (WARN(check_for_unclaimed_mmio(uncore) && !before, |
dda96033 CW |
1031 | "Unclaimed %s register 0x%x\n", |
1032 | read ? "read from" : "write to", | |
4bd0a25d | 1033 | i915_mmio_reg_offset(reg))) |
4f044a88 MW |
1034 | /* Only report the first N failures */ |
1035 | i915_modparams.mmio_debug--; | |
907b28c5 CW |
1036 | } |
1037 | ||
9c053501 | 1038 | static inline void |
2cf7bf6f | 1039 | unclaimed_reg_debug(struct intel_uncore *uncore, |
9c053501 MK |
1040 | const i915_reg_t reg, |
1041 | const bool read, | |
1042 | const bool before) | |
1043 | { | |
4f044a88 | 1044 | if (likely(!i915_modparams.mmio_debug)) |
9c053501 MK |
1045 | return; |
1046 | ||
2cf7bf6f | 1047 | __unclaimed_reg_debug(uncore, reg, read, before); |
9c053501 MK |
1048 | } |
1049 | ||
51f67885 | 1050 | #define GEN2_READ_HEADER(x) \ |
5d738795 | 1051 | u##x val = 0; \ |
eb17af67 | 1052 | __assert_rpm_wakelock_held(uncore->rpm); |
5d738795 | 1053 | |
51f67885 | 1054 | #define GEN2_READ_FOOTER \ |
5d738795 BW |
1055 | trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ |
1056 | return val | |
1057 | ||
51f67885 | 1058 | #define __gen2_read(x) \ |
0b274481 | 1059 | static u##x \ |
a2b4abfc | 1060 | gen2_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \ |
51f67885 | 1061 | GEN2_READ_HEADER(x); \ |
6cc5ca76 | 1062 | val = __raw_uncore_read##x(uncore, reg); \ |
51f67885 | 1063 | GEN2_READ_FOOTER; \ |
3967018e BW |
1064 | } |
1065 | ||
1066 | #define __gen5_read(x) \ | |
1067 | static u##x \ | |
a2b4abfc | 1068 | gen5_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \ |
51f67885 | 1069 | GEN2_READ_HEADER(x); \ |
6ebc9692 | 1070 | ilk_dummy_write(uncore); \ |
6cc5ca76 | 1071 | val = __raw_uncore_read##x(uncore, reg); \ |
51f67885 | 1072 | GEN2_READ_FOOTER; \ |
3967018e BW |
1073 | } |
1074 | ||
51f67885 CW |
1075 | __gen5_read(8) |
1076 | __gen5_read(16) | |
1077 | __gen5_read(32) | |
1078 | __gen5_read(64) | |
1079 | __gen2_read(8) | |
1080 | __gen2_read(16) | |
1081 | __gen2_read(32) | |
1082 | __gen2_read(64) | |
1083 | ||
1084 | #undef __gen5_read | |
1085 | #undef __gen2_read | |
1086 | ||
1087 | #undef GEN2_READ_FOOTER | |
1088 | #undef GEN2_READ_HEADER | |
1089 | ||
1090 | #define GEN6_READ_HEADER(x) \ | |
f0f59a00 | 1091 | u32 offset = i915_mmio_reg_offset(reg); \ |
51f67885 CW |
1092 | unsigned long irqflags; \ |
1093 | u##x val = 0; \ | |
eb17af67 | 1094 | __assert_rpm_wakelock_held(uncore->rpm); \ |
272c7e52 | 1095 | spin_lock_irqsave(&uncore->lock, irqflags); \ |
2cf7bf6f | 1096 | unclaimed_reg_debug(uncore, reg, true, true) |
51f67885 CW |
1097 | |
1098 | #define GEN6_READ_FOOTER \ | |
2cf7bf6f | 1099 | unclaimed_reg_debug(uncore, reg, true, false); \ |
272c7e52 | 1100 | spin_unlock_irqrestore(&uncore->lock, irqflags); \ |
51f67885 CW |
1101 | trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ |
1102 | return val | |
1103 | ||
f568eeee | 1104 | static noinline void ___force_wake_auto(struct intel_uncore *uncore, |
c521b0c8 | 1105 | enum forcewake_domains fw_domains) |
b2cff0db CW |
1106 | { |
1107 | struct intel_uncore_forcewake_domain *domain; | |
d2dc94bc CW |
1108 | unsigned int tmp; |
1109 | ||
f568eeee | 1110 | GEM_BUG_ON(fw_domains & ~uncore->fw_domains); |
b2cff0db | 1111 | |
f568eeee | 1112 | for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) |
c521b0c8 TU |
1113 | fw_domain_arm_timer(domain); |
1114 | ||
f568eeee | 1115 | uncore->funcs.force_wake_get(uncore, fw_domains); |
c521b0c8 TU |
1116 | } |
1117 | ||
f568eeee | 1118 | static inline void __force_wake_auto(struct intel_uncore *uncore, |
c521b0c8 TU |
1119 | enum forcewake_domains fw_domains) |
1120 | { | |
b2cff0db CW |
1121 | if (WARN_ON(!fw_domains)) |
1122 | return; | |
1123 | ||
003342a5 | 1124 | /* Turn on all requested but inactive supported forcewake domains. */ |
f568eeee DCS |
1125 | fw_domains &= uncore->fw_domains; |
1126 | fw_domains &= ~uncore->fw_domains_active; | |
b2cff0db | 1127 | |
c521b0c8 | 1128 | if (fw_domains) |
f568eeee | 1129 | ___force_wake_auto(uncore, fw_domains); |
b2cff0db CW |
1130 | } |
1131 | ||
ccfceda2 | 1132 | #define __gen_read(func, x) \ |
3967018e | 1133 | static u##x \ |
a2b4abfc | 1134 | func##_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \ |
6863b76c | 1135 | enum forcewake_domains fw_engine; \ |
51f67885 | 1136 | GEN6_READ_HEADER(x); \ |
272c7e52 | 1137 | fw_engine = __##func##_reg_read_fw_domains(uncore, offset); \ |
6a42d0f4 | 1138 | if (fw_engine) \ |
272c7e52 | 1139 | __force_wake_auto(uncore, fw_engine); \ |
6cc5ca76 | 1140 | val = __raw_uncore_read##x(uncore, reg); \ |
51f67885 | 1141 | GEN6_READ_FOOTER; \ |
940aece4 | 1142 | } |
ccfceda2 DCS |
1143 | #define __gen6_read(x) __gen_read(gen6, x) |
1144 | #define __fwtable_read(x) __gen_read(fwtable, x) | |
a89a70a8 | 1145 | #define __gen11_fwtable_read(x) __gen_read(gen11_fwtable, x) |
940aece4 | 1146 | |
a89a70a8 DCS |
1147 | __gen11_fwtable_read(8) |
1148 | __gen11_fwtable_read(16) | |
1149 | __gen11_fwtable_read(32) | |
1150 | __gen11_fwtable_read(64) | |
6044c4a3 TU |
1151 | __fwtable_read(8) |
1152 | __fwtable_read(16) | |
1153 | __fwtable_read(32) | |
1154 | __fwtable_read(64) | |
3967018e BW |
1155 | __gen6_read(8) |
1156 | __gen6_read(16) | |
1157 | __gen6_read(32) | |
1158 | __gen6_read(64) | |
3967018e | 1159 | |
a89a70a8 | 1160 | #undef __gen11_fwtable_read |
6044c4a3 | 1161 | #undef __fwtable_read |
3967018e | 1162 | #undef __gen6_read |
51f67885 CW |
1163 | #undef GEN6_READ_FOOTER |
1164 | #undef GEN6_READ_HEADER | |
5d738795 | 1165 | |
51f67885 | 1166 | #define GEN2_WRITE_HEADER \ |
5d738795 | 1167 | trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ |
eb17af67 | 1168 | __assert_rpm_wakelock_held(uncore->rpm); \ |
907b28c5 | 1169 | |
51f67885 | 1170 | #define GEN2_WRITE_FOOTER |
0d965301 | 1171 | |
51f67885 | 1172 | #define __gen2_write(x) \ |
0b274481 | 1173 | static void \ |
a2b4abfc | 1174 | gen2_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ |
51f67885 | 1175 | GEN2_WRITE_HEADER; \ |
6cc5ca76 | 1176 | __raw_uncore_write##x(uncore, reg, val); \ |
51f67885 | 1177 | GEN2_WRITE_FOOTER; \ |
4032ef43 BW |
1178 | } |
1179 | ||
1180 | #define __gen5_write(x) \ | |
1181 | static void \ | |
a2b4abfc | 1182 | gen5_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ |
51f67885 | 1183 | GEN2_WRITE_HEADER; \ |
6ebc9692 | 1184 | ilk_dummy_write(uncore); \ |
6cc5ca76 | 1185 | __raw_uncore_write##x(uncore, reg, val); \ |
51f67885 | 1186 | GEN2_WRITE_FOOTER; \ |
4032ef43 BW |
1187 | } |
1188 | ||
51f67885 CW |
1189 | __gen5_write(8) |
1190 | __gen5_write(16) | |
1191 | __gen5_write(32) | |
51f67885 CW |
1192 | __gen2_write(8) |
1193 | __gen2_write(16) | |
1194 | __gen2_write(32) | |
51f67885 CW |
1195 | |
1196 | #undef __gen5_write | |
1197 | #undef __gen2_write | |
1198 | ||
1199 | #undef GEN2_WRITE_FOOTER | |
1200 | #undef GEN2_WRITE_HEADER | |
1201 | ||
1202 | #define GEN6_WRITE_HEADER \ | |
f0f59a00 | 1203 | u32 offset = i915_mmio_reg_offset(reg); \ |
51f67885 CW |
1204 | unsigned long irqflags; \ |
1205 | trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ | |
eb17af67 | 1206 | __assert_rpm_wakelock_held(uncore->rpm); \ |
272c7e52 | 1207 | spin_lock_irqsave(&uncore->lock, irqflags); \ |
2cf7bf6f | 1208 | unclaimed_reg_debug(uncore, reg, false, true) |
51f67885 CW |
1209 | |
1210 | #define GEN6_WRITE_FOOTER \ | |
2cf7bf6f | 1211 | unclaimed_reg_debug(uncore, reg, false, false); \ |
272c7e52 | 1212 | spin_unlock_irqrestore(&uncore->lock, irqflags) |
51f67885 | 1213 | |
4032ef43 BW |
1214 | #define __gen6_write(x) \ |
1215 | static void \ | |
a2b4abfc | 1216 | gen6_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ |
51f67885 | 1217 | GEN6_WRITE_HEADER; \ |
a338908c | 1218 | if (NEEDS_FORCE_WAKE(offset)) \ |
6ebc9692 | 1219 | __gen6_gt_wait_for_fifo(uncore); \ |
6cc5ca76 | 1220 | __raw_uncore_write##x(uncore, reg, val); \ |
51f67885 | 1221 | GEN6_WRITE_FOOTER; \ |
4032ef43 BW |
1222 | } |
1223 | ||
ccfceda2 | 1224 | #define __gen_write(func, x) \ |
ab2aa47e | 1225 | static void \ |
a2b4abfc | 1226 | func##_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ |
6863b76c | 1227 | enum forcewake_domains fw_engine; \ |
51f67885 | 1228 | GEN6_WRITE_HEADER; \ |
272c7e52 | 1229 | fw_engine = __##func##_reg_write_fw_domains(uncore, offset); \ |
6a42d0f4 | 1230 | if (fw_engine) \ |
272c7e52 | 1231 | __force_wake_auto(uncore, fw_engine); \ |
6cc5ca76 | 1232 | __raw_uncore_write##x(uncore, reg, val); \ |
51f67885 | 1233 | GEN6_WRITE_FOOTER; \ |
1938e59a | 1234 | } |
ccfceda2 DCS |
1235 | #define __gen8_write(x) __gen_write(gen8, x) |
1236 | #define __fwtable_write(x) __gen_write(fwtable, x) | |
a89a70a8 | 1237 | #define __gen11_fwtable_write(x) __gen_write(gen11_fwtable, x) |
1938e59a | 1238 | |
a89a70a8 DCS |
1239 | __gen11_fwtable_write(8) |
1240 | __gen11_fwtable_write(16) | |
1241 | __gen11_fwtable_write(32) | |
22d48c55 TU |
1242 | __fwtable_write(8) |
1243 | __fwtable_write(16) | |
1244 | __fwtable_write(32) | |
ab2aa47e BW |
1245 | __gen8_write(8) |
1246 | __gen8_write(16) | |
1247 | __gen8_write(32) | |
4032ef43 BW |
1248 | __gen6_write(8) |
1249 | __gen6_write(16) | |
1250 | __gen6_write(32) | |
4032ef43 | 1251 | |
a89a70a8 | 1252 | #undef __gen11_fwtable_write |
22d48c55 | 1253 | #undef __fwtable_write |
ab2aa47e | 1254 | #undef __gen8_write |
4032ef43 | 1255 | #undef __gen6_write |
51f67885 CW |
1256 | #undef GEN6_WRITE_FOOTER |
1257 | #undef GEN6_WRITE_HEADER | |
907b28c5 | 1258 | |
f7de5027 | 1259 | #define ASSIGN_WRITE_MMIO_VFUNCS(uncore, x) \ |
43d942a7 | 1260 | do { \ |
f7de5027 DCS |
1261 | (uncore)->funcs.mmio_writeb = x##_write8; \ |
1262 | (uncore)->funcs.mmio_writew = x##_write16; \ | |
1263 | (uncore)->funcs.mmio_writel = x##_write32; \ | |
43d942a7 YZ |
1264 | } while (0) |
1265 | ||
f7de5027 | 1266 | #define ASSIGN_READ_MMIO_VFUNCS(uncore, x) \ |
43d942a7 | 1267 | do { \ |
f7de5027 DCS |
1268 | (uncore)->funcs.mmio_readb = x##_read8; \ |
1269 | (uncore)->funcs.mmio_readw = x##_read16; \ | |
1270 | (uncore)->funcs.mmio_readl = x##_read32; \ | |
1271 | (uncore)->funcs.mmio_readq = x##_read64; \ | |
43d942a7 YZ |
1272 | } while (0) |
1273 | ||
05a2fb15 | 1274 | |
f7de5027 | 1275 | static void fw_domain_init(struct intel_uncore *uncore, |
48c1026a | 1276 | enum forcewake_domain_id domain_id, |
f0f59a00 VS |
1277 | i915_reg_t reg_set, |
1278 | i915_reg_t reg_ack) | |
05a2fb15 MK |
1279 | { |
1280 | struct intel_uncore_forcewake_domain *d; | |
1281 | ||
1282 | if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT)) | |
1283 | return; | |
1284 | ||
535d8d27 | 1285 | d = &uncore->fw_domain[domain_id]; |
05a2fb15 MK |
1286 | |
1287 | WARN_ON(d->wake_count); | |
1288 | ||
6e3955a5 CW |
1289 | WARN_ON(!i915_mmio_reg_valid(reg_set)); |
1290 | WARN_ON(!i915_mmio_reg_valid(reg_ack)); | |
1291 | ||
05a2fb15 | 1292 | d->wake_count = 0; |
25286aac DCS |
1293 | d->reg_set = uncore->regs + i915_mmio_reg_offset(reg_set); |
1294 | d->reg_ack = uncore->regs + i915_mmio_reg_offset(reg_ack); | |
05a2fb15 | 1295 | |
05a2fb15 MK |
1296 | d->id = domain_id; |
1297 | ||
33c582c1 TU |
1298 | BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER)); |
1299 | BUILD_BUG_ON(FORCEWAKE_BLITTER != (1 << FW_DOMAIN_ID_BLITTER)); | |
1300 | BUILD_BUG_ON(FORCEWAKE_MEDIA != (1 << FW_DOMAIN_ID_MEDIA)); | |
a89a70a8 DCS |
1301 | BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX0)); |
1302 | BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX1)); | |
1303 | BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX2 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX2)); | |
1304 | BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX3 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX3)); | |
1305 | BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX0)); | |
1306 | BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX1)); | |
1307 | ||
33c582c1 | 1308 | |
d2dc94bc | 1309 | d->mask = BIT(domain_id); |
33c582c1 | 1310 | |
a57a4a67 TU |
1311 | hrtimer_init(&d->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); |
1312 | d->timer.function = intel_uncore_fw_release_timer; | |
05a2fb15 | 1313 | |
535d8d27 | 1314 | uncore->fw_domains |= BIT(domain_id); |
f9b3927a | 1315 | |
159367bb | 1316 | fw_domain_reset(d); |
05a2fb15 MK |
1317 | } |
1318 | ||
f7de5027 | 1319 | static void fw_domain_fini(struct intel_uncore *uncore, |
26376a7e OM |
1320 | enum forcewake_domain_id domain_id) |
1321 | { | |
1322 | struct intel_uncore_forcewake_domain *d; | |
1323 | ||
1324 | if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT)) | |
1325 | return; | |
1326 | ||
f7de5027 | 1327 | d = &uncore->fw_domain[domain_id]; |
26376a7e OM |
1328 | |
1329 | WARN_ON(d->wake_count); | |
1330 | WARN_ON(hrtimer_cancel(&d->timer)); | |
1331 | memset(d, 0, sizeof(*d)); | |
1332 | ||
f7de5027 | 1333 | uncore->fw_domains &= ~BIT(domain_id); |
26376a7e OM |
1334 | } |
1335 | ||
f7de5027 | 1336 | static void intel_uncore_fw_domains_init(struct intel_uncore *uncore) |
0b274481 | 1337 | { |
f7de5027 DCS |
1338 | struct drm_i915_private *i915 = uncore_to_i915(uncore); |
1339 | ||
5a0ba777 | 1340 | if (!intel_uncore_has_forcewake(uncore)) |
3225b2f9 MK |
1341 | return; |
1342 | ||
f7de5027 | 1343 | if (INTEL_GEN(i915) >= 11) { |
a89a70a8 DCS |
1344 | int i; |
1345 | ||
f7de5027 | 1346 | uncore->funcs.force_wake_get = |
cc38cae7 | 1347 | fw_domains_get_with_fallback; |
f7de5027 DCS |
1348 | uncore->funcs.force_wake_put = fw_domains_put; |
1349 | fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, | |
a89a70a8 DCS |
1350 | FORCEWAKE_RENDER_GEN9, |
1351 | FORCEWAKE_ACK_RENDER_GEN9); | |
f7de5027 | 1352 | fw_domain_init(uncore, FW_DOMAIN_ID_BLITTER, |
a89a70a8 DCS |
1353 | FORCEWAKE_BLITTER_GEN9, |
1354 | FORCEWAKE_ACK_BLITTER_GEN9); | |
1355 | for (i = 0; i < I915_MAX_VCS; i++) { | |
f7de5027 | 1356 | if (!HAS_ENGINE(i915, _VCS(i))) |
a89a70a8 DCS |
1357 | continue; |
1358 | ||
f7de5027 | 1359 | fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VDBOX0 + i, |
a89a70a8 DCS |
1360 | FORCEWAKE_MEDIA_VDBOX_GEN11(i), |
1361 | FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(i)); | |
1362 | } | |
1363 | for (i = 0; i < I915_MAX_VECS; i++) { | |
f7de5027 | 1364 | if (!HAS_ENGINE(i915, _VECS(i))) |
a89a70a8 DCS |
1365 | continue; |
1366 | ||
f7de5027 | 1367 | fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VEBOX0 + i, |
a89a70a8 DCS |
1368 | FORCEWAKE_MEDIA_VEBOX_GEN11(i), |
1369 | FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i)); | |
1370 | } | |
f7de5027 DCS |
1371 | } else if (IS_GEN_RANGE(i915, 9, 10)) { |
1372 | uncore->funcs.force_wake_get = | |
71306303 | 1373 | fw_domains_get_with_fallback; |
f7de5027 DCS |
1374 | uncore->funcs.force_wake_put = fw_domains_put; |
1375 | fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, | |
05a2fb15 MK |
1376 | FORCEWAKE_RENDER_GEN9, |
1377 | FORCEWAKE_ACK_RENDER_GEN9); | |
f7de5027 | 1378 | fw_domain_init(uncore, FW_DOMAIN_ID_BLITTER, |
05a2fb15 MK |
1379 | FORCEWAKE_BLITTER_GEN9, |
1380 | FORCEWAKE_ACK_BLITTER_GEN9); | |
f7de5027 | 1381 | fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA, |
05a2fb15 | 1382 | FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9); |
f7de5027 DCS |
1383 | } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { |
1384 | uncore->funcs.force_wake_get = fw_domains_get; | |
1385 | uncore->funcs.force_wake_put = fw_domains_put; | |
1386 | fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, | |
05a2fb15 | 1387 | FORCEWAKE_VLV, FORCEWAKE_ACK_VLV); |
f7de5027 | 1388 | fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA, |
05a2fb15 | 1389 | FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV); |
f7de5027 DCS |
1390 | } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { |
1391 | uncore->funcs.force_wake_get = | |
05a2fb15 | 1392 | fw_domains_get_with_thread_status; |
f7de5027 DCS |
1393 | uncore->funcs.force_wake_put = fw_domains_put; |
1394 | fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, | |
05a2fb15 | 1395 | FORCEWAKE_MT, FORCEWAKE_ACK_HSW); |
f7de5027 | 1396 | } else if (IS_IVYBRIDGE(i915)) { |
0b274481 BW |
1397 | u32 ecobus; |
1398 | ||
1399 | /* IVB configs may use multi-threaded forcewake */ | |
1400 | ||
1401 | /* A small trick here - if the bios hasn't configured | |
1402 | * MT forcewake, and if the device is in RC6, then | |
1403 | * force_wake_mt_get will not wake the device and the | |
1404 | * ECOBUS read will return zero. Which will be | |
1405 | * (correctly) interpreted by the test below as MT | |
1406 | * forcewake being disabled. | |
1407 | */ | |
f7de5027 | 1408 | uncore->funcs.force_wake_get = |
05a2fb15 | 1409 | fw_domains_get_with_thread_status; |
f7de5027 | 1410 | uncore->funcs.force_wake_put = fw_domains_put; |
05a2fb15 | 1411 | |
f9b3927a MK |
1412 | /* We need to init first for ECOBUS access and then |
1413 | * determine later if we want to reinit, in case of MT access is | |
6ea2556f MK |
1414 | * not working. In this stage we don't know which flavour this |
1415 | * ivb is, so it is better to reset also the gen6 fw registers | |
1416 | * before the ecobus check. | |
f9b3927a | 1417 | */ |
6ea2556f | 1418 | |
6cc5ca76 | 1419 | __raw_uncore_write32(uncore, FORCEWAKE, 0); |
6ebc9692 | 1420 | __raw_posting_read(uncore, ECOBUS); |
6ea2556f | 1421 | |
f7de5027 | 1422 | fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, |
05a2fb15 | 1423 | FORCEWAKE_MT, FORCEWAKE_MT_ACK); |
f9b3927a | 1424 | |
f7de5027 DCS |
1425 | spin_lock_irq(&uncore->lock); |
1426 | fw_domains_get_with_thread_status(uncore, FORCEWAKE_RENDER); | |
6cc5ca76 | 1427 | ecobus = __raw_uncore_read32(uncore, ECOBUS); |
f7de5027 DCS |
1428 | fw_domains_put(uncore, FORCEWAKE_RENDER); |
1429 | spin_unlock_irq(&uncore->lock); | |
0b274481 | 1430 | |
05a2fb15 | 1431 | if (!(ecobus & FORCEWAKE_MT_ENABLE)) { |
0b274481 BW |
1432 | DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n"); |
1433 | DRM_INFO("when using vblank-synced partial screen updates.\n"); | |
f7de5027 | 1434 | fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, |
05a2fb15 | 1435 | FORCEWAKE, FORCEWAKE_ACK); |
0b274481 | 1436 | } |
f7de5027 DCS |
1437 | } else if (IS_GEN(i915, 6)) { |
1438 | uncore->funcs.force_wake_get = | |
05a2fb15 | 1439 | fw_domains_get_with_thread_status; |
f7de5027 DCS |
1440 | uncore->funcs.force_wake_put = fw_domains_put; |
1441 | fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, | |
05a2fb15 | 1442 | FORCEWAKE, FORCEWAKE_ACK); |
0b274481 | 1443 | } |
3225b2f9 MK |
1444 | |
1445 | /* All future platforms are expected to require complex power gating */ | |
f7de5027 | 1446 | WARN_ON(uncore->fw_domains == 0); |
f9b3927a MK |
1447 | } |
1448 | ||
f7de5027 | 1449 | #define ASSIGN_FW_DOMAINS_TABLE(uncore, d) \ |
15157970 | 1450 | { \ |
f7de5027 | 1451 | (uncore)->fw_domains_table = \ |
15157970 | 1452 | (struct intel_forcewake_range *)(d); \ |
f7de5027 | 1453 | (uncore)->fw_domains_table_entries = ARRAY_SIZE((d)); \ |
15157970 TU |
1454 | } |
1455 | ||
264ec1a8 HG |
1456 | static int i915_pmic_bus_access_notifier(struct notifier_block *nb, |
1457 | unsigned long action, void *data) | |
1458 | { | |
1459 | struct drm_i915_private *dev_priv = container_of(nb, | |
1460 | struct drm_i915_private, uncore.pmic_bus_access_nb); | |
1461 | ||
1462 | switch (action) { | |
1463 | case MBI_PMIC_BUS_ACCESS_BEGIN: | |
1464 | /* | |
1465 | * forcewake all now to make sure that we don't need to do a | |
1466 | * forcewake later which on systems where this notifier gets | |
1467 | * called requires the punit to access to the shared pmic i2c | |
1468 | * bus, which will be busy after this notification, leading to: | |
1469 | * "render: timed out waiting for forcewake ack request." | |
1470 | * errors. | |
ce30560c HG |
1471 | * |
1472 | * The notifier is unregistered during intel_runtime_suspend(), | |
1473 | * so it's ok to access the HW here without holding a RPM | |
1474 | * wake reference -> disable wakeref asserts for the time of | |
1475 | * the access. | |
264ec1a8 | 1476 | */ |
ce30560c | 1477 | disable_rpm_wakeref_asserts(dev_priv); |
3ceea6a1 | 1478 | intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL); |
ce30560c | 1479 | enable_rpm_wakeref_asserts(dev_priv); |
264ec1a8 HG |
1480 | break; |
1481 | case MBI_PMIC_BUS_ACCESS_END: | |
3ceea6a1 | 1482 | intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); |
264ec1a8 HG |
1483 | break; |
1484 | } | |
1485 | ||
1486 | return NOTIFY_OK; | |
1487 | } | |
1488 | ||
25286aac DCS |
1489 | static int uncore_mmio_setup(struct intel_uncore *uncore) |
1490 | { | |
1491 | struct drm_i915_private *i915 = uncore_to_i915(uncore); | |
1492 | struct pci_dev *pdev = i915->drm.pdev; | |
1493 | int mmio_bar; | |
1494 | int mmio_size; | |
1495 | ||
1496 | mmio_bar = IS_GEN(i915, 2) ? 1 : 0; | |
1497 | /* | |
1498 | * Before gen4, the registers and the GTT are behind different BARs. | |
1499 | * However, from gen4 onwards, the registers and the GTT are shared | |
1500 | * in the same BAR, so we want to restrict this ioremap from | |
1501 | * clobbering the GTT which we want ioremap_wc instead. Fortunately, | |
1502 | * the register BAR remains the same size for all the earlier | |
1503 | * generations up to Ironlake. | |
1504 | */ | |
1505 | if (INTEL_GEN(i915) < 5) | |
1506 | mmio_size = 512 * 1024; | |
1507 | else | |
1508 | mmio_size = 2 * 1024 * 1024; | |
1509 | uncore->regs = pci_iomap(pdev, mmio_bar, mmio_size); | |
1510 | if (uncore->regs == NULL) { | |
1511 | DRM_ERROR("failed to map registers\n"); | |
1512 | ||
1513 | return -EIO; | |
1514 | } | |
1515 | ||
1516 | return 0; | |
1517 | } | |
1518 | ||
1519 | static void uncore_mmio_cleanup(struct intel_uncore *uncore) | |
1520 | { | |
1521 | struct drm_i915_private *i915 = uncore_to_i915(uncore); | |
1522 | struct pci_dev *pdev = i915->drm.pdev; | |
1523 | ||
1524 | pci_iounmap(pdev, uncore->regs); | |
1525 | } | |
1526 | ||
6cbe8830 DCS |
1527 | void intel_uncore_init_early(struct intel_uncore *uncore) |
1528 | { | |
1529 | spin_lock_init(&uncore->lock); | |
1530 | } | |
25286aac | 1531 | |
3de6f852 | 1532 | int intel_uncore_init_mmio(struct intel_uncore *uncore) |
f9b3927a | 1533 | { |
f7de5027 | 1534 | struct drm_i915_private *i915 = uncore_to_i915(uncore); |
25286aac DCS |
1535 | int ret; |
1536 | ||
1537 | ret = uncore_mmio_setup(uncore); | |
1538 | if (ret) | |
1539 | return ret; | |
f7de5027 DCS |
1540 | |
1541 | i915_check_vgpu(i915); | |
cf9d2890 | 1542 | |
5a0ba777 DCS |
1543 | if (INTEL_GEN(i915) > 5 && !intel_vgpu_active(i915)) |
1544 | uncore->flags |= UNCORE_HAS_FORCEWAKE; | |
1545 | ||
f7de5027 DCS |
1546 | intel_uncore_fw_domains_init(uncore); |
1547 | __intel_uncore_early_sanitize(uncore, 0); | |
0b274481 | 1548 | |
f7de5027 DCS |
1549 | uncore->unclaimed_mmio_check = 1; |
1550 | uncore->pmic_bus_access_nb.notifier_call = | |
264ec1a8 | 1551 | i915_pmic_bus_access_notifier; |
75714940 | 1552 | |
eb17af67 DCS |
1553 | uncore->rpm = &i915->runtime_pm; |
1554 | ||
5a0ba777 DCS |
1555 | if (!intel_uncore_has_forcewake(uncore)) { |
1556 | if (IS_GEN(i915, 5)) { | |
1557 | ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen5); | |
1558 | ASSIGN_READ_MMIO_VFUNCS(uncore, gen5); | |
1559 | } else { | |
1560 | ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen2); | |
1561 | ASSIGN_READ_MMIO_VFUNCS(uncore, gen2); | |
1562 | } | |
f7de5027 DCS |
1563 | } else if (IS_GEN_RANGE(i915, 6, 7)) { |
1564 | ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6); | |
1565 | ||
1566 | if (IS_VALLEYVIEW(i915)) { | |
1567 | ASSIGN_FW_DOMAINS_TABLE(uncore, __vlv_fw_ranges); | |
1568 | ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable); | |
e3b1895f | 1569 | } else { |
f7de5027 | 1570 | ASSIGN_READ_MMIO_VFUNCS(uncore, gen6); |
85ee17eb | 1571 | } |
f7de5027 DCS |
1572 | } else if (IS_GEN(i915, 8)) { |
1573 | if (IS_CHERRYVIEW(i915)) { | |
1574 | ASSIGN_FW_DOMAINS_TABLE(uncore, __chv_fw_ranges); | |
1575 | ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable); | |
1576 | ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable); | |
1938e59a D |
1577 | |
1578 | } else { | |
f7de5027 DCS |
1579 | ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen8); |
1580 | ASSIGN_READ_MMIO_VFUNCS(uncore, gen6); | |
1938e59a | 1581 | } |
f7de5027 DCS |
1582 | } else if (IS_GEN_RANGE(i915, 9, 10)) { |
1583 | ASSIGN_FW_DOMAINS_TABLE(uncore, __gen9_fw_ranges); | |
1584 | ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable); | |
1585 | ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable); | |
a89a70a8 | 1586 | } else { |
f7de5027 DCS |
1587 | ASSIGN_FW_DOMAINS_TABLE(uncore, __gen11_fw_ranges); |
1588 | ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen11_fwtable); | |
1589 | ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable); | |
3967018e | 1590 | } |
ed493883 | 1591 | |
2cf7bf6f DCS |
1592 | if (HAS_FPGA_DBG_UNCLAIMED(i915)) |
1593 | uncore->flags |= UNCORE_HAS_FPGA_DBG_UNCLAIMED; | |
1594 | ||
1595 | if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) | |
1596 | uncore->flags |= UNCORE_HAS_DBG_UNCLAIMED; | |
1597 | ||
1598 | if (IS_GEN_RANGE(i915, 6, 7)) | |
1599 | uncore->flags |= UNCORE_HAS_FIFO; | |
1600 | ||
f7de5027 | 1601 | iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb); |
25286aac DCS |
1602 | |
1603 | return 0; | |
0b274481 BW |
1604 | } |
1605 | ||
26376a7e OM |
1606 | /* |
1607 | * We might have detected that some engines are fused off after we initialized | |
1608 | * the forcewake domains. Prune them, to make sure they only reference existing | |
1609 | * engines. | |
1610 | */ | |
3de6f852 | 1611 | void intel_uncore_prune_mmio_domains(struct intel_uncore *uncore) |
26376a7e | 1612 | { |
f7de5027 DCS |
1613 | struct drm_i915_private *i915 = uncore_to_i915(uncore); |
1614 | ||
1615 | if (INTEL_GEN(i915) >= 11) { | |
1616 | enum forcewake_domains fw_domains = uncore->fw_domains; | |
26376a7e OM |
1617 | enum forcewake_domain_id domain_id; |
1618 | int i; | |
1619 | ||
1620 | for (i = 0; i < I915_MAX_VCS; i++) { | |
1621 | domain_id = FW_DOMAIN_ID_MEDIA_VDBOX0 + i; | |
1622 | ||
f7de5027 | 1623 | if (HAS_ENGINE(i915, _VCS(i))) |
26376a7e OM |
1624 | continue; |
1625 | ||
1626 | if (fw_domains & BIT(domain_id)) | |
f7de5027 | 1627 | fw_domain_fini(uncore, domain_id); |
26376a7e OM |
1628 | } |
1629 | ||
1630 | for (i = 0; i < I915_MAX_VECS; i++) { | |
1631 | domain_id = FW_DOMAIN_ID_MEDIA_VEBOX0 + i; | |
1632 | ||
f7de5027 | 1633 | if (HAS_ENGINE(i915, _VECS(i))) |
26376a7e OM |
1634 | continue; |
1635 | ||
1636 | if (fw_domains & BIT(domain_id)) | |
f7de5027 | 1637 | fw_domain_fini(uncore, domain_id); |
26376a7e OM |
1638 | } |
1639 | } | |
1640 | } | |
1641 | ||
3de6f852 | 1642 | void intel_uncore_fini_mmio(struct intel_uncore *uncore) |
0b274481 | 1643 | { |
0b274481 | 1644 | /* Paranoia: make sure we have disabled everything before we exit. */ |
f7de5027 | 1645 | intel_uncore_sanitize(uncore_to_i915(uncore)); |
a5266db4 HG |
1646 | |
1647 | iosf_mbi_punit_acquire(); | |
1648 | iosf_mbi_unregister_pmic_bus_access_notifier_unlocked( | |
f7de5027 DCS |
1649 | &uncore->pmic_bus_access_nb); |
1650 | intel_uncore_forcewake_reset(uncore); | |
a5266db4 | 1651 | iosf_mbi_punit_release(); |
25286aac | 1652 | uncore_mmio_cleanup(uncore); |
0b274481 BW |
1653 | } |
1654 | ||
3fd3a6ff JL |
1655 | static const struct reg_whitelist { |
1656 | i915_reg_t offset_ldw; | |
1657 | i915_reg_t offset_udw; | |
1658 | u16 gen_mask; | |
1659 | u8 size; | |
1660 | } reg_read_whitelist[] = { { | |
1661 | .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE), | |
1662 | .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE), | |
164daaf2 | 1663 | .gen_mask = INTEL_GEN_MASK(4, 11), |
3fd3a6ff JL |
1664 | .size = 8 |
1665 | } }; | |
907b28c5 CW |
1666 | |
1667 | int i915_reg_read_ioctl(struct drm_device *dev, | |
1668 | void *data, struct drm_file *file) | |
1669 | { | |
fac5e23e | 1670 | struct drm_i915_private *dev_priv = to_i915(dev); |
907b28c5 | 1671 | struct drm_i915_reg_read *reg = data; |
3fd3a6ff | 1672 | struct reg_whitelist const *entry; |
538ef96b | 1673 | intel_wakeref_t wakeref; |
3fd3a6ff JL |
1674 | unsigned int flags; |
1675 | int remain; | |
1676 | int ret = 0; | |
1677 | ||
1678 | entry = reg_read_whitelist; | |
1679 | remain = ARRAY_SIZE(reg_read_whitelist); | |
1680 | while (remain) { | |
1681 | u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw); | |
1682 | ||
1683 | GEM_BUG_ON(!is_power_of_2(entry->size)); | |
1684 | GEM_BUG_ON(entry->size > 8); | |
1685 | GEM_BUG_ON(entry_offset & (entry->size - 1)); | |
1686 | ||
1687 | if (INTEL_INFO(dev_priv)->gen_mask & entry->gen_mask && | |
1688 | entry_offset == (reg->offset & -entry->size)) | |
907b28c5 | 1689 | break; |
3fd3a6ff JL |
1690 | entry++; |
1691 | remain--; | |
907b28c5 CW |
1692 | } |
1693 | ||
3fd3a6ff | 1694 | if (!remain) |
907b28c5 CW |
1695 | return -EINVAL; |
1696 | ||
3fd3a6ff | 1697 | flags = reg->offset & (entry->size - 1); |
648a9bc5 | 1698 | |
d4225a53 CW |
1699 | with_intel_runtime_pm(dev_priv, wakeref) { |
1700 | if (entry->size == 8 && flags == I915_REG_READ_8B_WA) | |
1701 | reg->val = I915_READ64_2x32(entry->offset_ldw, | |
1702 | entry->offset_udw); | |
1703 | else if (entry->size == 8 && flags == 0) | |
1704 | reg->val = I915_READ64(entry->offset_ldw); | |
1705 | else if (entry->size == 4 && flags == 0) | |
1706 | reg->val = I915_READ(entry->offset_ldw); | |
1707 | else if (entry->size == 2 && flags == 0) | |
1708 | reg->val = I915_READ16(entry->offset_ldw); | |
1709 | else if (entry->size == 1 && flags == 0) | |
1710 | reg->val = I915_READ8(entry->offset_ldw); | |
1711 | else | |
1712 | ret = -EINVAL; | |
1713 | } | |
3fd3a6ff | 1714 | |
cf67c70f | 1715 | return ret; |
907b28c5 CW |
1716 | } |
1717 | ||
1758b90e | 1718 | /** |
1d1a9774 | 1719 | * __intel_wait_for_register_fw - wait until register matches expected state |
d2d551c0 | 1720 | * @uncore: the struct intel_uncore |
1758b90e CW |
1721 | * @reg: the register to read |
1722 | * @mask: mask to apply to register value | |
1723 | * @value: expected value | |
1d1a9774 MW |
1724 | * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait |
1725 | * @slow_timeout_ms: slow timeout in millisecond | |
1726 | * @out_value: optional placeholder to hold registry value | |
1758b90e CW |
1727 | * |
1728 | * This routine waits until the target register @reg contains the expected | |
3d466cd6 DV |
1729 | * @value after applying the @mask, i.e. it waits until :: |
1730 | * | |
1731 | * (I915_READ_FW(reg) & mask) == value | |
1732 | * | |
1d1a9774 | 1733 | * Otherwise, the wait will timeout after @slow_timeout_ms milliseconds. |
6976e74b | 1734 | * For atomic context @slow_timeout_ms must be zero and @fast_timeout_us |
84d84cb7 | 1735 | * must be not larger than 20,0000 microseconds. |
1758b90e CW |
1736 | * |
1737 | * Note that this routine assumes the caller holds forcewake asserted, it is | |
1738 | * not suitable for very long waits. See intel_wait_for_register() if you | |
1739 | * wish to wait without holding forcewake for the duration (i.e. you expect | |
1740 | * the wait to be slow). | |
1741 | * | |
1742 | * Returns 0 if the register matches the desired condition, or -ETIMEOUT. | |
1743 | */ | |
d2d551c0 | 1744 | int __intel_wait_for_register_fw(struct intel_uncore *uncore, |
1d1a9774 | 1745 | i915_reg_t reg, |
3fc7d86b MW |
1746 | u32 mask, |
1747 | u32 value, | |
1748 | unsigned int fast_timeout_us, | |
1749 | unsigned int slow_timeout_ms, | |
1d1a9774 | 1750 | u32 *out_value) |
1758b90e | 1751 | { |
ff26ffa8 | 1752 | u32 uninitialized_var(reg_value); |
d2d551c0 | 1753 | #define done (((reg_value = intel_uncore_read_fw(uncore, reg)) & mask) == value) |
1d1a9774 MW |
1754 | int ret; |
1755 | ||
6976e74b | 1756 | /* Catch any overuse of this function */ |
84d84cb7 CW |
1757 | might_sleep_if(slow_timeout_ms); |
1758 | GEM_BUG_ON(fast_timeout_us > 20000); | |
6976e74b | 1759 | |
84d84cb7 CW |
1760 | ret = -ETIMEDOUT; |
1761 | if (fast_timeout_us && fast_timeout_us <= 20000) | |
1d1a9774 | 1762 | ret = _wait_for_atomic(done, fast_timeout_us, 0); |
ff26ffa8 | 1763 | if (ret && slow_timeout_ms) |
1d1a9774 | 1764 | ret = wait_for(done, slow_timeout_ms); |
84d84cb7 | 1765 | |
1d1a9774 MW |
1766 | if (out_value) |
1767 | *out_value = reg_value; | |
84d84cb7 | 1768 | |
1758b90e CW |
1769 | return ret; |
1770 | #undef done | |
1771 | } | |
1772 | ||
1773 | /** | |
23fdbdd7 | 1774 | * __intel_wait_for_register - wait until register matches expected state |
baba6e57 | 1775 | * @uncore: the struct intel_uncore |
1758b90e CW |
1776 | * @reg: the register to read |
1777 | * @mask: mask to apply to register value | |
1778 | * @value: expected value | |
23fdbdd7 SP |
1779 | * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait |
1780 | * @slow_timeout_ms: slow timeout in millisecond | |
1781 | * @out_value: optional placeholder to hold registry value | |
1758b90e CW |
1782 | * |
1783 | * This routine waits until the target register @reg contains the expected | |
3d466cd6 DV |
1784 | * @value after applying the @mask, i.e. it waits until :: |
1785 | * | |
1786 | * (I915_READ(reg) & mask) == value | |
1787 | * | |
1758b90e CW |
1788 | * Otherwise, the wait will timeout after @timeout_ms milliseconds. |
1789 | * | |
1790 | * Returns 0 if the register matches the desired condition, or -ETIMEOUT. | |
1791 | */ | |
97a04e0d DCS |
1792 | int __intel_wait_for_register(struct intel_uncore *uncore, |
1793 | i915_reg_t reg, | |
1794 | u32 mask, | |
1795 | u32 value, | |
1796 | unsigned int fast_timeout_us, | |
1797 | unsigned int slow_timeout_ms, | |
1798 | u32 *out_value) | |
1799 | { | |
1758b90e | 1800 | unsigned fw = |
4319382e | 1801 | intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ); |
23fdbdd7 | 1802 | u32 reg_value; |
1758b90e CW |
1803 | int ret; |
1804 | ||
3df82dd4 | 1805 | might_sleep_if(slow_timeout_ms); |
05646543 | 1806 | |
272c7e52 DCS |
1807 | spin_lock_irq(&uncore->lock); |
1808 | intel_uncore_forcewake_get__locked(uncore, fw); | |
05646543 | 1809 | |
d2d551c0 | 1810 | ret = __intel_wait_for_register_fw(uncore, |
05646543 | 1811 | reg, mask, value, |
23fdbdd7 | 1812 | fast_timeout_us, 0, ®_value); |
05646543 | 1813 | |
272c7e52 DCS |
1814 | intel_uncore_forcewake_put__locked(uncore, fw); |
1815 | spin_unlock_irq(&uncore->lock); | |
05646543 | 1816 | |
3df82dd4 | 1817 | if (ret && slow_timeout_ms) |
d2d551c0 DCS |
1818 | ret = __wait_for(reg_value = intel_uncore_read_notrace(uncore, |
1819 | reg), | |
23fdbdd7 SP |
1820 | (reg_value & mask) == value, |
1821 | slow_timeout_ms * 1000, 10, 1000); | |
1822 | ||
39806c3f VS |
1823 | /* just trace the final value */ |
1824 | trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true); | |
1825 | ||
23fdbdd7 SP |
1826 | if (out_value) |
1827 | *out_value = reg_value; | |
1758b90e CW |
1828 | |
1829 | return ret; | |
d431440c TE |
1830 | } |
1831 | ||
2cf7bf6f | 1832 | bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore) |
907b28c5 | 1833 | { |
2cf7bf6f | 1834 | return check_for_unclaimed_mmio(uncore); |
907b28c5 | 1835 | } |
75714940 | 1836 | |
bc3b9346 | 1837 | bool |
2cf7bf6f | 1838 | intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore) |
75714940 | 1839 | { |
a167b1e1 CW |
1840 | bool ret = false; |
1841 | ||
272c7e52 | 1842 | spin_lock_irq(&uncore->lock); |
a167b1e1 | 1843 | |
272c7e52 | 1844 | if (unlikely(uncore->unclaimed_mmio_check <= 0)) |
a167b1e1 | 1845 | goto out; |
75714940 | 1846 | |
2cf7bf6f | 1847 | if (unlikely(intel_uncore_unclaimed_mmio(uncore))) { |
7ef4ac6e CW |
1848 | if (!i915_modparams.mmio_debug) { |
1849 | DRM_DEBUG("Unclaimed register detected, " | |
1850 | "enabling oneshot unclaimed register reporting. " | |
1851 | "Please use i915.mmio_debug=N for more information.\n"); | |
1852 | i915_modparams.mmio_debug++; | |
1853 | } | |
272c7e52 | 1854 | uncore->unclaimed_mmio_check--; |
a167b1e1 | 1855 | ret = true; |
75714940 | 1856 | } |
bc3b9346 | 1857 | |
a167b1e1 | 1858 | out: |
272c7e52 | 1859 | spin_unlock_irq(&uncore->lock); |
a167b1e1 CW |
1860 | |
1861 | return ret; | |
75714940 | 1862 | } |
3756685a TU |
1863 | |
1864 | static enum forcewake_domains | |
4319382e | 1865 | intel_uncore_forcewake_for_read(struct intel_uncore *uncore, |
3756685a TU |
1866 | i915_reg_t reg) |
1867 | { | |
4319382e | 1868 | struct drm_i915_private *i915 = uncore_to_i915(uncore); |
895833bd | 1869 | u32 offset = i915_mmio_reg_offset(reg); |
3756685a TU |
1870 | enum forcewake_domains fw_domains; |
1871 | ||
4319382e | 1872 | if (INTEL_GEN(i915) >= 11) { |
272c7e52 | 1873 | fw_domains = __gen11_fwtable_reg_read_fw_domains(uncore, offset); |
4319382e | 1874 | } else if (HAS_FWTABLE(i915)) { |
272c7e52 | 1875 | fw_domains = __fwtable_reg_read_fw_domains(uncore, offset); |
4319382e | 1876 | } else if (INTEL_GEN(i915) >= 6) { |
272c7e52 | 1877 | fw_domains = __gen6_reg_read_fw_domains(uncore, offset); |
895833bd | 1878 | } else { |
5a0ba777 DCS |
1879 | /* on devices with FW we expect to hit one of the above cases */ |
1880 | if (intel_uncore_has_forcewake(uncore)) | |
4319382e | 1881 | MISSING_CASE(INTEL_GEN(i915)); |
5a0ba777 | 1882 | |
895833bd | 1883 | fw_domains = 0; |
3756685a TU |
1884 | } |
1885 | ||
272c7e52 | 1886 | WARN_ON(fw_domains & ~uncore->fw_domains); |
3756685a TU |
1887 | |
1888 | return fw_domains; | |
1889 | } | |
1890 | ||
1891 | static enum forcewake_domains | |
4319382e | 1892 | intel_uncore_forcewake_for_write(struct intel_uncore *uncore, |
3756685a TU |
1893 | i915_reg_t reg) |
1894 | { | |
4319382e | 1895 | struct drm_i915_private *i915 = uncore_to_i915(uncore); |
22d48c55 | 1896 | u32 offset = i915_mmio_reg_offset(reg); |
3756685a TU |
1897 | enum forcewake_domains fw_domains; |
1898 | ||
4319382e | 1899 | if (INTEL_GEN(i915) >= 11) { |
272c7e52 | 1900 | fw_domains = __gen11_fwtable_reg_write_fw_domains(uncore, offset); |
4319382e | 1901 | } else if (HAS_FWTABLE(i915) && !IS_VALLEYVIEW(i915)) { |
272c7e52 | 1902 | fw_domains = __fwtable_reg_write_fw_domains(uncore, offset); |
4319382e | 1903 | } else if (IS_GEN(i915, 8)) { |
272c7e52 | 1904 | fw_domains = __gen8_reg_write_fw_domains(uncore, offset); |
4319382e | 1905 | } else if (IS_GEN_RANGE(i915, 6, 7)) { |
3756685a | 1906 | fw_domains = FORCEWAKE_RENDER; |
22d48c55 | 1907 | } else { |
5a0ba777 DCS |
1908 | /* on devices with FW we expect to hit one of the above cases */ |
1909 | if (intel_uncore_has_forcewake(uncore)) | |
4319382e | 1910 | MISSING_CASE(INTEL_GEN(i915)); |
5a0ba777 | 1911 | |
22d48c55 | 1912 | fw_domains = 0; |
3756685a TU |
1913 | } |
1914 | ||
272c7e52 | 1915 | WARN_ON(fw_domains & ~uncore->fw_domains); |
3756685a TU |
1916 | |
1917 | return fw_domains; | |
1918 | } | |
1919 | ||
1920 | /** | |
1921 | * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access | |
1922 | * a register | |
4319382e | 1923 | * @uncore: pointer to struct intel_uncore |
3756685a TU |
1924 | * @reg: register in question |
1925 | * @op: operation bitmask of FW_REG_READ and/or FW_REG_WRITE | |
1926 | * | |
1927 | * Returns a set of forcewake domains required to be taken with for example | |
1928 | * intel_uncore_forcewake_get for the specified register to be accessible in the | |
1929 | * specified mode (read, write or read/write) with raw mmio accessors. | |
1930 | * | |
1931 | * NOTE: On Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the | |
1932 | * callers to do FIFO management on their own or risk losing writes. | |
1933 | */ | |
1934 | enum forcewake_domains | |
4319382e | 1935 | intel_uncore_forcewake_for_reg(struct intel_uncore *uncore, |
3756685a TU |
1936 | i915_reg_t reg, unsigned int op) |
1937 | { | |
1938 | enum forcewake_domains fw_domains = 0; | |
1939 | ||
1940 | WARN_ON(!op); | |
1941 | ||
4319382e | 1942 | if (!intel_uncore_has_forcewake(uncore)) |
895833bd TU |
1943 | return 0; |
1944 | ||
3756685a | 1945 | if (op & FW_REG_READ) |
4319382e | 1946 | fw_domains = intel_uncore_forcewake_for_read(uncore, reg); |
3756685a TU |
1947 | |
1948 | if (op & FW_REG_WRITE) | |
4319382e | 1949 | fw_domains |= intel_uncore_forcewake_for_write(uncore, reg); |
3756685a TU |
1950 | |
1951 | return fw_domains; | |
1952 | } | |
26e7a2a1 CW |
1953 | |
1954 | #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) | |
0757ac8f | 1955 | #include "selftests/mock_uncore.c" |
26e7a2a1 CW |
1956 | #include "selftests/intel_uncore.c" |
1957 | #endif |