Commit | Line | Data |
---|---|---|
b840d907 JB |
1 | /* |
2 | * Copyright © 2011 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
21 | * SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Jesse Barnes <jbarnes@virtuousgeek.org> | |
25 | * | |
26 | * New plane/sprite handling. | |
27 | * | |
28 | * The older chips had a separate interface for programming plane related | |
29 | * registers; newer ones are much simpler and we can use the new DRM plane | |
30 | * support. | |
31 | */ | |
760285e7 DH |
32 | #include <drm/drmP.h> |
33 | #include <drm/drm_crtc.h> | |
34 | #include <drm/drm_fourcc.h> | |
1731693a | 35 | #include <drm/drm_rect.h> |
c331879c | 36 | #include <drm/drm_atomic.h> |
ea2c67bb | 37 | #include <drm/drm_plane_helper.h> |
b840d907 | 38 | #include "intel_drv.h" |
760285e7 | 39 | #include <drm/i915_drm.h> |
b840d907 JB |
40 | #include "i915_drv.h" |
41 | ||
6ca2aeb2 VS |
42 | static bool |
43 | format_is_yuv(uint32_t format) | |
44 | { | |
45 | switch (format) { | |
46 | case DRM_FORMAT_YUYV: | |
47 | case DRM_FORMAT_UYVY: | |
48 | case DRM_FORMAT_VYUY: | |
49 | case DRM_FORMAT_YVYU: | |
50 | return true; | |
51 | default: | |
52 | return false; | |
53 | } | |
54 | } | |
55 | ||
5e7234c9 VS |
56 | static int usecs_to_scanlines(const struct drm_display_mode *adjusted_mode, |
57 | int usecs) | |
8d7849db VS |
58 | { |
59 | /* paranoia */ | |
5e7234c9 | 60 | if (!adjusted_mode->crtc_htotal) |
8d7849db VS |
61 | return 1; |
62 | ||
5e7234c9 VS |
63 | return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock, |
64 | 1000 * adjusted_mode->crtc_htotal); | |
8d7849db VS |
65 | } |
66 | ||
26ff2762 ACO |
67 | /** |
68 | * intel_pipe_update_start() - start update of a set of display registers | |
69 | * @crtc: the crtc of which the registers are going to be updated | |
70 | * @start_vbl_count: vblank counter return pointer used for error checking | |
71 | * | |
72 | * Mark the start of an update to pipe registers that should be updated | |
73 | * atomically regarding vblank. If the next vblank will happens within | |
74 | * the next 100 us, this function waits until the vblank passes. | |
75 | * | |
76 | * After a successful call to this function, interrupts will be disabled | |
77 | * until a subsequent call to intel_pipe_update_end(). That is done to | |
78 | * avoid random delays. The value written to @start_vbl_count should be | |
79 | * supplied to intel_pipe_update_end() for error checking. | |
26ff2762 | 80 | */ |
34e0adbb | 81 | void intel_pipe_update_start(struct intel_crtc *crtc) |
8d7849db VS |
82 | { |
83 | struct drm_device *dev = crtc->base.dev; | |
124abe07 | 84 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
8d7849db VS |
85 | enum pipe pipe = crtc->pipe; |
86 | long timeout = msecs_to_jiffies_timeout(1); | |
87 | int scanline, min, max, vblank_start; | |
210871b6 | 88 | wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base); |
8d7849db VS |
89 | DEFINE_WAIT(wait); |
90 | ||
124abe07 VS |
91 | vblank_start = adjusted_mode->crtc_vblank_start; |
92 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
8d7849db VS |
93 | vblank_start = DIV_ROUND_UP(vblank_start, 2); |
94 | ||
95 | /* FIXME needs to be calibrated sensibly */ | |
124abe07 | 96 | min = vblank_start - usecs_to_scanlines(adjusted_mode, 100); |
8d7849db VS |
97 | max = vblank_start - 1; |
98 | ||
8f539a83 | 99 | local_irq_disable(); |
8f539a83 | 100 | |
8d7849db | 101 | if (min <= 0 || max <= 0) |
8f539a83 | 102 | return; |
8d7849db | 103 | |
1e3feefd | 104 | if (WARN_ON(drm_crtc_vblank_get(&crtc->base))) |
8f539a83 | 105 | return; |
8d7849db | 106 | |
d637ce3f JB |
107 | crtc->debug.min_vbl = min; |
108 | crtc->debug.max_vbl = max; | |
109 | trace_i915_pipe_update_start(crtc); | |
25ef284a | 110 | |
8d7849db VS |
111 | for (;;) { |
112 | /* | |
113 | * prepare_to_wait() has a memory barrier, which guarantees | |
114 | * other CPUs can see the task state update by the time we | |
115 | * read the scanline. | |
116 | */ | |
210871b6 | 117 | prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE); |
8d7849db VS |
118 | |
119 | scanline = intel_get_crtc_scanline(crtc); | |
120 | if (scanline < min || scanline > max) | |
121 | break; | |
122 | ||
123 | if (timeout <= 0) { | |
124 | DRM_ERROR("Potential atomic update failure on pipe %c\n", | |
125 | pipe_name(crtc->pipe)); | |
126 | break; | |
127 | } | |
128 | ||
129 | local_irq_enable(); | |
130 | ||
131 | timeout = schedule_timeout(timeout); | |
132 | ||
133 | local_irq_disable(); | |
134 | } | |
135 | ||
210871b6 | 136 | finish_wait(wq, &wait); |
8d7849db | 137 | |
1e3feefd | 138 | drm_crtc_vblank_put(&crtc->base); |
8d7849db | 139 | |
eb120ef6 JB |
140 | crtc->debug.scanline_start = scanline; |
141 | crtc->debug.start_vbl_time = ktime_get(); | |
142 | crtc->debug.start_vbl_count = | |
143 | dev->driver->get_vblank_counter(dev, pipe); | |
8d7849db | 144 | |
d637ce3f | 145 | trace_i915_pipe_update_vblank_evaded(crtc); |
8d7849db VS |
146 | } |
147 | ||
26ff2762 ACO |
148 | /** |
149 | * intel_pipe_update_end() - end update of a set of display registers | |
150 | * @crtc: the crtc of which the registers were updated | |
151 | * @start_vbl_count: start vblank counter (used for error checking) | |
152 | * | |
153 | * Mark the end of an update started with intel_pipe_update_start(). This | |
154 | * re-enables interrupts and verifies the update was actually completed | |
155 | * before a vblank using the value of @start_vbl_count. | |
156 | */ | |
34e0adbb | 157 | void intel_pipe_update_end(struct intel_crtc *crtc) |
8d7849db VS |
158 | { |
159 | struct drm_device *dev = crtc->base.dev; | |
160 | enum pipe pipe = crtc->pipe; | |
eb120ef6 | 161 | int scanline_end = intel_get_crtc_scanline(crtc); |
8d7849db | 162 | u32 end_vbl_count = dev->driver->get_vblank_counter(dev, pipe); |
85a62bf9 | 163 | ktime_t end_vbl_time = ktime_get(); |
8d7849db | 164 | |
d637ce3f | 165 | trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end); |
25ef284a | 166 | |
8d7849db VS |
167 | local_irq_enable(); |
168 | ||
eb120ef6 JB |
169 | if (crtc->debug.start_vbl_count && |
170 | crtc->debug.start_vbl_count != end_vbl_count) { | |
171 | DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n", | |
172 | pipe_name(pipe), crtc->debug.start_vbl_count, | |
173 | end_vbl_count, | |
174 | ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time), | |
175 | crtc->debug.min_vbl, crtc->debug.max_vbl, | |
176 | crtc->debug.scanline_start, scanline_end); | |
177 | } | |
8d7849db VS |
178 | } |
179 | ||
dc2a41b4 DL |
180 | static void |
181 | skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, | |
182 | struct drm_framebuffer *fb, | |
bdd7554d | 183 | int crtc_x, int crtc_y, |
dc2a41b4 DL |
184 | unsigned int crtc_w, unsigned int crtc_h, |
185 | uint32_t x, uint32_t y, | |
186 | uint32_t src_w, uint32_t src_h) | |
187 | { | |
188 | struct drm_device *dev = drm_plane->dev; | |
189 | struct drm_i915_private *dev_priv = dev->dev_private; | |
190 | struct intel_plane *intel_plane = to_intel_plane(drm_plane); | |
bdd7554d | 191 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
dc2a41b4 DL |
192 | const int pipe = intel_plane->pipe; |
193 | const int plane = intel_plane->plane + 1; | |
3b7a5119 | 194 | u32 plane_ctl, stride_div, stride; |
818ed961 ML |
195 | const struct drm_intel_sprite_colorkey *key = |
196 | &to_intel_plane_state(drm_plane->state)->ckey; | |
44eb0cb9 | 197 | u32 surf_addr; |
3b7a5119 SJ |
198 | u32 tile_height, plane_offset, plane_size; |
199 | unsigned int rotation; | |
200 | int x_offset, y_offset; | |
c331879c CK |
201 | struct intel_crtc_state *crtc_state = to_intel_crtc(crtc)->config; |
202 | int scaler_id; | |
dc2a41b4 | 203 | |
48fe4691 | 204 | plane_ctl = PLANE_CTL_ENABLE | |
e12c8ce8 | 205 | PLANE_CTL_PIPE_GAMMA_ENABLE | |
48fe4691 | 206 | PLANE_CTL_PIPE_CSC_ENABLE; |
dc2a41b4 | 207 | |
c331879c CK |
208 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); |
209 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); | |
b321803d | 210 | |
3b7a5119 | 211 | rotation = drm_plane->state->rotation; |
c331879c | 212 | plane_ctl |= skl_plane_ctl_rotation(rotation); |
dc2a41b4 | 213 | |
b321803d DL |
214 | stride_div = intel_fb_stride_alignment(dev, fb->modifier[0], |
215 | fb->pixel_format); | |
216 | ||
c331879c CK |
217 | scaler_id = to_intel_plane_state(drm_plane->state)->scaler_id; |
218 | ||
dc2a41b4 DL |
219 | /* Sizes are 0 based */ |
220 | src_w--; | |
221 | src_h--; | |
222 | crtc_w--; | |
223 | crtc_h--; | |
224 | ||
47ecbb20 VS |
225 | if (key->flags) { |
226 | I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value); | |
227 | I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value); | |
228 | I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask); | |
229 | } | |
230 | ||
231 | if (key->flags & I915_SET_COLORKEY_DESTINATION) | |
232 | plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION; | |
233 | else if (key->flags & I915_SET_COLORKEY_SOURCE) | |
234 | plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE; | |
235 | ||
dedf278c | 236 | surf_addr = intel_plane_obj_offset(intel_plane, obj, 0); |
121920fa | 237 | |
3b7a5119 SJ |
238 | if (intel_rotation_90_or_270(rotation)) { |
239 | /* stride: Surface height in tiles */ | |
2614f17d | 240 | tile_height = intel_tile_height(dev, fb->pixel_format, |
fe47ea0c | 241 | fb->modifier[0], 0); |
3b7a5119 SJ |
242 | stride = DIV_ROUND_UP(fb->height, tile_height); |
243 | plane_size = (src_w << 16) | src_h; | |
244 | x_offset = stride * tile_height - y - (src_h + 1); | |
245 | y_offset = x; | |
246 | } else { | |
247 | stride = fb->pitches[0] / stride_div; | |
248 | plane_size = (src_h << 16) | src_w; | |
249 | x_offset = x; | |
250 | y_offset = y; | |
251 | } | |
252 | plane_offset = y_offset << 16 | x_offset; | |
253 | ||
254 | I915_WRITE(PLANE_OFFSET(pipe, plane), plane_offset); | |
255 | I915_WRITE(PLANE_STRIDE(pipe, plane), stride); | |
3b7a5119 | 256 | I915_WRITE(PLANE_SIZE(pipe, plane), plane_size); |
c331879c CK |
257 | |
258 | /* program plane scaler */ | |
259 | if (scaler_id >= 0) { | |
260 | uint32_t ps_ctrl = 0; | |
261 | ||
262 | DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane, | |
263 | PS_PLANE_SEL(plane)); | |
264 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane) | | |
265 | crtc_state->scaler_state.scalers[scaler_id].mode; | |
266 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
267 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
268 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y); | |
269 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), | |
270 | ((crtc_w + 1) << 16)|(crtc_h + 1)); | |
271 | ||
272 | I915_WRITE(PLANE_POS(pipe, plane), 0); | |
273 | } else { | |
274 | I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x); | |
275 | } | |
276 | ||
dc2a41b4 | 277 | I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl); |
121920fa | 278 | I915_WRITE(PLANE_SURF(pipe, plane), surf_addr); |
dc2a41b4 DL |
279 | POSTING_READ(PLANE_SURF(pipe, plane)); |
280 | } | |
281 | ||
282 | static void | |
7fabf5ef | 283 | skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc) |
dc2a41b4 | 284 | { |
a8ad0d8e | 285 | struct drm_device *dev = dplane->dev; |
dc2a41b4 | 286 | struct drm_i915_private *dev_priv = dev->dev_private; |
a8ad0d8e | 287 | struct intel_plane *intel_plane = to_intel_plane(dplane); |
dc2a41b4 DL |
288 | const int pipe = intel_plane->pipe; |
289 | const int plane = intel_plane->plane + 1; | |
290 | ||
48fe4691 | 291 | I915_WRITE(PLANE_CTL(pipe, plane), 0); |
dc2a41b4 | 292 | |
2ddc1dad VS |
293 | I915_WRITE(PLANE_SURF(pipe, plane), 0); |
294 | POSTING_READ(PLANE_SURF(pipe, plane)); | |
dc2a41b4 DL |
295 | } |
296 | ||
6ca2aeb2 VS |
297 | static void |
298 | chv_update_csc(struct intel_plane *intel_plane, uint32_t format) | |
299 | { | |
300 | struct drm_i915_private *dev_priv = intel_plane->base.dev->dev_private; | |
301 | int plane = intel_plane->plane; | |
302 | ||
303 | /* Seems RGB data bypasses the CSC always */ | |
304 | if (!format_is_yuv(format)) | |
305 | return; | |
306 | ||
307 | /* | |
308 | * BT.601 limited range YCbCr -> full range RGB | |
309 | * | |
310 | * |r| | 6537 4769 0| |cr | | |
311 | * |g| = |-3330 4769 -1605| x |y-64| | |
312 | * |b| | 0 4769 8263| |cb | | |
313 | * | |
314 | * Cb and Cr apparently come in as signed already, so no | |
315 | * need for any offset. For Y we need to remove the offset. | |
316 | */ | |
317 | I915_WRITE(SPCSCYGOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(-64)); | |
318 | I915_WRITE(SPCSCCBOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0)); | |
319 | I915_WRITE(SPCSCCROFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0)); | |
320 | ||
321 | I915_WRITE(SPCSCC01(plane), SPCSC_C1(4769) | SPCSC_C0(6537)); | |
322 | I915_WRITE(SPCSCC23(plane), SPCSC_C1(-3330) | SPCSC_C0(0)); | |
323 | I915_WRITE(SPCSCC45(plane), SPCSC_C1(-1605) | SPCSC_C0(4769)); | |
324 | I915_WRITE(SPCSCC67(plane), SPCSC_C1(4769) | SPCSC_C0(0)); | |
325 | I915_WRITE(SPCSCC8(plane), SPCSC_C0(8263)); | |
326 | ||
327 | I915_WRITE(SPCSCYGICLAMP(plane), SPCSC_IMAX(940) | SPCSC_IMIN(64)); | |
328 | I915_WRITE(SPCSCCBICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448)); | |
329 | I915_WRITE(SPCSCCRICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448)); | |
330 | ||
331 | I915_WRITE(SPCSCYGOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); | |
332 | I915_WRITE(SPCSCCBOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); | |
333 | I915_WRITE(SPCSCCROCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); | |
334 | } | |
335 | ||
7f1f3851 | 336 | static void |
b39d53f6 VS |
337 | vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc, |
338 | struct drm_framebuffer *fb, | |
bdd7554d | 339 | int crtc_x, int crtc_y, |
7f1f3851 JB |
340 | unsigned int crtc_w, unsigned int crtc_h, |
341 | uint32_t x, uint32_t y, | |
342 | uint32_t src_w, uint32_t src_h) | |
343 | { | |
344 | struct drm_device *dev = dplane->dev; | |
345 | struct drm_i915_private *dev_priv = dev->dev_private; | |
346 | struct intel_plane *intel_plane = to_intel_plane(dplane); | |
bdd7554d | 347 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
7f1f3851 JB |
348 | int pipe = intel_plane->pipe; |
349 | int plane = intel_plane->plane; | |
350 | u32 sprctl; | |
351 | unsigned long sprsurf_offset, linear_offset; | |
352 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
818ed961 ML |
353 | const struct drm_intel_sprite_colorkey *key = |
354 | &to_intel_plane_state(dplane->state)->ckey; | |
7f1f3851 | 355 | |
48fe4691 | 356 | sprctl = SP_ENABLE; |
7f1f3851 JB |
357 | |
358 | switch (fb->pixel_format) { | |
359 | case DRM_FORMAT_YUYV: | |
360 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV; | |
361 | break; | |
362 | case DRM_FORMAT_YVYU: | |
363 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU; | |
364 | break; | |
365 | case DRM_FORMAT_UYVY: | |
366 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY; | |
367 | break; | |
368 | case DRM_FORMAT_VYUY: | |
369 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY; | |
370 | break; | |
371 | case DRM_FORMAT_RGB565: | |
372 | sprctl |= SP_FORMAT_BGR565; | |
373 | break; | |
374 | case DRM_FORMAT_XRGB8888: | |
375 | sprctl |= SP_FORMAT_BGRX8888; | |
376 | break; | |
377 | case DRM_FORMAT_ARGB8888: | |
378 | sprctl |= SP_FORMAT_BGRA8888; | |
379 | break; | |
380 | case DRM_FORMAT_XBGR2101010: | |
381 | sprctl |= SP_FORMAT_RGBX1010102; | |
382 | break; | |
383 | case DRM_FORMAT_ABGR2101010: | |
384 | sprctl |= SP_FORMAT_RGBA1010102; | |
385 | break; | |
386 | case DRM_FORMAT_XBGR8888: | |
387 | sprctl |= SP_FORMAT_RGBX8888; | |
388 | break; | |
389 | case DRM_FORMAT_ABGR8888: | |
390 | sprctl |= SP_FORMAT_RGBA8888; | |
391 | break; | |
392 | default: | |
393 | /* | |
394 | * If we get here one of the upper layers failed to filter | |
395 | * out the unsupported plane formats | |
396 | */ | |
397 | BUG(); | |
398 | break; | |
399 | } | |
400 | ||
4ea67bc7 VS |
401 | /* |
402 | * Enable gamma to match primary/cursor plane behaviour. | |
403 | * FIXME should be user controllable via propertiesa. | |
404 | */ | |
405 | sprctl |= SP_GAMMA_ENABLE; | |
406 | ||
7f1f3851 JB |
407 | if (obj->tiling_mode != I915_TILING_NONE) |
408 | sprctl |= SP_TILED; | |
409 | ||
7f1f3851 JB |
410 | /* Sizes are 0 based */ |
411 | src_w--; | |
412 | src_h--; | |
413 | crtc_w--; | |
414 | crtc_h--; | |
415 | ||
7f1f3851 | 416 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
4e9a86b6 VS |
417 | sprsurf_offset = intel_gen4_compute_page_offset(dev_priv, |
418 | &x, &y, | |
7f1f3851 JB |
419 | obj->tiling_mode, |
420 | pixel_size, | |
421 | fb->pitches[0]); | |
422 | linear_offset -= sprsurf_offset; | |
423 | ||
8e7d688b | 424 | if (dplane->state->rotation == BIT(DRM_ROTATE_180)) { |
76eebda7 VS |
425 | sprctl |= SP_ROTATE_180; |
426 | ||
427 | x += src_w; | |
428 | y += src_h; | |
429 | linear_offset += src_h * fb->pitches[0] + src_w * pixel_size; | |
430 | } | |
431 | ||
47ecbb20 VS |
432 | if (key->flags) { |
433 | I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value); | |
434 | I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value); | |
435 | I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask); | |
436 | } | |
437 | ||
438 | if (key->flags & I915_SET_COLORKEY_SOURCE) | |
439 | sprctl |= SP_SOURCE_KEY; | |
440 | ||
6ca2aeb2 VS |
441 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) |
442 | chv_update_csc(intel_plane, fb->pixel_format); | |
443 | ||
ca6ad025 VS |
444 | I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]); |
445 | I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x); | |
446 | ||
7f1f3851 JB |
447 | if (obj->tiling_mode != I915_TILING_NONE) |
448 | I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x); | |
449 | else | |
450 | I915_WRITE(SPLINOFF(pipe, plane), linear_offset); | |
451 | ||
c14b0485 VS |
452 | I915_WRITE(SPCONSTALPHA(pipe, plane), 0); |
453 | ||
7f1f3851 JB |
454 | I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w); |
455 | I915_WRITE(SPCNTR(pipe, plane), sprctl); | |
85ba7b7d DV |
456 | I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) + |
457 | sprsurf_offset); | |
b12ce1d8 | 458 | POSTING_READ(SPSURF(pipe, plane)); |
7f1f3851 JB |
459 | } |
460 | ||
461 | static void | |
7fabf5ef | 462 | vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc) |
7f1f3851 JB |
463 | { |
464 | struct drm_device *dev = dplane->dev; | |
465 | struct drm_i915_private *dev_priv = dev->dev_private; | |
466 | struct intel_plane *intel_plane = to_intel_plane(dplane); | |
467 | int pipe = intel_plane->pipe; | |
468 | int plane = intel_plane->plane; | |
469 | ||
48fe4691 VS |
470 | I915_WRITE(SPCNTR(pipe, plane), 0); |
471 | ||
85ba7b7d | 472 | I915_WRITE(SPSURF(pipe, plane), 0); |
b12ce1d8 | 473 | POSTING_READ(SPSURF(pipe, plane)); |
7f1f3851 JB |
474 | } |
475 | ||
b840d907 | 476 | static void |
b39d53f6 VS |
477 | ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, |
478 | struct drm_framebuffer *fb, | |
bdd7554d | 479 | int crtc_x, int crtc_y, |
b840d907 JB |
480 | unsigned int crtc_w, unsigned int crtc_h, |
481 | uint32_t x, uint32_t y, | |
482 | uint32_t src_w, uint32_t src_h) | |
483 | { | |
484 | struct drm_device *dev = plane->dev; | |
485 | struct drm_i915_private *dev_priv = dev->dev_private; | |
486 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
bdd7554d | 487 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
47ecbb20 | 488 | enum pipe pipe = intel_plane->pipe; |
b840d907 | 489 | u32 sprctl, sprscale = 0; |
5a35e99e | 490 | unsigned long sprsurf_offset, linear_offset; |
2bd3c3cb | 491 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
818ed961 ML |
492 | const struct drm_intel_sprite_colorkey *key = |
493 | &to_intel_plane_state(plane->state)->ckey; | |
b840d907 | 494 | |
48fe4691 | 495 | sprctl = SPRITE_ENABLE; |
b840d907 JB |
496 | |
497 | switch (fb->pixel_format) { | |
498 | case DRM_FORMAT_XBGR8888: | |
5ee36913 | 499 | sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX; |
b840d907 JB |
500 | break; |
501 | case DRM_FORMAT_XRGB8888: | |
5ee36913 | 502 | sprctl |= SPRITE_FORMAT_RGBX888; |
b840d907 JB |
503 | break; |
504 | case DRM_FORMAT_YUYV: | |
505 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV; | |
b840d907 JB |
506 | break; |
507 | case DRM_FORMAT_YVYU: | |
508 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU; | |
b840d907 JB |
509 | break; |
510 | case DRM_FORMAT_UYVY: | |
511 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY; | |
b840d907 JB |
512 | break; |
513 | case DRM_FORMAT_VYUY: | |
514 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY; | |
b840d907 JB |
515 | break; |
516 | default: | |
28d491df | 517 | BUG(); |
b840d907 JB |
518 | } |
519 | ||
4ea67bc7 VS |
520 | /* |
521 | * Enable gamma to match primary/cursor plane behaviour. | |
522 | * FIXME should be user controllable via propertiesa. | |
523 | */ | |
524 | sprctl |= SPRITE_GAMMA_ENABLE; | |
525 | ||
b840d907 JB |
526 | if (obj->tiling_mode != I915_TILING_NONE) |
527 | sprctl |= SPRITE_TILED; | |
528 | ||
b42c6009 | 529 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
1f5d76db PZ |
530 | sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE; |
531 | else | |
532 | sprctl |= SPRITE_TRICKLE_FEED_DISABLE; | |
533 | ||
6bbfa1c5 | 534 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
86d3efce VS |
535 | sprctl |= SPRITE_PIPE_CSC_ENABLE; |
536 | ||
b840d907 JB |
537 | /* Sizes are 0 based */ |
538 | src_w--; | |
539 | src_h--; | |
540 | crtc_w--; | |
541 | crtc_h--; | |
542 | ||
8553c18e | 543 | if (crtc_w != src_w || crtc_h != src_h) |
b840d907 | 544 | sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h; |
b840d907 | 545 | |
ca320ac4 | 546 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
5a35e99e | 547 | sprsurf_offset = |
4e9a86b6 VS |
548 | intel_gen4_compute_page_offset(dev_priv, |
549 | &x, &y, obj->tiling_mode, | |
bc752862 | 550 | pixel_size, fb->pitches[0]); |
5a35e99e DL |
551 | linear_offset -= sprsurf_offset; |
552 | ||
8e7d688b | 553 | if (plane->state->rotation == BIT(DRM_ROTATE_180)) { |
76eebda7 VS |
554 | sprctl |= SPRITE_ROTATE_180; |
555 | ||
556 | /* HSW and BDW does this automagically in hardware */ | |
557 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
558 | x += src_w; | |
559 | y += src_h; | |
560 | linear_offset += src_h * fb->pitches[0] + | |
561 | src_w * pixel_size; | |
562 | } | |
563 | } | |
564 | ||
47ecbb20 VS |
565 | if (key->flags) { |
566 | I915_WRITE(SPRKEYVAL(pipe), key->min_value); | |
567 | I915_WRITE(SPRKEYMAX(pipe), key->max_value); | |
568 | I915_WRITE(SPRKEYMSK(pipe), key->channel_mask); | |
569 | } | |
570 | ||
571 | if (key->flags & I915_SET_COLORKEY_DESTINATION) | |
572 | sprctl |= SPRITE_DEST_KEY; | |
573 | else if (key->flags & I915_SET_COLORKEY_SOURCE) | |
574 | sprctl |= SPRITE_SOURCE_KEY; | |
575 | ||
ca6ad025 VS |
576 | I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]); |
577 | I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x); | |
578 | ||
5a35e99e DL |
579 | /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET |
580 | * register */ | |
b3dc685e | 581 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
c54173a8 | 582 | I915_WRITE(SPROFFSET(pipe), (y << 16) | x); |
5a35e99e | 583 | else if (obj->tiling_mode != I915_TILING_NONE) |
b840d907 | 584 | I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x); |
5a35e99e DL |
585 | else |
586 | I915_WRITE(SPRLINOFF(pipe), linear_offset); | |
c54173a8 | 587 | |
b840d907 | 588 | I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w); |
2d354c34 DL |
589 | if (intel_plane->can_scale) |
590 | I915_WRITE(SPRSCALE(pipe), sprscale); | |
b840d907 | 591 | I915_WRITE(SPRCTL(pipe), sprctl); |
85ba7b7d DV |
592 | I915_WRITE(SPRSURF(pipe), |
593 | i915_gem_obj_ggtt_offset(obj) + sprsurf_offset); | |
b12ce1d8 | 594 | POSTING_READ(SPRSURF(pipe)); |
b840d907 JB |
595 | } |
596 | ||
597 | static void | |
7fabf5ef | 598 | ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc) |
b840d907 JB |
599 | { |
600 | struct drm_device *dev = plane->dev; | |
601 | struct drm_i915_private *dev_priv = dev->dev_private; | |
602 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
603 | int pipe = intel_plane->pipe; | |
604 | ||
c562657a | 605 | I915_WRITE(SPRCTL(pipe), 0); |
b840d907 | 606 | /* Can't leave the scaler enabled... */ |
2d354c34 DL |
607 | if (intel_plane->can_scale) |
608 | I915_WRITE(SPRSCALE(pipe), 0); | |
5b633d6b | 609 | |
b12ce1d8 VS |
610 | I915_WRITE(SPRSURF(pipe), 0); |
611 | POSTING_READ(SPRSURF(pipe)); | |
b840d907 JB |
612 | } |
613 | ||
614 | static void | |
b39d53f6 VS |
615 | ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, |
616 | struct drm_framebuffer *fb, | |
bdd7554d | 617 | int crtc_x, int crtc_y, |
b840d907 JB |
618 | unsigned int crtc_w, unsigned int crtc_h, |
619 | uint32_t x, uint32_t y, | |
620 | uint32_t src_w, uint32_t src_h) | |
621 | { | |
622 | struct drm_device *dev = plane->dev; | |
623 | struct drm_i915_private *dev_priv = dev->dev_private; | |
624 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
bdd7554d | 625 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
2bd3c3cb | 626 | int pipe = intel_plane->pipe; |
5a35e99e | 627 | unsigned long dvssurf_offset, linear_offset; |
8aaa81a1 | 628 | u32 dvscntr, dvsscale; |
2bd3c3cb | 629 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
818ed961 ML |
630 | const struct drm_intel_sprite_colorkey *key = |
631 | &to_intel_plane_state(plane->state)->ckey; | |
b840d907 | 632 | |
48fe4691 | 633 | dvscntr = DVS_ENABLE; |
b840d907 JB |
634 | |
635 | switch (fb->pixel_format) { | |
636 | case DRM_FORMAT_XBGR8888: | |
ab2f9df1 | 637 | dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR; |
b840d907 JB |
638 | break; |
639 | case DRM_FORMAT_XRGB8888: | |
ab2f9df1 | 640 | dvscntr |= DVS_FORMAT_RGBX888; |
b840d907 JB |
641 | break; |
642 | case DRM_FORMAT_YUYV: | |
643 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV; | |
b840d907 JB |
644 | break; |
645 | case DRM_FORMAT_YVYU: | |
646 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU; | |
b840d907 JB |
647 | break; |
648 | case DRM_FORMAT_UYVY: | |
649 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY; | |
b840d907 JB |
650 | break; |
651 | case DRM_FORMAT_VYUY: | |
652 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY; | |
b840d907 JB |
653 | break; |
654 | default: | |
28d491df | 655 | BUG(); |
b840d907 JB |
656 | } |
657 | ||
4ea67bc7 VS |
658 | /* |
659 | * Enable gamma to match primary/cursor plane behaviour. | |
660 | * FIXME should be user controllable via propertiesa. | |
661 | */ | |
662 | dvscntr |= DVS_GAMMA_ENABLE; | |
663 | ||
b840d907 JB |
664 | if (obj->tiling_mode != I915_TILING_NONE) |
665 | dvscntr |= DVS_TILED; | |
666 | ||
d1686ae3 CW |
667 | if (IS_GEN6(dev)) |
668 | dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */ | |
b840d907 JB |
669 | |
670 | /* Sizes are 0 based */ | |
671 | src_w--; | |
672 | src_h--; | |
673 | crtc_w--; | |
674 | crtc_h--; | |
675 | ||
8aaa81a1 | 676 | dvsscale = 0; |
8368f014 | 677 | if (crtc_w != src_w || crtc_h != src_h) |
b840d907 JB |
678 | dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h; |
679 | ||
ca320ac4 | 680 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
5a35e99e | 681 | dvssurf_offset = |
4e9a86b6 VS |
682 | intel_gen4_compute_page_offset(dev_priv, |
683 | &x, &y, obj->tiling_mode, | |
bc752862 | 684 | pixel_size, fb->pitches[0]); |
5a35e99e DL |
685 | linear_offset -= dvssurf_offset; |
686 | ||
8e7d688b | 687 | if (plane->state->rotation == BIT(DRM_ROTATE_180)) { |
76eebda7 VS |
688 | dvscntr |= DVS_ROTATE_180; |
689 | ||
690 | x += src_w; | |
691 | y += src_h; | |
692 | linear_offset += src_h * fb->pitches[0] + src_w * pixel_size; | |
693 | } | |
694 | ||
47ecbb20 VS |
695 | if (key->flags) { |
696 | I915_WRITE(DVSKEYVAL(pipe), key->min_value); | |
697 | I915_WRITE(DVSKEYMAX(pipe), key->max_value); | |
698 | I915_WRITE(DVSKEYMSK(pipe), key->channel_mask); | |
699 | } | |
700 | ||
701 | if (key->flags & I915_SET_COLORKEY_DESTINATION) | |
702 | dvscntr |= DVS_DEST_KEY; | |
703 | else if (key->flags & I915_SET_COLORKEY_SOURCE) | |
704 | dvscntr |= DVS_SOURCE_KEY; | |
705 | ||
ca6ad025 VS |
706 | I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]); |
707 | I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x); | |
708 | ||
5a35e99e | 709 | if (obj->tiling_mode != I915_TILING_NONE) |
b840d907 | 710 | I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x); |
5a35e99e DL |
711 | else |
712 | I915_WRITE(DVSLINOFF(pipe), linear_offset); | |
b840d907 | 713 | |
b840d907 JB |
714 | I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w); |
715 | I915_WRITE(DVSSCALE(pipe), dvsscale); | |
716 | I915_WRITE(DVSCNTR(pipe), dvscntr); | |
85ba7b7d DV |
717 | I915_WRITE(DVSSURF(pipe), |
718 | i915_gem_obj_ggtt_offset(obj) + dvssurf_offset); | |
b12ce1d8 | 719 | POSTING_READ(DVSSURF(pipe)); |
b840d907 JB |
720 | } |
721 | ||
722 | static void | |
7fabf5ef | 723 | ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc) |
b840d907 JB |
724 | { |
725 | struct drm_device *dev = plane->dev; | |
726 | struct drm_i915_private *dev_priv = dev->dev_private; | |
727 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
728 | int pipe = intel_plane->pipe; | |
729 | ||
48fe4691 | 730 | I915_WRITE(DVSCNTR(pipe), 0); |
b840d907 JB |
731 | /* Disable the scaler */ |
732 | I915_WRITE(DVSSCALE(pipe), 0); | |
48fe4691 | 733 | |
85ba7b7d | 734 | I915_WRITE(DVSSURF(pipe), 0); |
b12ce1d8 | 735 | POSTING_READ(DVSSURF(pipe)); |
b840d907 JB |
736 | } |
737 | ||
738 | static int | |
96d61a7f | 739 | intel_check_sprite_plane(struct drm_plane *plane, |
061e4b8d | 740 | struct intel_crtc_state *crtc_state, |
96d61a7f | 741 | struct intel_plane_state *state) |
b840d907 | 742 | { |
c331879c | 743 | struct drm_device *dev = plane->dev; |
061e4b8d ML |
744 | struct drm_crtc *crtc = state->base.crtc; |
745 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b840d907 | 746 | struct intel_plane *intel_plane = to_intel_plane(plane); |
2b875c22 | 747 | struct drm_framebuffer *fb = state->base.fb; |
96d61a7f GP |
748 | int crtc_x, crtc_y; |
749 | unsigned int crtc_w, crtc_h; | |
750 | uint32_t src_x, src_y, src_w, src_h; | |
751 | struct drm_rect *src = &state->src; | |
752 | struct drm_rect *dst = &state->dst; | |
96d61a7f | 753 | const struct drm_rect *clip = &state->clip; |
1731693a VS |
754 | int hscale, vscale; |
755 | int max_scale, min_scale; | |
225c228a | 756 | bool can_scale; |
cf4c7c12 MR |
757 | int pixel_size; |
758 | ||
759 | if (!fb) { | |
760 | state->visible = false; | |
da20eabd | 761 | return 0; |
cf4c7c12 | 762 | } |
5e1bac2f | 763 | |
1731693a VS |
764 | /* Don't modify another pipe's plane */ |
765 | if (intel_plane->pipe != intel_crtc->pipe) { | |
766 | DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n"); | |
b840d907 | 767 | return -EINVAL; |
1731693a | 768 | } |
b840d907 | 769 | |
1731693a VS |
770 | /* FIXME check all gen limits */ |
771 | if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) { | |
772 | DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n"); | |
b840d907 | 773 | return -EINVAL; |
1731693a | 774 | } |
b840d907 | 775 | |
225c228a CK |
776 | /* setup can_scale, min_scale, max_scale */ |
777 | if (INTEL_INFO(dev)->gen >= 9) { | |
778 | /* use scaler when colorkey is not required */ | |
818ed961 | 779 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { |
225c228a CK |
780 | can_scale = 1; |
781 | min_scale = 1; | |
782 | max_scale = skl_max_scale(intel_crtc, crtc_state); | |
783 | } else { | |
784 | can_scale = 0; | |
785 | min_scale = DRM_PLANE_HELPER_NO_SCALING; | |
786 | max_scale = DRM_PLANE_HELPER_NO_SCALING; | |
787 | } | |
788 | } else { | |
789 | can_scale = intel_plane->can_scale; | |
790 | max_scale = intel_plane->max_downscale << 16; | |
791 | min_scale = intel_plane->can_scale ? 1 : (1 << 16); | |
792 | } | |
793 | ||
3c3686cd VS |
794 | /* |
795 | * FIXME the following code does a bunch of fuzzy adjustments to the | |
796 | * coordinates and sizes. We probably need some way to decide whether | |
797 | * more strict checking should be done instead. | |
798 | */ | |
96d61a7f | 799 | drm_rect_rotate(src, fb->width << 16, fb->height << 16, |
8e7d688b | 800 | state->base.rotation); |
76eebda7 | 801 | |
96d61a7f | 802 | hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale); |
3c3686cd | 803 | BUG_ON(hscale < 0); |
1731693a | 804 | |
96d61a7f | 805 | vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale); |
3c3686cd | 806 | BUG_ON(vscale < 0); |
b840d907 | 807 | |
818ed961 | 808 | state->visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale); |
b840d907 | 809 | |
96d61a7f GP |
810 | crtc_x = dst->x1; |
811 | crtc_y = dst->y1; | |
812 | crtc_w = drm_rect_width(dst); | |
813 | crtc_h = drm_rect_height(dst); | |
2d354c34 | 814 | |
96d61a7f | 815 | if (state->visible) { |
3c3686cd | 816 | /* check again in case clipping clamped the results */ |
96d61a7f | 817 | hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale); |
3c3686cd VS |
818 | if (hscale < 0) { |
819 | DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n"); | |
c70f577a VS |
820 | drm_rect_debug_print("src: ", src, true); |
821 | drm_rect_debug_print("dst: ", dst, false); | |
3c3686cd VS |
822 | |
823 | return hscale; | |
824 | } | |
825 | ||
96d61a7f | 826 | vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale); |
3c3686cd VS |
827 | if (vscale < 0) { |
828 | DRM_DEBUG_KMS("Vertical scaling factor out of limits\n"); | |
c70f577a VS |
829 | drm_rect_debug_print("src: ", src, true); |
830 | drm_rect_debug_print("dst: ", dst, false); | |
3c3686cd VS |
831 | |
832 | return vscale; | |
833 | } | |
834 | ||
1731693a | 835 | /* Make the source viewport size an exact multiple of the scaling factors. */ |
96d61a7f GP |
836 | drm_rect_adjust_size(src, |
837 | drm_rect_width(dst) * hscale - drm_rect_width(src), | |
838 | drm_rect_height(dst) * vscale - drm_rect_height(src)); | |
1731693a | 839 | |
96d61a7f | 840 | drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16, |
8e7d688b | 841 | state->base.rotation); |
76eebda7 | 842 | |
1731693a | 843 | /* sanity check to make sure the src viewport wasn't enlarged */ |
ea2c67bb MR |
844 | WARN_ON(src->x1 < (int) state->base.src_x || |
845 | src->y1 < (int) state->base.src_y || | |
846 | src->x2 > (int) state->base.src_x + state->base.src_w || | |
847 | src->y2 > (int) state->base.src_y + state->base.src_h); | |
1731693a VS |
848 | |
849 | /* | |
850 | * Hardware doesn't handle subpixel coordinates. | |
851 | * Adjust to (macro)pixel boundary, but be careful not to | |
852 | * increase the source viewport size, because that could | |
853 | * push the downscaling factor out of bounds. | |
1731693a | 854 | */ |
96d61a7f GP |
855 | src_x = src->x1 >> 16; |
856 | src_w = drm_rect_width(src) >> 16; | |
857 | src_y = src->y1 >> 16; | |
858 | src_h = drm_rect_height(src) >> 16; | |
1731693a VS |
859 | |
860 | if (format_is_yuv(fb->pixel_format)) { | |
861 | src_x &= ~1; | |
862 | src_w &= ~1; | |
863 | ||
864 | /* | |
865 | * Must keep src and dst the | |
866 | * same if we can't scale. | |
867 | */ | |
225c228a | 868 | if (!can_scale) |
1731693a VS |
869 | crtc_w &= ~1; |
870 | ||
871 | if (crtc_w == 0) | |
96d61a7f | 872 | state->visible = false; |
1731693a VS |
873 | } |
874 | } | |
875 | ||
876 | /* Check size restrictions when scaling */ | |
96d61a7f | 877 | if (state->visible && (src_w != crtc_w || src_h != crtc_h)) { |
1731693a VS |
878 | unsigned int width_bytes; |
879 | ||
225c228a | 880 | WARN_ON(!can_scale); |
1731693a VS |
881 | |
882 | /* FIXME interlacing min height is 6 */ | |
883 | ||
884 | if (crtc_w < 3 || crtc_h < 3) | |
96d61a7f | 885 | state->visible = false; |
1731693a VS |
886 | |
887 | if (src_w < 3 || src_h < 3) | |
96d61a7f | 888 | state->visible = false; |
1731693a | 889 | |
cf4c7c12 | 890 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
96d61a7f GP |
891 | width_bytes = ((src_x * pixel_size) & 63) + |
892 | src_w * pixel_size; | |
1731693a | 893 | |
c331879c CK |
894 | if (INTEL_INFO(dev)->gen < 9 && (src_w > 2048 || src_h > 2048 || |
895 | width_bytes > 4096 || fb->pitches[0] > 4096)) { | |
1731693a VS |
896 | DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n"); |
897 | return -EINVAL; | |
898 | } | |
899 | } | |
900 | ||
96d61a7f | 901 | if (state->visible) { |
0a5ae1b0 CK |
902 | src->x1 = src_x << 16; |
903 | src->x2 = (src_x + src_w) << 16; | |
904 | src->y1 = src_y << 16; | |
905 | src->y2 = (src_y + src_h) << 16; | |
96d61a7f GP |
906 | } |
907 | ||
908 | dst->x1 = crtc_x; | |
909 | dst->x2 = crtc_x + crtc_w; | |
910 | dst->y1 = crtc_y; | |
911 | dst->y2 = crtc_y + crtc_h; | |
912 | ||
913 | return 0; | |
914 | } | |
915 | ||
34aa50a9 GP |
916 | static void |
917 | intel_commit_sprite_plane(struct drm_plane *plane, | |
918 | struct intel_plane_state *state) | |
919 | { | |
2b875c22 | 920 | struct drm_crtc *crtc = state->base.crtc; |
34aa50a9 | 921 | struct intel_plane *intel_plane = to_intel_plane(plane); |
2b875c22 | 922 | struct drm_framebuffer *fb = state->base.fb; |
34aa50a9 | 923 | |
ea2c67bb | 924 | crtc = crtc ? crtc : plane->crtc; |
ea2c67bb | 925 | |
302d19ac ML |
926 | if (state->visible) { |
927 | intel_plane->update_plane(plane, crtc, fb, | |
928 | state->dst.x1, state->dst.y1, | |
929 | drm_rect_width(&state->dst), | |
930 | drm_rect_height(&state->dst), | |
931 | state->src.x1 >> 16, | |
932 | state->src.y1 >> 16, | |
933 | drm_rect_width(&state->src) >> 16, | |
934 | drm_rect_height(&state->src) >> 16); | |
935 | } else { | |
7fabf5ef | 936 | intel_plane->disable_plane(plane, crtc); |
03c5b25f | 937 | } |
b840d907 JB |
938 | } |
939 | ||
8ea30864 JB |
940 | int intel_sprite_set_colorkey(struct drm_device *dev, void *data, |
941 | struct drm_file *file_priv) | |
942 | { | |
943 | struct drm_intel_sprite_colorkey *set = data; | |
8ea30864 | 944 | struct drm_plane *plane; |
818ed961 ML |
945 | struct drm_plane_state *plane_state; |
946 | struct drm_atomic_state *state; | |
947 | struct drm_modeset_acquire_ctx ctx; | |
8ea30864 JB |
948 | int ret = 0; |
949 | ||
8ea30864 JB |
950 | /* Make sure we don't try to enable both src & dest simultaneously */ |
951 | if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) | |
952 | return -EINVAL; | |
953 | ||
47ecbb20 VS |
954 | if (IS_VALLEYVIEW(dev) && |
955 | set->flags & I915_SET_COLORKEY_DESTINATION) | |
956 | return -EINVAL; | |
957 | ||
7707e653 | 958 | plane = drm_plane_find(dev, set->plane_id); |
818ed961 ML |
959 | if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY) |
960 | return -ENOENT; | |
8ea30864 | 961 | |
818ed961 | 962 | drm_modeset_acquire_init(&ctx, 0); |
6156a456 | 963 | |
818ed961 ML |
964 | state = drm_atomic_state_alloc(plane->dev); |
965 | if (!state) { | |
966 | ret = -ENOMEM; | |
967 | goto out; | |
6156a456 | 968 | } |
818ed961 ML |
969 | state->acquire_ctx = &ctx; |
970 | ||
971 | while (1) { | |
972 | plane_state = drm_atomic_get_plane_state(state, plane); | |
973 | ret = PTR_ERR_OR_ZERO(plane_state); | |
974 | if (!ret) { | |
975 | to_intel_plane_state(plane_state)->ckey = *set; | |
976 | ret = drm_atomic_commit(state); | |
977 | } | |
6156a456 | 978 | |
818ed961 ML |
979 | if (ret != -EDEADLK) |
980 | break; | |
8ea30864 | 981 | |
818ed961 ML |
982 | drm_atomic_state_clear(state); |
983 | drm_modeset_backoff(&ctx); | |
984 | } | |
8ea30864 | 985 | |
818ed961 ML |
986 | if (ret) |
987 | drm_atomic_state_free(state); | |
5e1bac2f | 988 | |
818ed961 ML |
989 | out: |
990 | drm_modeset_drop_locks(&ctx); | |
991 | drm_modeset_acquire_fini(&ctx); | |
992 | return ret; | |
5e1bac2f JB |
993 | } |
994 | ||
dada2d53 | 995 | static const uint32_t ilk_plane_formats[] = { |
d1686ae3 CW |
996 | DRM_FORMAT_XRGB8888, |
997 | DRM_FORMAT_YUYV, | |
998 | DRM_FORMAT_YVYU, | |
999 | DRM_FORMAT_UYVY, | |
1000 | DRM_FORMAT_VYUY, | |
1001 | }; | |
1002 | ||
dada2d53 | 1003 | static const uint32_t snb_plane_formats[] = { |
b840d907 JB |
1004 | DRM_FORMAT_XBGR8888, |
1005 | DRM_FORMAT_XRGB8888, | |
1006 | DRM_FORMAT_YUYV, | |
1007 | DRM_FORMAT_YVYU, | |
1008 | DRM_FORMAT_UYVY, | |
1009 | DRM_FORMAT_VYUY, | |
1010 | }; | |
1011 | ||
dada2d53 | 1012 | static const uint32_t vlv_plane_formats[] = { |
7f1f3851 JB |
1013 | DRM_FORMAT_RGB565, |
1014 | DRM_FORMAT_ABGR8888, | |
1015 | DRM_FORMAT_ARGB8888, | |
1016 | DRM_FORMAT_XBGR8888, | |
1017 | DRM_FORMAT_XRGB8888, | |
1018 | DRM_FORMAT_XBGR2101010, | |
1019 | DRM_FORMAT_ABGR2101010, | |
1020 | DRM_FORMAT_YUYV, | |
1021 | DRM_FORMAT_YVYU, | |
1022 | DRM_FORMAT_UYVY, | |
1023 | DRM_FORMAT_VYUY, | |
1024 | }; | |
1025 | ||
dc2a41b4 DL |
1026 | static uint32_t skl_plane_formats[] = { |
1027 | DRM_FORMAT_RGB565, | |
1028 | DRM_FORMAT_ABGR8888, | |
1029 | DRM_FORMAT_ARGB8888, | |
1030 | DRM_FORMAT_XBGR8888, | |
1031 | DRM_FORMAT_XRGB8888, | |
1032 | DRM_FORMAT_YUYV, | |
1033 | DRM_FORMAT_YVYU, | |
1034 | DRM_FORMAT_UYVY, | |
1035 | DRM_FORMAT_VYUY, | |
1036 | }; | |
1037 | ||
b840d907 | 1038 | int |
7f1f3851 | 1039 | intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane) |
b840d907 JB |
1040 | { |
1041 | struct intel_plane *intel_plane; | |
8e7d688b | 1042 | struct intel_plane_state *state; |
b840d907 | 1043 | unsigned long possible_crtcs; |
d1686ae3 CW |
1044 | const uint32_t *plane_formats; |
1045 | int num_plane_formats; | |
b840d907 JB |
1046 | int ret; |
1047 | ||
d1686ae3 | 1048 | if (INTEL_INFO(dev)->gen < 5) |
b840d907 | 1049 | return -ENODEV; |
b840d907 | 1050 | |
b14c5679 | 1051 | intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL); |
b840d907 JB |
1052 | if (!intel_plane) |
1053 | return -ENOMEM; | |
1054 | ||
8e7d688b MR |
1055 | state = intel_create_plane_state(&intel_plane->base); |
1056 | if (!state) { | |
ea2c67bb MR |
1057 | kfree(intel_plane); |
1058 | return -ENOMEM; | |
1059 | } | |
8e7d688b | 1060 | intel_plane->base.state = &state->base; |
ea2c67bb | 1061 | |
d1686ae3 CW |
1062 | switch (INTEL_INFO(dev)->gen) { |
1063 | case 5: | |
1064 | case 6: | |
2d354c34 | 1065 | intel_plane->can_scale = true; |
b840d907 | 1066 | intel_plane->max_downscale = 16; |
d1686ae3 CW |
1067 | intel_plane->update_plane = ilk_update_plane; |
1068 | intel_plane->disable_plane = ilk_disable_plane; | |
d1686ae3 CW |
1069 | |
1070 | if (IS_GEN6(dev)) { | |
1071 | plane_formats = snb_plane_formats; | |
1072 | num_plane_formats = ARRAY_SIZE(snb_plane_formats); | |
1073 | } else { | |
1074 | plane_formats = ilk_plane_formats; | |
1075 | num_plane_formats = ARRAY_SIZE(ilk_plane_formats); | |
1076 | } | |
1077 | break; | |
1078 | ||
1079 | case 7: | |
4e0bbc31 | 1080 | case 8: |
d49f7091 | 1081 | if (IS_IVYBRIDGE(dev)) { |
2d354c34 | 1082 | intel_plane->can_scale = true; |
d49f7091 DL |
1083 | intel_plane->max_downscale = 2; |
1084 | } else { | |
1085 | intel_plane->can_scale = false; | |
1086 | intel_plane->max_downscale = 1; | |
1087 | } | |
7f1f3851 JB |
1088 | |
1089 | if (IS_VALLEYVIEW(dev)) { | |
7f1f3851 JB |
1090 | intel_plane->update_plane = vlv_update_plane; |
1091 | intel_plane->disable_plane = vlv_disable_plane; | |
7f1f3851 JB |
1092 | |
1093 | plane_formats = vlv_plane_formats; | |
1094 | num_plane_formats = ARRAY_SIZE(vlv_plane_formats); | |
1095 | } else { | |
7f1f3851 JB |
1096 | intel_plane->update_plane = ivb_update_plane; |
1097 | intel_plane->disable_plane = ivb_disable_plane; | |
7f1f3851 JB |
1098 | |
1099 | plane_formats = snb_plane_formats; | |
1100 | num_plane_formats = ARRAY_SIZE(snb_plane_formats); | |
1101 | } | |
d1686ae3 | 1102 | break; |
dc2a41b4 | 1103 | case 9: |
c331879c | 1104 | intel_plane->can_scale = true; |
dc2a41b4 DL |
1105 | intel_plane->update_plane = skl_update_plane; |
1106 | intel_plane->disable_plane = skl_disable_plane; | |
549e2bfb | 1107 | state->scaler_id = -1; |
dc2a41b4 DL |
1108 | |
1109 | plane_formats = skl_plane_formats; | |
1110 | num_plane_formats = ARRAY_SIZE(skl_plane_formats); | |
1111 | break; | |
d1686ae3 | 1112 | default: |
a8b0bbab | 1113 | kfree(intel_plane); |
d1686ae3 | 1114 | return -ENODEV; |
b840d907 JB |
1115 | } |
1116 | ||
1117 | intel_plane->pipe = pipe; | |
7f1f3851 | 1118 | intel_plane->plane = plane; |
d1b9d039 | 1119 | intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane); |
c59cb179 MR |
1120 | intel_plane->check_plane = intel_check_sprite_plane; |
1121 | intel_plane->commit_plane = intel_commit_sprite_plane; | |
b840d907 | 1122 | possible_crtcs = (1 << pipe); |
8fe8a3fe | 1123 | ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs, |
65a3fea0 | 1124 | &intel_plane_funcs, |
8fe8a3fe | 1125 | plane_formats, num_plane_formats, |
b0b3b795 | 1126 | DRM_PLANE_TYPE_OVERLAY, NULL); |
7ed6eeee | 1127 | if (ret) { |
b840d907 | 1128 | kfree(intel_plane); |
7ed6eeee VS |
1129 | goto out; |
1130 | } | |
1131 | ||
3b7a5119 | 1132 | intel_create_rotation_property(dev, intel_plane); |
b840d907 | 1133 | |
ea2c67bb MR |
1134 | drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs); |
1135 | ||
caf4e252 | 1136 | out: |
b840d907 JB |
1137 | return ret; |
1138 | } |