Commit | Line | Data |
---|---|---|
b840d907 JB |
1 | /* |
2 | * Copyright © 2011 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
21 | * SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Jesse Barnes <jbarnes@virtuousgeek.org> | |
25 | * | |
26 | * New plane/sprite handling. | |
27 | * | |
28 | * The older chips had a separate interface for programming plane related | |
29 | * registers; newer ones are much simpler and we can use the new DRM plane | |
30 | * support. | |
31 | */ | |
760285e7 DH |
32 | #include <drm/drmP.h> |
33 | #include <drm/drm_crtc.h> | |
34 | #include <drm/drm_fourcc.h> | |
1731693a | 35 | #include <drm/drm_rect.h> |
b840d907 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
b840d907 JB |
38 | #include "i915_drv.h" |
39 | ||
7f1f3851 | 40 | static void |
b39d53f6 VS |
41 | vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc, |
42 | struct drm_framebuffer *fb, | |
7f1f3851 JB |
43 | struct drm_i915_gem_object *obj, int crtc_x, int crtc_y, |
44 | unsigned int crtc_w, unsigned int crtc_h, | |
45 | uint32_t x, uint32_t y, | |
46 | uint32_t src_w, uint32_t src_h) | |
47 | { | |
48 | struct drm_device *dev = dplane->dev; | |
49 | struct drm_i915_private *dev_priv = dev->dev_private; | |
50 | struct intel_plane *intel_plane = to_intel_plane(dplane); | |
51 | int pipe = intel_plane->pipe; | |
52 | int plane = intel_plane->plane; | |
53 | u32 sprctl; | |
54 | unsigned long sprsurf_offset, linear_offset; | |
55 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
56 | ||
57 | sprctl = I915_READ(SPCNTR(pipe, plane)); | |
58 | ||
59 | /* Mask out pixel format bits in case we change it */ | |
60 | sprctl &= ~SP_PIXFORMAT_MASK; | |
61 | sprctl &= ~SP_YUV_BYTE_ORDER_MASK; | |
62 | sprctl &= ~SP_TILED; | |
63 | ||
64 | switch (fb->pixel_format) { | |
65 | case DRM_FORMAT_YUYV: | |
66 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV; | |
67 | break; | |
68 | case DRM_FORMAT_YVYU: | |
69 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU; | |
70 | break; | |
71 | case DRM_FORMAT_UYVY: | |
72 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY; | |
73 | break; | |
74 | case DRM_FORMAT_VYUY: | |
75 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY; | |
76 | break; | |
77 | case DRM_FORMAT_RGB565: | |
78 | sprctl |= SP_FORMAT_BGR565; | |
79 | break; | |
80 | case DRM_FORMAT_XRGB8888: | |
81 | sprctl |= SP_FORMAT_BGRX8888; | |
82 | break; | |
83 | case DRM_FORMAT_ARGB8888: | |
84 | sprctl |= SP_FORMAT_BGRA8888; | |
85 | break; | |
86 | case DRM_FORMAT_XBGR2101010: | |
87 | sprctl |= SP_FORMAT_RGBX1010102; | |
88 | break; | |
89 | case DRM_FORMAT_ABGR2101010: | |
90 | sprctl |= SP_FORMAT_RGBA1010102; | |
91 | break; | |
92 | case DRM_FORMAT_XBGR8888: | |
93 | sprctl |= SP_FORMAT_RGBX8888; | |
94 | break; | |
95 | case DRM_FORMAT_ABGR8888: | |
96 | sprctl |= SP_FORMAT_RGBA8888; | |
97 | break; | |
98 | default: | |
99 | /* | |
100 | * If we get here one of the upper layers failed to filter | |
101 | * out the unsupported plane formats | |
102 | */ | |
103 | BUG(); | |
104 | break; | |
105 | } | |
106 | ||
107 | if (obj->tiling_mode != I915_TILING_NONE) | |
108 | sprctl |= SP_TILED; | |
109 | ||
110 | sprctl |= SP_ENABLE; | |
111 | ||
adf3d35e | 112 | intel_update_sprite_watermarks(dplane, crtc, src_w, pixel_size, true, |
67ca28f3 VS |
113 | src_w != crtc_w || src_h != crtc_h); |
114 | ||
7f1f3851 JB |
115 | /* Sizes are 0 based */ |
116 | src_w--; | |
117 | src_h--; | |
118 | crtc_w--; | |
119 | crtc_h--; | |
120 | ||
7f1f3851 JB |
121 | I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]); |
122 | I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x); | |
123 | ||
124 | linear_offset = y * fb->pitches[0] + x * pixel_size; | |
125 | sprsurf_offset = intel_gen4_compute_page_offset(&x, &y, | |
126 | obj->tiling_mode, | |
127 | pixel_size, | |
128 | fb->pitches[0]); | |
129 | linear_offset -= sprsurf_offset; | |
130 | ||
131 | if (obj->tiling_mode != I915_TILING_NONE) | |
132 | I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x); | |
133 | else | |
134 | I915_WRITE(SPLINOFF(pipe, plane), linear_offset); | |
135 | ||
136 | I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w); | |
137 | I915_WRITE(SPCNTR(pipe, plane), sprctl); | |
f343c5f6 | 138 | I915_MODIFY_DISPBASE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) + |
7f1f3851 JB |
139 | sprsurf_offset); |
140 | POSTING_READ(SPSURF(pipe, plane)); | |
141 | } | |
142 | ||
143 | static void | |
b39d53f6 | 144 | vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc) |
7f1f3851 JB |
145 | { |
146 | struct drm_device *dev = dplane->dev; | |
147 | struct drm_i915_private *dev_priv = dev->dev_private; | |
148 | struct intel_plane *intel_plane = to_intel_plane(dplane); | |
149 | int pipe = intel_plane->pipe; | |
150 | int plane = intel_plane->plane; | |
151 | ||
152 | I915_WRITE(SPCNTR(pipe, plane), I915_READ(SPCNTR(pipe, plane)) & | |
153 | ~SP_ENABLE); | |
154 | /* Activate double buffered register update */ | |
155 | I915_MODIFY_DISPBASE(SPSURF(pipe, plane), 0); | |
156 | POSTING_READ(SPSURF(pipe, plane)); | |
157 | } | |
158 | ||
159 | static int | |
160 | vlv_update_colorkey(struct drm_plane *dplane, | |
161 | struct drm_intel_sprite_colorkey *key) | |
162 | { | |
163 | struct drm_device *dev = dplane->dev; | |
164 | struct drm_i915_private *dev_priv = dev->dev_private; | |
165 | struct intel_plane *intel_plane = to_intel_plane(dplane); | |
166 | int pipe = intel_plane->pipe; | |
167 | int plane = intel_plane->plane; | |
168 | u32 sprctl; | |
169 | ||
170 | if (key->flags & I915_SET_COLORKEY_DESTINATION) | |
171 | return -EINVAL; | |
172 | ||
173 | I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value); | |
174 | I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value); | |
175 | I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask); | |
176 | ||
177 | sprctl = I915_READ(SPCNTR(pipe, plane)); | |
178 | sprctl &= ~SP_SOURCE_KEY; | |
179 | if (key->flags & I915_SET_COLORKEY_SOURCE) | |
180 | sprctl |= SP_SOURCE_KEY; | |
181 | I915_WRITE(SPCNTR(pipe, plane), sprctl); | |
182 | ||
183 | POSTING_READ(SPKEYMSK(pipe, plane)); | |
184 | ||
185 | return 0; | |
186 | } | |
187 | ||
188 | static void | |
189 | vlv_get_colorkey(struct drm_plane *dplane, | |
190 | struct drm_intel_sprite_colorkey *key) | |
191 | { | |
192 | struct drm_device *dev = dplane->dev; | |
193 | struct drm_i915_private *dev_priv = dev->dev_private; | |
194 | struct intel_plane *intel_plane = to_intel_plane(dplane); | |
195 | int pipe = intel_plane->pipe; | |
196 | int plane = intel_plane->plane; | |
197 | u32 sprctl; | |
198 | ||
199 | key->min_value = I915_READ(SPKEYMINVAL(pipe, plane)); | |
200 | key->max_value = I915_READ(SPKEYMAXVAL(pipe, plane)); | |
201 | key->channel_mask = I915_READ(SPKEYMSK(pipe, plane)); | |
202 | ||
203 | sprctl = I915_READ(SPCNTR(pipe, plane)); | |
204 | if (sprctl & SP_SOURCE_KEY) | |
205 | key->flags = I915_SET_COLORKEY_SOURCE; | |
206 | else | |
207 | key->flags = I915_SET_COLORKEY_NONE; | |
208 | } | |
209 | ||
b840d907 | 210 | static void |
b39d53f6 VS |
211 | ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, |
212 | struct drm_framebuffer *fb, | |
b840d907 JB |
213 | struct drm_i915_gem_object *obj, int crtc_x, int crtc_y, |
214 | unsigned int crtc_w, unsigned int crtc_h, | |
215 | uint32_t x, uint32_t y, | |
216 | uint32_t src_w, uint32_t src_h) | |
217 | { | |
218 | struct drm_device *dev = plane->dev; | |
219 | struct drm_i915_private *dev_priv = dev->dev_private; | |
220 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
221 | int pipe = intel_plane->pipe; | |
222 | u32 sprctl, sprscale = 0; | |
5a35e99e | 223 | unsigned long sprsurf_offset, linear_offset; |
2bd3c3cb | 224 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
2c6602df | 225 | bool scaling_was_enabled = dev_priv->sprite_scaling_enabled; |
b840d907 JB |
226 | |
227 | sprctl = I915_READ(SPRCTL(pipe)); | |
228 | ||
229 | /* Mask out pixel format bits in case we change it */ | |
230 | sprctl &= ~SPRITE_PIXFORMAT_MASK; | |
231 | sprctl &= ~SPRITE_RGB_ORDER_RGBX; | |
232 | sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK; | |
e86fe0d3 | 233 | sprctl &= ~SPRITE_TILED; |
b840d907 JB |
234 | |
235 | switch (fb->pixel_format) { | |
236 | case DRM_FORMAT_XBGR8888: | |
5ee36913 | 237 | sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX; |
b840d907 JB |
238 | break; |
239 | case DRM_FORMAT_XRGB8888: | |
5ee36913 | 240 | sprctl |= SPRITE_FORMAT_RGBX888; |
b840d907 JB |
241 | break; |
242 | case DRM_FORMAT_YUYV: | |
243 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV; | |
b840d907 JB |
244 | break; |
245 | case DRM_FORMAT_YVYU: | |
246 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU; | |
b840d907 JB |
247 | break; |
248 | case DRM_FORMAT_UYVY: | |
249 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY; | |
b840d907 JB |
250 | break; |
251 | case DRM_FORMAT_VYUY: | |
252 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY; | |
b840d907 JB |
253 | break; |
254 | default: | |
28d491df | 255 | BUG(); |
b840d907 JB |
256 | } |
257 | ||
258 | if (obj->tiling_mode != I915_TILING_NONE) | |
259 | sprctl |= SPRITE_TILED; | |
260 | ||
261 | /* must disable */ | |
262 | sprctl |= SPRITE_TRICKLE_FEED_DISABLE; | |
263 | sprctl |= SPRITE_ENABLE; | |
264 | ||
86d3efce VS |
265 | if (IS_HASWELL(dev)) |
266 | sprctl |= SPRITE_PIPE_CSC_ENABLE; | |
267 | ||
adf3d35e | 268 | intel_update_sprite_watermarks(plane, crtc, src_w, pixel_size, true, |
67ca28f3 VS |
269 | src_w != crtc_w || src_h != crtc_h); |
270 | ||
b840d907 JB |
271 | /* Sizes are 0 based */ |
272 | src_w--; | |
273 | src_h--; | |
274 | crtc_w--; | |
275 | crtc_h--; | |
276 | ||
b840d907 JB |
277 | /* |
278 | * IVB workaround: must disable low power watermarks for at least | |
279 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
280 | * when scaling is disabled. | |
281 | */ | |
282 | if (crtc_w != src_w || crtc_h != src_h) { | |
2c6602df VS |
283 | dev_priv->sprite_scaling_enabled |= 1 << pipe; |
284 | ||
285 | if (!scaling_was_enabled) { | |
828ed3e1 CW |
286 | intel_update_watermarks(dev); |
287 | intel_wait_for_vblank(dev, pipe); | |
288 | } | |
b840d907 | 289 | sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h; |
2c6602df VS |
290 | } else |
291 | dev_priv->sprite_scaling_enabled &= ~(1 << pipe); | |
b840d907 JB |
292 | |
293 | I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]); | |
294 | I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x); | |
c54173a8 | 295 | |
ca320ac4 | 296 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
5a35e99e | 297 | sprsurf_offset = |
bc752862 CW |
298 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
299 | pixel_size, fb->pitches[0]); | |
5a35e99e DL |
300 | linear_offset -= sprsurf_offset; |
301 | ||
302 | /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET | |
303 | * register */ | |
304 | if (IS_HASWELL(dev)) | |
c54173a8 | 305 | I915_WRITE(SPROFFSET(pipe), (y << 16) | x); |
5a35e99e | 306 | else if (obj->tiling_mode != I915_TILING_NONE) |
b840d907 | 307 | I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x); |
5a35e99e DL |
308 | else |
309 | I915_WRITE(SPRLINOFF(pipe), linear_offset); | |
c54173a8 | 310 | |
b840d907 | 311 | I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w); |
2d354c34 DL |
312 | if (intel_plane->can_scale) |
313 | I915_WRITE(SPRSCALE(pipe), sprscale); | |
b840d907 | 314 | I915_WRITE(SPRCTL(pipe), sprctl); |
f343c5f6 BW |
315 | I915_MODIFY_DISPBASE(SPRSURF(pipe), |
316 | i915_gem_obj_ggtt_offset(obj) + sprsurf_offset); | |
b840d907 | 317 | POSTING_READ(SPRSURF(pipe)); |
2c6602df VS |
318 | |
319 | /* potentially re-enable LP watermarks */ | |
320 | if (scaling_was_enabled && !dev_priv->sprite_scaling_enabled) | |
321 | intel_update_watermarks(dev); | |
b840d907 JB |
322 | } |
323 | ||
324 | static void | |
b39d53f6 | 325 | ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc) |
b840d907 JB |
326 | { |
327 | struct drm_device *dev = plane->dev; | |
328 | struct drm_i915_private *dev_priv = dev->dev_private; | |
329 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
330 | int pipe = intel_plane->pipe; | |
2c6602df | 331 | bool scaling_was_enabled = dev_priv->sprite_scaling_enabled; |
b840d907 JB |
332 | |
333 | I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE); | |
334 | /* Can't leave the scaler enabled... */ | |
2d354c34 DL |
335 | if (intel_plane->can_scale) |
336 | I915_WRITE(SPRSCALE(pipe), 0); | |
b840d907 | 337 | /* Activate double buffered register update */ |
446f2545 | 338 | I915_MODIFY_DISPBASE(SPRSURF(pipe), 0); |
b840d907 | 339 | POSTING_READ(SPRSURF(pipe)); |
828ed3e1 | 340 | |
2c6602df VS |
341 | dev_priv->sprite_scaling_enabled &= ~(1 << pipe); |
342 | ||
adf3d35e | 343 | intel_update_sprite_watermarks(plane, crtc, 0, 0, false, false); |
4c4ff43a | 344 | |
2c6602df VS |
345 | /* potentially re-enable LP watermarks */ |
346 | if (scaling_was_enabled && !dev_priv->sprite_scaling_enabled) | |
347 | intel_update_watermarks(dev); | |
b840d907 JB |
348 | } |
349 | ||
8ea30864 JB |
350 | static int |
351 | ivb_update_colorkey(struct drm_plane *plane, | |
352 | struct drm_intel_sprite_colorkey *key) | |
353 | { | |
354 | struct drm_device *dev = plane->dev; | |
355 | struct drm_i915_private *dev_priv = dev->dev_private; | |
356 | struct intel_plane *intel_plane; | |
357 | u32 sprctl; | |
358 | int ret = 0; | |
359 | ||
360 | intel_plane = to_intel_plane(plane); | |
361 | ||
362 | I915_WRITE(SPRKEYVAL(intel_plane->pipe), key->min_value); | |
363 | I915_WRITE(SPRKEYMAX(intel_plane->pipe), key->max_value); | |
364 | I915_WRITE(SPRKEYMSK(intel_plane->pipe), key->channel_mask); | |
365 | ||
366 | sprctl = I915_READ(SPRCTL(intel_plane->pipe)); | |
367 | sprctl &= ~(SPRITE_SOURCE_KEY | SPRITE_DEST_KEY); | |
368 | if (key->flags & I915_SET_COLORKEY_DESTINATION) | |
369 | sprctl |= SPRITE_DEST_KEY; | |
370 | else if (key->flags & I915_SET_COLORKEY_SOURCE) | |
371 | sprctl |= SPRITE_SOURCE_KEY; | |
372 | I915_WRITE(SPRCTL(intel_plane->pipe), sprctl); | |
373 | ||
374 | POSTING_READ(SPRKEYMSK(intel_plane->pipe)); | |
375 | ||
376 | return ret; | |
377 | } | |
378 | ||
379 | static void | |
380 | ivb_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key) | |
381 | { | |
382 | struct drm_device *dev = plane->dev; | |
383 | struct drm_i915_private *dev_priv = dev->dev_private; | |
384 | struct intel_plane *intel_plane; | |
385 | u32 sprctl; | |
386 | ||
387 | intel_plane = to_intel_plane(plane); | |
388 | ||
389 | key->min_value = I915_READ(SPRKEYVAL(intel_plane->pipe)); | |
390 | key->max_value = I915_READ(SPRKEYMAX(intel_plane->pipe)); | |
391 | key->channel_mask = I915_READ(SPRKEYMSK(intel_plane->pipe)); | |
392 | key->flags = 0; | |
393 | ||
394 | sprctl = I915_READ(SPRCTL(intel_plane->pipe)); | |
395 | ||
396 | if (sprctl & SPRITE_DEST_KEY) | |
397 | key->flags = I915_SET_COLORKEY_DESTINATION; | |
398 | else if (sprctl & SPRITE_SOURCE_KEY) | |
399 | key->flags = I915_SET_COLORKEY_SOURCE; | |
400 | else | |
401 | key->flags = I915_SET_COLORKEY_NONE; | |
402 | } | |
403 | ||
b840d907 | 404 | static void |
b39d53f6 VS |
405 | ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, |
406 | struct drm_framebuffer *fb, | |
b840d907 JB |
407 | struct drm_i915_gem_object *obj, int crtc_x, int crtc_y, |
408 | unsigned int crtc_w, unsigned int crtc_h, | |
409 | uint32_t x, uint32_t y, | |
410 | uint32_t src_w, uint32_t src_h) | |
411 | { | |
412 | struct drm_device *dev = plane->dev; | |
413 | struct drm_i915_private *dev_priv = dev->dev_private; | |
414 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
2bd3c3cb | 415 | int pipe = intel_plane->pipe; |
5a35e99e | 416 | unsigned long dvssurf_offset, linear_offset; |
8aaa81a1 | 417 | u32 dvscntr, dvsscale; |
2bd3c3cb | 418 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
b840d907 JB |
419 | |
420 | dvscntr = I915_READ(DVSCNTR(pipe)); | |
421 | ||
422 | /* Mask out pixel format bits in case we change it */ | |
423 | dvscntr &= ~DVS_PIXFORMAT_MASK; | |
ab2f9df1 | 424 | dvscntr &= ~DVS_RGB_ORDER_XBGR; |
b840d907 | 425 | dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK; |
79626523 | 426 | dvscntr &= ~DVS_TILED; |
b840d907 JB |
427 | |
428 | switch (fb->pixel_format) { | |
429 | case DRM_FORMAT_XBGR8888: | |
ab2f9df1 | 430 | dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR; |
b840d907 JB |
431 | break; |
432 | case DRM_FORMAT_XRGB8888: | |
ab2f9df1 | 433 | dvscntr |= DVS_FORMAT_RGBX888; |
b840d907 JB |
434 | break; |
435 | case DRM_FORMAT_YUYV: | |
436 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV; | |
b840d907 JB |
437 | break; |
438 | case DRM_FORMAT_YVYU: | |
439 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU; | |
b840d907 JB |
440 | break; |
441 | case DRM_FORMAT_UYVY: | |
442 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY; | |
b840d907 JB |
443 | break; |
444 | case DRM_FORMAT_VYUY: | |
445 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY; | |
b840d907 JB |
446 | break; |
447 | default: | |
28d491df | 448 | BUG(); |
b840d907 JB |
449 | } |
450 | ||
451 | if (obj->tiling_mode != I915_TILING_NONE) | |
452 | dvscntr |= DVS_TILED; | |
453 | ||
d1686ae3 CW |
454 | if (IS_GEN6(dev)) |
455 | dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */ | |
b840d907 JB |
456 | dvscntr |= DVS_ENABLE; |
457 | ||
adf3d35e | 458 | intel_update_sprite_watermarks(plane, crtc, src_w, pixel_size, true, |
67ca28f3 VS |
459 | src_w != crtc_w || src_h != crtc_h); |
460 | ||
b840d907 JB |
461 | /* Sizes are 0 based */ |
462 | src_w--; | |
463 | src_h--; | |
464 | crtc_w--; | |
465 | crtc_h--; | |
466 | ||
8aaa81a1 CW |
467 | dvsscale = 0; |
468 | if (IS_GEN5(dev) || crtc_w != src_w || crtc_h != src_h) | |
b840d907 JB |
469 | dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h; |
470 | ||
471 | I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]); | |
472 | I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x); | |
5a35e99e | 473 | |
ca320ac4 | 474 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
5a35e99e | 475 | dvssurf_offset = |
bc752862 CW |
476 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
477 | pixel_size, fb->pitches[0]); | |
5a35e99e DL |
478 | linear_offset -= dvssurf_offset; |
479 | ||
480 | if (obj->tiling_mode != I915_TILING_NONE) | |
b840d907 | 481 | I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x); |
5a35e99e DL |
482 | else |
483 | I915_WRITE(DVSLINOFF(pipe), linear_offset); | |
b840d907 | 484 | |
b840d907 JB |
485 | I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w); |
486 | I915_WRITE(DVSSCALE(pipe), dvsscale); | |
487 | I915_WRITE(DVSCNTR(pipe), dvscntr); | |
f343c5f6 BW |
488 | I915_MODIFY_DISPBASE(DVSSURF(pipe), |
489 | i915_gem_obj_ggtt_offset(obj) + dvssurf_offset); | |
b840d907 JB |
490 | POSTING_READ(DVSSURF(pipe)); |
491 | } | |
492 | ||
493 | static void | |
b39d53f6 | 494 | ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc) |
b840d907 JB |
495 | { |
496 | struct drm_device *dev = plane->dev; | |
497 | struct drm_i915_private *dev_priv = dev->dev_private; | |
498 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
499 | int pipe = intel_plane->pipe; | |
500 | ||
501 | I915_WRITE(DVSCNTR(pipe), I915_READ(DVSCNTR(pipe)) & ~DVS_ENABLE); | |
502 | /* Disable the scaler */ | |
503 | I915_WRITE(DVSSCALE(pipe), 0); | |
504 | /* Flush double buffered register updates */ | |
446f2545 | 505 | I915_MODIFY_DISPBASE(DVSSURF(pipe), 0); |
b840d907 JB |
506 | POSTING_READ(DVSSURF(pipe)); |
507 | } | |
508 | ||
175bd420 JB |
509 | static void |
510 | intel_enable_primary(struct drm_crtc *crtc) | |
511 | { | |
512 | struct drm_device *dev = crtc->dev; | |
513 | struct drm_i915_private *dev_priv = dev->dev_private; | |
514 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
515 | int reg = DSPCNTR(intel_crtc->plane); | |
516 | ||
93314b5b CW |
517 | if (!intel_crtc->primary_disabled) |
518 | return; | |
519 | ||
520 | intel_crtc->primary_disabled = false; | |
521 | intel_update_fbc(dev); | |
522 | ||
175bd420 JB |
523 | I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE); |
524 | } | |
525 | ||
526 | static void | |
527 | intel_disable_primary(struct drm_crtc *crtc) | |
528 | { | |
529 | struct drm_device *dev = crtc->dev; | |
530 | struct drm_i915_private *dev_priv = dev->dev_private; | |
531 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
532 | int reg = DSPCNTR(intel_crtc->plane); | |
533 | ||
93314b5b CW |
534 | if (intel_crtc->primary_disabled) |
535 | return; | |
536 | ||
175bd420 | 537 | I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE); |
93314b5b CW |
538 | |
539 | intel_crtc->primary_disabled = true; | |
540 | intel_update_fbc(dev); | |
175bd420 JB |
541 | } |
542 | ||
8ea30864 | 543 | static int |
d1686ae3 | 544 | ilk_update_colorkey(struct drm_plane *plane, |
8ea30864 JB |
545 | struct drm_intel_sprite_colorkey *key) |
546 | { | |
547 | struct drm_device *dev = plane->dev; | |
548 | struct drm_i915_private *dev_priv = dev->dev_private; | |
549 | struct intel_plane *intel_plane; | |
550 | u32 dvscntr; | |
551 | int ret = 0; | |
552 | ||
553 | intel_plane = to_intel_plane(plane); | |
554 | ||
555 | I915_WRITE(DVSKEYVAL(intel_plane->pipe), key->min_value); | |
556 | I915_WRITE(DVSKEYMAX(intel_plane->pipe), key->max_value); | |
557 | I915_WRITE(DVSKEYMSK(intel_plane->pipe), key->channel_mask); | |
558 | ||
559 | dvscntr = I915_READ(DVSCNTR(intel_plane->pipe)); | |
560 | dvscntr &= ~(DVS_SOURCE_KEY | DVS_DEST_KEY); | |
561 | if (key->flags & I915_SET_COLORKEY_DESTINATION) | |
562 | dvscntr |= DVS_DEST_KEY; | |
563 | else if (key->flags & I915_SET_COLORKEY_SOURCE) | |
564 | dvscntr |= DVS_SOURCE_KEY; | |
565 | I915_WRITE(DVSCNTR(intel_plane->pipe), dvscntr); | |
566 | ||
567 | POSTING_READ(DVSKEYMSK(intel_plane->pipe)); | |
568 | ||
569 | return ret; | |
570 | } | |
571 | ||
572 | static void | |
d1686ae3 | 573 | ilk_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key) |
8ea30864 JB |
574 | { |
575 | struct drm_device *dev = plane->dev; | |
576 | struct drm_i915_private *dev_priv = dev->dev_private; | |
577 | struct intel_plane *intel_plane; | |
578 | u32 dvscntr; | |
579 | ||
580 | intel_plane = to_intel_plane(plane); | |
581 | ||
582 | key->min_value = I915_READ(DVSKEYVAL(intel_plane->pipe)); | |
583 | key->max_value = I915_READ(DVSKEYMAX(intel_plane->pipe)); | |
584 | key->channel_mask = I915_READ(DVSKEYMSK(intel_plane->pipe)); | |
585 | key->flags = 0; | |
586 | ||
587 | dvscntr = I915_READ(DVSCNTR(intel_plane->pipe)); | |
588 | ||
589 | if (dvscntr & DVS_DEST_KEY) | |
590 | key->flags = I915_SET_COLORKEY_DESTINATION; | |
591 | else if (dvscntr & DVS_SOURCE_KEY) | |
592 | key->flags = I915_SET_COLORKEY_SOURCE; | |
593 | else | |
594 | key->flags = I915_SET_COLORKEY_NONE; | |
595 | } | |
596 | ||
1731693a VS |
597 | static bool |
598 | format_is_yuv(uint32_t format) | |
599 | { | |
600 | switch (format) { | |
601 | case DRM_FORMAT_YUYV: | |
602 | case DRM_FORMAT_UYVY: | |
603 | case DRM_FORMAT_VYUY: | |
604 | case DRM_FORMAT_YVYU: | |
605 | return true; | |
606 | default: | |
607 | return false; | |
608 | } | |
609 | } | |
610 | ||
b840d907 JB |
611 | static int |
612 | intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, | |
613 | struct drm_framebuffer *fb, int crtc_x, int crtc_y, | |
614 | unsigned int crtc_w, unsigned int crtc_h, | |
615 | uint32_t src_x, uint32_t src_y, | |
616 | uint32_t src_w, uint32_t src_h) | |
617 | { | |
618 | struct drm_device *dev = plane->dev; | |
619 | struct drm_i915_private *dev_priv = dev->dev_private; | |
620 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
621 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
622 | struct intel_framebuffer *intel_fb; | |
623 | struct drm_i915_gem_object *obj, *old_obj; | |
624 | int pipe = intel_plane->pipe; | |
702e7a56 PZ |
625 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
626 | pipe); | |
b840d907 | 627 | int ret = 0; |
b840d907 | 628 | bool disable_primary = false; |
1731693a VS |
629 | bool visible; |
630 | int hscale, vscale; | |
631 | int max_scale, min_scale; | |
632 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
633 | struct drm_rect src = { | |
634 | /* sample coordinates in 16.16 fixed point */ | |
635 | .x1 = src_x, | |
636 | .x2 = src_x + src_w, | |
637 | .y1 = src_y, | |
638 | .y2 = src_y + src_h, | |
639 | }; | |
640 | struct drm_rect dst = { | |
641 | /* integer pixels */ | |
642 | .x1 = crtc_x, | |
643 | .x2 = crtc_x + crtc_w, | |
644 | .y1 = crtc_y, | |
645 | .y2 = crtc_y + crtc_h, | |
646 | }; | |
647 | const struct drm_rect clip = { | |
648 | .x2 = crtc->mode.hdisplay, | |
649 | .y2 = crtc->mode.vdisplay, | |
650 | }; | |
b840d907 JB |
651 | |
652 | intel_fb = to_intel_framebuffer(fb); | |
653 | obj = intel_fb->obj; | |
654 | ||
655 | old_obj = intel_plane->obj; | |
656 | ||
5e1bac2f JB |
657 | intel_plane->crtc_x = crtc_x; |
658 | intel_plane->crtc_y = crtc_y; | |
659 | intel_plane->crtc_w = crtc_w; | |
660 | intel_plane->crtc_h = crtc_h; | |
661 | intel_plane->src_x = src_x; | |
662 | intel_plane->src_y = src_y; | |
663 | intel_plane->src_w = src_w; | |
664 | intel_plane->src_h = src_h; | |
665 | ||
b840d907 | 666 | /* Pipe must be running... */ |
1731693a VS |
667 | if (!(I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE)) { |
668 | DRM_DEBUG_KMS("Pipe disabled\n"); | |
b840d907 | 669 | return -EINVAL; |
1731693a | 670 | } |
b840d907 | 671 | |
1731693a VS |
672 | /* Don't modify another pipe's plane */ |
673 | if (intel_plane->pipe != intel_crtc->pipe) { | |
674 | DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n"); | |
b840d907 | 675 | return -EINVAL; |
1731693a | 676 | } |
b840d907 | 677 | |
1731693a VS |
678 | /* FIXME check all gen limits */ |
679 | if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) { | |
680 | DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n"); | |
b840d907 | 681 | return -EINVAL; |
1731693a | 682 | } |
b840d907 | 683 | |
94c6419e DL |
684 | /* Sprite planes can be linear or x-tiled surfaces */ |
685 | switch (obj->tiling_mode) { | |
686 | case I915_TILING_NONE: | |
687 | case I915_TILING_X: | |
688 | break; | |
689 | default: | |
1731693a | 690 | DRM_DEBUG_KMS("Unsupported tiling mode\n"); |
94c6419e DL |
691 | return -EINVAL; |
692 | } | |
693 | ||
3c3686cd VS |
694 | /* |
695 | * FIXME the following code does a bunch of fuzzy adjustments to the | |
696 | * coordinates and sizes. We probably need some way to decide whether | |
697 | * more strict checking should be done instead. | |
698 | */ | |
1731693a VS |
699 | max_scale = intel_plane->max_downscale << 16; |
700 | min_scale = intel_plane->can_scale ? 1 : (1 << 16); | |
701 | ||
3c3686cd VS |
702 | hscale = drm_rect_calc_hscale_relaxed(&src, &dst, min_scale, max_scale); |
703 | BUG_ON(hscale < 0); | |
1731693a | 704 | |
3c3686cd VS |
705 | vscale = drm_rect_calc_vscale_relaxed(&src, &dst, min_scale, max_scale); |
706 | BUG_ON(vscale < 0); | |
b840d907 | 707 | |
1731693a | 708 | visible = drm_rect_clip_scaled(&src, &dst, &clip, hscale, vscale); |
b840d907 | 709 | |
1731693a VS |
710 | crtc_x = dst.x1; |
711 | crtc_y = dst.y1; | |
712 | crtc_w = drm_rect_width(&dst); | |
713 | crtc_h = drm_rect_height(&dst); | |
2d354c34 | 714 | |
1731693a | 715 | if (visible) { |
3c3686cd VS |
716 | /* check again in case clipping clamped the results */ |
717 | hscale = drm_rect_calc_hscale(&src, &dst, min_scale, max_scale); | |
718 | if (hscale < 0) { | |
719 | DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n"); | |
720 | drm_rect_debug_print(&src, true); | |
721 | drm_rect_debug_print(&dst, false); | |
722 | ||
723 | return hscale; | |
724 | } | |
725 | ||
726 | vscale = drm_rect_calc_vscale(&src, &dst, min_scale, max_scale); | |
727 | if (vscale < 0) { | |
728 | DRM_DEBUG_KMS("Vertical scaling factor out of limits\n"); | |
729 | drm_rect_debug_print(&src, true); | |
730 | drm_rect_debug_print(&dst, false); | |
731 | ||
732 | return vscale; | |
733 | } | |
734 | ||
1731693a VS |
735 | /* Make the source viewport size an exact multiple of the scaling factors. */ |
736 | drm_rect_adjust_size(&src, | |
737 | drm_rect_width(&dst) * hscale - drm_rect_width(&src), | |
738 | drm_rect_height(&dst) * vscale - drm_rect_height(&src)); | |
739 | ||
740 | /* sanity check to make sure the src viewport wasn't enlarged */ | |
741 | WARN_ON(src.x1 < (int) src_x || | |
742 | src.y1 < (int) src_y || | |
743 | src.x2 > (int) (src_x + src_w) || | |
744 | src.y2 > (int) (src_y + src_h)); | |
745 | ||
746 | /* | |
747 | * Hardware doesn't handle subpixel coordinates. | |
748 | * Adjust to (macro)pixel boundary, but be careful not to | |
749 | * increase the source viewport size, because that could | |
750 | * push the downscaling factor out of bounds. | |
1731693a VS |
751 | */ |
752 | src_x = src.x1 >> 16; | |
753 | src_w = drm_rect_width(&src) >> 16; | |
754 | src_y = src.y1 >> 16; | |
755 | src_h = drm_rect_height(&src) >> 16; | |
756 | ||
757 | if (format_is_yuv(fb->pixel_format)) { | |
758 | src_x &= ~1; | |
759 | src_w &= ~1; | |
760 | ||
761 | /* | |
762 | * Must keep src and dst the | |
763 | * same if we can't scale. | |
764 | */ | |
765 | if (!intel_plane->can_scale) | |
766 | crtc_w &= ~1; | |
767 | ||
768 | if (crtc_w == 0) | |
769 | visible = false; | |
770 | } | |
771 | } | |
772 | ||
773 | /* Check size restrictions when scaling */ | |
774 | if (visible && (src_w != crtc_w || src_h != crtc_h)) { | |
775 | unsigned int width_bytes; | |
776 | ||
777 | WARN_ON(!intel_plane->can_scale); | |
778 | ||
779 | /* FIXME interlacing min height is 6 */ | |
780 | ||
781 | if (crtc_w < 3 || crtc_h < 3) | |
782 | visible = false; | |
783 | ||
784 | if (src_w < 3 || src_h < 3) | |
785 | visible = false; | |
786 | ||
787 | width_bytes = ((src_x * pixel_size) & 63) + src_w * pixel_size; | |
788 | ||
789 | if (src_w > 2048 || src_h > 2048 || | |
790 | width_bytes > 4096 || fb->pitches[0] > 4096) { | |
791 | DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n"); | |
792 | return -EINVAL; | |
793 | } | |
794 | } | |
795 | ||
796 | dst.x1 = crtc_x; | |
797 | dst.x2 = crtc_x + crtc_w; | |
798 | dst.y1 = crtc_y; | |
799 | dst.y2 = crtc_y + crtc_h; | |
b840d907 JB |
800 | |
801 | /* | |
802 | * If the sprite is completely covering the primary plane, | |
803 | * we can disable the primary and save power. | |
804 | */ | |
1731693a VS |
805 | disable_primary = drm_rect_equals(&dst, &clip); |
806 | WARN_ON(disable_primary && !visible); | |
b840d907 JB |
807 | |
808 | mutex_lock(&dev->struct_mutex); | |
809 | ||
693db184 CW |
810 | /* Note that this will apply the VT-d workaround for scanouts, |
811 | * which is more restrictive than required for sprites. (The | |
812 | * primary plane requires 256KiB alignment with 64 PTE padding, | |
813 | * the sprite planes only require 128KiB alignment and 32 PTE padding. | |
814 | */ | |
b840d907 | 815 | ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); |
00c2064b | 816 | if (ret) |
b840d907 | 817 | goto out_unlock; |
b840d907 JB |
818 | |
819 | intel_plane->obj = obj; | |
820 | ||
175bd420 JB |
821 | /* |
822 | * Be sure to re-enable the primary before the sprite is no longer | |
823 | * covering it fully. | |
824 | */ | |
93314b5b | 825 | if (!disable_primary) |
175bd420 | 826 | intel_enable_primary(crtc); |
175bd420 | 827 | |
1731693a | 828 | if (visible) |
b39d53f6 | 829 | intel_plane->update_plane(plane, crtc, fb, obj, |
1731693a VS |
830 | crtc_x, crtc_y, crtc_w, crtc_h, |
831 | src_x, src_y, src_w, src_h); | |
832 | else | |
b39d53f6 | 833 | intel_plane->disable_plane(plane, crtc); |
b840d907 | 834 | |
93314b5b | 835 | if (disable_primary) |
175bd420 | 836 | intel_disable_primary(crtc); |
175bd420 | 837 | |
b840d907 JB |
838 | /* Unpin old obj after new one is active to avoid ugliness */ |
839 | if (old_obj) { | |
840 | /* | |
841 | * It's fairly common to simply update the position of | |
842 | * an existing object. In that case, we don't need to | |
843 | * wait for vblank to avoid ugliness, we only need to | |
844 | * do the pin & ref bookkeeping. | |
845 | */ | |
846 | if (old_obj != obj) { | |
847 | mutex_unlock(&dev->struct_mutex); | |
848 | intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe); | |
849 | mutex_lock(&dev->struct_mutex); | |
850 | } | |
1690e1eb | 851 | intel_unpin_fb_obj(old_obj); |
b840d907 JB |
852 | } |
853 | ||
854 | out_unlock: | |
855 | mutex_unlock(&dev->struct_mutex); | |
b840d907 JB |
856 | return ret; |
857 | } | |
858 | ||
859 | static int | |
860 | intel_disable_plane(struct drm_plane *plane) | |
861 | { | |
862 | struct drm_device *dev = plane->dev; | |
863 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
864 | int ret = 0; | |
865 | ||
88a94a58 VS |
866 | if (!plane->fb) |
867 | return 0; | |
868 | ||
869 | if (WARN_ON(!plane->crtc)) | |
870 | return -EINVAL; | |
871 | ||
872 | intel_enable_primary(plane->crtc); | |
b39d53f6 | 873 | intel_plane->disable_plane(plane, plane->crtc); |
b840d907 JB |
874 | |
875 | if (!intel_plane->obj) | |
876 | goto out; | |
877 | ||
c626d317 VS |
878 | intel_wait_for_vblank(dev, intel_plane->pipe); |
879 | ||
b840d907 | 880 | mutex_lock(&dev->struct_mutex); |
1690e1eb | 881 | intel_unpin_fb_obj(intel_plane->obj); |
b840d907 JB |
882 | intel_plane->obj = NULL; |
883 | mutex_unlock(&dev->struct_mutex); | |
884 | out: | |
885 | ||
886 | return ret; | |
887 | } | |
888 | ||
889 | static void intel_destroy_plane(struct drm_plane *plane) | |
890 | { | |
891 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
892 | intel_disable_plane(plane); | |
893 | drm_plane_cleanup(plane); | |
894 | kfree(intel_plane); | |
895 | } | |
896 | ||
8ea30864 JB |
897 | int intel_sprite_set_colorkey(struct drm_device *dev, void *data, |
898 | struct drm_file *file_priv) | |
899 | { | |
900 | struct drm_intel_sprite_colorkey *set = data; | |
8ea30864 JB |
901 | struct drm_mode_object *obj; |
902 | struct drm_plane *plane; | |
903 | struct intel_plane *intel_plane; | |
904 | int ret = 0; | |
905 | ||
1cff8f6b DV |
906 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
907 | return -ENODEV; | |
8ea30864 JB |
908 | |
909 | /* Make sure we don't try to enable both src & dest simultaneously */ | |
910 | if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) | |
911 | return -EINVAL; | |
912 | ||
a0e99e68 | 913 | drm_modeset_lock_all(dev); |
8ea30864 JB |
914 | |
915 | obj = drm_mode_object_find(dev, set->plane_id, DRM_MODE_OBJECT_PLANE); | |
916 | if (!obj) { | |
917 | ret = -EINVAL; | |
918 | goto out_unlock; | |
919 | } | |
920 | ||
921 | plane = obj_to_plane(obj); | |
922 | intel_plane = to_intel_plane(plane); | |
923 | ret = intel_plane->update_colorkey(plane, set); | |
924 | ||
925 | out_unlock: | |
a0e99e68 | 926 | drm_modeset_unlock_all(dev); |
8ea30864 JB |
927 | return ret; |
928 | } | |
929 | ||
930 | int intel_sprite_get_colorkey(struct drm_device *dev, void *data, | |
931 | struct drm_file *file_priv) | |
932 | { | |
933 | struct drm_intel_sprite_colorkey *get = data; | |
8ea30864 JB |
934 | struct drm_mode_object *obj; |
935 | struct drm_plane *plane; | |
936 | struct intel_plane *intel_plane; | |
937 | int ret = 0; | |
938 | ||
1cff8f6b DV |
939 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
940 | return -ENODEV; | |
8ea30864 | 941 | |
a0e99e68 | 942 | drm_modeset_lock_all(dev); |
8ea30864 JB |
943 | |
944 | obj = drm_mode_object_find(dev, get->plane_id, DRM_MODE_OBJECT_PLANE); | |
945 | if (!obj) { | |
946 | ret = -EINVAL; | |
947 | goto out_unlock; | |
948 | } | |
949 | ||
950 | plane = obj_to_plane(obj); | |
951 | intel_plane = to_intel_plane(plane); | |
952 | intel_plane->get_colorkey(plane, get); | |
953 | ||
954 | out_unlock: | |
a0e99e68 | 955 | drm_modeset_unlock_all(dev); |
8ea30864 JB |
956 | return ret; |
957 | } | |
958 | ||
5e1bac2f JB |
959 | void intel_plane_restore(struct drm_plane *plane) |
960 | { | |
961 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
962 | ||
963 | if (!plane->crtc || !plane->fb) | |
964 | return; | |
965 | ||
966 | intel_update_plane(plane, plane->crtc, plane->fb, | |
967 | intel_plane->crtc_x, intel_plane->crtc_y, | |
968 | intel_plane->crtc_w, intel_plane->crtc_h, | |
969 | intel_plane->src_x, intel_plane->src_y, | |
970 | intel_plane->src_w, intel_plane->src_h); | |
971 | } | |
972 | ||
bb53d4ae VS |
973 | void intel_plane_disable(struct drm_plane *plane) |
974 | { | |
975 | if (!plane->crtc || !plane->fb) | |
976 | return; | |
977 | ||
978 | intel_disable_plane(plane); | |
979 | } | |
980 | ||
b840d907 JB |
981 | static const struct drm_plane_funcs intel_plane_funcs = { |
982 | .update_plane = intel_update_plane, | |
983 | .disable_plane = intel_disable_plane, | |
984 | .destroy = intel_destroy_plane, | |
985 | }; | |
986 | ||
d1686ae3 CW |
987 | static uint32_t ilk_plane_formats[] = { |
988 | DRM_FORMAT_XRGB8888, | |
989 | DRM_FORMAT_YUYV, | |
990 | DRM_FORMAT_YVYU, | |
991 | DRM_FORMAT_UYVY, | |
992 | DRM_FORMAT_VYUY, | |
993 | }; | |
994 | ||
b840d907 JB |
995 | static uint32_t snb_plane_formats[] = { |
996 | DRM_FORMAT_XBGR8888, | |
997 | DRM_FORMAT_XRGB8888, | |
998 | DRM_FORMAT_YUYV, | |
999 | DRM_FORMAT_YVYU, | |
1000 | DRM_FORMAT_UYVY, | |
1001 | DRM_FORMAT_VYUY, | |
1002 | }; | |
1003 | ||
7f1f3851 JB |
1004 | static uint32_t vlv_plane_formats[] = { |
1005 | DRM_FORMAT_RGB565, | |
1006 | DRM_FORMAT_ABGR8888, | |
1007 | DRM_FORMAT_ARGB8888, | |
1008 | DRM_FORMAT_XBGR8888, | |
1009 | DRM_FORMAT_XRGB8888, | |
1010 | DRM_FORMAT_XBGR2101010, | |
1011 | DRM_FORMAT_ABGR2101010, | |
1012 | DRM_FORMAT_YUYV, | |
1013 | DRM_FORMAT_YVYU, | |
1014 | DRM_FORMAT_UYVY, | |
1015 | DRM_FORMAT_VYUY, | |
1016 | }; | |
1017 | ||
b840d907 | 1018 | int |
7f1f3851 | 1019 | intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane) |
b840d907 JB |
1020 | { |
1021 | struct intel_plane *intel_plane; | |
1022 | unsigned long possible_crtcs; | |
d1686ae3 CW |
1023 | const uint32_t *plane_formats; |
1024 | int num_plane_formats; | |
b840d907 JB |
1025 | int ret; |
1026 | ||
d1686ae3 | 1027 | if (INTEL_INFO(dev)->gen < 5) |
b840d907 | 1028 | return -ENODEV; |
b840d907 JB |
1029 | |
1030 | intel_plane = kzalloc(sizeof(struct intel_plane), GFP_KERNEL); | |
1031 | if (!intel_plane) | |
1032 | return -ENOMEM; | |
1033 | ||
d1686ae3 CW |
1034 | switch (INTEL_INFO(dev)->gen) { |
1035 | case 5: | |
1036 | case 6: | |
2d354c34 | 1037 | intel_plane->can_scale = true; |
b840d907 | 1038 | intel_plane->max_downscale = 16; |
d1686ae3 CW |
1039 | intel_plane->update_plane = ilk_update_plane; |
1040 | intel_plane->disable_plane = ilk_disable_plane; | |
1041 | intel_plane->update_colorkey = ilk_update_colorkey; | |
1042 | intel_plane->get_colorkey = ilk_get_colorkey; | |
1043 | ||
1044 | if (IS_GEN6(dev)) { | |
1045 | plane_formats = snb_plane_formats; | |
1046 | num_plane_formats = ARRAY_SIZE(snb_plane_formats); | |
1047 | } else { | |
1048 | plane_formats = ilk_plane_formats; | |
1049 | num_plane_formats = ARRAY_SIZE(ilk_plane_formats); | |
1050 | } | |
1051 | break; | |
1052 | ||
1053 | case 7: | |
d49f7091 | 1054 | if (IS_IVYBRIDGE(dev)) { |
2d354c34 | 1055 | intel_plane->can_scale = true; |
d49f7091 DL |
1056 | intel_plane->max_downscale = 2; |
1057 | } else { | |
1058 | intel_plane->can_scale = false; | |
1059 | intel_plane->max_downscale = 1; | |
1060 | } | |
7f1f3851 JB |
1061 | |
1062 | if (IS_VALLEYVIEW(dev)) { | |
7f1f3851 JB |
1063 | intel_plane->update_plane = vlv_update_plane; |
1064 | intel_plane->disable_plane = vlv_disable_plane; | |
1065 | intel_plane->update_colorkey = vlv_update_colorkey; | |
1066 | intel_plane->get_colorkey = vlv_get_colorkey; | |
1067 | ||
1068 | plane_formats = vlv_plane_formats; | |
1069 | num_plane_formats = ARRAY_SIZE(vlv_plane_formats); | |
1070 | } else { | |
7f1f3851 JB |
1071 | intel_plane->update_plane = ivb_update_plane; |
1072 | intel_plane->disable_plane = ivb_disable_plane; | |
1073 | intel_plane->update_colorkey = ivb_update_colorkey; | |
1074 | intel_plane->get_colorkey = ivb_get_colorkey; | |
1075 | ||
1076 | plane_formats = snb_plane_formats; | |
1077 | num_plane_formats = ARRAY_SIZE(snb_plane_formats); | |
1078 | } | |
d1686ae3 CW |
1079 | break; |
1080 | ||
1081 | default: | |
a8b0bbab | 1082 | kfree(intel_plane); |
d1686ae3 | 1083 | return -ENODEV; |
b840d907 JB |
1084 | } |
1085 | ||
1086 | intel_plane->pipe = pipe; | |
7f1f3851 | 1087 | intel_plane->plane = plane; |
b840d907 JB |
1088 | possible_crtcs = (1 << pipe); |
1089 | ret = drm_plane_init(dev, &intel_plane->base, possible_crtcs, | |
d1686ae3 CW |
1090 | &intel_plane_funcs, |
1091 | plane_formats, num_plane_formats, | |
1092 | false); | |
b840d907 JB |
1093 | if (ret) |
1094 | kfree(intel_plane); | |
1095 | ||
1096 | return ret; | |
1097 | } |