Commit | Line | Data |
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b840d907 JB |
1 | /* |
2 | * Copyright © 2011 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
21 | * SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Jesse Barnes <jbarnes@virtuousgeek.org> | |
25 | * | |
26 | * New plane/sprite handling. | |
27 | * | |
28 | * The older chips had a separate interface for programming plane related | |
29 | * registers; newer ones are much simpler and we can use the new DRM plane | |
30 | * support. | |
31 | */ | |
760285e7 DH |
32 | #include <drm/drmP.h> |
33 | #include <drm/drm_crtc.h> | |
34 | #include <drm/drm_fourcc.h> | |
1731693a | 35 | #include <drm/drm_rect.h> |
b840d907 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
b840d907 JB |
38 | #include "i915_drv.h" |
39 | ||
8d7849db VS |
40 | static int usecs_to_scanlines(const struct drm_display_mode *mode, int usecs) |
41 | { | |
42 | /* paranoia */ | |
43 | if (!mode->crtc_htotal) | |
44 | return 1; | |
45 | ||
46 | return DIV_ROUND_UP(usecs * mode->crtc_clock, 1000 * mode->crtc_htotal); | |
47 | } | |
48 | ||
49 | static bool intel_pipe_update_start(struct intel_crtc *crtc, uint32_t *start_vbl_count) | |
50 | { | |
51 | struct drm_device *dev = crtc->base.dev; | |
52 | const struct drm_display_mode *mode = &crtc->config.adjusted_mode; | |
53 | enum pipe pipe = crtc->pipe; | |
54 | long timeout = msecs_to_jiffies_timeout(1); | |
55 | int scanline, min, max, vblank_start; | |
210871b6 | 56 | wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base); |
8d7849db VS |
57 | DEFINE_WAIT(wait); |
58 | ||
51fd371b | 59 | WARN_ON(!drm_modeset_is_locked(&crtc->base.mutex)); |
8d7849db VS |
60 | |
61 | vblank_start = mode->crtc_vblank_start; | |
62 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
63 | vblank_start = DIV_ROUND_UP(vblank_start, 2); | |
64 | ||
65 | /* FIXME needs to be calibrated sensibly */ | |
66 | min = vblank_start - usecs_to_scanlines(mode, 100); | |
67 | max = vblank_start - 1; | |
68 | ||
69 | if (min <= 0 || max <= 0) | |
70 | return false; | |
71 | ||
72 | if (WARN_ON(drm_vblank_get(dev, pipe))) | |
73 | return false; | |
74 | ||
75 | local_irq_disable(); | |
76 | ||
25ef284a VS |
77 | trace_i915_pipe_update_start(crtc, min, max); |
78 | ||
8d7849db VS |
79 | for (;;) { |
80 | /* | |
81 | * prepare_to_wait() has a memory barrier, which guarantees | |
82 | * other CPUs can see the task state update by the time we | |
83 | * read the scanline. | |
84 | */ | |
210871b6 | 85 | prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE); |
8d7849db VS |
86 | |
87 | scanline = intel_get_crtc_scanline(crtc); | |
88 | if (scanline < min || scanline > max) | |
89 | break; | |
90 | ||
91 | if (timeout <= 0) { | |
92 | DRM_ERROR("Potential atomic update failure on pipe %c\n", | |
93 | pipe_name(crtc->pipe)); | |
94 | break; | |
95 | } | |
96 | ||
97 | local_irq_enable(); | |
98 | ||
99 | timeout = schedule_timeout(timeout); | |
100 | ||
101 | local_irq_disable(); | |
102 | } | |
103 | ||
210871b6 | 104 | finish_wait(wq, &wait); |
8d7849db VS |
105 | |
106 | drm_vblank_put(dev, pipe); | |
107 | ||
108 | *start_vbl_count = dev->driver->get_vblank_counter(dev, pipe); | |
109 | ||
25ef284a VS |
110 | trace_i915_pipe_update_vblank_evaded(crtc, min, max, *start_vbl_count); |
111 | ||
8d7849db VS |
112 | return true; |
113 | } | |
114 | ||
115 | static void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count) | |
116 | { | |
117 | struct drm_device *dev = crtc->base.dev; | |
118 | enum pipe pipe = crtc->pipe; | |
119 | u32 end_vbl_count = dev->driver->get_vblank_counter(dev, pipe); | |
120 | ||
25ef284a VS |
121 | trace_i915_pipe_update_end(crtc, end_vbl_count); |
122 | ||
8d7849db VS |
123 | local_irq_enable(); |
124 | ||
125 | if (start_vbl_count != end_vbl_count) | |
126 | DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u)\n", | |
127 | pipe_name(pipe), start_vbl_count, end_vbl_count); | |
128 | } | |
129 | ||
5b633d6b VS |
130 | static void intel_update_primary_plane(struct intel_crtc *crtc) |
131 | { | |
132 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
133 | int reg = DSPCNTR(crtc->plane); | |
134 | ||
135 | if (crtc->primary_enabled) | |
136 | I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE); | |
137 | else | |
138 | I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE); | |
139 | } | |
140 | ||
dc2a41b4 DL |
141 | static void |
142 | skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, | |
143 | struct drm_framebuffer *fb, | |
144 | struct drm_i915_gem_object *obj, int crtc_x, int crtc_y, | |
145 | unsigned int crtc_w, unsigned int crtc_h, | |
146 | uint32_t x, uint32_t y, | |
147 | uint32_t src_w, uint32_t src_h) | |
148 | { | |
149 | struct drm_device *dev = drm_plane->dev; | |
150 | struct drm_i915_private *dev_priv = dev->dev_private; | |
151 | struct intel_plane *intel_plane = to_intel_plane(drm_plane); | |
152 | const int pipe = intel_plane->pipe; | |
153 | const int plane = intel_plane->plane + 1; | |
154 | u32 plane_ctl, stride; | |
155 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
156 | ||
157 | plane_ctl = I915_READ(PLANE_CTL(pipe, plane)); | |
158 | ||
159 | /* Mask out pixel format bits in case we change it */ | |
160 | plane_ctl &= ~PLANE_CTL_FORMAT_MASK; | |
161 | plane_ctl &= ~PLANE_CTL_ORDER_RGBX; | |
162 | plane_ctl &= ~PLANE_CTL_YUV422_ORDER_MASK; | |
163 | plane_ctl &= ~PLANE_CTL_TILED_MASK; | |
164 | plane_ctl &= ~PLANE_CTL_ALPHA_MASK; | |
1447dde0 | 165 | plane_ctl &= ~PLANE_CTL_ROTATE_MASK; |
dc2a41b4 DL |
166 | |
167 | /* Trickle feed has to be enabled */ | |
168 | plane_ctl &= ~PLANE_CTL_TRICKLE_FEED_DISABLE; | |
169 | ||
170 | switch (fb->pixel_format) { | |
171 | case DRM_FORMAT_RGB565: | |
172 | plane_ctl |= PLANE_CTL_FORMAT_RGB_565; | |
173 | break; | |
174 | case DRM_FORMAT_XBGR8888: | |
175 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; | |
176 | break; | |
177 | case DRM_FORMAT_XRGB8888: | |
178 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; | |
179 | break; | |
180 | /* | |
181 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
182 | * to be already pre-multiplied. We need to add a knob (or a different | |
183 | * DRM_FORMAT) for user-space to configure that. | |
184 | */ | |
185 | case DRM_FORMAT_ABGR8888: | |
186 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888 | | |
187 | PLANE_CTL_ORDER_RGBX | | |
188 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; | |
189 | break; | |
190 | case DRM_FORMAT_ARGB8888: | |
191 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888 | | |
192 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; | |
193 | break; | |
194 | case DRM_FORMAT_YUYV: | |
195 | plane_ctl |= PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; | |
196 | break; | |
197 | case DRM_FORMAT_YVYU: | |
198 | plane_ctl |= PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; | |
199 | break; | |
200 | case DRM_FORMAT_UYVY: | |
201 | plane_ctl |= PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; | |
202 | break; | |
203 | case DRM_FORMAT_VYUY: | |
204 | plane_ctl |= PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; | |
205 | break; | |
206 | default: | |
207 | BUG(); | |
208 | } | |
209 | ||
210 | switch (obj->tiling_mode) { | |
211 | case I915_TILING_NONE: | |
212 | stride = fb->pitches[0] >> 6; | |
213 | break; | |
214 | case I915_TILING_X: | |
215 | plane_ctl |= PLANE_CTL_TILED_X; | |
216 | stride = fb->pitches[0] >> 9; | |
217 | break; | |
218 | default: | |
219 | BUG(); | |
220 | } | |
1447dde0 SJ |
221 | if (intel_plane->rotation == BIT(DRM_ROTATE_180)) |
222 | plane_ctl |= PLANE_CTL_ROTATE_180; | |
dc2a41b4 DL |
223 | |
224 | plane_ctl |= PLANE_CTL_ENABLE; | |
225 | plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE; | |
226 | ||
227 | intel_update_sprite_watermarks(drm_plane, crtc, src_w, src_h, | |
228 | pixel_size, true, | |
229 | src_w != crtc_w || src_h != crtc_h); | |
230 | ||
231 | /* Sizes are 0 based */ | |
232 | src_w--; | |
233 | src_h--; | |
234 | crtc_w--; | |
235 | crtc_h--; | |
236 | ||
237 | I915_WRITE(PLANE_OFFSET(pipe, plane), (y << 16) | x); | |
238 | I915_WRITE(PLANE_STRIDE(pipe, plane), stride); | |
239 | I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x); | |
240 | I915_WRITE(PLANE_SIZE(pipe, plane), (crtc_h << 16) | crtc_w); | |
241 | I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl); | |
242 | I915_WRITE(PLANE_SURF(pipe, plane), i915_gem_obj_ggtt_offset(obj)); | |
243 | POSTING_READ(PLANE_SURF(pipe, plane)); | |
244 | } | |
245 | ||
246 | static void | |
247 | skl_disable_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc) | |
248 | { | |
249 | struct drm_device *dev = drm_plane->dev; | |
250 | struct drm_i915_private *dev_priv = dev->dev_private; | |
251 | struct intel_plane *intel_plane = to_intel_plane(drm_plane); | |
252 | const int pipe = intel_plane->pipe; | |
253 | const int plane = intel_plane->plane + 1; | |
254 | ||
255 | I915_WRITE(PLANE_CTL(pipe, plane), | |
256 | I915_READ(PLANE_CTL(pipe, plane)) & ~PLANE_CTL_ENABLE); | |
257 | ||
258 | /* Activate double buffered register update */ | |
259 | I915_WRITE(PLANE_CTL(pipe, plane), 0); | |
260 | POSTING_READ(PLANE_CTL(pipe, plane)); | |
261 | ||
262 | intel_update_sprite_watermarks(drm_plane, crtc, 0, 0, 0, false, false); | |
263 | } | |
264 | ||
265 | static int | |
266 | skl_update_colorkey(struct drm_plane *drm_plane, | |
267 | struct drm_intel_sprite_colorkey *key) | |
268 | { | |
269 | struct drm_device *dev = drm_plane->dev; | |
270 | struct drm_i915_private *dev_priv = dev->dev_private; | |
271 | struct intel_plane *intel_plane = to_intel_plane(drm_plane); | |
272 | const int pipe = intel_plane->pipe; | |
273 | const int plane = intel_plane->plane; | |
274 | u32 plane_ctl; | |
275 | ||
276 | I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value); | |
277 | I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value); | |
278 | I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask); | |
279 | ||
280 | plane_ctl = I915_READ(PLANE_CTL(pipe, plane)); | |
281 | plane_ctl &= ~PLANE_CTL_KEY_ENABLE_MASK; | |
282 | if (key->flags & I915_SET_COLORKEY_DESTINATION) | |
283 | plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION; | |
284 | else if (key->flags & I915_SET_COLORKEY_SOURCE) | |
285 | plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE; | |
286 | I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl); | |
287 | ||
288 | POSTING_READ(PLANE_CTL(pipe, plane)); | |
289 | ||
290 | return 0; | |
291 | } | |
292 | ||
293 | static void | |
294 | skl_get_colorkey(struct drm_plane *drm_plane, | |
295 | struct drm_intel_sprite_colorkey *key) | |
296 | { | |
297 | struct drm_device *dev = drm_plane->dev; | |
298 | struct drm_i915_private *dev_priv = dev->dev_private; | |
299 | struct intel_plane *intel_plane = to_intel_plane(drm_plane); | |
300 | const int pipe = intel_plane->pipe; | |
301 | const int plane = intel_plane->plane; | |
302 | u32 plane_ctl; | |
303 | ||
304 | key->min_value = I915_READ(PLANE_KEYVAL(pipe, plane)); | |
305 | key->max_value = I915_READ(PLANE_KEYMAX(pipe, plane)); | |
306 | key->channel_mask = I915_READ(PLANE_KEYMSK(pipe, plane)); | |
307 | ||
308 | plane_ctl = I915_READ(PLANE_CTL(pipe, plane)); | |
309 | ||
310 | switch (plane_ctl & PLANE_CTL_KEY_ENABLE_MASK) { | |
311 | case PLANE_CTL_KEY_ENABLE_DESTINATION: | |
312 | key->flags = I915_SET_COLORKEY_DESTINATION; | |
313 | break; | |
314 | case PLANE_CTL_KEY_ENABLE_SOURCE: | |
315 | key->flags = I915_SET_COLORKEY_SOURCE; | |
316 | break; | |
317 | default: | |
318 | key->flags = I915_SET_COLORKEY_NONE; | |
319 | } | |
320 | } | |
321 | ||
7f1f3851 | 322 | static void |
b39d53f6 VS |
323 | vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc, |
324 | struct drm_framebuffer *fb, | |
7f1f3851 JB |
325 | struct drm_i915_gem_object *obj, int crtc_x, int crtc_y, |
326 | unsigned int crtc_w, unsigned int crtc_h, | |
327 | uint32_t x, uint32_t y, | |
328 | uint32_t src_w, uint32_t src_h) | |
329 | { | |
330 | struct drm_device *dev = dplane->dev; | |
331 | struct drm_i915_private *dev_priv = dev->dev_private; | |
332 | struct intel_plane *intel_plane = to_intel_plane(dplane); | |
8d7849db | 333 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7f1f3851 JB |
334 | int pipe = intel_plane->pipe; |
335 | int plane = intel_plane->plane; | |
336 | u32 sprctl; | |
337 | unsigned long sprsurf_offset, linear_offset; | |
338 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
8d7849db VS |
339 | u32 start_vbl_count; |
340 | bool atomic_update; | |
7f1f3851 JB |
341 | |
342 | sprctl = I915_READ(SPCNTR(pipe, plane)); | |
343 | ||
344 | /* Mask out pixel format bits in case we change it */ | |
345 | sprctl &= ~SP_PIXFORMAT_MASK; | |
346 | sprctl &= ~SP_YUV_BYTE_ORDER_MASK; | |
347 | sprctl &= ~SP_TILED; | |
76eebda7 | 348 | sprctl &= ~SP_ROTATE_180; |
7f1f3851 JB |
349 | |
350 | switch (fb->pixel_format) { | |
351 | case DRM_FORMAT_YUYV: | |
352 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV; | |
353 | break; | |
354 | case DRM_FORMAT_YVYU: | |
355 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU; | |
356 | break; | |
357 | case DRM_FORMAT_UYVY: | |
358 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY; | |
359 | break; | |
360 | case DRM_FORMAT_VYUY: | |
361 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY; | |
362 | break; | |
363 | case DRM_FORMAT_RGB565: | |
364 | sprctl |= SP_FORMAT_BGR565; | |
365 | break; | |
366 | case DRM_FORMAT_XRGB8888: | |
367 | sprctl |= SP_FORMAT_BGRX8888; | |
368 | break; | |
369 | case DRM_FORMAT_ARGB8888: | |
370 | sprctl |= SP_FORMAT_BGRA8888; | |
371 | break; | |
372 | case DRM_FORMAT_XBGR2101010: | |
373 | sprctl |= SP_FORMAT_RGBX1010102; | |
374 | break; | |
375 | case DRM_FORMAT_ABGR2101010: | |
376 | sprctl |= SP_FORMAT_RGBA1010102; | |
377 | break; | |
378 | case DRM_FORMAT_XBGR8888: | |
379 | sprctl |= SP_FORMAT_RGBX8888; | |
380 | break; | |
381 | case DRM_FORMAT_ABGR8888: | |
382 | sprctl |= SP_FORMAT_RGBA8888; | |
383 | break; | |
384 | default: | |
385 | /* | |
386 | * If we get here one of the upper layers failed to filter | |
387 | * out the unsupported plane formats | |
388 | */ | |
389 | BUG(); | |
390 | break; | |
391 | } | |
392 | ||
4ea67bc7 VS |
393 | /* |
394 | * Enable gamma to match primary/cursor plane behaviour. | |
395 | * FIXME should be user controllable via propertiesa. | |
396 | */ | |
397 | sprctl |= SP_GAMMA_ENABLE; | |
398 | ||
7f1f3851 JB |
399 | if (obj->tiling_mode != I915_TILING_NONE) |
400 | sprctl |= SP_TILED; | |
401 | ||
402 | sprctl |= SP_ENABLE; | |
403 | ||
ed57cb8a DL |
404 | intel_update_sprite_watermarks(dplane, crtc, src_w, src_h, |
405 | pixel_size, true, | |
67ca28f3 VS |
406 | src_w != crtc_w || src_h != crtc_h); |
407 | ||
7f1f3851 JB |
408 | /* Sizes are 0 based */ |
409 | src_w--; | |
410 | src_h--; | |
411 | crtc_w--; | |
412 | crtc_h--; | |
413 | ||
7f1f3851 JB |
414 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
415 | sprsurf_offset = intel_gen4_compute_page_offset(&x, &y, | |
416 | obj->tiling_mode, | |
417 | pixel_size, | |
418 | fb->pitches[0]); | |
419 | linear_offset -= sprsurf_offset; | |
420 | ||
76eebda7 VS |
421 | if (intel_plane->rotation == BIT(DRM_ROTATE_180)) { |
422 | sprctl |= SP_ROTATE_180; | |
423 | ||
424 | x += src_w; | |
425 | y += src_h; | |
426 | linear_offset += src_h * fb->pitches[0] + src_w * pixel_size; | |
427 | } | |
428 | ||
8d7849db VS |
429 | atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count); |
430 | ||
5b633d6b VS |
431 | intel_update_primary_plane(intel_crtc); |
432 | ||
ca6ad025 VS |
433 | I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]); |
434 | I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x); | |
435 | ||
7f1f3851 JB |
436 | if (obj->tiling_mode != I915_TILING_NONE) |
437 | I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x); | |
438 | else | |
439 | I915_WRITE(SPLINOFF(pipe, plane), linear_offset); | |
440 | ||
441 | I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w); | |
442 | I915_WRITE(SPCNTR(pipe, plane), sprctl); | |
85ba7b7d DV |
443 | I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) + |
444 | sprsurf_offset); | |
5b633d6b VS |
445 | |
446 | intel_flush_primary_plane(dev_priv, intel_crtc->plane); | |
8d7849db VS |
447 | |
448 | if (atomic_update) | |
449 | intel_pipe_update_end(intel_crtc, start_vbl_count); | |
7f1f3851 JB |
450 | } |
451 | ||
452 | static void | |
b39d53f6 | 453 | vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc) |
7f1f3851 JB |
454 | { |
455 | struct drm_device *dev = dplane->dev; | |
456 | struct drm_i915_private *dev_priv = dev->dev_private; | |
457 | struct intel_plane *intel_plane = to_intel_plane(dplane); | |
8d7849db | 458 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7f1f3851 JB |
459 | int pipe = intel_plane->pipe; |
460 | int plane = intel_plane->plane; | |
8d7849db VS |
461 | u32 start_vbl_count; |
462 | bool atomic_update; | |
463 | ||
464 | atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count); | |
7f1f3851 | 465 | |
5b633d6b VS |
466 | intel_update_primary_plane(intel_crtc); |
467 | ||
7f1f3851 JB |
468 | I915_WRITE(SPCNTR(pipe, plane), I915_READ(SPCNTR(pipe, plane)) & |
469 | ~SP_ENABLE); | |
470 | /* Activate double buffered register update */ | |
85ba7b7d | 471 | I915_WRITE(SPSURF(pipe, plane), 0); |
5b633d6b VS |
472 | |
473 | intel_flush_primary_plane(dev_priv, intel_crtc->plane); | |
a95fd8ca | 474 | |
8d7849db VS |
475 | if (atomic_update) |
476 | intel_pipe_update_end(intel_crtc, start_vbl_count); | |
477 | ||
ed57cb8a | 478 | intel_update_sprite_watermarks(dplane, crtc, 0, 0, 0, false, false); |
7f1f3851 JB |
479 | } |
480 | ||
481 | static int | |
482 | vlv_update_colorkey(struct drm_plane *dplane, | |
483 | struct drm_intel_sprite_colorkey *key) | |
484 | { | |
485 | struct drm_device *dev = dplane->dev; | |
486 | struct drm_i915_private *dev_priv = dev->dev_private; | |
487 | struct intel_plane *intel_plane = to_intel_plane(dplane); | |
488 | int pipe = intel_plane->pipe; | |
489 | int plane = intel_plane->plane; | |
490 | u32 sprctl; | |
491 | ||
492 | if (key->flags & I915_SET_COLORKEY_DESTINATION) | |
493 | return -EINVAL; | |
494 | ||
495 | I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value); | |
496 | I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value); | |
497 | I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask); | |
498 | ||
499 | sprctl = I915_READ(SPCNTR(pipe, plane)); | |
500 | sprctl &= ~SP_SOURCE_KEY; | |
501 | if (key->flags & I915_SET_COLORKEY_SOURCE) | |
502 | sprctl |= SP_SOURCE_KEY; | |
503 | I915_WRITE(SPCNTR(pipe, plane), sprctl); | |
504 | ||
505 | POSTING_READ(SPKEYMSK(pipe, plane)); | |
506 | ||
507 | return 0; | |
508 | } | |
509 | ||
510 | static void | |
511 | vlv_get_colorkey(struct drm_plane *dplane, | |
512 | struct drm_intel_sprite_colorkey *key) | |
513 | { | |
514 | struct drm_device *dev = dplane->dev; | |
515 | struct drm_i915_private *dev_priv = dev->dev_private; | |
516 | struct intel_plane *intel_plane = to_intel_plane(dplane); | |
517 | int pipe = intel_plane->pipe; | |
518 | int plane = intel_plane->plane; | |
519 | u32 sprctl; | |
520 | ||
521 | key->min_value = I915_READ(SPKEYMINVAL(pipe, plane)); | |
522 | key->max_value = I915_READ(SPKEYMAXVAL(pipe, plane)); | |
523 | key->channel_mask = I915_READ(SPKEYMSK(pipe, plane)); | |
524 | ||
525 | sprctl = I915_READ(SPCNTR(pipe, plane)); | |
526 | if (sprctl & SP_SOURCE_KEY) | |
527 | key->flags = I915_SET_COLORKEY_SOURCE; | |
528 | else | |
529 | key->flags = I915_SET_COLORKEY_NONE; | |
530 | } | |
531 | ||
b840d907 | 532 | static void |
b39d53f6 VS |
533 | ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, |
534 | struct drm_framebuffer *fb, | |
b840d907 JB |
535 | struct drm_i915_gem_object *obj, int crtc_x, int crtc_y, |
536 | unsigned int crtc_w, unsigned int crtc_h, | |
537 | uint32_t x, uint32_t y, | |
538 | uint32_t src_w, uint32_t src_h) | |
539 | { | |
540 | struct drm_device *dev = plane->dev; | |
541 | struct drm_i915_private *dev_priv = dev->dev_private; | |
542 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
8d7849db | 543 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
b840d907 JB |
544 | int pipe = intel_plane->pipe; |
545 | u32 sprctl, sprscale = 0; | |
5a35e99e | 546 | unsigned long sprsurf_offset, linear_offset; |
2bd3c3cb | 547 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
8d7849db VS |
548 | u32 start_vbl_count; |
549 | bool atomic_update; | |
b840d907 JB |
550 | |
551 | sprctl = I915_READ(SPRCTL(pipe)); | |
552 | ||
553 | /* Mask out pixel format bits in case we change it */ | |
554 | sprctl &= ~SPRITE_PIXFORMAT_MASK; | |
555 | sprctl &= ~SPRITE_RGB_ORDER_RGBX; | |
556 | sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK; | |
e86fe0d3 | 557 | sprctl &= ~SPRITE_TILED; |
76eebda7 | 558 | sprctl &= ~SPRITE_ROTATE_180; |
b840d907 JB |
559 | |
560 | switch (fb->pixel_format) { | |
561 | case DRM_FORMAT_XBGR8888: | |
5ee36913 | 562 | sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX; |
b840d907 JB |
563 | break; |
564 | case DRM_FORMAT_XRGB8888: | |
5ee36913 | 565 | sprctl |= SPRITE_FORMAT_RGBX888; |
b840d907 JB |
566 | break; |
567 | case DRM_FORMAT_YUYV: | |
568 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV; | |
b840d907 JB |
569 | break; |
570 | case DRM_FORMAT_YVYU: | |
571 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU; | |
b840d907 JB |
572 | break; |
573 | case DRM_FORMAT_UYVY: | |
574 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY; | |
b840d907 JB |
575 | break; |
576 | case DRM_FORMAT_VYUY: | |
577 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY; | |
b840d907 JB |
578 | break; |
579 | default: | |
28d491df | 580 | BUG(); |
b840d907 JB |
581 | } |
582 | ||
4ea67bc7 VS |
583 | /* |
584 | * Enable gamma to match primary/cursor plane behaviour. | |
585 | * FIXME should be user controllable via propertiesa. | |
586 | */ | |
587 | sprctl |= SPRITE_GAMMA_ENABLE; | |
588 | ||
b840d907 JB |
589 | if (obj->tiling_mode != I915_TILING_NONE) |
590 | sprctl |= SPRITE_TILED; | |
591 | ||
b42c6009 | 592 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
1f5d76db PZ |
593 | sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE; |
594 | else | |
595 | sprctl |= SPRITE_TRICKLE_FEED_DISABLE; | |
596 | ||
b840d907 JB |
597 | sprctl |= SPRITE_ENABLE; |
598 | ||
6bbfa1c5 | 599 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
86d3efce VS |
600 | sprctl |= SPRITE_PIPE_CSC_ENABLE; |
601 | ||
ed57cb8a DL |
602 | intel_update_sprite_watermarks(plane, crtc, src_w, src_h, pixel_size, |
603 | true, | |
67ca28f3 VS |
604 | src_w != crtc_w || src_h != crtc_h); |
605 | ||
b840d907 JB |
606 | /* Sizes are 0 based */ |
607 | src_w--; | |
608 | src_h--; | |
609 | crtc_w--; | |
610 | crtc_h--; | |
611 | ||
8553c18e | 612 | if (crtc_w != src_w || crtc_h != src_h) |
b840d907 | 613 | sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h; |
b840d907 | 614 | |
ca320ac4 | 615 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
5a35e99e | 616 | sprsurf_offset = |
bc752862 CW |
617 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
618 | pixel_size, fb->pitches[0]); | |
5a35e99e DL |
619 | linear_offset -= sprsurf_offset; |
620 | ||
76eebda7 VS |
621 | if (intel_plane->rotation == BIT(DRM_ROTATE_180)) { |
622 | sprctl |= SPRITE_ROTATE_180; | |
623 | ||
624 | /* HSW and BDW does this automagically in hardware */ | |
625 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
626 | x += src_w; | |
627 | y += src_h; | |
628 | linear_offset += src_h * fb->pitches[0] + | |
629 | src_w * pixel_size; | |
630 | } | |
631 | } | |
632 | ||
8d7849db VS |
633 | atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count); |
634 | ||
5b633d6b VS |
635 | intel_update_primary_plane(intel_crtc); |
636 | ||
ca6ad025 VS |
637 | I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]); |
638 | I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x); | |
639 | ||
5a35e99e DL |
640 | /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET |
641 | * register */ | |
b3dc685e | 642 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
c54173a8 | 643 | I915_WRITE(SPROFFSET(pipe), (y << 16) | x); |
5a35e99e | 644 | else if (obj->tiling_mode != I915_TILING_NONE) |
b840d907 | 645 | I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x); |
5a35e99e DL |
646 | else |
647 | I915_WRITE(SPRLINOFF(pipe), linear_offset); | |
c54173a8 | 648 | |
b840d907 | 649 | I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w); |
2d354c34 DL |
650 | if (intel_plane->can_scale) |
651 | I915_WRITE(SPRSCALE(pipe), sprscale); | |
b840d907 | 652 | I915_WRITE(SPRCTL(pipe), sprctl); |
85ba7b7d DV |
653 | I915_WRITE(SPRSURF(pipe), |
654 | i915_gem_obj_ggtt_offset(obj) + sprsurf_offset); | |
5b633d6b VS |
655 | |
656 | intel_flush_primary_plane(dev_priv, intel_crtc->plane); | |
8d7849db VS |
657 | |
658 | if (atomic_update) | |
659 | intel_pipe_update_end(intel_crtc, start_vbl_count); | |
b840d907 JB |
660 | } |
661 | ||
662 | static void | |
b39d53f6 | 663 | ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc) |
b840d907 JB |
664 | { |
665 | struct drm_device *dev = plane->dev; | |
666 | struct drm_i915_private *dev_priv = dev->dev_private; | |
667 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
8d7849db | 668 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
b840d907 | 669 | int pipe = intel_plane->pipe; |
8d7849db VS |
670 | u32 start_vbl_count; |
671 | bool atomic_update; | |
672 | ||
673 | atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count); | |
b840d907 | 674 | |
5b633d6b VS |
675 | intel_update_primary_plane(intel_crtc); |
676 | ||
b840d907 JB |
677 | I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE); |
678 | /* Can't leave the scaler enabled... */ | |
2d354c34 DL |
679 | if (intel_plane->can_scale) |
680 | I915_WRITE(SPRSCALE(pipe), 0); | |
b840d907 | 681 | /* Activate double buffered register update */ |
85ba7b7d | 682 | I915_WRITE(SPRSURF(pipe), 0); |
5b633d6b VS |
683 | |
684 | intel_flush_primary_plane(dev_priv, intel_crtc->plane); | |
828ed3e1 | 685 | |
8d7849db VS |
686 | if (atomic_update) |
687 | intel_pipe_update_end(intel_crtc, start_vbl_count); | |
688 | ||
1bd09ec7 VS |
689 | /* |
690 | * Avoid underruns when disabling the sprite. | |
691 | * FIXME remove once watermark updates are done properly. | |
692 | */ | |
693 | intel_wait_for_vblank(dev, pipe); | |
694 | ||
ed57cb8a | 695 | intel_update_sprite_watermarks(plane, crtc, 0, 0, 0, false, false); |
b840d907 JB |
696 | } |
697 | ||
8ea30864 JB |
698 | static int |
699 | ivb_update_colorkey(struct drm_plane *plane, | |
700 | struct drm_intel_sprite_colorkey *key) | |
701 | { | |
702 | struct drm_device *dev = plane->dev; | |
703 | struct drm_i915_private *dev_priv = dev->dev_private; | |
704 | struct intel_plane *intel_plane; | |
705 | u32 sprctl; | |
706 | int ret = 0; | |
707 | ||
708 | intel_plane = to_intel_plane(plane); | |
709 | ||
710 | I915_WRITE(SPRKEYVAL(intel_plane->pipe), key->min_value); | |
711 | I915_WRITE(SPRKEYMAX(intel_plane->pipe), key->max_value); | |
712 | I915_WRITE(SPRKEYMSK(intel_plane->pipe), key->channel_mask); | |
713 | ||
714 | sprctl = I915_READ(SPRCTL(intel_plane->pipe)); | |
715 | sprctl &= ~(SPRITE_SOURCE_KEY | SPRITE_DEST_KEY); | |
716 | if (key->flags & I915_SET_COLORKEY_DESTINATION) | |
717 | sprctl |= SPRITE_DEST_KEY; | |
718 | else if (key->flags & I915_SET_COLORKEY_SOURCE) | |
719 | sprctl |= SPRITE_SOURCE_KEY; | |
720 | I915_WRITE(SPRCTL(intel_plane->pipe), sprctl); | |
721 | ||
722 | POSTING_READ(SPRKEYMSK(intel_plane->pipe)); | |
723 | ||
724 | return ret; | |
725 | } | |
726 | ||
727 | static void | |
728 | ivb_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key) | |
729 | { | |
730 | struct drm_device *dev = plane->dev; | |
731 | struct drm_i915_private *dev_priv = dev->dev_private; | |
732 | struct intel_plane *intel_plane; | |
733 | u32 sprctl; | |
734 | ||
735 | intel_plane = to_intel_plane(plane); | |
736 | ||
737 | key->min_value = I915_READ(SPRKEYVAL(intel_plane->pipe)); | |
738 | key->max_value = I915_READ(SPRKEYMAX(intel_plane->pipe)); | |
739 | key->channel_mask = I915_READ(SPRKEYMSK(intel_plane->pipe)); | |
740 | key->flags = 0; | |
741 | ||
742 | sprctl = I915_READ(SPRCTL(intel_plane->pipe)); | |
743 | ||
744 | if (sprctl & SPRITE_DEST_KEY) | |
745 | key->flags = I915_SET_COLORKEY_DESTINATION; | |
746 | else if (sprctl & SPRITE_SOURCE_KEY) | |
747 | key->flags = I915_SET_COLORKEY_SOURCE; | |
748 | else | |
749 | key->flags = I915_SET_COLORKEY_NONE; | |
750 | } | |
751 | ||
b840d907 | 752 | static void |
b39d53f6 VS |
753 | ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, |
754 | struct drm_framebuffer *fb, | |
b840d907 JB |
755 | struct drm_i915_gem_object *obj, int crtc_x, int crtc_y, |
756 | unsigned int crtc_w, unsigned int crtc_h, | |
757 | uint32_t x, uint32_t y, | |
758 | uint32_t src_w, uint32_t src_h) | |
759 | { | |
760 | struct drm_device *dev = plane->dev; | |
761 | struct drm_i915_private *dev_priv = dev->dev_private; | |
762 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
8d7849db | 763 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2bd3c3cb | 764 | int pipe = intel_plane->pipe; |
5a35e99e | 765 | unsigned long dvssurf_offset, linear_offset; |
8aaa81a1 | 766 | u32 dvscntr, dvsscale; |
2bd3c3cb | 767 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
8d7849db VS |
768 | u32 start_vbl_count; |
769 | bool atomic_update; | |
b840d907 JB |
770 | |
771 | dvscntr = I915_READ(DVSCNTR(pipe)); | |
772 | ||
773 | /* Mask out pixel format bits in case we change it */ | |
774 | dvscntr &= ~DVS_PIXFORMAT_MASK; | |
ab2f9df1 | 775 | dvscntr &= ~DVS_RGB_ORDER_XBGR; |
b840d907 | 776 | dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK; |
79626523 | 777 | dvscntr &= ~DVS_TILED; |
76eebda7 | 778 | dvscntr &= ~DVS_ROTATE_180; |
b840d907 JB |
779 | |
780 | switch (fb->pixel_format) { | |
781 | case DRM_FORMAT_XBGR8888: | |
ab2f9df1 | 782 | dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR; |
b840d907 JB |
783 | break; |
784 | case DRM_FORMAT_XRGB8888: | |
ab2f9df1 | 785 | dvscntr |= DVS_FORMAT_RGBX888; |
b840d907 JB |
786 | break; |
787 | case DRM_FORMAT_YUYV: | |
788 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV; | |
b840d907 JB |
789 | break; |
790 | case DRM_FORMAT_YVYU: | |
791 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU; | |
b840d907 JB |
792 | break; |
793 | case DRM_FORMAT_UYVY: | |
794 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY; | |
b840d907 JB |
795 | break; |
796 | case DRM_FORMAT_VYUY: | |
797 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY; | |
b840d907 JB |
798 | break; |
799 | default: | |
28d491df | 800 | BUG(); |
b840d907 JB |
801 | } |
802 | ||
4ea67bc7 VS |
803 | /* |
804 | * Enable gamma to match primary/cursor plane behaviour. | |
805 | * FIXME should be user controllable via propertiesa. | |
806 | */ | |
807 | dvscntr |= DVS_GAMMA_ENABLE; | |
808 | ||
b840d907 JB |
809 | if (obj->tiling_mode != I915_TILING_NONE) |
810 | dvscntr |= DVS_TILED; | |
811 | ||
d1686ae3 CW |
812 | if (IS_GEN6(dev)) |
813 | dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */ | |
b840d907 JB |
814 | dvscntr |= DVS_ENABLE; |
815 | ||
ed57cb8a DL |
816 | intel_update_sprite_watermarks(plane, crtc, src_w, src_h, |
817 | pixel_size, true, | |
67ca28f3 VS |
818 | src_w != crtc_w || src_h != crtc_h); |
819 | ||
b840d907 JB |
820 | /* Sizes are 0 based */ |
821 | src_w--; | |
822 | src_h--; | |
823 | crtc_w--; | |
824 | crtc_h--; | |
825 | ||
8aaa81a1 | 826 | dvsscale = 0; |
8368f014 | 827 | if (crtc_w != src_w || crtc_h != src_h) |
b840d907 JB |
828 | dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h; |
829 | ||
ca320ac4 | 830 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
5a35e99e | 831 | dvssurf_offset = |
bc752862 CW |
832 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
833 | pixel_size, fb->pitches[0]); | |
5a35e99e DL |
834 | linear_offset -= dvssurf_offset; |
835 | ||
76eebda7 VS |
836 | if (intel_plane->rotation == BIT(DRM_ROTATE_180)) { |
837 | dvscntr |= DVS_ROTATE_180; | |
838 | ||
839 | x += src_w; | |
840 | y += src_h; | |
841 | linear_offset += src_h * fb->pitches[0] + src_w * pixel_size; | |
842 | } | |
843 | ||
8d7849db VS |
844 | atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count); |
845 | ||
5b633d6b VS |
846 | intel_update_primary_plane(intel_crtc); |
847 | ||
ca6ad025 VS |
848 | I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]); |
849 | I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x); | |
850 | ||
5a35e99e | 851 | if (obj->tiling_mode != I915_TILING_NONE) |
b840d907 | 852 | I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x); |
5a35e99e DL |
853 | else |
854 | I915_WRITE(DVSLINOFF(pipe), linear_offset); | |
b840d907 | 855 | |
b840d907 JB |
856 | I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w); |
857 | I915_WRITE(DVSSCALE(pipe), dvsscale); | |
858 | I915_WRITE(DVSCNTR(pipe), dvscntr); | |
85ba7b7d DV |
859 | I915_WRITE(DVSSURF(pipe), |
860 | i915_gem_obj_ggtt_offset(obj) + dvssurf_offset); | |
5b633d6b VS |
861 | |
862 | intel_flush_primary_plane(dev_priv, intel_crtc->plane); | |
8d7849db VS |
863 | |
864 | if (atomic_update) | |
865 | intel_pipe_update_end(intel_crtc, start_vbl_count); | |
b840d907 JB |
866 | } |
867 | ||
868 | static void | |
b39d53f6 | 869 | ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc) |
b840d907 JB |
870 | { |
871 | struct drm_device *dev = plane->dev; | |
872 | struct drm_i915_private *dev_priv = dev->dev_private; | |
873 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
8d7849db | 874 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
b840d907 | 875 | int pipe = intel_plane->pipe; |
8d7849db VS |
876 | u32 start_vbl_count; |
877 | bool atomic_update; | |
878 | ||
879 | atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count); | |
b840d907 | 880 | |
5b633d6b VS |
881 | intel_update_primary_plane(intel_crtc); |
882 | ||
b840d907 JB |
883 | I915_WRITE(DVSCNTR(pipe), I915_READ(DVSCNTR(pipe)) & ~DVS_ENABLE); |
884 | /* Disable the scaler */ | |
885 | I915_WRITE(DVSSCALE(pipe), 0); | |
886 | /* Flush double buffered register updates */ | |
85ba7b7d | 887 | I915_WRITE(DVSSURF(pipe), 0); |
5b633d6b VS |
888 | |
889 | intel_flush_primary_plane(dev_priv, intel_crtc->plane); | |
a95fd8ca | 890 | |
8d7849db VS |
891 | if (atomic_update) |
892 | intel_pipe_update_end(intel_crtc, start_vbl_count); | |
893 | ||
1bd09ec7 VS |
894 | /* |
895 | * Avoid underruns when disabling the sprite. | |
896 | * FIXME remove once watermark updates are done properly. | |
897 | */ | |
898 | intel_wait_for_vblank(dev, pipe); | |
899 | ||
ed57cb8a | 900 | intel_update_sprite_watermarks(plane, crtc, 0, 0, 0, false, false); |
b840d907 JB |
901 | } |
902 | ||
175bd420 | 903 | static void |
5b633d6b | 904 | intel_post_enable_primary(struct drm_crtc *crtc) |
175bd420 JB |
905 | { |
906 | struct drm_device *dev = crtc->dev; | |
175bd420 | 907 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
abae50ed | 908 | |
33c3b0d1 VS |
909 | /* |
910 | * BDW signals flip done immediately if the plane | |
911 | * is disabled, even if the plane enable is already | |
912 | * armed to occur at the next vblank :( | |
913 | */ | |
914 | if (IS_BROADWELL(dev)) | |
915 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
916 | ||
20bc8673 VS |
917 | /* |
918 | * FIXME IPS should be fine as long as one plane is | |
919 | * enabled, but in practice it seems to have problems | |
920 | * when going from primary only to sprite only and vice | |
921 | * versa. | |
922 | */ | |
cea165c3 | 923 | hsw_enable_ips(intel_crtc); |
20bc8673 | 924 | |
82284b6b | 925 | mutex_lock(&dev->struct_mutex); |
93314b5b | 926 | intel_update_fbc(dev); |
82284b6b | 927 | mutex_unlock(&dev->struct_mutex); |
175bd420 JB |
928 | } |
929 | ||
930 | static void | |
5b633d6b | 931 | intel_pre_disable_primary(struct drm_crtc *crtc) |
175bd420 JB |
932 | { |
933 | struct drm_device *dev = crtc->dev; | |
934 | struct drm_i915_private *dev_priv = dev->dev_private; | |
935 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
82284b6b VS |
936 | |
937 | mutex_lock(&dev->struct_mutex); | |
abae50ed VS |
938 | if (dev_priv->fbc.plane == intel_crtc->plane) |
939 | intel_disable_fbc(dev); | |
82284b6b | 940 | mutex_unlock(&dev->struct_mutex); |
abae50ed | 941 | |
20bc8673 VS |
942 | /* |
943 | * FIXME IPS should be fine as long as one plane is | |
944 | * enabled, but in practice it seems to have problems | |
945 | * when going from primary only to sprite only and vice | |
946 | * versa. | |
947 | */ | |
948 | hsw_disable_ips(intel_crtc); | |
175bd420 JB |
949 | } |
950 | ||
8ea30864 | 951 | static int |
d1686ae3 | 952 | ilk_update_colorkey(struct drm_plane *plane, |
8ea30864 JB |
953 | struct drm_intel_sprite_colorkey *key) |
954 | { | |
955 | struct drm_device *dev = plane->dev; | |
956 | struct drm_i915_private *dev_priv = dev->dev_private; | |
957 | struct intel_plane *intel_plane; | |
958 | u32 dvscntr; | |
959 | int ret = 0; | |
960 | ||
961 | intel_plane = to_intel_plane(plane); | |
962 | ||
963 | I915_WRITE(DVSKEYVAL(intel_plane->pipe), key->min_value); | |
964 | I915_WRITE(DVSKEYMAX(intel_plane->pipe), key->max_value); | |
965 | I915_WRITE(DVSKEYMSK(intel_plane->pipe), key->channel_mask); | |
966 | ||
967 | dvscntr = I915_READ(DVSCNTR(intel_plane->pipe)); | |
968 | dvscntr &= ~(DVS_SOURCE_KEY | DVS_DEST_KEY); | |
969 | if (key->flags & I915_SET_COLORKEY_DESTINATION) | |
970 | dvscntr |= DVS_DEST_KEY; | |
971 | else if (key->flags & I915_SET_COLORKEY_SOURCE) | |
972 | dvscntr |= DVS_SOURCE_KEY; | |
973 | I915_WRITE(DVSCNTR(intel_plane->pipe), dvscntr); | |
974 | ||
975 | POSTING_READ(DVSKEYMSK(intel_plane->pipe)); | |
976 | ||
977 | return ret; | |
978 | } | |
979 | ||
980 | static void | |
d1686ae3 | 981 | ilk_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key) |
8ea30864 JB |
982 | { |
983 | struct drm_device *dev = plane->dev; | |
984 | struct drm_i915_private *dev_priv = dev->dev_private; | |
985 | struct intel_plane *intel_plane; | |
986 | u32 dvscntr; | |
987 | ||
988 | intel_plane = to_intel_plane(plane); | |
989 | ||
990 | key->min_value = I915_READ(DVSKEYVAL(intel_plane->pipe)); | |
991 | key->max_value = I915_READ(DVSKEYMAX(intel_plane->pipe)); | |
992 | key->channel_mask = I915_READ(DVSKEYMSK(intel_plane->pipe)); | |
993 | key->flags = 0; | |
994 | ||
995 | dvscntr = I915_READ(DVSCNTR(intel_plane->pipe)); | |
996 | ||
997 | if (dvscntr & DVS_DEST_KEY) | |
998 | key->flags = I915_SET_COLORKEY_DESTINATION; | |
999 | else if (dvscntr & DVS_SOURCE_KEY) | |
1000 | key->flags = I915_SET_COLORKEY_SOURCE; | |
1001 | else | |
1002 | key->flags = I915_SET_COLORKEY_NONE; | |
1003 | } | |
1004 | ||
1731693a VS |
1005 | static bool |
1006 | format_is_yuv(uint32_t format) | |
1007 | { | |
1008 | switch (format) { | |
1009 | case DRM_FORMAT_YUYV: | |
1010 | case DRM_FORMAT_UYVY: | |
1011 | case DRM_FORMAT_VYUY: | |
1012 | case DRM_FORMAT_YVYU: | |
1013 | return true; | |
1014 | default: | |
1015 | return false; | |
1016 | } | |
1017 | } | |
1018 | ||
efb31d15 VS |
1019 | static bool colorkey_enabled(struct intel_plane *intel_plane) |
1020 | { | |
1021 | struct drm_intel_sprite_colorkey key; | |
1022 | ||
1023 | intel_plane->get_colorkey(&intel_plane->base, &key); | |
1024 | ||
1025 | return key.flags != I915_SET_COLORKEY_NONE; | |
1026 | } | |
1027 | ||
b840d907 | 1028 | static int |
96d61a7f GP |
1029 | intel_check_sprite_plane(struct drm_plane *plane, |
1030 | struct intel_plane_state *state) | |
b840d907 | 1031 | { |
96d61a7f | 1032 | struct intel_crtc *intel_crtc = to_intel_crtc(state->crtc); |
b840d907 | 1033 | struct intel_plane *intel_plane = to_intel_plane(plane); |
96d61a7f | 1034 | struct drm_framebuffer *fb = state->fb; |
77cde952 | 1035 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
96d61a7f GP |
1036 | int crtc_x, crtc_y; |
1037 | unsigned int crtc_w, crtc_h; | |
1038 | uint32_t src_x, src_y, src_w, src_h; | |
1039 | struct drm_rect *src = &state->src; | |
1040 | struct drm_rect *dst = &state->dst; | |
1041 | struct drm_rect *orig_src = &state->orig_src; | |
1042 | const struct drm_rect *clip = &state->clip; | |
1731693a VS |
1043 | int hscale, vscale; |
1044 | int max_scale, min_scale; | |
1045 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
5e1bac2f | 1046 | |
1731693a VS |
1047 | /* Don't modify another pipe's plane */ |
1048 | if (intel_plane->pipe != intel_crtc->pipe) { | |
1049 | DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n"); | |
b840d907 | 1050 | return -EINVAL; |
1731693a | 1051 | } |
b840d907 | 1052 | |
1731693a VS |
1053 | /* FIXME check all gen limits */ |
1054 | if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) { | |
1055 | DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n"); | |
b840d907 | 1056 | return -EINVAL; |
1731693a | 1057 | } |
b840d907 | 1058 | |
94c6419e DL |
1059 | /* Sprite planes can be linear or x-tiled surfaces */ |
1060 | switch (obj->tiling_mode) { | |
1061 | case I915_TILING_NONE: | |
1062 | case I915_TILING_X: | |
1063 | break; | |
1064 | default: | |
1731693a | 1065 | DRM_DEBUG_KMS("Unsupported tiling mode\n"); |
94c6419e DL |
1066 | return -EINVAL; |
1067 | } | |
1068 | ||
3c3686cd VS |
1069 | /* |
1070 | * FIXME the following code does a bunch of fuzzy adjustments to the | |
1071 | * coordinates and sizes. We probably need some way to decide whether | |
1072 | * more strict checking should be done instead. | |
1073 | */ | |
1731693a VS |
1074 | max_scale = intel_plane->max_downscale << 16; |
1075 | min_scale = intel_plane->can_scale ? 1 : (1 << 16); | |
1076 | ||
96d61a7f | 1077 | drm_rect_rotate(src, fb->width << 16, fb->height << 16, |
76eebda7 VS |
1078 | intel_plane->rotation); |
1079 | ||
96d61a7f | 1080 | hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale); |
3c3686cd | 1081 | BUG_ON(hscale < 0); |
1731693a | 1082 | |
96d61a7f | 1083 | vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale); |
3c3686cd | 1084 | BUG_ON(vscale < 0); |
b840d907 | 1085 | |
96d61a7f | 1086 | state->visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale); |
b840d907 | 1087 | |
96d61a7f GP |
1088 | crtc_x = dst->x1; |
1089 | crtc_y = dst->y1; | |
1090 | crtc_w = drm_rect_width(dst); | |
1091 | crtc_h = drm_rect_height(dst); | |
2d354c34 | 1092 | |
96d61a7f | 1093 | if (state->visible) { |
3c3686cd | 1094 | /* check again in case clipping clamped the results */ |
96d61a7f | 1095 | hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale); |
3c3686cd VS |
1096 | if (hscale < 0) { |
1097 | DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n"); | |
96d61a7f GP |
1098 | drm_rect_debug_print(src, true); |
1099 | drm_rect_debug_print(dst, false); | |
3c3686cd VS |
1100 | |
1101 | return hscale; | |
1102 | } | |
1103 | ||
96d61a7f | 1104 | vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale); |
3c3686cd VS |
1105 | if (vscale < 0) { |
1106 | DRM_DEBUG_KMS("Vertical scaling factor out of limits\n"); | |
96d61a7f GP |
1107 | drm_rect_debug_print(src, true); |
1108 | drm_rect_debug_print(dst, false); | |
3c3686cd VS |
1109 | |
1110 | return vscale; | |
1111 | } | |
1112 | ||
1731693a | 1113 | /* Make the source viewport size an exact multiple of the scaling factors. */ |
96d61a7f GP |
1114 | drm_rect_adjust_size(src, |
1115 | drm_rect_width(dst) * hscale - drm_rect_width(src), | |
1116 | drm_rect_height(dst) * vscale - drm_rect_height(src)); | |
1731693a | 1117 | |
96d61a7f | 1118 | drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16, |
76eebda7 VS |
1119 | intel_plane->rotation); |
1120 | ||
1731693a | 1121 | /* sanity check to make sure the src viewport wasn't enlarged */ |
96d61a7f GP |
1122 | WARN_ON(src->x1 < (int) orig_src->x1 || |
1123 | src->y1 < (int) orig_src->y1 || | |
1124 | src->x2 > (int) orig_src->x2 || | |
1125 | src->y2 > (int) orig_src->y2); | |
1731693a VS |
1126 | |
1127 | /* | |
1128 | * Hardware doesn't handle subpixel coordinates. | |
1129 | * Adjust to (macro)pixel boundary, but be careful not to | |
1130 | * increase the source viewport size, because that could | |
1131 | * push the downscaling factor out of bounds. | |
1731693a | 1132 | */ |
96d61a7f GP |
1133 | src_x = src->x1 >> 16; |
1134 | src_w = drm_rect_width(src) >> 16; | |
1135 | src_y = src->y1 >> 16; | |
1136 | src_h = drm_rect_height(src) >> 16; | |
1731693a VS |
1137 | |
1138 | if (format_is_yuv(fb->pixel_format)) { | |
1139 | src_x &= ~1; | |
1140 | src_w &= ~1; | |
1141 | ||
1142 | /* | |
1143 | * Must keep src and dst the | |
1144 | * same if we can't scale. | |
1145 | */ | |
1146 | if (!intel_plane->can_scale) | |
1147 | crtc_w &= ~1; | |
1148 | ||
1149 | if (crtc_w == 0) | |
96d61a7f | 1150 | state->visible = false; |
1731693a VS |
1151 | } |
1152 | } | |
1153 | ||
1154 | /* Check size restrictions when scaling */ | |
96d61a7f | 1155 | if (state->visible && (src_w != crtc_w || src_h != crtc_h)) { |
1731693a VS |
1156 | unsigned int width_bytes; |
1157 | ||
1158 | WARN_ON(!intel_plane->can_scale); | |
1159 | ||
1160 | /* FIXME interlacing min height is 6 */ | |
1161 | ||
1162 | if (crtc_w < 3 || crtc_h < 3) | |
96d61a7f | 1163 | state->visible = false; |
1731693a VS |
1164 | |
1165 | if (src_w < 3 || src_h < 3) | |
96d61a7f | 1166 | state->visible = false; |
1731693a | 1167 | |
96d61a7f GP |
1168 | width_bytes = ((src_x * pixel_size) & 63) + |
1169 | src_w * pixel_size; | |
1731693a VS |
1170 | |
1171 | if (src_w > 2048 || src_h > 2048 || | |
1172 | width_bytes > 4096 || fb->pitches[0] > 4096) { | |
1173 | DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n"); | |
1174 | return -EINVAL; | |
1175 | } | |
1176 | } | |
1177 | ||
96d61a7f GP |
1178 | if (state->visible) { |
1179 | src->x1 = src_x; | |
1180 | src->x2 = src_x + src_w; | |
1181 | src->y1 = src_y; | |
1182 | src->y2 = src_y + src_h; | |
1183 | } | |
1184 | ||
1185 | dst->x1 = crtc_x; | |
1186 | dst->x2 = crtc_x + crtc_w; | |
1187 | dst->y1 = crtc_y; | |
1188 | dst->y2 = crtc_y + crtc_h; | |
1189 | ||
1190 | return 0; | |
1191 | } | |
1192 | ||
1193 | static int | |
34aa50a9 GP |
1194 | intel_prepare_sprite_plane(struct drm_plane *plane, |
1195 | struct intel_plane_state *state) | |
96d61a7f GP |
1196 | { |
1197 | struct drm_device *dev = plane->dev; | |
1198 | struct drm_crtc *crtc = state->crtc; | |
1199 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
96d61a7f GP |
1200 | enum pipe pipe = intel_crtc->pipe; |
1201 | struct drm_framebuffer *fb = state->fb; | |
34aa50a9 GP |
1202 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1203 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb); | |
96d61a7f | 1204 | int ret; |
b840d907 | 1205 | |
25067bfc GP |
1206 | if (old_obj != obj) { |
1207 | mutex_lock(&dev->struct_mutex); | |
82284b6b | 1208 | |
25067bfc GP |
1209 | /* Note that this will apply the VT-d workaround for scanouts, |
1210 | * which is more restrictive than required for sprites. (The | |
1211 | * primary plane requires 256KiB alignment with 64 PTE padding, | |
1212 | * the sprite planes only require 128KiB alignment and 32 PTE | |
1213 | * padding. | |
1214 | */ | |
1215 | ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); | |
1216 | if (ret == 0) | |
1217 | i915_gem_track_fb(old_obj, obj, | |
1218 | INTEL_FRONTBUFFER_SPRITE(pipe)); | |
1219 | mutex_unlock(&dev->struct_mutex); | |
1220 | if (ret) | |
1221 | return ret; | |
1222 | } | |
b840d907 | 1223 | |
34aa50a9 GP |
1224 | return 0; |
1225 | } | |
1226 | ||
1227 | static void | |
1228 | intel_commit_sprite_plane(struct drm_plane *plane, | |
1229 | struct intel_plane_state *state) | |
1230 | { | |
1231 | struct drm_device *dev = plane->dev; | |
1232 | struct drm_crtc *crtc = state->crtc; | |
1233 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1234 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
1235 | enum pipe pipe = intel_crtc->pipe; | |
1236 | struct drm_framebuffer *fb = state->fb; | |
77cde952 GP |
1237 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1238 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb); | |
34aa50a9 GP |
1239 | int crtc_x, crtc_y; |
1240 | unsigned int crtc_w, crtc_h; | |
1241 | uint32_t src_x, src_y, src_w, src_h; | |
1242 | struct drm_rect *dst = &state->dst; | |
1243 | const struct drm_rect *clip = &state->clip; | |
1244 | bool primary_enabled; | |
1245 | ||
1246 | /* | |
1247 | * If the sprite is completely covering the primary plane, | |
1248 | * we can disable the primary and save power. | |
1249 | */ | |
1250 | primary_enabled = !drm_rect_equals(dst, clip) || colorkey_enabled(intel_plane); | |
1251 | WARN_ON(!primary_enabled && !state->visible && intel_crtc->active); | |
1252 | ||
96d61a7f GP |
1253 | intel_plane->crtc_x = state->orig_dst.x1; |
1254 | intel_plane->crtc_y = state->orig_dst.y1; | |
1255 | intel_plane->crtc_w = drm_rect_width(&state->orig_dst); | |
1256 | intel_plane->crtc_h = drm_rect_height(&state->orig_dst); | |
1257 | intel_plane->src_x = state->orig_src.x1; | |
1258 | intel_plane->src_y = state->orig_src.y1; | |
1259 | intel_plane->src_w = drm_rect_width(&state->orig_src); | |
1260 | intel_plane->src_h = drm_rect_height(&state->orig_src); | |
b840d907 JB |
1261 | intel_plane->obj = obj; |
1262 | ||
03c5b25f | 1263 | if (intel_crtc->active) { |
5b633d6b VS |
1264 | bool primary_was_enabled = intel_crtc->primary_enabled; |
1265 | ||
1266 | intel_crtc->primary_enabled = primary_enabled; | |
1267 | ||
46a55d30 VS |
1268 | if (primary_was_enabled != primary_enabled) |
1269 | intel_crtc_wait_for_pending_flips(crtc); | |
1270 | ||
5b633d6b VS |
1271 | if (primary_was_enabled && !primary_enabled) |
1272 | intel_pre_disable_primary(crtc); | |
03c5b25f | 1273 | |
96d61a7f GP |
1274 | if (state->visible) { |
1275 | crtc_x = state->dst.x1; | |
e259f172 | 1276 | crtc_y = state->dst.y1; |
96d61a7f GP |
1277 | crtc_w = drm_rect_width(&state->dst); |
1278 | crtc_h = drm_rect_height(&state->dst); | |
1279 | src_x = state->src.x1; | |
1280 | src_y = state->src.y1; | |
1281 | src_w = drm_rect_width(&state->src); | |
1282 | src_h = drm_rect_height(&state->src); | |
03c5b25f VS |
1283 | intel_plane->update_plane(plane, crtc, fb, obj, |
1284 | crtc_x, crtc_y, crtc_w, crtc_h, | |
1285 | src_x, src_y, src_w, src_h); | |
96d61a7f | 1286 | } else { |
03c5b25f | 1287 | intel_plane->disable_plane(plane, crtc); |
96d61a7f GP |
1288 | } |
1289 | ||
03c5b25f | 1290 | |
f99d7069 DV |
1291 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_SPRITE(pipe)); |
1292 | ||
5b633d6b VS |
1293 | if (!primary_was_enabled && primary_enabled) |
1294 | intel_post_enable_primary(crtc); | |
03c5b25f | 1295 | } |
175bd420 | 1296 | |
b840d907 | 1297 | /* Unpin old obj after new one is active to avoid ugliness */ |
25067bfc GP |
1298 | if (old_obj && old_obj != obj) { |
1299 | ||
b840d907 JB |
1300 | /* |
1301 | * It's fairly common to simply update the position of | |
1302 | * an existing object. In that case, we don't need to | |
1303 | * wait for vblank to avoid ugliness, we only need to | |
1304 | * do the pin & ref bookkeeping. | |
1305 | */ | |
25067bfc | 1306 | if (intel_crtc->active) |
2afd9efd | 1307 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
82284b6b VS |
1308 | |
1309 | mutex_lock(&dev->struct_mutex); | |
1690e1eb | 1310 | intel_unpin_fb_obj(old_obj); |
82284b6b | 1311 | mutex_unlock(&dev->struct_mutex); |
b840d907 | 1312 | } |
b840d907 JB |
1313 | } |
1314 | ||
96d61a7f GP |
1315 | static int |
1316 | intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, | |
1317 | struct drm_framebuffer *fb, int crtc_x, int crtc_y, | |
1318 | unsigned int crtc_w, unsigned int crtc_h, | |
1319 | uint32_t src_x, uint32_t src_y, | |
1320 | uint32_t src_w, uint32_t src_h) | |
1321 | { | |
1322 | struct intel_plane_state state; | |
1323 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1324 | int ret; | |
1325 | ||
1326 | state.crtc = crtc; | |
1327 | state.fb = fb; | |
1328 | ||
1329 | /* sample coordinates in 16.16 fixed point */ | |
1330 | state.src.x1 = src_x; | |
1331 | state.src.x2 = src_x + src_w; | |
1332 | state.src.y1 = src_y; | |
1333 | state.src.y2 = src_y + src_h; | |
1334 | ||
1335 | /* integer pixels */ | |
1336 | state.dst.x1 = crtc_x; | |
1337 | state.dst.x2 = crtc_x + crtc_w; | |
1338 | state.dst.y1 = crtc_y; | |
1339 | state.dst.y2 = crtc_y + crtc_h; | |
1340 | ||
1341 | state.clip.x1 = 0; | |
1342 | state.clip.y1 = 0; | |
1343 | state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0; | |
1344 | state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0; | |
1345 | state.orig_src = state.src; | |
1346 | state.orig_dst = state.dst; | |
1347 | ||
1348 | ret = intel_check_sprite_plane(plane, &state); | |
1349 | if (ret) | |
1350 | return ret; | |
1351 | ||
34aa50a9 GP |
1352 | ret = intel_prepare_sprite_plane(plane, &state); |
1353 | if (ret) | |
1354 | return ret; | |
1355 | ||
1356 | intel_commit_sprite_plane(plane, &state); | |
1357 | return 0; | |
96d61a7f GP |
1358 | } |
1359 | ||
b840d907 JB |
1360 | static int |
1361 | intel_disable_plane(struct drm_plane *plane) | |
1362 | { | |
1363 | struct drm_device *dev = plane->dev; | |
1364 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
03c5b25f | 1365 | struct intel_crtc *intel_crtc; |
a071fa00 | 1366 | enum pipe pipe; |
b840d907 | 1367 | |
88a94a58 VS |
1368 | if (!plane->fb) |
1369 | return 0; | |
1370 | ||
1371 | if (WARN_ON(!plane->crtc)) | |
1372 | return -EINVAL; | |
1373 | ||
03c5b25f | 1374 | intel_crtc = to_intel_crtc(plane->crtc); |
a071fa00 | 1375 | pipe = intel_crtc->pipe; |
03c5b25f VS |
1376 | |
1377 | if (intel_crtc->active) { | |
5b633d6b VS |
1378 | bool primary_was_enabled = intel_crtc->primary_enabled; |
1379 | ||
1380 | intel_crtc->primary_enabled = true; | |
1381 | ||
03c5b25f | 1382 | intel_plane->disable_plane(plane, plane->crtc); |
5b633d6b VS |
1383 | |
1384 | if (!primary_was_enabled && intel_crtc->primary_enabled) | |
1385 | intel_post_enable_primary(plane->crtc); | |
03c5b25f | 1386 | } |
b840d907 | 1387 | |
5f3fb46b VS |
1388 | if (intel_plane->obj) { |
1389 | if (intel_crtc->active) | |
1390 | intel_wait_for_vblank(dev, intel_plane->pipe); | |
c626d317 | 1391 | |
5f3fb46b VS |
1392 | mutex_lock(&dev->struct_mutex); |
1393 | intel_unpin_fb_obj(intel_plane->obj); | |
a071fa00 DV |
1394 | i915_gem_track_fb(intel_plane->obj, NULL, |
1395 | INTEL_FRONTBUFFER_SPRITE(pipe)); | |
5f3fb46b | 1396 | mutex_unlock(&dev->struct_mutex); |
82284b6b | 1397 | |
5f3fb46b VS |
1398 | intel_plane->obj = NULL; |
1399 | } | |
b840d907 | 1400 | |
5f3fb46b | 1401 | return 0; |
b840d907 JB |
1402 | } |
1403 | ||
1404 | static void intel_destroy_plane(struct drm_plane *plane) | |
1405 | { | |
1406 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
1407 | intel_disable_plane(plane); | |
1408 | drm_plane_cleanup(plane); | |
1409 | kfree(intel_plane); | |
1410 | } | |
1411 | ||
8ea30864 JB |
1412 | int intel_sprite_set_colorkey(struct drm_device *dev, void *data, |
1413 | struct drm_file *file_priv) | |
1414 | { | |
1415 | struct drm_intel_sprite_colorkey *set = data; | |
8ea30864 JB |
1416 | struct drm_plane *plane; |
1417 | struct intel_plane *intel_plane; | |
1418 | int ret = 0; | |
1419 | ||
1cff8f6b DV |
1420 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
1421 | return -ENODEV; | |
8ea30864 JB |
1422 | |
1423 | /* Make sure we don't try to enable both src & dest simultaneously */ | |
1424 | if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) | |
1425 | return -EINVAL; | |
1426 | ||
a0e99e68 | 1427 | drm_modeset_lock_all(dev); |
8ea30864 | 1428 | |
7707e653 RC |
1429 | plane = drm_plane_find(dev, set->plane_id); |
1430 | if (!plane) { | |
3f2c2057 | 1431 | ret = -ENOENT; |
8ea30864 JB |
1432 | goto out_unlock; |
1433 | } | |
1434 | ||
8ea30864 JB |
1435 | intel_plane = to_intel_plane(plane); |
1436 | ret = intel_plane->update_colorkey(plane, set); | |
1437 | ||
1438 | out_unlock: | |
a0e99e68 | 1439 | drm_modeset_unlock_all(dev); |
8ea30864 JB |
1440 | return ret; |
1441 | } | |
1442 | ||
1443 | int intel_sprite_get_colorkey(struct drm_device *dev, void *data, | |
1444 | struct drm_file *file_priv) | |
1445 | { | |
1446 | struct drm_intel_sprite_colorkey *get = data; | |
8ea30864 JB |
1447 | struct drm_plane *plane; |
1448 | struct intel_plane *intel_plane; | |
1449 | int ret = 0; | |
1450 | ||
1cff8f6b DV |
1451 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
1452 | return -ENODEV; | |
8ea30864 | 1453 | |
a0e99e68 | 1454 | drm_modeset_lock_all(dev); |
8ea30864 | 1455 | |
7707e653 RC |
1456 | plane = drm_plane_find(dev, get->plane_id); |
1457 | if (!plane) { | |
3f2c2057 | 1458 | ret = -ENOENT; |
8ea30864 JB |
1459 | goto out_unlock; |
1460 | } | |
1461 | ||
8ea30864 JB |
1462 | intel_plane = to_intel_plane(plane); |
1463 | intel_plane->get_colorkey(plane, get); | |
1464 | ||
1465 | out_unlock: | |
a0e99e68 | 1466 | drm_modeset_unlock_all(dev); |
8ea30864 JB |
1467 | return ret; |
1468 | } | |
1469 | ||
48404c1e SJ |
1470 | int intel_plane_set_property(struct drm_plane *plane, |
1471 | struct drm_property *prop, | |
1472 | uint64_t val) | |
7ed6eeee VS |
1473 | { |
1474 | struct drm_device *dev = plane->dev; | |
1475 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
1476 | uint64_t old_val; | |
1477 | int ret = -ENOENT; | |
1478 | ||
1479 | if (prop == dev->mode_config.rotation_property) { | |
1480 | /* exactly one rotation angle please */ | |
1481 | if (hweight32(val & 0xf) != 1) | |
1482 | return -EINVAL; | |
1483 | ||
09dba00c VS |
1484 | if (intel_plane->rotation == val) |
1485 | return 0; | |
1486 | ||
7ed6eeee VS |
1487 | old_val = intel_plane->rotation; |
1488 | intel_plane->rotation = val; | |
1489 | ret = intel_plane_restore(plane); | |
1490 | if (ret) | |
1491 | intel_plane->rotation = old_val; | |
1492 | } | |
1493 | ||
1494 | return ret; | |
1495 | } | |
1496 | ||
e57465f3 | 1497 | int intel_plane_restore(struct drm_plane *plane) |
5e1bac2f JB |
1498 | { |
1499 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
1500 | ||
1501 | if (!plane->crtc || !plane->fb) | |
e57465f3 | 1502 | return 0; |
5e1bac2f | 1503 | |
48404c1e | 1504 | return plane->funcs->update_plane(plane, plane->crtc, plane->fb, |
e57465f3 VS |
1505 | intel_plane->crtc_x, intel_plane->crtc_y, |
1506 | intel_plane->crtc_w, intel_plane->crtc_h, | |
1507 | intel_plane->src_x, intel_plane->src_y, | |
1508 | intel_plane->src_w, intel_plane->src_h); | |
5e1bac2f JB |
1509 | } |
1510 | ||
bb53d4ae VS |
1511 | void intel_plane_disable(struct drm_plane *plane) |
1512 | { | |
1513 | if (!plane->crtc || !plane->fb) | |
1514 | return; | |
1515 | ||
1516 | intel_disable_plane(plane); | |
1517 | } | |
1518 | ||
b840d907 JB |
1519 | static const struct drm_plane_funcs intel_plane_funcs = { |
1520 | .update_plane = intel_update_plane, | |
1521 | .disable_plane = intel_disable_plane, | |
1522 | .destroy = intel_destroy_plane, | |
7ed6eeee | 1523 | .set_property = intel_plane_set_property, |
b840d907 JB |
1524 | }; |
1525 | ||
d1686ae3 CW |
1526 | static uint32_t ilk_plane_formats[] = { |
1527 | DRM_FORMAT_XRGB8888, | |
1528 | DRM_FORMAT_YUYV, | |
1529 | DRM_FORMAT_YVYU, | |
1530 | DRM_FORMAT_UYVY, | |
1531 | DRM_FORMAT_VYUY, | |
1532 | }; | |
1533 | ||
b840d907 JB |
1534 | static uint32_t snb_plane_formats[] = { |
1535 | DRM_FORMAT_XBGR8888, | |
1536 | DRM_FORMAT_XRGB8888, | |
1537 | DRM_FORMAT_YUYV, | |
1538 | DRM_FORMAT_YVYU, | |
1539 | DRM_FORMAT_UYVY, | |
1540 | DRM_FORMAT_VYUY, | |
1541 | }; | |
1542 | ||
7f1f3851 JB |
1543 | static uint32_t vlv_plane_formats[] = { |
1544 | DRM_FORMAT_RGB565, | |
1545 | DRM_FORMAT_ABGR8888, | |
1546 | DRM_FORMAT_ARGB8888, | |
1547 | DRM_FORMAT_XBGR8888, | |
1548 | DRM_FORMAT_XRGB8888, | |
1549 | DRM_FORMAT_XBGR2101010, | |
1550 | DRM_FORMAT_ABGR2101010, | |
1551 | DRM_FORMAT_YUYV, | |
1552 | DRM_FORMAT_YVYU, | |
1553 | DRM_FORMAT_UYVY, | |
1554 | DRM_FORMAT_VYUY, | |
1555 | }; | |
1556 | ||
dc2a41b4 DL |
1557 | static uint32_t skl_plane_formats[] = { |
1558 | DRM_FORMAT_RGB565, | |
1559 | DRM_FORMAT_ABGR8888, | |
1560 | DRM_FORMAT_ARGB8888, | |
1561 | DRM_FORMAT_XBGR8888, | |
1562 | DRM_FORMAT_XRGB8888, | |
1563 | DRM_FORMAT_YUYV, | |
1564 | DRM_FORMAT_YVYU, | |
1565 | DRM_FORMAT_UYVY, | |
1566 | DRM_FORMAT_VYUY, | |
1567 | }; | |
1568 | ||
b840d907 | 1569 | int |
7f1f3851 | 1570 | intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane) |
b840d907 JB |
1571 | { |
1572 | struct intel_plane *intel_plane; | |
1573 | unsigned long possible_crtcs; | |
d1686ae3 CW |
1574 | const uint32_t *plane_formats; |
1575 | int num_plane_formats; | |
b840d907 JB |
1576 | int ret; |
1577 | ||
d1686ae3 | 1578 | if (INTEL_INFO(dev)->gen < 5) |
b840d907 | 1579 | return -ENODEV; |
b840d907 | 1580 | |
b14c5679 | 1581 | intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL); |
b840d907 JB |
1582 | if (!intel_plane) |
1583 | return -ENOMEM; | |
1584 | ||
d1686ae3 CW |
1585 | switch (INTEL_INFO(dev)->gen) { |
1586 | case 5: | |
1587 | case 6: | |
2d354c34 | 1588 | intel_plane->can_scale = true; |
b840d907 | 1589 | intel_plane->max_downscale = 16; |
d1686ae3 CW |
1590 | intel_plane->update_plane = ilk_update_plane; |
1591 | intel_plane->disable_plane = ilk_disable_plane; | |
1592 | intel_plane->update_colorkey = ilk_update_colorkey; | |
1593 | intel_plane->get_colorkey = ilk_get_colorkey; | |
1594 | ||
1595 | if (IS_GEN6(dev)) { | |
1596 | plane_formats = snb_plane_formats; | |
1597 | num_plane_formats = ARRAY_SIZE(snb_plane_formats); | |
1598 | } else { | |
1599 | plane_formats = ilk_plane_formats; | |
1600 | num_plane_formats = ARRAY_SIZE(ilk_plane_formats); | |
1601 | } | |
1602 | break; | |
1603 | ||
1604 | case 7: | |
4e0bbc31 | 1605 | case 8: |
d49f7091 | 1606 | if (IS_IVYBRIDGE(dev)) { |
2d354c34 | 1607 | intel_plane->can_scale = true; |
d49f7091 DL |
1608 | intel_plane->max_downscale = 2; |
1609 | } else { | |
1610 | intel_plane->can_scale = false; | |
1611 | intel_plane->max_downscale = 1; | |
1612 | } | |
7f1f3851 JB |
1613 | |
1614 | if (IS_VALLEYVIEW(dev)) { | |
7f1f3851 JB |
1615 | intel_plane->update_plane = vlv_update_plane; |
1616 | intel_plane->disable_plane = vlv_disable_plane; | |
1617 | intel_plane->update_colorkey = vlv_update_colorkey; | |
1618 | intel_plane->get_colorkey = vlv_get_colorkey; | |
1619 | ||
1620 | plane_formats = vlv_plane_formats; | |
1621 | num_plane_formats = ARRAY_SIZE(vlv_plane_formats); | |
1622 | } else { | |
7f1f3851 JB |
1623 | intel_plane->update_plane = ivb_update_plane; |
1624 | intel_plane->disable_plane = ivb_disable_plane; | |
1625 | intel_plane->update_colorkey = ivb_update_colorkey; | |
1626 | intel_plane->get_colorkey = ivb_get_colorkey; | |
1627 | ||
1628 | plane_formats = snb_plane_formats; | |
1629 | num_plane_formats = ARRAY_SIZE(snb_plane_formats); | |
1630 | } | |
d1686ae3 | 1631 | break; |
dc2a41b4 DL |
1632 | case 9: |
1633 | /* | |
1634 | * FIXME: Skylake planes can be scaled (with some restrictions), | |
1635 | * but this is for another time. | |
1636 | */ | |
1637 | intel_plane->can_scale = false; | |
1638 | intel_plane->max_downscale = 1; | |
1639 | intel_plane->update_plane = skl_update_plane; | |
1640 | intel_plane->disable_plane = skl_disable_plane; | |
1641 | intel_plane->update_colorkey = skl_update_colorkey; | |
1642 | intel_plane->get_colorkey = skl_get_colorkey; | |
1643 | ||
1644 | plane_formats = skl_plane_formats; | |
1645 | num_plane_formats = ARRAY_SIZE(skl_plane_formats); | |
1646 | break; | |
d1686ae3 | 1647 | default: |
a8b0bbab | 1648 | kfree(intel_plane); |
d1686ae3 | 1649 | return -ENODEV; |
b840d907 JB |
1650 | } |
1651 | ||
1652 | intel_plane->pipe = pipe; | |
7f1f3851 | 1653 | intel_plane->plane = plane; |
76eebda7 | 1654 | intel_plane->rotation = BIT(DRM_ROTATE_0); |
b840d907 | 1655 | possible_crtcs = (1 << pipe); |
8fe8a3fe DF |
1656 | ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs, |
1657 | &intel_plane_funcs, | |
1658 | plane_formats, num_plane_formats, | |
1659 | DRM_PLANE_TYPE_OVERLAY); | |
7ed6eeee | 1660 | if (ret) { |
b840d907 | 1661 | kfree(intel_plane); |
7ed6eeee VS |
1662 | goto out; |
1663 | } | |
1664 | ||
1665 | if (!dev->mode_config.rotation_property) | |
1666 | dev->mode_config.rotation_property = | |
1667 | drm_mode_create_rotation_property(dev, | |
1668 | BIT(DRM_ROTATE_0) | | |
1669 | BIT(DRM_ROTATE_180)); | |
1670 | ||
1671 | if (dev->mode_config.rotation_property) | |
1672 | drm_object_attach_property(&intel_plane->base.base, | |
1673 | dev->mode_config.rotation_property, | |
1674 | intel_plane->rotation); | |
b840d907 | 1675 | |
7ed6eeee | 1676 | out: |
b840d907 JB |
1677 | return ret; |
1678 | } |