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b840d907 JB |
1 | /* |
2 | * Copyright © 2011 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
21 | * SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Jesse Barnes <jbarnes@virtuousgeek.org> | |
25 | * | |
26 | * New plane/sprite handling. | |
27 | * | |
28 | * The older chips had a separate interface for programming plane related | |
29 | * registers; newer ones are much simpler and we can use the new DRM plane | |
30 | * support. | |
31 | */ | |
760285e7 DH |
32 | #include <drm/drmP.h> |
33 | #include <drm/drm_crtc.h> | |
34 | #include <drm/drm_fourcc.h> | |
b840d907 | 35 | #include "intel_drv.h" |
760285e7 | 36 | #include <drm/i915_drm.h> |
b840d907 JB |
37 | #include "i915_drv.h" |
38 | ||
39 | static void | |
40 | ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, | |
41 | struct drm_i915_gem_object *obj, int crtc_x, int crtc_y, | |
42 | unsigned int crtc_w, unsigned int crtc_h, | |
43 | uint32_t x, uint32_t y, | |
44 | uint32_t src_w, uint32_t src_h) | |
45 | { | |
46 | struct drm_device *dev = plane->dev; | |
47 | struct drm_i915_private *dev_priv = dev->dev_private; | |
48 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
49 | int pipe = intel_plane->pipe; | |
50 | u32 sprctl, sprscale = 0; | |
5a35e99e | 51 | unsigned long sprsurf_offset, linear_offset; |
2bd3c3cb | 52 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
2c6602df | 53 | bool scaling_was_enabled = dev_priv->sprite_scaling_enabled; |
b840d907 JB |
54 | |
55 | sprctl = I915_READ(SPRCTL(pipe)); | |
56 | ||
57 | /* Mask out pixel format bits in case we change it */ | |
58 | sprctl &= ~SPRITE_PIXFORMAT_MASK; | |
59 | sprctl &= ~SPRITE_RGB_ORDER_RGBX; | |
60 | sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK; | |
e86fe0d3 | 61 | sprctl &= ~SPRITE_TILED; |
b840d907 JB |
62 | |
63 | switch (fb->pixel_format) { | |
64 | case DRM_FORMAT_XBGR8888: | |
5ee36913 | 65 | sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX; |
b840d907 JB |
66 | break; |
67 | case DRM_FORMAT_XRGB8888: | |
5ee36913 | 68 | sprctl |= SPRITE_FORMAT_RGBX888; |
b840d907 JB |
69 | break; |
70 | case DRM_FORMAT_YUYV: | |
71 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV; | |
b840d907 JB |
72 | break; |
73 | case DRM_FORMAT_YVYU: | |
74 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU; | |
b840d907 JB |
75 | break; |
76 | case DRM_FORMAT_UYVY: | |
77 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY; | |
b840d907 JB |
78 | break; |
79 | case DRM_FORMAT_VYUY: | |
80 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY; | |
b840d907 JB |
81 | break; |
82 | default: | |
28d491df | 83 | BUG(); |
b840d907 JB |
84 | } |
85 | ||
86 | if (obj->tiling_mode != I915_TILING_NONE) | |
87 | sprctl |= SPRITE_TILED; | |
88 | ||
89 | /* must disable */ | |
90 | sprctl |= SPRITE_TRICKLE_FEED_DISABLE; | |
91 | sprctl |= SPRITE_ENABLE; | |
92 | ||
86d3efce VS |
93 | if (IS_HASWELL(dev)) |
94 | sprctl |= SPRITE_PIPE_CSC_ENABLE; | |
95 | ||
b840d907 JB |
96 | /* Sizes are 0 based */ |
97 | src_w--; | |
98 | src_h--; | |
99 | crtc_w--; | |
100 | crtc_h--; | |
101 | ||
102 | intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size); | |
103 | ||
104 | /* | |
105 | * IVB workaround: must disable low power watermarks for at least | |
106 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
107 | * when scaling is disabled. | |
108 | */ | |
109 | if (crtc_w != src_w || crtc_h != src_h) { | |
2c6602df VS |
110 | dev_priv->sprite_scaling_enabled |= 1 << pipe; |
111 | ||
112 | if (!scaling_was_enabled) { | |
828ed3e1 CW |
113 | intel_update_watermarks(dev); |
114 | intel_wait_for_vblank(dev, pipe); | |
115 | } | |
b840d907 | 116 | sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h; |
2c6602df VS |
117 | } else |
118 | dev_priv->sprite_scaling_enabled &= ~(1 << pipe); | |
b840d907 JB |
119 | |
120 | I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]); | |
121 | I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x); | |
c54173a8 | 122 | |
ca320ac4 | 123 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
5a35e99e | 124 | sprsurf_offset = |
bc752862 CW |
125 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
126 | pixel_size, fb->pitches[0]); | |
5a35e99e DL |
127 | linear_offset -= sprsurf_offset; |
128 | ||
129 | /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET | |
130 | * register */ | |
131 | if (IS_HASWELL(dev)) | |
c54173a8 | 132 | I915_WRITE(SPROFFSET(pipe), (y << 16) | x); |
5a35e99e | 133 | else if (obj->tiling_mode != I915_TILING_NONE) |
b840d907 | 134 | I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x); |
5a35e99e DL |
135 | else |
136 | I915_WRITE(SPRLINOFF(pipe), linear_offset); | |
c54173a8 | 137 | |
b840d907 | 138 | I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w); |
2d354c34 DL |
139 | if (intel_plane->can_scale) |
140 | I915_WRITE(SPRSCALE(pipe), sprscale); | |
b840d907 | 141 | I915_WRITE(SPRCTL(pipe), sprctl); |
5a35e99e | 142 | I915_MODIFY_DISPBASE(SPRSURF(pipe), obj->gtt_offset + sprsurf_offset); |
b840d907 | 143 | POSTING_READ(SPRSURF(pipe)); |
2c6602df VS |
144 | |
145 | /* potentially re-enable LP watermarks */ | |
146 | if (scaling_was_enabled && !dev_priv->sprite_scaling_enabled) | |
147 | intel_update_watermarks(dev); | |
b840d907 JB |
148 | } |
149 | ||
150 | static void | |
151 | ivb_disable_plane(struct drm_plane *plane) | |
152 | { | |
153 | struct drm_device *dev = plane->dev; | |
154 | struct drm_i915_private *dev_priv = dev->dev_private; | |
155 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
156 | int pipe = intel_plane->pipe; | |
2c6602df | 157 | bool scaling_was_enabled = dev_priv->sprite_scaling_enabled; |
b840d907 JB |
158 | |
159 | I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE); | |
160 | /* Can't leave the scaler enabled... */ | |
2d354c34 DL |
161 | if (intel_plane->can_scale) |
162 | I915_WRITE(SPRSCALE(pipe), 0); | |
b840d907 | 163 | /* Activate double buffered register update */ |
446f2545 | 164 | I915_MODIFY_DISPBASE(SPRSURF(pipe), 0); |
b840d907 | 165 | POSTING_READ(SPRSURF(pipe)); |
828ed3e1 | 166 | |
2c6602df VS |
167 | dev_priv->sprite_scaling_enabled &= ~(1 << pipe); |
168 | ||
169 | /* potentially re-enable LP watermarks */ | |
170 | if (scaling_was_enabled && !dev_priv->sprite_scaling_enabled) | |
171 | intel_update_watermarks(dev); | |
b840d907 JB |
172 | } |
173 | ||
8ea30864 JB |
174 | static int |
175 | ivb_update_colorkey(struct drm_plane *plane, | |
176 | struct drm_intel_sprite_colorkey *key) | |
177 | { | |
178 | struct drm_device *dev = plane->dev; | |
179 | struct drm_i915_private *dev_priv = dev->dev_private; | |
180 | struct intel_plane *intel_plane; | |
181 | u32 sprctl; | |
182 | int ret = 0; | |
183 | ||
184 | intel_plane = to_intel_plane(plane); | |
185 | ||
186 | I915_WRITE(SPRKEYVAL(intel_plane->pipe), key->min_value); | |
187 | I915_WRITE(SPRKEYMAX(intel_plane->pipe), key->max_value); | |
188 | I915_WRITE(SPRKEYMSK(intel_plane->pipe), key->channel_mask); | |
189 | ||
190 | sprctl = I915_READ(SPRCTL(intel_plane->pipe)); | |
191 | sprctl &= ~(SPRITE_SOURCE_KEY | SPRITE_DEST_KEY); | |
192 | if (key->flags & I915_SET_COLORKEY_DESTINATION) | |
193 | sprctl |= SPRITE_DEST_KEY; | |
194 | else if (key->flags & I915_SET_COLORKEY_SOURCE) | |
195 | sprctl |= SPRITE_SOURCE_KEY; | |
196 | I915_WRITE(SPRCTL(intel_plane->pipe), sprctl); | |
197 | ||
198 | POSTING_READ(SPRKEYMSK(intel_plane->pipe)); | |
199 | ||
200 | return ret; | |
201 | } | |
202 | ||
203 | static void | |
204 | ivb_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key) | |
205 | { | |
206 | struct drm_device *dev = plane->dev; | |
207 | struct drm_i915_private *dev_priv = dev->dev_private; | |
208 | struct intel_plane *intel_plane; | |
209 | u32 sprctl; | |
210 | ||
211 | intel_plane = to_intel_plane(plane); | |
212 | ||
213 | key->min_value = I915_READ(SPRKEYVAL(intel_plane->pipe)); | |
214 | key->max_value = I915_READ(SPRKEYMAX(intel_plane->pipe)); | |
215 | key->channel_mask = I915_READ(SPRKEYMSK(intel_plane->pipe)); | |
216 | key->flags = 0; | |
217 | ||
218 | sprctl = I915_READ(SPRCTL(intel_plane->pipe)); | |
219 | ||
220 | if (sprctl & SPRITE_DEST_KEY) | |
221 | key->flags = I915_SET_COLORKEY_DESTINATION; | |
222 | else if (sprctl & SPRITE_SOURCE_KEY) | |
223 | key->flags = I915_SET_COLORKEY_SOURCE; | |
224 | else | |
225 | key->flags = I915_SET_COLORKEY_NONE; | |
226 | } | |
227 | ||
b840d907 | 228 | static void |
d1686ae3 | 229 | ilk_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, |
b840d907 JB |
230 | struct drm_i915_gem_object *obj, int crtc_x, int crtc_y, |
231 | unsigned int crtc_w, unsigned int crtc_h, | |
232 | uint32_t x, uint32_t y, | |
233 | uint32_t src_w, uint32_t src_h) | |
234 | { | |
235 | struct drm_device *dev = plane->dev; | |
236 | struct drm_i915_private *dev_priv = dev->dev_private; | |
237 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
2bd3c3cb | 238 | int pipe = intel_plane->pipe; |
5a35e99e | 239 | unsigned long dvssurf_offset, linear_offset; |
8aaa81a1 | 240 | u32 dvscntr, dvsscale; |
2bd3c3cb | 241 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
b840d907 JB |
242 | |
243 | dvscntr = I915_READ(DVSCNTR(pipe)); | |
244 | ||
245 | /* Mask out pixel format bits in case we change it */ | |
246 | dvscntr &= ~DVS_PIXFORMAT_MASK; | |
ab2f9df1 | 247 | dvscntr &= ~DVS_RGB_ORDER_XBGR; |
b840d907 | 248 | dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK; |
79626523 | 249 | dvscntr &= ~DVS_TILED; |
b840d907 JB |
250 | |
251 | switch (fb->pixel_format) { | |
252 | case DRM_FORMAT_XBGR8888: | |
ab2f9df1 | 253 | dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR; |
b840d907 JB |
254 | break; |
255 | case DRM_FORMAT_XRGB8888: | |
ab2f9df1 | 256 | dvscntr |= DVS_FORMAT_RGBX888; |
b840d907 JB |
257 | break; |
258 | case DRM_FORMAT_YUYV: | |
259 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV; | |
b840d907 JB |
260 | break; |
261 | case DRM_FORMAT_YVYU: | |
262 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU; | |
b840d907 JB |
263 | break; |
264 | case DRM_FORMAT_UYVY: | |
265 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY; | |
b840d907 JB |
266 | break; |
267 | case DRM_FORMAT_VYUY: | |
268 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY; | |
b840d907 JB |
269 | break; |
270 | default: | |
28d491df | 271 | BUG(); |
b840d907 JB |
272 | } |
273 | ||
274 | if (obj->tiling_mode != I915_TILING_NONE) | |
275 | dvscntr |= DVS_TILED; | |
276 | ||
d1686ae3 CW |
277 | if (IS_GEN6(dev)) |
278 | dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */ | |
b840d907 JB |
279 | dvscntr |= DVS_ENABLE; |
280 | ||
281 | /* Sizes are 0 based */ | |
282 | src_w--; | |
283 | src_h--; | |
284 | crtc_w--; | |
285 | crtc_h--; | |
286 | ||
287 | intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size); | |
288 | ||
8aaa81a1 CW |
289 | dvsscale = 0; |
290 | if (IS_GEN5(dev) || crtc_w != src_w || crtc_h != src_h) | |
b840d907 JB |
291 | dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h; |
292 | ||
293 | I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]); | |
294 | I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x); | |
5a35e99e | 295 | |
ca320ac4 | 296 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
5a35e99e | 297 | dvssurf_offset = |
bc752862 CW |
298 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
299 | pixel_size, fb->pitches[0]); | |
5a35e99e DL |
300 | linear_offset -= dvssurf_offset; |
301 | ||
302 | if (obj->tiling_mode != I915_TILING_NONE) | |
b840d907 | 303 | I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x); |
5a35e99e DL |
304 | else |
305 | I915_WRITE(DVSLINOFF(pipe), linear_offset); | |
b840d907 | 306 | |
b840d907 JB |
307 | I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w); |
308 | I915_WRITE(DVSSCALE(pipe), dvsscale); | |
309 | I915_WRITE(DVSCNTR(pipe), dvscntr); | |
5a35e99e | 310 | I915_MODIFY_DISPBASE(DVSSURF(pipe), obj->gtt_offset + dvssurf_offset); |
b840d907 JB |
311 | POSTING_READ(DVSSURF(pipe)); |
312 | } | |
313 | ||
314 | static void | |
d1686ae3 | 315 | ilk_disable_plane(struct drm_plane *plane) |
b840d907 JB |
316 | { |
317 | struct drm_device *dev = plane->dev; | |
318 | struct drm_i915_private *dev_priv = dev->dev_private; | |
319 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
320 | int pipe = intel_plane->pipe; | |
321 | ||
322 | I915_WRITE(DVSCNTR(pipe), I915_READ(DVSCNTR(pipe)) & ~DVS_ENABLE); | |
323 | /* Disable the scaler */ | |
324 | I915_WRITE(DVSSCALE(pipe), 0); | |
325 | /* Flush double buffered register updates */ | |
446f2545 | 326 | I915_MODIFY_DISPBASE(DVSSURF(pipe), 0); |
b840d907 JB |
327 | POSTING_READ(DVSSURF(pipe)); |
328 | } | |
329 | ||
175bd420 JB |
330 | static void |
331 | intel_enable_primary(struct drm_crtc *crtc) | |
332 | { | |
333 | struct drm_device *dev = crtc->dev; | |
334 | struct drm_i915_private *dev_priv = dev->dev_private; | |
335 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
336 | int reg = DSPCNTR(intel_crtc->plane); | |
337 | ||
93314b5b CW |
338 | if (!intel_crtc->primary_disabled) |
339 | return; | |
340 | ||
341 | intel_crtc->primary_disabled = false; | |
342 | intel_update_fbc(dev); | |
343 | ||
175bd420 JB |
344 | I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE); |
345 | } | |
346 | ||
347 | static void | |
348 | intel_disable_primary(struct drm_crtc *crtc) | |
349 | { | |
350 | struct drm_device *dev = crtc->dev; | |
351 | struct drm_i915_private *dev_priv = dev->dev_private; | |
352 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
353 | int reg = DSPCNTR(intel_crtc->plane); | |
354 | ||
93314b5b CW |
355 | if (intel_crtc->primary_disabled) |
356 | return; | |
357 | ||
175bd420 | 358 | I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE); |
93314b5b CW |
359 | |
360 | intel_crtc->primary_disabled = true; | |
361 | intel_update_fbc(dev); | |
175bd420 JB |
362 | } |
363 | ||
8ea30864 | 364 | static int |
d1686ae3 | 365 | ilk_update_colorkey(struct drm_plane *plane, |
8ea30864 JB |
366 | struct drm_intel_sprite_colorkey *key) |
367 | { | |
368 | struct drm_device *dev = plane->dev; | |
369 | struct drm_i915_private *dev_priv = dev->dev_private; | |
370 | struct intel_plane *intel_plane; | |
371 | u32 dvscntr; | |
372 | int ret = 0; | |
373 | ||
374 | intel_plane = to_intel_plane(plane); | |
375 | ||
376 | I915_WRITE(DVSKEYVAL(intel_plane->pipe), key->min_value); | |
377 | I915_WRITE(DVSKEYMAX(intel_plane->pipe), key->max_value); | |
378 | I915_WRITE(DVSKEYMSK(intel_plane->pipe), key->channel_mask); | |
379 | ||
380 | dvscntr = I915_READ(DVSCNTR(intel_plane->pipe)); | |
381 | dvscntr &= ~(DVS_SOURCE_KEY | DVS_DEST_KEY); | |
382 | if (key->flags & I915_SET_COLORKEY_DESTINATION) | |
383 | dvscntr |= DVS_DEST_KEY; | |
384 | else if (key->flags & I915_SET_COLORKEY_SOURCE) | |
385 | dvscntr |= DVS_SOURCE_KEY; | |
386 | I915_WRITE(DVSCNTR(intel_plane->pipe), dvscntr); | |
387 | ||
388 | POSTING_READ(DVSKEYMSK(intel_plane->pipe)); | |
389 | ||
390 | return ret; | |
391 | } | |
392 | ||
393 | static void | |
d1686ae3 | 394 | ilk_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key) |
8ea30864 JB |
395 | { |
396 | struct drm_device *dev = plane->dev; | |
397 | struct drm_i915_private *dev_priv = dev->dev_private; | |
398 | struct intel_plane *intel_plane; | |
399 | u32 dvscntr; | |
400 | ||
401 | intel_plane = to_intel_plane(plane); | |
402 | ||
403 | key->min_value = I915_READ(DVSKEYVAL(intel_plane->pipe)); | |
404 | key->max_value = I915_READ(DVSKEYMAX(intel_plane->pipe)); | |
405 | key->channel_mask = I915_READ(DVSKEYMSK(intel_plane->pipe)); | |
406 | key->flags = 0; | |
407 | ||
408 | dvscntr = I915_READ(DVSCNTR(intel_plane->pipe)); | |
409 | ||
410 | if (dvscntr & DVS_DEST_KEY) | |
411 | key->flags = I915_SET_COLORKEY_DESTINATION; | |
412 | else if (dvscntr & DVS_SOURCE_KEY) | |
413 | key->flags = I915_SET_COLORKEY_SOURCE; | |
414 | else | |
415 | key->flags = I915_SET_COLORKEY_NONE; | |
416 | } | |
417 | ||
b840d907 JB |
418 | static int |
419 | intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, | |
420 | struct drm_framebuffer *fb, int crtc_x, int crtc_y, | |
421 | unsigned int crtc_w, unsigned int crtc_h, | |
422 | uint32_t src_x, uint32_t src_y, | |
423 | uint32_t src_w, uint32_t src_h) | |
424 | { | |
425 | struct drm_device *dev = plane->dev; | |
426 | struct drm_i915_private *dev_priv = dev->dev_private; | |
427 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
428 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
429 | struct intel_framebuffer *intel_fb; | |
430 | struct drm_i915_gem_object *obj, *old_obj; | |
431 | int pipe = intel_plane->pipe; | |
702e7a56 PZ |
432 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
433 | pipe); | |
b840d907 JB |
434 | int ret = 0; |
435 | int x = src_x >> 16, y = src_y >> 16; | |
436 | int primary_w = crtc->mode.hdisplay, primary_h = crtc->mode.vdisplay; | |
437 | bool disable_primary = false; | |
438 | ||
439 | intel_fb = to_intel_framebuffer(fb); | |
440 | obj = intel_fb->obj; | |
441 | ||
442 | old_obj = intel_plane->obj; | |
443 | ||
5e1bac2f JB |
444 | intel_plane->crtc_x = crtc_x; |
445 | intel_plane->crtc_y = crtc_y; | |
446 | intel_plane->crtc_w = crtc_w; | |
447 | intel_plane->crtc_h = crtc_h; | |
448 | intel_plane->src_x = src_x; | |
449 | intel_plane->src_y = src_y; | |
450 | intel_plane->src_w = src_w; | |
451 | intel_plane->src_h = src_h; | |
452 | ||
b4db1e35 JB |
453 | src_w = src_w >> 16; |
454 | src_h = src_h >> 16; | |
455 | ||
b840d907 | 456 | /* Pipe must be running... */ |
702e7a56 | 457 | if (!(I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE)) |
b840d907 JB |
458 | return -EINVAL; |
459 | ||
460 | if (crtc_x >= primary_w || crtc_y >= primary_h) | |
461 | return -EINVAL; | |
462 | ||
463 | /* Don't modify another pipe's plane */ | |
464 | if (intel_plane->pipe != intel_crtc->pipe) | |
465 | return -EINVAL; | |
466 | ||
94c6419e DL |
467 | /* Sprite planes can be linear or x-tiled surfaces */ |
468 | switch (obj->tiling_mode) { | |
469 | case I915_TILING_NONE: | |
470 | case I915_TILING_X: | |
471 | break; | |
472 | default: | |
473 | return -EINVAL; | |
474 | } | |
475 | ||
b840d907 JB |
476 | /* |
477 | * Clamp the width & height into the visible area. Note we don't | |
478 | * try to scale the source if part of the visible region is offscreen. | |
479 | * The caller must handle that by adjusting source offset and size. | |
480 | */ | |
481 | if ((crtc_x < 0) && ((crtc_x + crtc_w) > 0)) { | |
482 | crtc_w += crtc_x; | |
483 | crtc_x = 0; | |
484 | } | |
485 | if ((crtc_x + crtc_w) <= 0) /* Nothing to display */ | |
486 | goto out; | |
487 | if ((crtc_x + crtc_w) > primary_w) | |
488 | crtc_w = primary_w - crtc_x; | |
489 | ||
490 | if ((crtc_y < 0) && ((crtc_y + crtc_h) > 0)) { | |
491 | crtc_h += crtc_y; | |
492 | crtc_y = 0; | |
493 | } | |
494 | if ((crtc_y + crtc_h) <= 0) /* Nothing to display */ | |
495 | goto out; | |
496 | if (crtc_y + crtc_h > primary_h) | |
497 | crtc_h = primary_h - crtc_y; | |
498 | ||
499 | if (!crtc_w || !crtc_h) /* Again, nothing to display */ | |
500 | goto out; | |
501 | ||
2d354c34 DL |
502 | /* |
503 | * We may not have a scaler, eg. HSW does not have it any more | |
504 | */ | |
505 | if (!intel_plane->can_scale && (crtc_w != src_w || crtc_h != src_h)) | |
506 | return -EINVAL; | |
507 | ||
b840d907 JB |
508 | /* |
509 | * We can take a larger source and scale it down, but | |
510 | * only so much... 16x is the max on SNB. | |
511 | */ | |
512 | if (((src_w * src_h) / (crtc_w * crtc_h)) > intel_plane->max_downscale) | |
513 | return -EINVAL; | |
514 | ||
515 | /* | |
516 | * If the sprite is completely covering the primary plane, | |
517 | * we can disable the primary and save power. | |
518 | */ | |
519 | if ((crtc_x == 0) && (crtc_y == 0) && | |
520 | (crtc_w == primary_w) && (crtc_h == primary_h)) | |
521 | disable_primary = true; | |
522 | ||
523 | mutex_lock(&dev->struct_mutex); | |
524 | ||
525 | ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); | |
00c2064b | 526 | if (ret) |
b840d907 | 527 | goto out_unlock; |
b840d907 JB |
528 | |
529 | intel_plane->obj = obj; | |
530 | ||
175bd420 JB |
531 | /* |
532 | * Be sure to re-enable the primary before the sprite is no longer | |
533 | * covering it fully. | |
534 | */ | |
93314b5b | 535 | if (!disable_primary) |
175bd420 | 536 | intel_enable_primary(crtc); |
175bd420 | 537 | |
b840d907 JB |
538 | intel_plane->update_plane(plane, fb, obj, crtc_x, crtc_y, |
539 | crtc_w, crtc_h, x, y, src_w, src_h); | |
540 | ||
93314b5b | 541 | if (disable_primary) |
175bd420 | 542 | intel_disable_primary(crtc); |
175bd420 | 543 | |
b840d907 JB |
544 | /* Unpin old obj after new one is active to avoid ugliness */ |
545 | if (old_obj) { | |
546 | /* | |
547 | * It's fairly common to simply update the position of | |
548 | * an existing object. In that case, we don't need to | |
549 | * wait for vblank to avoid ugliness, we only need to | |
550 | * do the pin & ref bookkeeping. | |
551 | */ | |
552 | if (old_obj != obj) { | |
553 | mutex_unlock(&dev->struct_mutex); | |
554 | intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe); | |
555 | mutex_lock(&dev->struct_mutex); | |
556 | } | |
1690e1eb | 557 | intel_unpin_fb_obj(old_obj); |
b840d907 JB |
558 | } |
559 | ||
560 | out_unlock: | |
561 | mutex_unlock(&dev->struct_mutex); | |
562 | out: | |
563 | return ret; | |
564 | } | |
565 | ||
566 | static int | |
567 | intel_disable_plane(struct drm_plane *plane) | |
568 | { | |
569 | struct drm_device *dev = plane->dev; | |
570 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
571 | int ret = 0; | |
572 | ||
93314b5b | 573 | if (plane->crtc) |
175bd420 | 574 | intel_enable_primary(plane->crtc); |
b840d907 JB |
575 | intel_plane->disable_plane(plane); |
576 | ||
577 | if (!intel_plane->obj) | |
578 | goto out; | |
579 | ||
580 | mutex_lock(&dev->struct_mutex); | |
1690e1eb | 581 | intel_unpin_fb_obj(intel_plane->obj); |
b840d907 JB |
582 | intel_plane->obj = NULL; |
583 | mutex_unlock(&dev->struct_mutex); | |
584 | out: | |
585 | ||
586 | return ret; | |
587 | } | |
588 | ||
589 | static void intel_destroy_plane(struct drm_plane *plane) | |
590 | { | |
591 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
592 | intel_disable_plane(plane); | |
593 | drm_plane_cleanup(plane); | |
594 | kfree(intel_plane); | |
595 | } | |
596 | ||
8ea30864 JB |
597 | int intel_sprite_set_colorkey(struct drm_device *dev, void *data, |
598 | struct drm_file *file_priv) | |
599 | { | |
600 | struct drm_intel_sprite_colorkey *set = data; | |
8ea30864 JB |
601 | struct drm_mode_object *obj; |
602 | struct drm_plane *plane; | |
603 | struct intel_plane *intel_plane; | |
604 | int ret = 0; | |
605 | ||
1cff8f6b DV |
606 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
607 | return -ENODEV; | |
8ea30864 JB |
608 | |
609 | /* Make sure we don't try to enable both src & dest simultaneously */ | |
610 | if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) | |
611 | return -EINVAL; | |
612 | ||
a0e99e68 | 613 | drm_modeset_lock_all(dev); |
8ea30864 JB |
614 | |
615 | obj = drm_mode_object_find(dev, set->plane_id, DRM_MODE_OBJECT_PLANE); | |
616 | if (!obj) { | |
617 | ret = -EINVAL; | |
618 | goto out_unlock; | |
619 | } | |
620 | ||
621 | plane = obj_to_plane(obj); | |
622 | intel_plane = to_intel_plane(plane); | |
623 | ret = intel_plane->update_colorkey(plane, set); | |
624 | ||
625 | out_unlock: | |
a0e99e68 | 626 | drm_modeset_unlock_all(dev); |
8ea30864 JB |
627 | return ret; |
628 | } | |
629 | ||
630 | int intel_sprite_get_colorkey(struct drm_device *dev, void *data, | |
631 | struct drm_file *file_priv) | |
632 | { | |
633 | struct drm_intel_sprite_colorkey *get = data; | |
8ea30864 JB |
634 | struct drm_mode_object *obj; |
635 | struct drm_plane *plane; | |
636 | struct intel_plane *intel_plane; | |
637 | int ret = 0; | |
638 | ||
1cff8f6b DV |
639 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
640 | return -ENODEV; | |
8ea30864 | 641 | |
a0e99e68 | 642 | drm_modeset_lock_all(dev); |
8ea30864 JB |
643 | |
644 | obj = drm_mode_object_find(dev, get->plane_id, DRM_MODE_OBJECT_PLANE); | |
645 | if (!obj) { | |
646 | ret = -EINVAL; | |
647 | goto out_unlock; | |
648 | } | |
649 | ||
650 | plane = obj_to_plane(obj); | |
651 | intel_plane = to_intel_plane(plane); | |
652 | intel_plane->get_colorkey(plane, get); | |
653 | ||
654 | out_unlock: | |
a0e99e68 | 655 | drm_modeset_unlock_all(dev); |
8ea30864 JB |
656 | return ret; |
657 | } | |
658 | ||
5e1bac2f JB |
659 | void intel_plane_restore(struct drm_plane *plane) |
660 | { | |
661 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
662 | ||
663 | if (!plane->crtc || !plane->fb) | |
664 | return; | |
665 | ||
666 | intel_update_plane(plane, plane->crtc, plane->fb, | |
667 | intel_plane->crtc_x, intel_plane->crtc_y, | |
668 | intel_plane->crtc_w, intel_plane->crtc_h, | |
669 | intel_plane->src_x, intel_plane->src_y, | |
670 | intel_plane->src_w, intel_plane->src_h); | |
671 | } | |
672 | ||
b840d907 JB |
673 | static const struct drm_plane_funcs intel_plane_funcs = { |
674 | .update_plane = intel_update_plane, | |
675 | .disable_plane = intel_disable_plane, | |
676 | .destroy = intel_destroy_plane, | |
677 | }; | |
678 | ||
d1686ae3 CW |
679 | static uint32_t ilk_plane_formats[] = { |
680 | DRM_FORMAT_XRGB8888, | |
681 | DRM_FORMAT_YUYV, | |
682 | DRM_FORMAT_YVYU, | |
683 | DRM_FORMAT_UYVY, | |
684 | DRM_FORMAT_VYUY, | |
685 | }; | |
686 | ||
b840d907 JB |
687 | static uint32_t snb_plane_formats[] = { |
688 | DRM_FORMAT_XBGR8888, | |
689 | DRM_FORMAT_XRGB8888, | |
690 | DRM_FORMAT_YUYV, | |
691 | DRM_FORMAT_YVYU, | |
692 | DRM_FORMAT_UYVY, | |
693 | DRM_FORMAT_VYUY, | |
694 | }; | |
695 | ||
696 | int | |
697 | intel_plane_init(struct drm_device *dev, enum pipe pipe) | |
698 | { | |
699 | struct intel_plane *intel_plane; | |
700 | unsigned long possible_crtcs; | |
d1686ae3 CW |
701 | const uint32_t *plane_formats; |
702 | int num_plane_formats; | |
b840d907 JB |
703 | int ret; |
704 | ||
d1686ae3 | 705 | if (INTEL_INFO(dev)->gen < 5) |
b840d907 | 706 | return -ENODEV; |
b840d907 JB |
707 | |
708 | intel_plane = kzalloc(sizeof(struct intel_plane), GFP_KERNEL); | |
709 | if (!intel_plane) | |
710 | return -ENOMEM; | |
711 | ||
d1686ae3 CW |
712 | switch (INTEL_INFO(dev)->gen) { |
713 | case 5: | |
714 | case 6: | |
2d354c34 | 715 | intel_plane->can_scale = true; |
b840d907 | 716 | intel_plane->max_downscale = 16; |
d1686ae3 CW |
717 | intel_plane->update_plane = ilk_update_plane; |
718 | intel_plane->disable_plane = ilk_disable_plane; | |
719 | intel_plane->update_colorkey = ilk_update_colorkey; | |
720 | intel_plane->get_colorkey = ilk_get_colorkey; | |
721 | ||
722 | if (IS_GEN6(dev)) { | |
723 | plane_formats = snb_plane_formats; | |
724 | num_plane_formats = ARRAY_SIZE(snb_plane_formats); | |
725 | } else { | |
726 | plane_formats = ilk_plane_formats; | |
727 | num_plane_formats = ARRAY_SIZE(ilk_plane_formats); | |
728 | } | |
729 | break; | |
730 | ||
731 | case 7: | |
4d8d71b5 | 732 | if (IS_HASWELL(dev) || IS_VALLEYVIEW(dev)) |
2d354c34 DL |
733 | intel_plane->can_scale = false; |
734 | else | |
735 | intel_plane->can_scale = true; | |
b840d907 JB |
736 | intel_plane->max_downscale = 2; |
737 | intel_plane->update_plane = ivb_update_plane; | |
738 | intel_plane->disable_plane = ivb_disable_plane; | |
8ea30864 JB |
739 | intel_plane->update_colorkey = ivb_update_colorkey; |
740 | intel_plane->get_colorkey = ivb_get_colorkey; | |
d1686ae3 CW |
741 | |
742 | plane_formats = snb_plane_formats; | |
743 | num_plane_formats = ARRAY_SIZE(snb_plane_formats); | |
744 | break; | |
745 | ||
746 | default: | |
a8b0bbab | 747 | kfree(intel_plane); |
d1686ae3 | 748 | return -ENODEV; |
b840d907 JB |
749 | } |
750 | ||
751 | intel_plane->pipe = pipe; | |
752 | possible_crtcs = (1 << pipe); | |
753 | ret = drm_plane_init(dev, &intel_plane->base, possible_crtcs, | |
d1686ae3 CW |
754 | &intel_plane_funcs, |
755 | plane_formats, num_plane_formats, | |
756 | false); | |
b840d907 JB |
757 | if (ret) |
758 | kfree(intel_plane); | |
759 | ||
760 | return ret; | |
761 | } |