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b840d907 JB |
1 | /* |
2 | * Copyright © 2011 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
21 | * SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Jesse Barnes <jbarnes@virtuousgeek.org> | |
25 | * | |
26 | * New plane/sprite handling. | |
27 | * | |
28 | * The older chips had a separate interface for programming plane related | |
29 | * registers; newer ones are much simpler and we can use the new DRM plane | |
30 | * support. | |
31 | */ | |
32 | #include "drmP.h" | |
33 | #include "drm_crtc.h" | |
34 | #include "drm_fourcc.h" | |
35 | #include "intel_drv.h" | |
36 | #include "i915_drm.h" | |
37 | #include "i915_drv.h" | |
38 | ||
39 | static void | |
40 | ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, | |
41 | struct drm_i915_gem_object *obj, int crtc_x, int crtc_y, | |
42 | unsigned int crtc_w, unsigned int crtc_h, | |
43 | uint32_t x, uint32_t y, | |
44 | uint32_t src_w, uint32_t src_h) | |
45 | { | |
46 | struct drm_device *dev = plane->dev; | |
47 | struct drm_i915_private *dev_priv = dev->dev_private; | |
48 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
49 | int pipe = intel_plane->pipe; | |
50 | u32 sprctl, sprscale = 0; | |
51 | int pixel_size; | |
52 | ||
53 | sprctl = I915_READ(SPRCTL(pipe)); | |
54 | ||
55 | /* Mask out pixel format bits in case we change it */ | |
56 | sprctl &= ~SPRITE_PIXFORMAT_MASK; | |
57 | sprctl &= ~SPRITE_RGB_ORDER_RGBX; | |
58 | sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK; | |
59 | ||
60 | switch (fb->pixel_format) { | |
61 | case DRM_FORMAT_XBGR8888: | |
62 | sprctl |= SPRITE_FORMAT_RGBX888; | |
63 | pixel_size = 4; | |
64 | break; | |
65 | case DRM_FORMAT_XRGB8888: | |
66 | sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX; | |
67 | pixel_size = 4; | |
68 | break; | |
69 | case DRM_FORMAT_YUYV: | |
70 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV; | |
71 | pixel_size = 2; | |
72 | break; | |
73 | case DRM_FORMAT_YVYU: | |
74 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU; | |
75 | pixel_size = 2; | |
76 | break; | |
77 | case DRM_FORMAT_UYVY: | |
78 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY; | |
79 | pixel_size = 2; | |
80 | break; | |
81 | case DRM_FORMAT_VYUY: | |
82 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY; | |
83 | pixel_size = 2; | |
84 | break; | |
85 | default: | |
86 | DRM_DEBUG_DRIVER("bad pixel format, assuming RGBX888\n"); | |
87 | sprctl |= DVS_FORMAT_RGBX888; | |
88 | pixel_size = 4; | |
89 | break; | |
90 | } | |
91 | ||
92 | if (obj->tiling_mode != I915_TILING_NONE) | |
93 | sprctl |= SPRITE_TILED; | |
94 | ||
95 | /* must disable */ | |
96 | sprctl |= SPRITE_TRICKLE_FEED_DISABLE; | |
97 | sprctl |= SPRITE_ENABLE; | |
98 | ||
99 | /* Sizes are 0 based */ | |
100 | src_w--; | |
101 | src_h--; | |
102 | crtc_w--; | |
103 | crtc_h--; | |
104 | ||
105 | intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size); | |
106 | ||
107 | /* | |
108 | * IVB workaround: must disable low power watermarks for at least | |
109 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
110 | * when scaling is disabled. | |
111 | */ | |
112 | if (crtc_w != src_w || crtc_h != src_h) { | |
113 | dev_priv->sprite_scaling_enabled = true; | |
114 | sandybridge_update_wm(dev); | |
115 | intel_wait_for_vblank(dev, pipe); | |
116 | sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h; | |
117 | } else { | |
118 | dev_priv->sprite_scaling_enabled = false; | |
119 | /* potentially re-enable LP watermarks */ | |
120 | sandybridge_update_wm(dev); | |
121 | } | |
122 | ||
123 | I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]); | |
124 | I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x); | |
125 | if (obj->tiling_mode != I915_TILING_NONE) { | |
126 | I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x); | |
127 | } else { | |
128 | unsigned long offset; | |
129 | ||
130 | offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); | |
131 | I915_WRITE(SPRLINOFF(pipe), offset); | |
132 | } | |
133 | I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w); | |
134 | I915_WRITE(SPRSCALE(pipe), sprscale); | |
135 | I915_WRITE(SPRCTL(pipe), sprctl); | |
136 | I915_WRITE(SPRSURF(pipe), obj->gtt_offset); | |
137 | POSTING_READ(SPRSURF(pipe)); | |
138 | } | |
139 | ||
140 | static void | |
141 | ivb_disable_plane(struct drm_plane *plane) | |
142 | { | |
143 | struct drm_device *dev = plane->dev; | |
144 | struct drm_i915_private *dev_priv = dev->dev_private; | |
145 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
146 | int pipe = intel_plane->pipe; | |
147 | ||
148 | I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE); | |
149 | /* Can't leave the scaler enabled... */ | |
150 | I915_WRITE(SPRSCALE(pipe), 0); | |
151 | /* Activate double buffered register update */ | |
152 | I915_WRITE(SPRSURF(pipe), 0); | |
153 | POSTING_READ(SPRSURF(pipe)); | |
154 | } | |
155 | ||
156 | static void | |
157 | snb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, | |
158 | struct drm_i915_gem_object *obj, int crtc_x, int crtc_y, | |
159 | unsigned int crtc_w, unsigned int crtc_h, | |
160 | uint32_t x, uint32_t y, | |
161 | uint32_t src_w, uint32_t src_h) | |
162 | { | |
163 | struct drm_device *dev = plane->dev; | |
164 | struct drm_i915_private *dev_priv = dev->dev_private; | |
165 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
166 | int pipe = intel_plane->pipe, pixel_size; | |
167 | u32 dvscntr, dvsscale = 0; | |
168 | ||
169 | dvscntr = I915_READ(DVSCNTR(pipe)); | |
170 | ||
171 | /* Mask out pixel format bits in case we change it */ | |
172 | dvscntr &= ~DVS_PIXFORMAT_MASK; | |
173 | dvscntr &= ~DVS_RGB_ORDER_RGBX; | |
174 | dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK; | |
175 | ||
176 | switch (fb->pixel_format) { | |
177 | case DRM_FORMAT_XBGR8888: | |
178 | dvscntr |= DVS_FORMAT_RGBX888; | |
179 | pixel_size = 4; | |
180 | break; | |
181 | case DRM_FORMAT_XRGB8888: | |
182 | dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_RGBX; | |
183 | pixel_size = 4; | |
184 | break; | |
185 | case DRM_FORMAT_YUYV: | |
186 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV; | |
187 | pixel_size = 2; | |
188 | break; | |
189 | case DRM_FORMAT_YVYU: | |
190 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU; | |
191 | pixel_size = 2; | |
192 | break; | |
193 | case DRM_FORMAT_UYVY: | |
194 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY; | |
195 | pixel_size = 2; | |
196 | break; | |
197 | case DRM_FORMAT_VYUY: | |
198 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY; | |
199 | pixel_size = 2; | |
200 | break; | |
201 | default: | |
202 | DRM_DEBUG_DRIVER("bad pixel format, assuming RGBX888\n"); | |
203 | dvscntr |= DVS_FORMAT_RGBX888; | |
204 | pixel_size = 4; | |
205 | break; | |
206 | } | |
207 | ||
208 | if (obj->tiling_mode != I915_TILING_NONE) | |
209 | dvscntr |= DVS_TILED; | |
210 | ||
211 | /* must disable */ | |
212 | dvscntr |= DVS_TRICKLE_FEED_DISABLE; | |
213 | dvscntr |= DVS_ENABLE; | |
214 | ||
215 | /* Sizes are 0 based */ | |
216 | src_w--; | |
217 | src_h--; | |
218 | crtc_w--; | |
219 | crtc_h--; | |
220 | ||
221 | intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size); | |
222 | ||
223 | if (crtc_w != src_w || crtc_h != src_h) | |
224 | dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h; | |
225 | ||
226 | I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]); | |
227 | I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x); | |
228 | if (obj->tiling_mode != I915_TILING_NONE) { | |
229 | I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x); | |
230 | } else { | |
231 | unsigned long offset; | |
232 | ||
233 | offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); | |
234 | I915_WRITE(DVSLINOFF(pipe), offset); | |
235 | } | |
236 | I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w); | |
237 | I915_WRITE(DVSSCALE(pipe), dvsscale); | |
238 | I915_WRITE(DVSCNTR(pipe), dvscntr); | |
239 | I915_WRITE(DVSSURF(pipe), obj->gtt_offset); | |
240 | POSTING_READ(DVSSURF(pipe)); | |
241 | } | |
242 | ||
243 | static void | |
244 | snb_disable_plane(struct drm_plane *plane) | |
245 | { | |
246 | struct drm_device *dev = plane->dev; | |
247 | struct drm_i915_private *dev_priv = dev->dev_private; | |
248 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
249 | int pipe = intel_plane->pipe; | |
250 | ||
251 | I915_WRITE(DVSCNTR(pipe), I915_READ(DVSCNTR(pipe)) & ~DVS_ENABLE); | |
252 | /* Disable the scaler */ | |
253 | I915_WRITE(DVSSCALE(pipe), 0); | |
254 | /* Flush double buffered register updates */ | |
255 | I915_WRITE(DVSSURF(pipe), 0); | |
256 | POSTING_READ(DVSSURF(pipe)); | |
257 | } | |
258 | ||
175bd420 JB |
259 | static void |
260 | intel_enable_primary(struct drm_crtc *crtc) | |
261 | { | |
262 | struct drm_device *dev = crtc->dev; | |
263 | struct drm_i915_private *dev_priv = dev->dev_private; | |
264 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
265 | int reg = DSPCNTR(intel_crtc->plane); | |
266 | ||
267 | I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE); | |
268 | } | |
269 | ||
270 | static void | |
271 | intel_disable_primary(struct drm_crtc *crtc) | |
272 | { | |
273 | struct drm_device *dev = crtc->dev; | |
274 | struct drm_i915_private *dev_priv = dev->dev_private; | |
275 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
276 | int reg = DSPCNTR(intel_crtc->plane); | |
277 | ||
278 | I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE); | |
279 | } | |
280 | ||
b840d907 JB |
281 | static int |
282 | intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, | |
283 | struct drm_framebuffer *fb, int crtc_x, int crtc_y, | |
284 | unsigned int crtc_w, unsigned int crtc_h, | |
285 | uint32_t src_x, uint32_t src_y, | |
286 | uint32_t src_w, uint32_t src_h) | |
287 | { | |
288 | struct drm_device *dev = plane->dev; | |
289 | struct drm_i915_private *dev_priv = dev->dev_private; | |
290 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
291 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
292 | struct intel_framebuffer *intel_fb; | |
293 | struct drm_i915_gem_object *obj, *old_obj; | |
294 | int pipe = intel_plane->pipe; | |
295 | int ret = 0; | |
296 | int x = src_x >> 16, y = src_y >> 16; | |
297 | int primary_w = crtc->mode.hdisplay, primary_h = crtc->mode.vdisplay; | |
298 | bool disable_primary = false; | |
299 | ||
300 | intel_fb = to_intel_framebuffer(fb); | |
301 | obj = intel_fb->obj; | |
302 | ||
303 | old_obj = intel_plane->obj; | |
304 | ||
305 | /* Pipe must be running... */ | |
306 | if (!(I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE)) | |
307 | return -EINVAL; | |
308 | ||
309 | if (crtc_x >= primary_w || crtc_y >= primary_h) | |
310 | return -EINVAL; | |
311 | ||
312 | /* Don't modify another pipe's plane */ | |
313 | if (intel_plane->pipe != intel_crtc->pipe) | |
314 | return -EINVAL; | |
315 | ||
316 | /* | |
317 | * Clamp the width & height into the visible area. Note we don't | |
318 | * try to scale the source if part of the visible region is offscreen. | |
319 | * The caller must handle that by adjusting source offset and size. | |
320 | */ | |
321 | if ((crtc_x < 0) && ((crtc_x + crtc_w) > 0)) { | |
322 | crtc_w += crtc_x; | |
323 | crtc_x = 0; | |
324 | } | |
325 | if ((crtc_x + crtc_w) <= 0) /* Nothing to display */ | |
326 | goto out; | |
327 | if ((crtc_x + crtc_w) > primary_w) | |
328 | crtc_w = primary_w - crtc_x; | |
329 | ||
330 | if ((crtc_y < 0) && ((crtc_y + crtc_h) > 0)) { | |
331 | crtc_h += crtc_y; | |
332 | crtc_y = 0; | |
333 | } | |
334 | if ((crtc_y + crtc_h) <= 0) /* Nothing to display */ | |
335 | goto out; | |
336 | if (crtc_y + crtc_h > primary_h) | |
337 | crtc_h = primary_h - crtc_y; | |
338 | ||
339 | if (!crtc_w || !crtc_h) /* Again, nothing to display */ | |
340 | goto out; | |
341 | ||
342 | /* | |
343 | * We can take a larger source and scale it down, but | |
344 | * only so much... 16x is the max on SNB. | |
345 | */ | |
346 | if (((src_w * src_h) / (crtc_w * crtc_h)) > intel_plane->max_downscale) | |
347 | return -EINVAL; | |
348 | ||
349 | /* | |
350 | * If the sprite is completely covering the primary plane, | |
351 | * we can disable the primary and save power. | |
352 | */ | |
353 | if ((crtc_x == 0) && (crtc_y == 0) && | |
354 | (crtc_w == primary_w) && (crtc_h == primary_h)) | |
355 | disable_primary = true; | |
356 | ||
357 | mutex_lock(&dev->struct_mutex); | |
358 | ||
359 | ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); | |
360 | if (ret) { | |
361 | DRM_ERROR("failed to pin object\n"); | |
362 | goto out_unlock; | |
363 | } | |
364 | ||
365 | intel_plane->obj = obj; | |
366 | ||
175bd420 JB |
367 | /* |
368 | * Be sure to re-enable the primary before the sprite is no longer | |
369 | * covering it fully. | |
370 | */ | |
371 | if (!disable_primary && intel_plane->primary_disabled) { | |
372 | intel_enable_primary(crtc); | |
373 | intel_plane->primary_disabled = false; | |
374 | } | |
375 | ||
b840d907 JB |
376 | intel_plane->update_plane(plane, fb, obj, crtc_x, crtc_y, |
377 | crtc_w, crtc_h, x, y, src_w, src_h); | |
378 | ||
175bd420 JB |
379 | if (disable_primary) { |
380 | intel_disable_primary(crtc); | |
381 | intel_plane->primary_disabled = true; | |
382 | } | |
383 | ||
b840d907 JB |
384 | /* Unpin old obj after new one is active to avoid ugliness */ |
385 | if (old_obj) { | |
386 | /* | |
387 | * It's fairly common to simply update the position of | |
388 | * an existing object. In that case, we don't need to | |
389 | * wait for vblank to avoid ugliness, we only need to | |
390 | * do the pin & ref bookkeeping. | |
391 | */ | |
392 | if (old_obj != obj) { | |
393 | mutex_unlock(&dev->struct_mutex); | |
394 | intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe); | |
395 | mutex_lock(&dev->struct_mutex); | |
396 | } | |
397 | i915_gem_object_unpin(old_obj); | |
398 | } | |
399 | ||
400 | out_unlock: | |
401 | mutex_unlock(&dev->struct_mutex); | |
402 | out: | |
403 | return ret; | |
404 | } | |
405 | ||
406 | static int | |
407 | intel_disable_plane(struct drm_plane *plane) | |
408 | { | |
409 | struct drm_device *dev = plane->dev; | |
410 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
411 | int ret = 0; | |
412 | ||
175bd420 JB |
413 | if (intel_plane->primary_disabled) { |
414 | intel_enable_primary(plane->crtc); | |
415 | intel_plane->primary_disabled = false; | |
416 | } | |
417 | ||
b840d907 JB |
418 | intel_plane->disable_plane(plane); |
419 | ||
420 | if (!intel_plane->obj) | |
421 | goto out; | |
422 | ||
423 | mutex_lock(&dev->struct_mutex); | |
424 | i915_gem_object_unpin(intel_plane->obj); | |
425 | intel_plane->obj = NULL; | |
426 | mutex_unlock(&dev->struct_mutex); | |
427 | out: | |
428 | ||
429 | return ret; | |
430 | } | |
431 | ||
432 | static void intel_destroy_plane(struct drm_plane *plane) | |
433 | { | |
434 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
435 | intel_disable_plane(plane); | |
436 | drm_plane_cleanup(plane); | |
437 | kfree(intel_plane); | |
438 | } | |
439 | ||
440 | static const struct drm_plane_funcs intel_plane_funcs = { | |
441 | .update_plane = intel_update_plane, | |
442 | .disable_plane = intel_disable_plane, | |
443 | .destroy = intel_destroy_plane, | |
444 | }; | |
445 | ||
446 | static uint32_t snb_plane_formats[] = { | |
447 | DRM_FORMAT_XBGR8888, | |
448 | DRM_FORMAT_XRGB8888, | |
449 | DRM_FORMAT_YUYV, | |
450 | DRM_FORMAT_YVYU, | |
451 | DRM_FORMAT_UYVY, | |
452 | DRM_FORMAT_VYUY, | |
453 | }; | |
454 | ||
455 | int | |
456 | intel_plane_init(struct drm_device *dev, enum pipe pipe) | |
457 | { | |
458 | struct intel_plane *intel_plane; | |
459 | unsigned long possible_crtcs; | |
460 | int ret; | |
461 | ||
462 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) { | |
463 | DRM_ERROR("new plane code only for SNB+\n"); | |
464 | return -ENODEV; | |
465 | } | |
466 | ||
467 | intel_plane = kzalloc(sizeof(struct intel_plane), GFP_KERNEL); | |
468 | if (!intel_plane) | |
469 | return -ENOMEM; | |
470 | ||
471 | if (IS_GEN6(dev)) { | |
472 | intel_plane->max_downscale = 16; | |
473 | intel_plane->update_plane = snb_update_plane; | |
474 | intel_plane->disable_plane = snb_disable_plane; | |
475 | } else if (IS_GEN7(dev)) { | |
476 | intel_plane->max_downscale = 2; | |
477 | intel_plane->update_plane = ivb_update_plane; | |
478 | intel_plane->disable_plane = ivb_disable_plane; | |
479 | } | |
480 | ||
481 | intel_plane->pipe = pipe; | |
482 | possible_crtcs = (1 << pipe); | |
483 | ret = drm_plane_init(dev, &intel_plane->base, possible_crtcs, | |
484 | &intel_plane_funcs, snb_plane_formats, | |
485 | ARRAY_SIZE(snb_plane_formats)); | |
486 | if (ret) | |
487 | kfree(intel_plane); | |
488 | ||
489 | return ret; | |
490 | } | |
491 |