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b840d907 JB |
1 | /* |
2 | * Copyright © 2011 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
21 | * SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Jesse Barnes <jbarnes@virtuousgeek.org> | |
25 | * | |
26 | * New plane/sprite handling. | |
27 | * | |
28 | * The older chips had a separate interface for programming plane related | |
29 | * registers; newer ones are much simpler and we can use the new DRM plane | |
30 | * support. | |
31 | */ | |
760285e7 DH |
32 | #include <drm/drmP.h> |
33 | #include <drm/drm_crtc.h> | |
34 | #include <drm/drm_fourcc.h> | |
1731693a | 35 | #include <drm/drm_rect.h> |
b840d907 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
b840d907 JB |
38 | #include "i915_drv.h" |
39 | ||
7f1f3851 JB |
40 | static void |
41 | vlv_update_plane(struct drm_plane *dplane, struct drm_framebuffer *fb, | |
42 | struct drm_i915_gem_object *obj, int crtc_x, int crtc_y, | |
43 | unsigned int crtc_w, unsigned int crtc_h, | |
44 | uint32_t x, uint32_t y, | |
45 | uint32_t src_w, uint32_t src_h) | |
46 | { | |
47 | struct drm_device *dev = dplane->dev; | |
48 | struct drm_i915_private *dev_priv = dev->dev_private; | |
49 | struct intel_plane *intel_plane = to_intel_plane(dplane); | |
50 | int pipe = intel_plane->pipe; | |
51 | int plane = intel_plane->plane; | |
52 | u32 sprctl; | |
53 | unsigned long sprsurf_offset, linear_offset; | |
54 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
55 | ||
56 | sprctl = I915_READ(SPCNTR(pipe, plane)); | |
57 | ||
58 | /* Mask out pixel format bits in case we change it */ | |
59 | sprctl &= ~SP_PIXFORMAT_MASK; | |
60 | sprctl &= ~SP_YUV_BYTE_ORDER_MASK; | |
61 | sprctl &= ~SP_TILED; | |
62 | ||
63 | switch (fb->pixel_format) { | |
64 | case DRM_FORMAT_YUYV: | |
65 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV; | |
66 | break; | |
67 | case DRM_FORMAT_YVYU: | |
68 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU; | |
69 | break; | |
70 | case DRM_FORMAT_UYVY: | |
71 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY; | |
72 | break; | |
73 | case DRM_FORMAT_VYUY: | |
74 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY; | |
75 | break; | |
76 | case DRM_FORMAT_RGB565: | |
77 | sprctl |= SP_FORMAT_BGR565; | |
78 | break; | |
79 | case DRM_FORMAT_XRGB8888: | |
80 | sprctl |= SP_FORMAT_BGRX8888; | |
81 | break; | |
82 | case DRM_FORMAT_ARGB8888: | |
83 | sprctl |= SP_FORMAT_BGRA8888; | |
84 | break; | |
85 | case DRM_FORMAT_XBGR2101010: | |
86 | sprctl |= SP_FORMAT_RGBX1010102; | |
87 | break; | |
88 | case DRM_FORMAT_ABGR2101010: | |
89 | sprctl |= SP_FORMAT_RGBA1010102; | |
90 | break; | |
91 | case DRM_FORMAT_XBGR8888: | |
92 | sprctl |= SP_FORMAT_RGBX8888; | |
93 | break; | |
94 | case DRM_FORMAT_ABGR8888: | |
95 | sprctl |= SP_FORMAT_RGBA8888; | |
96 | break; | |
97 | default: | |
98 | /* | |
99 | * If we get here one of the upper layers failed to filter | |
100 | * out the unsupported plane formats | |
101 | */ | |
102 | BUG(); | |
103 | break; | |
104 | } | |
105 | ||
106 | if (obj->tiling_mode != I915_TILING_NONE) | |
107 | sprctl |= SP_TILED; | |
108 | ||
109 | sprctl |= SP_ENABLE; | |
110 | ||
111 | /* Sizes are 0 based */ | |
112 | src_w--; | |
113 | src_h--; | |
114 | crtc_w--; | |
115 | crtc_h--; | |
116 | ||
117 | intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size); | |
118 | ||
119 | I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]); | |
120 | I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x); | |
121 | ||
122 | linear_offset = y * fb->pitches[0] + x * pixel_size; | |
123 | sprsurf_offset = intel_gen4_compute_page_offset(&x, &y, | |
124 | obj->tiling_mode, | |
125 | pixel_size, | |
126 | fb->pitches[0]); | |
127 | linear_offset -= sprsurf_offset; | |
128 | ||
129 | if (obj->tiling_mode != I915_TILING_NONE) | |
130 | I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x); | |
131 | else | |
132 | I915_WRITE(SPLINOFF(pipe, plane), linear_offset); | |
133 | ||
134 | I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w); | |
135 | I915_WRITE(SPCNTR(pipe, plane), sprctl); | |
136 | I915_MODIFY_DISPBASE(SPSURF(pipe, plane), obj->gtt_offset + | |
137 | sprsurf_offset); | |
138 | POSTING_READ(SPSURF(pipe, plane)); | |
139 | } | |
140 | ||
141 | static void | |
142 | vlv_disable_plane(struct drm_plane *dplane) | |
143 | { | |
144 | struct drm_device *dev = dplane->dev; | |
145 | struct drm_i915_private *dev_priv = dev->dev_private; | |
146 | struct intel_plane *intel_plane = to_intel_plane(dplane); | |
147 | int pipe = intel_plane->pipe; | |
148 | int plane = intel_plane->plane; | |
149 | ||
150 | I915_WRITE(SPCNTR(pipe, plane), I915_READ(SPCNTR(pipe, plane)) & | |
151 | ~SP_ENABLE); | |
152 | /* Activate double buffered register update */ | |
153 | I915_MODIFY_DISPBASE(SPSURF(pipe, plane), 0); | |
154 | POSTING_READ(SPSURF(pipe, plane)); | |
155 | } | |
156 | ||
157 | static int | |
158 | vlv_update_colorkey(struct drm_plane *dplane, | |
159 | struct drm_intel_sprite_colorkey *key) | |
160 | { | |
161 | struct drm_device *dev = dplane->dev; | |
162 | struct drm_i915_private *dev_priv = dev->dev_private; | |
163 | struct intel_plane *intel_plane = to_intel_plane(dplane); | |
164 | int pipe = intel_plane->pipe; | |
165 | int plane = intel_plane->plane; | |
166 | u32 sprctl; | |
167 | ||
168 | if (key->flags & I915_SET_COLORKEY_DESTINATION) | |
169 | return -EINVAL; | |
170 | ||
171 | I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value); | |
172 | I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value); | |
173 | I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask); | |
174 | ||
175 | sprctl = I915_READ(SPCNTR(pipe, plane)); | |
176 | sprctl &= ~SP_SOURCE_KEY; | |
177 | if (key->flags & I915_SET_COLORKEY_SOURCE) | |
178 | sprctl |= SP_SOURCE_KEY; | |
179 | I915_WRITE(SPCNTR(pipe, plane), sprctl); | |
180 | ||
181 | POSTING_READ(SPKEYMSK(pipe, plane)); | |
182 | ||
183 | return 0; | |
184 | } | |
185 | ||
186 | static void | |
187 | vlv_get_colorkey(struct drm_plane *dplane, | |
188 | struct drm_intel_sprite_colorkey *key) | |
189 | { | |
190 | struct drm_device *dev = dplane->dev; | |
191 | struct drm_i915_private *dev_priv = dev->dev_private; | |
192 | struct intel_plane *intel_plane = to_intel_plane(dplane); | |
193 | int pipe = intel_plane->pipe; | |
194 | int plane = intel_plane->plane; | |
195 | u32 sprctl; | |
196 | ||
197 | key->min_value = I915_READ(SPKEYMINVAL(pipe, plane)); | |
198 | key->max_value = I915_READ(SPKEYMAXVAL(pipe, plane)); | |
199 | key->channel_mask = I915_READ(SPKEYMSK(pipe, plane)); | |
200 | ||
201 | sprctl = I915_READ(SPCNTR(pipe, plane)); | |
202 | if (sprctl & SP_SOURCE_KEY) | |
203 | key->flags = I915_SET_COLORKEY_SOURCE; | |
204 | else | |
205 | key->flags = I915_SET_COLORKEY_NONE; | |
206 | } | |
207 | ||
b840d907 JB |
208 | static void |
209 | ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, | |
210 | struct drm_i915_gem_object *obj, int crtc_x, int crtc_y, | |
211 | unsigned int crtc_w, unsigned int crtc_h, | |
212 | uint32_t x, uint32_t y, | |
213 | uint32_t src_w, uint32_t src_h) | |
214 | { | |
215 | struct drm_device *dev = plane->dev; | |
216 | struct drm_i915_private *dev_priv = dev->dev_private; | |
217 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
218 | int pipe = intel_plane->pipe; | |
219 | u32 sprctl, sprscale = 0; | |
5a35e99e | 220 | unsigned long sprsurf_offset, linear_offset; |
2bd3c3cb | 221 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
2c6602df | 222 | bool scaling_was_enabled = dev_priv->sprite_scaling_enabled; |
b840d907 JB |
223 | |
224 | sprctl = I915_READ(SPRCTL(pipe)); | |
225 | ||
226 | /* Mask out pixel format bits in case we change it */ | |
227 | sprctl &= ~SPRITE_PIXFORMAT_MASK; | |
228 | sprctl &= ~SPRITE_RGB_ORDER_RGBX; | |
229 | sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK; | |
e86fe0d3 | 230 | sprctl &= ~SPRITE_TILED; |
b840d907 JB |
231 | |
232 | switch (fb->pixel_format) { | |
233 | case DRM_FORMAT_XBGR8888: | |
5ee36913 | 234 | sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX; |
b840d907 JB |
235 | break; |
236 | case DRM_FORMAT_XRGB8888: | |
5ee36913 | 237 | sprctl |= SPRITE_FORMAT_RGBX888; |
b840d907 JB |
238 | break; |
239 | case DRM_FORMAT_YUYV: | |
240 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV; | |
b840d907 JB |
241 | break; |
242 | case DRM_FORMAT_YVYU: | |
243 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU; | |
b840d907 JB |
244 | break; |
245 | case DRM_FORMAT_UYVY: | |
246 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY; | |
b840d907 JB |
247 | break; |
248 | case DRM_FORMAT_VYUY: | |
249 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY; | |
b840d907 JB |
250 | break; |
251 | default: | |
28d491df | 252 | BUG(); |
b840d907 JB |
253 | } |
254 | ||
255 | if (obj->tiling_mode != I915_TILING_NONE) | |
256 | sprctl |= SPRITE_TILED; | |
257 | ||
258 | /* must disable */ | |
259 | sprctl |= SPRITE_TRICKLE_FEED_DISABLE; | |
260 | sprctl |= SPRITE_ENABLE; | |
261 | ||
86d3efce VS |
262 | if (IS_HASWELL(dev)) |
263 | sprctl |= SPRITE_PIPE_CSC_ENABLE; | |
264 | ||
b840d907 JB |
265 | /* Sizes are 0 based */ |
266 | src_w--; | |
267 | src_h--; | |
268 | crtc_w--; | |
269 | crtc_h--; | |
270 | ||
271 | intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size); | |
272 | ||
273 | /* | |
274 | * IVB workaround: must disable low power watermarks for at least | |
275 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
276 | * when scaling is disabled. | |
277 | */ | |
278 | if (crtc_w != src_w || crtc_h != src_h) { | |
2c6602df VS |
279 | dev_priv->sprite_scaling_enabled |= 1 << pipe; |
280 | ||
281 | if (!scaling_was_enabled) { | |
828ed3e1 CW |
282 | intel_update_watermarks(dev); |
283 | intel_wait_for_vblank(dev, pipe); | |
284 | } | |
b840d907 | 285 | sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h; |
2c6602df VS |
286 | } else |
287 | dev_priv->sprite_scaling_enabled &= ~(1 << pipe); | |
b840d907 JB |
288 | |
289 | I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]); | |
290 | I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x); | |
c54173a8 | 291 | |
ca320ac4 | 292 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
5a35e99e | 293 | sprsurf_offset = |
bc752862 CW |
294 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
295 | pixel_size, fb->pitches[0]); | |
5a35e99e DL |
296 | linear_offset -= sprsurf_offset; |
297 | ||
298 | /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET | |
299 | * register */ | |
300 | if (IS_HASWELL(dev)) | |
c54173a8 | 301 | I915_WRITE(SPROFFSET(pipe), (y << 16) | x); |
5a35e99e | 302 | else if (obj->tiling_mode != I915_TILING_NONE) |
b840d907 | 303 | I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x); |
5a35e99e DL |
304 | else |
305 | I915_WRITE(SPRLINOFF(pipe), linear_offset); | |
c54173a8 | 306 | |
b840d907 | 307 | I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w); |
2d354c34 DL |
308 | if (intel_plane->can_scale) |
309 | I915_WRITE(SPRSCALE(pipe), sprscale); | |
b840d907 | 310 | I915_WRITE(SPRCTL(pipe), sprctl); |
5a35e99e | 311 | I915_MODIFY_DISPBASE(SPRSURF(pipe), obj->gtt_offset + sprsurf_offset); |
b840d907 | 312 | POSTING_READ(SPRSURF(pipe)); |
2c6602df VS |
313 | |
314 | /* potentially re-enable LP watermarks */ | |
315 | if (scaling_was_enabled && !dev_priv->sprite_scaling_enabled) | |
316 | intel_update_watermarks(dev); | |
b840d907 JB |
317 | } |
318 | ||
319 | static void | |
320 | ivb_disable_plane(struct drm_plane *plane) | |
321 | { | |
322 | struct drm_device *dev = plane->dev; | |
323 | struct drm_i915_private *dev_priv = dev->dev_private; | |
324 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
325 | int pipe = intel_plane->pipe; | |
2c6602df | 326 | bool scaling_was_enabled = dev_priv->sprite_scaling_enabled; |
b840d907 JB |
327 | |
328 | I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE); | |
329 | /* Can't leave the scaler enabled... */ | |
2d354c34 DL |
330 | if (intel_plane->can_scale) |
331 | I915_WRITE(SPRSCALE(pipe), 0); | |
b840d907 | 332 | /* Activate double buffered register update */ |
446f2545 | 333 | I915_MODIFY_DISPBASE(SPRSURF(pipe), 0); |
b840d907 | 334 | POSTING_READ(SPRSURF(pipe)); |
828ed3e1 | 335 | |
2c6602df VS |
336 | dev_priv->sprite_scaling_enabled &= ~(1 << pipe); |
337 | ||
338 | /* potentially re-enable LP watermarks */ | |
339 | if (scaling_was_enabled && !dev_priv->sprite_scaling_enabled) | |
340 | intel_update_watermarks(dev); | |
b840d907 JB |
341 | } |
342 | ||
8ea30864 JB |
343 | static int |
344 | ivb_update_colorkey(struct drm_plane *plane, | |
345 | struct drm_intel_sprite_colorkey *key) | |
346 | { | |
347 | struct drm_device *dev = plane->dev; | |
348 | struct drm_i915_private *dev_priv = dev->dev_private; | |
349 | struct intel_plane *intel_plane; | |
350 | u32 sprctl; | |
351 | int ret = 0; | |
352 | ||
353 | intel_plane = to_intel_plane(plane); | |
354 | ||
355 | I915_WRITE(SPRKEYVAL(intel_plane->pipe), key->min_value); | |
356 | I915_WRITE(SPRKEYMAX(intel_plane->pipe), key->max_value); | |
357 | I915_WRITE(SPRKEYMSK(intel_plane->pipe), key->channel_mask); | |
358 | ||
359 | sprctl = I915_READ(SPRCTL(intel_plane->pipe)); | |
360 | sprctl &= ~(SPRITE_SOURCE_KEY | SPRITE_DEST_KEY); | |
361 | if (key->flags & I915_SET_COLORKEY_DESTINATION) | |
362 | sprctl |= SPRITE_DEST_KEY; | |
363 | else if (key->flags & I915_SET_COLORKEY_SOURCE) | |
364 | sprctl |= SPRITE_SOURCE_KEY; | |
365 | I915_WRITE(SPRCTL(intel_plane->pipe), sprctl); | |
366 | ||
367 | POSTING_READ(SPRKEYMSK(intel_plane->pipe)); | |
368 | ||
369 | return ret; | |
370 | } | |
371 | ||
372 | static void | |
373 | ivb_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key) | |
374 | { | |
375 | struct drm_device *dev = plane->dev; | |
376 | struct drm_i915_private *dev_priv = dev->dev_private; | |
377 | struct intel_plane *intel_plane; | |
378 | u32 sprctl; | |
379 | ||
380 | intel_plane = to_intel_plane(plane); | |
381 | ||
382 | key->min_value = I915_READ(SPRKEYVAL(intel_plane->pipe)); | |
383 | key->max_value = I915_READ(SPRKEYMAX(intel_plane->pipe)); | |
384 | key->channel_mask = I915_READ(SPRKEYMSK(intel_plane->pipe)); | |
385 | key->flags = 0; | |
386 | ||
387 | sprctl = I915_READ(SPRCTL(intel_plane->pipe)); | |
388 | ||
389 | if (sprctl & SPRITE_DEST_KEY) | |
390 | key->flags = I915_SET_COLORKEY_DESTINATION; | |
391 | else if (sprctl & SPRITE_SOURCE_KEY) | |
392 | key->flags = I915_SET_COLORKEY_SOURCE; | |
393 | else | |
394 | key->flags = I915_SET_COLORKEY_NONE; | |
395 | } | |
396 | ||
b840d907 | 397 | static void |
d1686ae3 | 398 | ilk_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, |
b840d907 JB |
399 | struct drm_i915_gem_object *obj, int crtc_x, int crtc_y, |
400 | unsigned int crtc_w, unsigned int crtc_h, | |
401 | uint32_t x, uint32_t y, | |
402 | uint32_t src_w, uint32_t src_h) | |
403 | { | |
404 | struct drm_device *dev = plane->dev; | |
405 | struct drm_i915_private *dev_priv = dev->dev_private; | |
406 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
2bd3c3cb | 407 | int pipe = intel_plane->pipe; |
5a35e99e | 408 | unsigned long dvssurf_offset, linear_offset; |
8aaa81a1 | 409 | u32 dvscntr, dvsscale; |
2bd3c3cb | 410 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
b840d907 JB |
411 | |
412 | dvscntr = I915_READ(DVSCNTR(pipe)); | |
413 | ||
414 | /* Mask out pixel format bits in case we change it */ | |
415 | dvscntr &= ~DVS_PIXFORMAT_MASK; | |
ab2f9df1 | 416 | dvscntr &= ~DVS_RGB_ORDER_XBGR; |
b840d907 | 417 | dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK; |
79626523 | 418 | dvscntr &= ~DVS_TILED; |
b840d907 JB |
419 | |
420 | switch (fb->pixel_format) { | |
421 | case DRM_FORMAT_XBGR8888: | |
ab2f9df1 | 422 | dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR; |
b840d907 JB |
423 | break; |
424 | case DRM_FORMAT_XRGB8888: | |
ab2f9df1 | 425 | dvscntr |= DVS_FORMAT_RGBX888; |
b840d907 JB |
426 | break; |
427 | case DRM_FORMAT_YUYV: | |
428 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV; | |
b840d907 JB |
429 | break; |
430 | case DRM_FORMAT_YVYU: | |
431 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU; | |
b840d907 JB |
432 | break; |
433 | case DRM_FORMAT_UYVY: | |
434 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY; | |
b840d907 JB |
435 | break; |
436 | case DRM_FORMAT_VYUY: | |
437 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY; | |
b840d907 JB |
438 | break; |
439 | default: | |
28d491df | 440 | BUG(); |
b840d907 JB |
441 | } |
442 | ||
443 | if (obj->tiling_mode != I915_TILING_NONE) | |
444 | dvscntr |= DVS_TILED; | |
445 | ||
d1686ae3 CW |
446 | if (IS_GEN6(dev)) |
447 | dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */ | |
b840d907 JB |
448 | dvscntr |= DVS_ENABLE; |
449 | ||
450 | /* Sizes are 0 based */ | |
451 | src_w--; | |
452 | src_h--; | |
453 | crtc_w--; | |
454 | crtc_h--; | |
455 | ||
456 | intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size); | |
457 | ||
8aaa81a1 CW |
458 | dvsscale = 0; |
459 | if (IS_GEN5(dev) || crtc_w != src_w || crtc_h != src_h) | |
b840d907 JB |
460 | dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h; |
461 | ||
462 | I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]); | |
463 | I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x); | |
5a35e99e | 464 | |
ca320ac4 | 465 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
5a35e99e | 466 | dvssurf_offset = |
bc752862 CW |
467 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
468 | pixel_size, fb->pitches[0]); | |
5a35e99e DL |
469 | linear_offset -= dvssurf_offset; |
470 | ||
471 | if (obj->tiling_mode != I915_TILING_NONE) | |
b840d907 | 472 | I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x); |
5a35e99e DL |
473 | else |
474 | I915_WRITE(DVSLINOFF(pipe), linear_offset); | |
b840d907 | 475 | |
b840d907 JB |
476 | I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w); |
477 | I915_WRITE(DVSSCALE(pipe), dvsscale); | |
478 | I915_WRITE(DVSCNTR(pipe), dvscntr); | |
5a35e99e | 479 | I915_MODIFY_DISPBASE(DVSSURF(pipe), obj->gtt_offset + dvssurf_offset); |
b840d907 JB |
480 | POSTING_READ(DVSSURF(pipe)); |
481 | } | |
482 | ||
483 | static void | |
d1686ae3 | 484 | ilk_disable_plane(struct drm_plane *plane) |
b840d907 JB |
485 | { |
486 | struct drm_device *dev = plane->dev; | |
487 | struct drm_i915_private *dev_priv = dev->dev_private; | |
488 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
489 | int pipe = intel_plane->pipe; | |
490 | ||
491 | I915_WRITE(DVSCNTR(pipe), I915_READ(DVSCNTR(pipe)) & ~DVS_ENABLE); | |
492 | /* Disable the scaler */ | |
493 | I915_WRITE(DVSSCALE(pipe), 0); | |
494 | /* Flush double buffered register updates */ | |
446f2545 | 495 | I915_MODIFY_DISPBASE(DVSSURF(pipe), 0); |
b840d907 JB |
496 | POSTING_READ(DVSSURF(pipe)); |
497 | } | |
498 | ||
175bd420 JB |
499 | static void |
500 | intel_enable_primary(struct drm_crtc *crtc) | |
501 | { | |
502 | struct drm_device *dev = crtc->dev; | |
503 | struct drm_i915_private *dev_priv = dev->dev_private; | |
504 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
505 | int reg = DSPCNTR(intel_crtc->plane); | |
506 | ||
93314b5b CW |
507 | if (!intel_crtc->primary_disabled) |
508 | return; | |
509 | ||
510 | intel_crtc->primary_disabled = false; | |
511 | intel_update_fbc(dev); | |
512 | ||
175bd420 JB |
513 | I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE); |
514 | } | |
515 | ||
516 | static void | |
517 | intel_disable_primary(struct drm_crtc *crtc) | |
518 | { | |
519 | struct drm_device *dev = crtc->dev; | |
520 | struct drm_i915_private *dev_priv = dev->dev_private; | |
521 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
522 | int reg = DSPCNTR(intel_crtc->plane); | |
523 | ||
93314b5b CW |
524 | if (intel_crtc->primary_disabled) |
525 | return; | |
526 | ||
175bd420 | 527 | I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE); |
93314b5b CW |
528 | |
529 | intel_crtc->primary_disabled = true; | |
530 | intel_update_fbc(dev); | |
175bd420 JB |
531 | } |
532 | ||
8ea30864 | 533 | static int |
d1686ae3 | 534 | ilk_update_colorkey(struct drm_plane *plane, |
8ea30864 JB |
535 | struct drm_intel_sprite_colorkey *key) |
536 | { | |
537 | struct drm_device *dev = plane->dev; | |
538 | struct drm_i915_private *dev_priv = dev->dev_private; | |
539 | struct intel_plane *intel_plane; | |
540 | u32 dvscntr; | |
541 | int ret = 0; | |
542 | ||
543 | intel_plane = to_intel_plane(plane); | |
544 | ||
545 | I915_WRITE(DVSKEYVAL(intel_plane->pipe), key->min_value); | |
546 | I915_WRITE(DVSKEYMAX(intel_plane->pipe), key->max_value); | |
547 | I915_WRITE(DVSKEYMSK(intel_plane->pipe), key->channel_mask); | |
548 | ||
549 | dvscntr = I915_READ(DVSCNTR(intel_plane->pipe)); | |
550 | dvscntr &= ~(DVS_SOURCE_KEY | DVS_DEST_KEY); | |
551 | if (key->flags & I915_SET_COLORKEY_DESTINATION) | |
552 | dvscntr |= DVS_DEST_KEY; | |
553 | else if (key->flags & I915_SET_COLORKEY_SOURCE) | |
554 | dvscntr |= DVS_SOURCE_KEY; | |
555 | I915_WRITE(DVSCNTR(intel_plane->pipe), dvscntr); | |
556 | ||
557 | POSTING_READ(DVSKEYMSK(intel_plane->pipe)); | |
558 | ||
559 | return ret; | |
560 | } | |
561 | ||
562 | static void | |
d1686ae3 | 563 | ilk_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key) |
8ea30864 JB |
564 | { |
565 | struct drm_device *dev = plane->dev; | |
566 | struct drm_i915_private *dev_priv = dev->dev_private; | |
567 | struct intel_plane *intel_plane; | |
568 | u32 dvscntr; | |
569 | ||
570 | intel_plane = to_intel_plane(plane); | |
571 | ||
572 | key->min_value = I915_READ(DVSKEYVAL(intel_plane->pipe)); | |
573 | key->max_value = I915_READ(DVSKEYMAX(intel_plane->pipe)); | |
574 | key->channel_mask = I915_READ(DVSKEYMSK(intel_plane->pipe)); | |
575 | key->flags = 0; | |
576 | ||
577 | dvscntr = I915_READ(DVSCNTR(intel_plane->pipe)); | |
578 | ||
579 | if (dvscntr & DVS_DEST_KEY) | |
580 | key->flags = I915_SET_COLORKEY_DESTINATION; | |
581 | else if (dvscntr & DVS_SOURCE_KEY) | |
582 | key->flags = I915_SET_COLORKEY_SOURCE; | |
583 | else | |
584 | key->flags = I915_SET_COLORKEY_NONE; | |
585 | } | |
586 | ||
1731693a VS |
587 | static bool |
588 | format_is_yuv(uint32_t format) | |
589 | { | |
590 | switch (format) { | |
591 | case DRM_FORMAT_YUYV: | |
592 | case DRM_FORMAT_UYVY: | |
593 | case DRM_FORMAT_VYUY: | |
594 | case DRM_FORMAT_YVYU: | |
595 | return true; | |
596 | default: | |
597 | return false; | |
598 | } | |
599 | } | |
600 | ||
b840d907 JB |
601 | static int |
602 | intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, | |
603 | struct drm_framebuffer *fb, int crtc_x, int crtc_y, | |
604 | unsigned int crtc_w, unsigned int crtc_h, | |
605 | uint32_t src_x, uint32_t src_y, | |
606 | uint32_t src_w, uint32_t src_h) | |
607 | { | |
608 | struct drm_device *dev = plane->dev; | |
609 | struct drm_i915_private *dev_priv = dev->dev_private; | |
610 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
611 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
612 | struct intel_framebuffer *intel_fb; | |
613 | struct drm_i915_gem_object *obj, *old_obj; | |
614 | int pipe = intel_plane->pipe; | |
702e7a56 PZ |
615 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
616 | pipe); | |
b840d907 | 617 | int ret = 0; |
b840d907 | 618 | bool disable_primary = false; |
1731693a VS |
619 | bool visible; |
620 | int hscale, vscale; | |
621 | int max_scale, min_scale; | |
622 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
623 | struct drm_rect src = { | |
624 | /* sample coordinates in 16.16 fixed point */ | |
625 | .x1 = src_x, | |
626 | .x2 = src_x + src_w, | |
627 | .y1 = src_y, | |
628 | .y2 = src_y + src_h, | |
629 | }; | |
630 | struct drm_rect dst = { | |
631 | /* integer pixels */ | |
632 | .x1 = crtc_x, | |
633 | .x2 = crtc_x + crtc_w, | |
634 | .y1 = crtc_y, | |
635 | .y2 = crtc_y + crtc_h, | |
636 | }; | |
637 | const struct drm_rect clip = { | |
638 | .x2 = crtc->mode.hdisplay, | |
639 | .y2 = crtc->mode.vdisplay, | |
640 | }; | |
b840d907 JB |
641 | |
642 | intel_fb = to_intel_framebuffer(fb); | |
643 | obj = intel_fb->obj; | |
644 | ||
645 | old_obj = intel_plane->obj; | |
646 | ||
5e1bac2f JB |
647 | intel_plane->crtc_x = crtc_x; |
648 | intel_plane->crtc_y = crtc_y; | |
649 | intel_plane->crtc_w = crtc_w; | |
650 | intel_plane->crtc_h = crtc_h; | |
651 | intel_plane->src_x = src_x; | |
652 | intel_plane->src_y = src_y; | |
653 | intel_plane->src_w = src_w; | |
654 | intel_plane->src_h = src_h; | |
655 | ||
b840d907 | 656 | /* Pipe must be running... */ |
1731693a VS |
657 | if (!(I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE)) { |
658 | DRM_DEBUG_KMS("Pipe disabled\n"); | |
b840d907 | 659 | return -EINVAL; |
1731693a | 660 | } |
b840d907 | 661 | |
1731693a VS |
662 | /* Don't modify another pipe's plane */ |
663 | if (intel_plane->pipe != intel_crtc->pipe) { | |
664 | DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n"); | |
b840d907 | 665 | return -EINVAL; |
1731693a | 666 | } |
b840d907 | 667 | |
1731693a VS |
668 | /* FIXME check all gen limits */ |
669 | if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) { | |
670 | DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n"); | |
b840d907 | 671 | return -EINVAL; |
1731693a | 672 | } |
b840d907 | 673 | |
94c6419e DL |
674 | /* Sprite planes can be linear or x-tiled surfaces */ |
675 | switch (obj->tiling_mode) { | |
676 | case I915_TILING_NONE: | |
677 | case I915_TILING_X: | |
678 | break; | |
679 | default: | |
1731693a | 680 | DRM_DEBUG_KMS("Unsupported tiling mode\n"); |
94c6419e DL |
681 | return -EINVAL; |
682 | } | |
683 | ||
1731693a VS |
684 | max_scale = intel_plane->max_downscale << 16; |
685 | min_scale = intel_plane->can_scale ? 1 : (1 << 16); | |
686 | ||
687 | hscale = drm_rect_calc_hscale(&src, &dst, min_scale, max_scale); | |
688 | if (hscale < 0) { | |
689 | DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n"); | |
690 | drm_rect_debug_print(&src, true); | |
691 | drm_rect_debug_print(&dst, false); | |
692 | ||
693 | return hscale; | |
b840d907 | 694 | } |
b840d907 | 695 | |
1731693a VS |
696 | vscale = drm_rect_calc_vscale(&src, &dst, min_scale, max_scale); |
697 | if (vscale < 0) { | |
698 | DRM_DEBUG_KMS("Vertical scaling factor out of limits\n"); | |
699 | drm_rect_debug_print(&src, true); | |
700 | drm_rect_debug_print(&dst, false); | |
701 | ||
702 | return vscale; | |
b840d907 | 703 | } |
b840d907 | 704 | |
1731693a | 705 | visible = drm_rect_clip_scaled(&src, &dst, &clip, hscale, vscale); |
b840d907 | 706 | |
1731693a VS |
707 | crtc_x = dst.x1; |
708 | crtc_y = dst.y1; | |
709 | crtc_w = drm_rect_width(&dst); | |
710 | crtc_h = drm_rect_height(&dst); | |
2d354c34 | 711 | |
1731693a VS |
712 | if (visible) { |
713 | /* Make the source viewport size an exact multiple of the scaling factors. */ | |
714 | drm_rect_adjust_size(&src, | |
715 | drm_rect_width(&dst) * hscale - drm_rect_width(&src), | |
716 | drm_rect_height(&dst) * vscale - drm_rect_height(&src)); | |
717 | ||
718 | /* sanity check to make sure the src viewport wasn't enlarged */ | |
719 | WARN_ON(src.x1 < (int) src_x || | |
720 | src.y1 < (int) src_y || | |
721 | src.x2 > (int) (src_x + src_w) || | |
722 | src.y2 > (int) (src_y + src_h)); | |
723 | ||
724 | /* | |
725 | * Hardware doesn't handle subpixel coordinates. | |
726 | * Adjust to (macro)pixel boundary, but be careful not to | |
727 | * increase the source viewport size, because that could | |
728 | * push the downscaling factor out of bounds. | |
729 | * | |
730 | * FIXME Should we be really strict and reject the | |
731 | * config if it results in non (macro)pixel aligned | |
732 | * coords? | |
733 | */ | |
734 | src_x = src.x1 >> 16; | |
735 | src_w = drm_rect_width(&src) >> 16; | |
736 | src_y = src.y1 >> 16; | |
737 | src_h = drm_rect_height(&src) >> 16; | |
738 | ||
739 | if (format_is_yuv(fb->pixel_format)) { | |
740 | src_x &= ~1; | |
741 | src_w &= ~1; | |
742 | ||
743 | /* | |
744 | * Must keep src and dst the | |
745 | * same if we can't scale. | |
746 | */ | |
747 | if (!intel_plane->can_scale) | |
748 | crtc_w &= ~1; | |
749 | ||
750 | if (crtc_w == 0) | |
751 | visible = false; | |
752 | } | |
753 | } | |
754 | ||
755 | /* Check size restrictions when scaling */ | |
756 | if (visible && (src_w != crtc_w || src_h != crtc_h)) { | |
757 | unsigned int width_bytes; | |
758 | ||
759 | WARN_ON(!intel_plane->can_scale); | |
760 | ||
761 | /* FIXME interlacing min height is 6 */ | |
762 | ||
763 | if (crtc_w < 3 || crtc_h < 3) | |
764 | visible = false; | |
765 | ||
766 | if (src_w < 3 || src_h < 3) | |
767 | visible = false; | |
768 | ||
769 | width_bytes = ((src_x * pixel_size) & 63) + src_w * pixel_size; | |
770 | ||
771 | if (src_w > 2048 || src_h > 2048 || | |
772 | width_bytes > 4096 || fb->pitches[0] > 4096) { | |
773 | DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n"); | |
774 | return -EINVAL; | |
775 | } | |
776 | } | |
777 | ||
778 | dst.x1 = crtc_x; | |
779 | dst.x2 = crtc_x + crtc_w; | |
780 | dst.y1 = crtc_y; | |
781 | dst.y2 = crtc_y + crtc_h; | |
b840d907 JB |
782 | |
783 | /* | |
784 | * If the sprite is completely covering the primary plane, | |
785 | * we can disable the primary and save power. | |
786 | */ | |
1731693a VS |
787 | disable_primary = drm_rect_equals(&dst, &clip); |
788 | WARN_ON(disable_primary && !visible); | |
b840d907 JB |
789 | |
790 | mutex_lock(&dev->struct_mutex); | |
791 | ||
693db184 CW |
792 | /* Note that this will apply the VT-d workaround for scanouts, |
793 | * which is more restrictive than required for sprites. (The | |
794 | * primary plane requires 256KiB alignment with 64 PTE padding, | |
795 | * the sprite planes only require 128KiB alignment and 32 PTE padding. | |
796 | */ | |
b840d907 | 797 | ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); |
00c2064b | 798 | if (ret) |
b840d907 | 799 | goto out_unlock; |
b840d907 JB |
800 | |
801 | intel_plane->obj = obj; | |
802 | ||
175bd420 JB |
803 | /* |
804 | * Be sure to re-enable the primary before the sprite is no longer | |
805 | * covering it fully. | |
806 | */ | |
93314b5b | 807 | if (!disable_primary) |
175bd420 | 808 | intel_enable_primary(crtc); |
175bd420 | 809 | |
1731693a VS |
810 | if (visible) |
811 | intel_plane->update_plane(plane, fb, obj, | |
812 | crtc_x, crtc_y, crtc_w, crtc_h, | |
813 | src_x, src_y, src_w, src_h); | |
814 | else | |
815 | intel_plane->disable_plane(plane); | |
b840d907 | 816 | |
93314b5b | 817 | if (disable_primary) |
175bd420 | 818 | intel_disable_primary(crtc); |
175bd420 | 819 | |
b840d907 JB |
820 | /* Unpin old obj after new one is active to avoid ugliness */ |
821 | if (old_obj) { | |
822 | /* | |
823 | * It's fairly common to simply update the position of | |
824 | * an existing object. In that case, we don't need to | |
825 | * wait for vblank to avoid ugliness, we only need to | |
826 | * do the pin & ref bookkeeping. | |
827 | */ | |
828 | if (old_obj != obj) { | |
829 | mutex_unlock(&dev->struct_mutex); | |
830 | intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe); | |
831 | mutex_lock(&dev->struct_mutex); | |
832 | } | |
1690e1eb | 833 | intel_unpin_fb_obj(old_obj); |
b840d907 JB |
834 | } |
835 | ||
836 | out_unlock: | |
837 | mutex_unlock(&dev->struct_mutex); | |
b840d907 JB |
838 | return ret; |
839 | } | |
840 | ||
841 | static int | |
842 | intel_disable_plane(struct drm_plane *plane) | |
843 | { | |
844 | struct drm_device *dev = plane->dev; | |
845 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
846 | int ret = 0; | |
847 | ||
93314b5b | 848 | if (plane->crtc) |
175bd420 | 849 | intel_enable_primary(plane->crtc); |
b840d907 JB |
850 | intel_plane->disable_plane(plane); |
851 | ||
852 | if (!intel_plane->obj) | |
853 | goto out; | |
854 | ||
c626d317 VS |
855 | intel_wait_for_vblank(dev, intel_plane->pipe); |
856 | ||
b840d907 | 857 | mutex_lock(&dev->struct_mutex); |
1690e1eb | 858 | intel_unpin_fb_obj(intel_plane->obj); |
b840d907 JB |
859 | intel_plane->obj = NULL; |
860 | mutex_unlock(&dev->struct_mutex); | |
861 | out: | |
862 | ||
863 | return ret; | |
864 | } | |
865 | ||
866 | static void intel_destroy_plane(struct drm_plane *plane) | |
867 | { | |
868 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
869 | intel_disable_plane(plane); | |
870 | drm_plane_cleanup(plane); | |
871 | kfree(intel_plane); | |
872 | } | |
873 | ||
8ea30864 JB |
874 | int intel_sprite_set_colorkey(struct drm_device *dev, void *data, |
875 | struct drm_file *file_priv) | |
876 | { | |
877 | struct drm_intel_sprite_colorkey *set = data; | |
8ea30864 JB |
878 | struct drm_mode_object *obj; |
879 | struct drm_plane *plane; | |
880 | struct intel_plane *intel_plane; | |
881 | int ret = 0; | |
882 | ||
1cff8f6b DV |
883 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
884 | return -ENODEV; | |
8ea30864 JB |
885 | |
886 | /* Make sure we don't try to enable both src & dest simultaneously */ | |
887 | if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) | |
888 | return -EINVAL; | |
889 | ||
a0e99e68 | 890 | drm_modeset_lock_all(dev); |
8ea30864 JB |
891 | |
892 | obj = drm_mode_object_find(dev, set->plane_id, DRM_MODE_OBJECT_PLANE); | |
893 | if (!obj) { | |
894 | ret = -EINVAL; | |
895 | goto out_unlock; | |
896 | } | |
897 | ||
898 | plane = obj_to_plane(obj); | |
899 | intel_plane = to_intel_plane(plane); | |
900 | ret = intel_plane->update_colorkey(plane, set); | |
901 | ||
902 | out_unlock: | |
a0e99e68 | 903 | drm_modeset_unlock_all(dev); |
8ea30864 JB |
904 | return ret; |
905 | } | |
906 | ||
907 | int intel_sprite_get_colorkey(struct drm_device *dev, void *data, | |
908 | struct drm_file *file_priv) | |
909 | { | |
910 | struct drm_intel_sprite_colorkey *get = data; | |
8ea30864 JB |
911 | struct drm_mode_object *obj; |
912 | struct drm_plane *plane; | |
913 | struct intel_plane *intel_plane; | |
914 | int ret = 0; | |
915 | ||
1cff8f6b DV |
916 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
917 | return -ENODEV; | |
8ea30864 | 918 | |
a0e99e68 | 919 | drm_modeset_lock_all(dev); |
8ea30864 JB |
920 | |
921 | obj = drm_mode_object_find(dev, get->plane_id, DRM_MODE_OBJECT_PLANE); | |
922 | if (!obj) { | |
923 | ret = -EINVAL; | |
924 | goto out_unlock; | |
925 | } | |
926 | ||
927 | plane = obj_to_plane(obj); | |
928 | intel_plane = to_intel_plane(plane); | |
929 | intel_plane->get_colorkey(plane, get); | |
930 | ||
931 | out_unlock: | |
a0e99e68 | 932 | drm_modeset_unlock_all(dev); |
8ea30864 JB |
933 | return ret; |
934 | } | |
935 | ||
5e1bac2f JB |
936 | void intel_plane_restore(struct drm_plane *plane) |
937 | { | |
938 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
939 | ||
940 | if (!plane->crtc || !plane->fb) | |
941 | return; | |
942 | ||
943 | intel_update_plane(plane, plane->crtc, plane->fb, | |
944 | intel_plane->crtc_x, intel_plane->crtc_y, | |
945 | intel_plane->crtc_w, intel_plane->crtc_h, | |
946 | intel_plane->src_x, intel_plane->src_y, | |
947 | intel_plane->src_w, intel_plane->src_h); | |
948 | } | |
949 | ||
b840d907 JB |
950 | static const struct drm_plane_funcs intel_plane_funcs = { |
951 | .update_plane = intel_update_plane, | |
952 | .disable_plane = intel_disable_plane, | |
953 | .destroy = intel_destroy_plane, | |
954 | }; | |
955 | ||
d1686ae3 CW |
956 | static uint32_t ilk_plane_formats[] = { |
957 | DRM_FORMAT_XRGB8888, | |
958 | DRM_FORMAT_YUYV, | |
959 | DRM_FORMAT_YVYU, | |
960 | DRM_FORMAT_UYVY, | |
961 | DRM_FORMAT_VYUY, | |
962 | }; | |
963 | ||
b840d907 JB |
964 | static uint32_t snb_plane_formats[] = { |
965 | DRM_FORMAT_XBGR8888, | |
966 | DRM_FORMAT_XRGB8888, | |
967 | DRM_FORMAT_YUYV, | |
968 | DRM_FORMAT_YVYU, | |
969 | DRM_FORMAT_UYVY, | |
970 | DRM_FORMAT_VYUY, | |
971 | }; | |
972 | ||
7f1f3851 JB |
973 | static uint32_t vlv_plane_formats[] = { |
974 | DRM_FORMAT_RGB565, | |
975 | DRM_FORMAT_ABGR8888, | |
976 | DRM_FORMAT_ARGB8888, | |
977 | DRM_FORMAT_XBGR8888, | |
978 | DRM_FORMAT_XRGB8888, | |
979 | DRM_FORMAT_XBGR2101010, | |
980 | DRM_FORMAT_ABGR2101010, | |
981 | DRM_FORMAT_YUYV, | |
982 | DRM_FORMAT_YVYU, | |
983 | DRM_FORMAT_UYVY, | |
984 | DRM_FORMAT_VYUY, | |
985 | }; | |
986 | ||
b840d907 | 987 | int |
7f1f3851 | 988 | intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane) |
b840d907 JB |
989 | { |
990 | struct intel_plane *intel_plane; | |
991 | unsigned long possible_crtcs; | |
d1686ae3 CW |
992 | const uint32_t *plane_formats; |
993 | int num_plane_formats; | |
b840d907 JB |
994 | int ret; |
995 | ||
d1686ae3 | 996 | if (INTEL_INFO(dev)->gen < 5) |
b840d907 | 997 | return -ENODEV; |
b840d907 JB |
998 | |
999 | intel_plane = kzalloc(sizeof(struct intel_plane), GFP_KERNEL); | |
1000 | if (!intel_plane) | |
1001 | return -ENOMEM; | |
1002 | ||
d1686ae3 CW |
1003 | switch (INTEL_INFO(dev)->gen) { |
1004 | case 5: | |
1005 | case 6: | |
2d354c34 | 1006 | intel_plane->can_scale = true; |
b840d907 | 1007 | intel_plane->max_downscale = 16; |
d1686ae3 CW |
1008 | intel_plane->update_plane = ilk_update_plane; |
1009 | intel_plane->disable_plane = ilk_disable_plane; | |
1010 | intel_plane->update_colorkey = ilk_update_colorkey; | |
1011 | intel_plane->get_colorkey = ilk_get_colorkey; | |
1012 | ||
1013 | if (IS_GEN6(dev)) { | |
1014 | plane_formats = snb_plane_formats; | |
1015 | num_plane_formats = ARRAY_SIZE(snb_plane_formats); | |
1016 | } else { | |
1017 | plane_formats = ilk_plane_formats; | |
1018 | num_plane_formats = ARRAY_SIZE(ilk_plane_formats); | |
1019 | } | |
1020 | break; | |
1021 | ||
1022 | case 7: | |
d49f7091 | 1023 | if (IS_IVYBRIDGE(dev)) { |
2d354c34 | 1024 | intel_plane->can_scale = true; |
d49f7091 DL |
1025 | intel_plane->max_downscale = 2; |
1026 | } else { | |
1027 | intel_plane->can_scale = false; | |
1028 | intel_plane->max_downscale = 1; | |
1029 | } | |
7f1f3851 JB |
1030 | |
1031 | if (IS_VALLEYVIEW(dev)) { | |
7f1f3851 JB |
1032 | intel_plane->update_plane = vlv_update_plane; |
1033 | intel_plane->disable_plane = vlv_disable_plane; | |
1034 | intel_plane->update_colorkey = vlv_update_colorkey; | |
1035 | intel_plane->get_colorkey = vlv_get_colorkey; | |
1036 | ||
1037 | plane_formats = vlv_plane_formats; | |
1038 | num_plane_formats = ARRAY_SIZE(vlv_plane_formats); | |
1039 | } else { | |
7f1f3851 JB |
1040 | intel_plane->update_plane = ivb_update_plane; |
1041 | intel_plane->disable_plane = ivb_disable_plane; | |
1042 | intel_plane->update_colorkey = ivb_update_colorkey; | |
1043 | intel_plane->get_colorkey = ivb_get_colorkey; | |
1044 | ||
1045 | plane_formats = snb_plane_formats; | |
1046 | num_plane_formats = ARRAY_SIZE(snb_plane_formats); | |
1047 | } | |
d1686ae3 CW |
1048 | break; |
1049 | ||
1050 | default: | |
a8b0bbab | 1051 | kfree(intel_plane); |
d1686ae3 | 1052 | return -ENODEV; |
b840d907 JB |
1053 | } |
1054 | ||
1055 | intel_plane->pipe = pipe; | |
7f1f3851 | 1056 | intel_plane->plane = plane; |
b840d907 JB |
1057 | possible_crtcs = (1 << pipe); |
1058 | ret = drm_plane_init(dev, &intel_plane->base, possible_crtcs, | |
d1686ae3 CW |
1059 | &intel_plane_funcs, |
1060 | plane_formats, num_plane_formats, | |
1061 | false); | |
b840d907 JB |
1062 | if (ret) |
1063 | kfree(intel_plane); | |
1064 | ||
1065 | return ret; | |
1066 | } |