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79e53945 JB |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2007 Intel Corporation | |
4 | * Jesse Barnes <jesse.barnes@intel.com> | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
23 | * DEALINGS IN THE SOFTWARE. | |
24 | * | |
25 | * Authors: | |
26 | * Eric Anholt <eric@anholt.net> | |
27 | */ | |
28 | #include <linux/i2c.h> | |
29 | #include <linux/delay.h> | |
30 | #include "drmP.h" | |
31 | #include "drm.h" | |
32 | #include "drm_crtc.h" | |
33 | #include "intel_drv.h" | |
34 | #include "i915_drm.h" | |
35 | #include "i915_drv.h" | |
36 | #include "intel_sdvo_regs.h" | |
37 | ||
38 | #undef SDVO_DEBUG | |
342dc382 | 39 | #define I915_SDVO "i915_sdvo" |
79e53945 | 40 | struct intel_sdvo_priv { |
f9c10a9b KP |
41 | struct i2c_adapter *i2c_bus; |
42 | u8 slave_addr; | |
e2f0ba97 JB |
43 | |
44 | /* Register for the SDVO device: SDVOB or SDVOC */ | |
79e53945 JB |
45 | int output_device; |
46 | ||
e2f0ba97 JB |
47 | /* Active outputs controlled by this SDVO output */ |
48 | uint16_t controlled_output; | |
79e53945 | 49 | |
e2f0ba97 JB |
50 | /* |
51 | * Capabilities of the SDVO device returned by | |
52 | * i830_sdvo_get_capabilities() | |
53 | */ | |
79e53945 | 54 | struct intel_sdvo_caps caps; |
e2f0ba97 JB |
55 | |
56 | /* Pixel clock limitations reported by the SDVO device, in kHz */ | |
79e53945 JB |
57 | int pixel_clock_min, pixel_clock_max; |
58 | ||
e2f0ba97 JB |
59 | /** |
60 | * This is set if we're going to treat the device as TV-out. | |
61 | * | |
62 | * While we have these nice friendly flags for output types that ought | |
63 | * to decide this for us, the S-Video output on our HDMI+S-Video card | |
64 | * shows up as RGB1 (VGA). | |
65 | */ | |
66 | bool is_tv; | |
67 | ||
68 | /** | |
69 | * This is set if we treat the device as HDMI, instead of DVI. | |
70 | */ | |
71 | bool is_hdmi; | |
7086c87f ML |
72 | /** |
73 | * This is set if we detect output of sdvo device as LVDS. | |
74 | */ | |
75 | bool is_lvds; | |
e2f0ba97 JB |
76 | |
77 | /** | |
78 | * Returned SDTV resolutions allowed for the current format, if the | |
79 | * device reported it. | |
80 | */ | |
81 | struct intel_sdvo_sdtv_resolution_reply sdtv_resolutions; | |
82 | ||
83 | /** | |
84 | * Current selected TV format. | |
85 | * | |
86 | * This is stored in the same structure that's passed to the device, for | |
87 | * convenience. | |
88 | */ | |
89 | struct intel_sdvo_tv_format tv_format; | |
90 | ||
91 | /* | |
92 | * supported encoding mode, used to determine whether HDMI is | |
93 | * supported | |
94 | */ | |
95 | struct intel_sdvo_encode encode; | |
96 | ||
97 | /* DDC bus used by this SDVO output */ | |
98 | uint8_t ddc_bus; | |
99 | ||
79e53945 JB |
100 | int save_sdvo_mult; |
101 | u16 save_active_outputs; | |
102 | struct intel_sdvo_dtd save_input_dtd_1, save_input_dtd_2; | |
103 | struct intel_sdvo_dtd save_output_dtd[16]; | |
104 | u32 save_SDVOX; | |
105 | }; | |
106 | ||
107 | /** | |
108 | * Writes the SDVOB or SDVOC with the given value, but always writes both | |
109 | * SDVOB and SDVOC to work around apparent hardware issues (according to | |
110 | * comments in the BIOS). | |
111 | */ | |
b358d0a6 | 112 | static void intel_sdvo_write_sdvox(struct intel_output *intel_output, u32 val) |
79e53945 JB |
113 | { |
114 | struct drm_device *dev = intel_output->base.dev; | |
115 | struct drm_i915_private *dev_priv = dev->dev_private; | |
116 | struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; | |
117 | u32 bval = val, cval = val; | |
118 | int i; | |
119 | ||
120 | if (sdvo_priv->output_device == SDVOB) { | |
121 | cval = I915_READ(SDVOC); | |
122 | } else { | |
123 | bval = I915_READ(SDVOB); | |
124 | } | |
125 | /* | |
126 | * Write the registers twice for luck. Sometimes, | |
127 | * writing them only once doesn't appear to 'stick'. | |
128 | * The BIOS does this too. Yay, magic | |
129 | */ | |
130 | for (i = 0; i < 2; i++) | |
131 | { | |
132 | I915_WRITE(SDVOB, bval); | |
133 | I915_READ(SDVOB); | |
134 | I915_WRITE(SDVOC, cval); | |
135 | I915_READ(SDVOC); | |
136 | } | |
137 | } | |
138 | ||
139 | static bool intel_sdvo_read_byte(struct intel_output *intel_output, u8 addr, | |
140 | u8 *ch) | |
141 | { | |
142 | struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; | |
143 | u8 out_buf[2]; | |
144 | u8 buf[2]; | |
145 | int ret; | |
146 | ||
147 | struct i2c_msg msgs[] = { | |
148 | { | |
f9c10a9b | 149 | .addr = sdvo_priv->slave_addr >> 1, |
79e53945 JB |
150 | .flags = 0, |
151 | .len = 1, | |
152 | .buf = out_buf, | |
153 | }, | |
154 | { | |
f9c10a9b | 155 | .addr = sdvo_priv->slave_addr >> 1, |
79e53945 JB |
156 | .flags = I2C_M_RD, |
157 | .len = 1, | |
158 | .buf = buf, | |
159 | } | |
160 | }; | |
161 | ||
162 | out_buf[0] = addr; | |
163 | out_buf[1] = 0; | |
164 | ||
f9c10a9b | 165 | if ((ret = i2c_transfer(sdvo_priv->i2c_bus, msgs, 2)) == 2) |
79e53945 JB |
166 | { |
167 | *ch = buf[0]; | |
168 | return true; | |
169 | } | |
170 | ||
171 | DRM_DEBUG("i2c transfer returned %d\n", ret); | |
172 | return false; | |
173 | } | |
174 | ||
175 | static bool intel_sdvo_write_byte(struct intel_output *intel_output, int addr, | |
176 | u8 ch) | |
177 | { | |
f9c10a9b | 178 | struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; |
79e53945 JB |
179 | u8 out_buf[2]; |
180 | struct i2c_msg msgs[] = { | |
181 | { | |
f9c10a9b | 182 | .addr = sdvo_priv->slave_addr >> 1, |
79e53945 JB |
183 | .flags = 0, |
184 | .len = 2, | |
185 | .buf = out_buf, | |
186 | } | |
187 | }; | |
188 | ||
189 | out_buf[0] = addr; | |
190 | out_buf[1] = ch; | |
191 | ||
f9c10a9b | 192 | if (i2c_transfer(intel_output->i2c_bus, msgs, 1) == 1) |
79e53945 JB |
193 | { |
194 | return true; | |
195 | } | |
196 | return false; | |
197 | } | |
198 | ||
199 | #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd} | |
200 | /** Mapping of command numbers to names, for debug output */ | |
005568be | 201 | static const struct _sdvo_cmd_name { |
e2f0ba97 JB |
202 | u8 cmd; |
203 | char *name; | |
79e53945 JB |
204 | } sdvo_cmd_names[] = { |
205 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET), | |
206 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS), | |
207 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV), | |
208 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS), | |
209 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS), | |
210 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS), | |
211 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP), | |
212 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP), | |
213 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS), | |
214 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT), | |
215 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG), | |
216 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG), | |
217 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE), | |
218 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT), | |
219 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT), | |
220 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1), | |
221 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2), | |
222 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), | |
223 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2), | |
224 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), | |
225 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1), | |
226 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2), | |
227 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1), | |
228 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2), | |
229 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING), | |
230 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1), | |
231 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2), | |
232 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE), | |
233 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE), | |
234 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS), | |
235 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT), | |
236 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT), | |
237 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS), | |
238 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT), | |
239 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT), | |
e2f0ba97 JB |
240 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES), |
241 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE), | |
242 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE), | |
243 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE), | |
79e53945 | 244 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH), |
e2f0ba97 JB |
245 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT), |
246 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT), | |
247 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS), | |
248 | /* HDMI op code */ | |
249 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE), | |
250 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE), | |
251 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE), | |
252 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI), | |
253 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI), | |
254 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP), | |
255 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY), | |
256 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY), | |
257 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER), | |
258 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT), | |
259 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT), | |
260 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX), | |
261 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX), | |
262 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO), | |
263 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT), | |
264 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT), | |
265 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE), | |
266 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE), | |
267 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA), | |
268 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA), | |
79e53945 JB |
269 | }; |
270 | ||
271 | #define SDVO_NAME(dev_priv) ((dev_priv)->output_device == SDVOB ? "SDVOB" : "SDVOC") | |
272 | #define SDVO_PRIV(output) ((struct intel_sdvo_priv *) (output)->dev_priv) | |
273 | ||
274 | #ifdef SDVO_DEBUG | |
275 | static void intel_sdvo_debug_write(struct intel_output *intel_output, u8 cmd, | |
276 | void *args, int args_len) | |
277 | { | |
278 | struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; | |
279 | int i; | |
280 | ||
342dc382 | 281 | DRM_DEBUG_KMS(I915_SDVO, "%s: W: %02X ", |
282 | SDVO_NAME(sdvo_priv), cmd); | |
79e53945 | 283 | for (i = 0; i < args_len; i++) |
342dc382 | 284 | DRM_LOG_KMS("%02X ", ((u8 *)args)[i]); |
79e53945 | 285 | for (; i < 8; i++) |
342dc382 | 286 | DRM_LOG_KMS(" "); |
79e53945 JB |
287 | for (i = 0; i < sizeof(sdvo_cmd_names) / sizeof(sdvo_cmd_names[0]); i++) { |
288 | if (cmd == sdvo_cmd_names[i].cmd) { | |
342dc382 | 289 | DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name); |
79e53945 JB |
290 | break; |
291 | } | |
292 | } | |
293 | if (i == sizeof(sdvo_cmd_names)/ sizeof(sdvo_cmd_names[0])) | |
342dc382 | 294 | DRM_LOG_KMS("(%02X)", cmd); |
295 | DRM_LOG_KMS("\n"); | |
79e53945 JB |
296 | } |
297 | #else | |
298 | #define intel_sdvo_debug_write(o, c, a, l) | |
299 | #endif | |
300 | ||
301 | static void intel_sdvo_write_cmd(struct intel_output *intel_output, u8 cmd, | |
302 | void *args, int args_len) | |
303 | { | |
304 | int i; | |
305 | ||
306 | intel_sdvo_debug_write(intel_output, cmd, args, args_len); | |
307 | ||
308 | for (i = 0; i < args_len; i++) { | |
309 | intel_sdvo_write_byte(intel_output, SDVO_I2C_ARG_0 - i, | |
310 | ((u8*)args)[i]); | |
311 | } | |
312 | ||
313 | intel_sdvo_write_byte(intel_output, SDVO_I2C_OPCODE, cmd); | |
314 | } | |
315 | ||
316 | #ifdef SDVO_DEBUG | |
317 | static const char *cmd_status_names[] = { | |
318 | "Power on", | |
319 | "Success", | |
320 | "Not supported", | |
321 | "Invalid arg", | |
322 | "Pending", | |
323 | "Target not specified", | |
324 | "Scaling not supported" | |
325 | }; | |
326 | ||
327 | static void intel_sdvo_debug_response(struct intel_output *intel_output, | |
328 | void *response, int response_len, | |
329 | u8 status) | |
330 | { | |
331 | struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; | |
33b52961 | 332 | int i; |
79e53945 | 333 | |
342dc382 | 334 | DRM_DEBUG_KMS(I915_SDVO, "%s: R: ", SDVO_NAME(sdvo_priv)); |
79e53945 | 335 | for (i = 0; i < response_len; i++) |
342dc382 | 336 | DRM_LOG_KMS("%02X ", ((u8 *)response)[i]); |
79e53945 | 337 | for (; i < 8; i++) |
342dc382 | 338 | DRM_LOG_KMS(" "); |
79e53945 | 339 | if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP) |
342dc382 | 340 | DRM_LOG_KMS("(%s)", cmd_status_names[status]); |
79e53945 | 341 | else |
342dc382 | 342 | DRM_LOG_KMS("(??? %d)", status); |
343 | DRM_LOG_KMS("\n"); | |
79e53945 JB |
344 | } |
345 | #else | |
346 | #define intel_sdvo_debug_response(o, r, l, s) | |
347 | #endif | |
348 | ||
349 | static u8 intel_sdvo_read_response(struct intel_output *intel_output, | |
350 | void *response, int response_len) | |
351 | { | |
352 | int i; | |
353 | u8 status; | |
354 | u8 retry = 50; | |
355 | ||
356 | while (retry--) { | |
357 | /* Read the command response */ | |
358 | for (i = 0; i < response_len; i++) { | |
359 | intel_sdvo_read_byte(intel_output, | |
360 | SDVO_I2C_RETURN_0 + i, | |
361 | &((u8 *)response)[i]); | |
362 | } | |
363 | ||
364 | /* read the return status */ | |
365 | intel_sdvo_read_byte(intel_output, SDVO_I2C_CMD_STATUS, | |
366 | &status); | |
367 | ||
368 | intel_sdvo_debug_response(intel_output, response, response_len, | |
369 | status); | |
370 | if (status != SDVO_CMD_STATUS_PENDING) | |
371 | return status; | |
372 | ||
373 | mdelay(50); | |
374 | } | |
375 | ||
376 | return status; | |
377 | } | |
378 | ||
b358d0a6 | 379 | static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode) |
79e53945 JB |
380 | { |
381 | if (mode->clock >= 100000) | |
382 | return 1; | |
383 | else if (mode->clock >= 50000) | |
384 | return 2; | |
385 | else | |
386 | return 4; | |
387 | } | |
388 | ||
389 | /** | |
390 | * Don't check status code from this as it switches the bus back to the | |
391 | * SDVO chips which defeats the purpose of doing a bus switch in the first | |
392 | * place. | |
393 | */ | |
b358d0a6 HE |
394 | static void intel_sdvo_set_control_bus_switch(struct intel_output *intel_output, |
395 | u8 target) | |
79e53945 JB |
396 | { |
397 | intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_CONTROL_BUS_SWITCH, &target, 1); | |
398 | } | |
399 | ||
400 | static bool intel_sdvo_set_target_input(struct intel_output *intel_output, bool target_0, bool target_1) | |
401 | { | |
402 | struct intel_sdvo_set_target_input_args targets = {0}; | |
403 | u8 status; | |
404 | ||
405 | if (target_0 && target_1) | |
406 | return SDVO_CMD_STATUS_NOTSUPP; | |
407 | ||
408 | if (target_1) | |
409 | targets.target_1 = 1; | |
410 | ||
411 | intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_TARGET_INPUT, &targets, | |
412 | sizeof(targets)); | |
413 | ||
414 | status = intel_sdvo_read_response(intel_output, NULL, 0); | |
415 | ||
416 | return (status == SDVO_CMD_STATUS_SUCCESS); | |
417 | } | |
418 | ||
419 | /** | |
420 | * Return whether each input is trained. | |
421 | * | |
422 | * This function is making an assumption about the layout of the response, | |
423 | * which should be checked against the docs. | |
424 | */ | |
425 | static bool intel_sdvo_get_trained_inputs(struct intel_output *intel_output, bool *input_1, bool *input_2) | |
426 | { | |
427 | struct intel_sdvo_get_trained_inputs_response response; | |
428 | u8 status; | |
429 | ||
430 | intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_TRAINED_INPUTS, NULL, 0); | |
431 | status = intel_sdvo_read_response(intel_output, &response, sizeof(response)); | |
432 | if (status != SDVO_CMD_STATUS_SUCCESS) | |
433 | return false; | |
434 | ||
435 | *input_1 = response.input0_trained; | |
436 | *input_2 = response.input1_trained; | |
437 | return true; | |
438 | } | |
439 | ||
440 | static bool intel_sdvo_get_active_outputs(struct intel_output *intel_output, | |
441 | u16 *outputs) | |
442 | { | |
443 | u8 status; | |
444 | ||
445 | intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_OUTPUTS, NULL, 0); | |
446 | status = intel_sdvo_read_response(intel_output, outputs, sizeof(*outputs)); | |
447 | ||
448 | return (status == SDVO_CMD_STATUS_SUCCESS); | |
449 | } | |
450 | ||
451 | static bool intel_sdvo_set_active_outputs(struct intel_output *intel_output, | |
452 | u16 outputs) | |
453 | { | |
454 | u8 status; | |
455 | ||
456 | intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_OUTPUTS, &outputs, | |
457 | sizeof(outputs)); | |
458 | status = intel_sdvo_read_response(intel_output, NULL, 0); | |
459 | return (status == SDVO_CMD_STATUS_SUCCESS); | |
460 | } | |
461 | ||
462 | static bool intel_sdvo_set_encoder_power_state(struct intel_output *intel_output, | |
463 | int mode) | |
464 | { | |
465 | u8 status, state = SDVO_ENCODER_STATE_ON; | |
466 | ||
467 | switch (mode) { | |
468 | case DRM_MODE_DPMS_ON: | |
469 | state = SDVO_ENCODER_STATE_ON; | |
470 | break; | |
471 | case DRM_MODE_DPMS_STANDBY: | |
472 | state = SDVO_ENCODER_STATE_STANDBY; | |
473 | break; | |
474 | case DRM_MODE_DPMS_SUSPEND: | |
475 | state = SDVO_ENCODER_STATE_SUSPEND; | |
476 | break; | |
477 | case DRM_MODE_DPMS_OFF: | |
478 | state = SDVO_ENCODER_STATE_OFF; | |
479 | break; | |
480 | } | |
481 | ||
482 | intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ENCODER_POWER_STATE, &state, | |
483 | sizeof(state)); | |
484 | status = intel_sdvo_read_response(intel_output, NULL, 0); | |
485 | ||
486 | return (status == SDVO_CMD_STATUS_SUCCESS); | |
487 | } | |
488 | ||
489 | static bool intel_sdvo_get_input_pixel_clock_range(struct intel_output *intel_output, | |
490 | int *clock_min, | |
491 | int *clock_max) | |
492 | { | |
493 | struct intel_sdvo_pixel_clock_range clocks; | |
494 | u8 status; | |
495 | ||
496 | intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, | |
497 | NULL, 0); | |
498 | ||
499 | status = intel_sdvo_read_response(intel_output, &clocks, sizeof(clocks)); | |
500 | ||
501 | if (status != SDVO_CMD_STATUS_SUCCESS) | |
502 | return false; | |
503 | ||
504 | /* Convert the values from units of 10 kHz to kHz. */ | |
505 | *clock_min = clocks.min * 10; | |
506 | *clock_max = clocks.max * 10; | |
507 | ||
508 | return true; | |
509 | } | |
510 | ||
511 | static bool intel_sdvo_set_target_output(struct intel_output *intel_output, | |
512 | u16 outputs) | |
513 | { | |
514 | u8 status; | |
515 | ||
516 | intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_TARGET_OUTPUT, &outputs, | |
517 | sizeof(outputs)); | |
518 | ||
519 | status = intel_sdvo_read_response(intel_output, NULL, 0); | |
520 | return (status == SDVO_CMD_STATUS_SUCCESS); | |
521 | } | |
522 | ||
523 | static bool intel_sdvo_get_timing(struct intel_output *intel_output, u8 cmd, | |
524 | struct intel_sdvo_dtd *dtd) | |
525 | { | |
526 | u8 status; | |
527 | ||
528 | intel_sdvo_write_cmd(intel_output, cmd, NULL, 0); | |
529 | status = intel_sdvo_read_response(intel_output, &dtd->part1, | |
530 | sizeof(dtd->part1)); | |
531 | if (status != SDVO_CMD_STATUS_SUCCESS) | |
532 | return false; | |
533 | ||
534 | intel_sdvo_write_cmd(intel_output, cmd + 1, NULL, 0); | |
535 | status = intel_sdvo_read_response(intel_output, &dtd->part2, | |
536 | sizeof(dtd->part2)); | |
537 | if (status != SDVO_CMD_STATUS_SUCCESS) | |
538 | return false; | |
539 | ||
540 | return true; | |
541 | } | |
542 | ||
543 | static bool intel_sdvo_get_input_timing(struct intel_output *intel_output, | |
544 | struct intel_sdvo_dtd *dtd) | |
545 | { | |
546 | return intel_sdvo_get_timing(intel_output, | |
547 | SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd); | |
548 | } | |
549 | ||
550 | static bool intel_sdvo_get_output_timing(struct intel_output *intel_output, | |
551 | struct intel_sdvo_dtd *dtd) | |
552 | { | |
553 | return intel_sdvo_get_timing(intel_output, | |
554 | SDVO_CMD_GET_OUTPUT_TIMINGS_PART1, dtd); | |
555 | } | |
556 | ||
557 | static bool intel_sdvo_set_timing(struct intel_output *intel_output, u8 cmd, | |
558 | struct intel_sdvo_dtd *dtd) | |
559 | { | |
560 | u8 status; | |
561 | ||
562 | intel_sdvo_write_cmd(intel_output, cmd, &dtd->part1, sizeof(dtd->part1)); | |
563 | status = intel_sdvo_read_response(intel_output, NULL, 0); | |
564 | if (status != SDVO_CMD_STATUS_SUCCESS) | |
565 | return false; | |
566 | ||
567 | intel_sdvo_write_cmd(intel_output, cmd + 1, &dtd->part2, sizeof(dtd->part2)); | |
568 | status = intel_sdvo_read_response(intel_output, NULL, 0); | |
569 | if (status != SDVO_CMD_STATUS_SUCCESS) | |
570 | return false; | |
571 | ||
572 | return true; | |
573 | } | |
574 | ||
575 | static bool intel_sdvo_set_input_timing(struct intel_output *intel_output, | |
576 | struct intel_sdvo_dtd *dtd) | |
577 | { | |
578 | return intel_sdvo_set_timing(intel_output, | |
579 | SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); | |
580 | } | |
581 | ||
582 | static bool intel_sdvo_set_output_timing(struct intel_output *intel_output, | |
583 | struct intel_sdvo_dtd *dtd) | |
584 | { | |
585 | return intel_sdvo_set_timing(intel_output, | |
586 | SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); | |
587 | } | |
588 | ||
e2f0ba97 JB |
589 | static bool |
590 | intel_sdvo_create_preferred_input_timing(struct intel_output *output, | |
591 | uint16_t clock, | |
592 | uint16_t width, | |
593 | uint16_t height) | |
594 | { | |
595 | struct intel_sdvo_preferred_input_timing_args args; | |
596 | uint8_t status; | |
597 | ||
e642c6f1 | 598 | memset(&args, 0, sizeof(args)); |
e2f0ba97 JB |
599 | args.clock = clock; |
600 | args.width = width; | |
601 | args.height = height; | |
e642c6f1 ZW |
602 | args.interlace = 0; |
603 | args.scaled = 0; | |
e2f0ba97 JB |
604 | intel_sdvo_write_cmd(output, SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, |
605 | &args, sizeof(args)); | |
606 | status = intel_sdvo_read_response(output, NULL, 0); | |
607 | if (status != SDVO_CMD_STATUS_SUCCESS) | |
608 | return false; | |
609 | ||
610 | return true; | |
611 | } | |
612 | ||
613 | static bool intel_sdvo_get_preferred_input_timing(struct intel_output *output, | |
614 | struct intel_sdvo_dtd *dtd) | |
615 | { | |
616 | bool status; | |
617 | ||
618 | intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, | |
619 | NULL, 0); | |
620 | ||
621 | status = intel_sdvo_read_response(output, &dtd->part1, | |
622 | sizeof(dtd->part1)); | |
623 | if (status != SDVO_CMD_STATUS_SUCCESS) | |
624 | return false; | |
625 | ||
626 | intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, | |
627 | NULL, 0); | |
628 | ||
629 | status = intel_sdvo_read_response(output, &dtd->part2, | |
630 | sizeof(dtd->part2)); | |
631 | if (status != SDVO_CMD_STATUS_SUCCESS) | |
632 | return false; | |
633 | ||
634 | return false; | |
635 | } | |
79e53945 JB |
636 | |
637 | static int intel_sdvo_get_clock_rate_mult(struct intel_output *intel_output) | |
638 | { | |
639 | u8 response, status; | |
640 | ||
641 | intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_CLOCK_RATE_MULT, NULL, 0); | |
642 | status = intel_sdvo_read_response(intel_output, &response, 1); | |
643 | ||
644 | if (status != SDVO_CMD_STATUS_SUCCESS) { | |
645 | DRM_DEBUG("Couldn't get SDVO clock rate multiplier\n"); | |
646 | return SDVO_CLOCK_RATE_MULT_1X; | |
647 | } else { | |
648 | DRM_DEBUG("Current clock rate multiplier: %d\n", response); | |
649 | } | |
650 | ||
651 | return response; | |
652 | } | |
653 | ||
654 | static bool intel_sdvo_set_clock_rate_mult(struct intel_output *intel_output, u8 val) | |
655 | { | |
656 | u8 status; | |
657 | ||
658 | intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); | |
659 | status = intel_sdvo_read_response(intel_output, NULL, 0); | |
660 | if (status != SDVO_CMD_STATUS_SUCCESS) | |
661 | return false; | |
662 | ||
663 | return true; | |
664 | } | |
665 | ||
e2f0ba97 JB |
666 | static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, |
667 | struct drm_display_mode *mode) | |
79e53945 | 668 | { |
e2f0ba97 JB |
669 | uint16_t width, height; |
670 | uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len; | |
671 | uint16_t h_sync_offset, v_sync_offset; | |
79e53945 JB |
672 | |
673 | width = mode->crtc_hdisplay; | |
674 | height = mode->crtc_vdisplay; | |
675 | ||
676 | /* do some mode translations */ | |
677 | h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start; | |
678 | h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; | |
679 | ||
680 | v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start; | |
681 | v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; | |
682 | ||
683 | h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start; | |
684 | v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start; | |
685 | ||
e2f0ba97 JB |
686 | dtd->part1.clock = mode->clock / 10; |
687 | dtd->part1.h_active = width & 0xff; | |
688 | dtd->part1.h_blank = h_blank_len & 0xff; | |
689 | dtd->part1.h_high = (((width >> 8) & 0xf) << 4) | | |
79e53945 | 690 | ((h_blank_len >> 8) & 0xf); |
e2f0ba97 JB |
691 | dtd->part1.v_active = height & 0xff; |
692 | dtd->part1.v_blank = v_blank_len & 0xff; | |
693 | dtd->part1.v_high = (((height >> 8) & 0xf) << 4) | | |
79e53945 JB |
694 | ((v_blank_len >> 8) & 0xf); |
695 | ||
171a9e96 | 696 | dtd->part2.h_sync_off = h_sync_offset & 0xff; |
e2f0ba97 JB |
697 | dtd->part2.h_sync_width = h_sync_len & 0xff; |
698 | dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 | | |
79e53945 | 699 | (v_sync_len & 0xf); |
e2f0ba97 | 700 | dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) | |
79e53945 JB |
701 | ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) | |
702 | ((v_sync_len & 0x30) >> 4); | |
703 | ||
e2f0ba97 | 704 | dtd->part2.dtd_flags = 0x18; |
79e53945 | 705 | if (mode->flags & DRM_MODE_FLAG_PHSYNC) |
e2f0ba97 | 706 | dtd->part2.dtd_flags |= 0x2; |
79e53945 | 707 | if (mode->flags & DRM_MODE_FLAG_PVSYNC) |
e2f0ba97 JB |
708 | dtd->part2.dtd_flags |= 0x4; |
709 | ||
710 | dtd->part2.sdvo_flags = 0; | |
711 | dtd->part2.v_sync_off_high = v_sync_offset & 0xc0; | |
712 | dtd->part2.reserved = 0; | |
713 | } | |
714 | ||
715 | static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode, | |
716 | struct intel_sdvo_dtd *dtd) | |
717 | { | |
e2f0ba97 JB |
718 | mode->hdisplay = dtd->part1.h_active; |
719 | mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; | |
720 | mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off; | |
171a9e96 | 721 | mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2; |
e2f0ba97 JB |
722 | mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width; |
723 | mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4; | |
724 | mode->htotal = mode->hdisplay + dtd->part1.h_blank; | |
725 | mode->htotal += (dtd->part1.h_high & 0xf) << 8; | |
726 | ||
727 | mode->vdisplay = dtd->part1.v_active; | |
728 | mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8; | |
729 | mode->vsync_start = mode->vdisplay; | |
730 | mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf; | |
171a9e96 | 731 | mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2; |
e2f0ba97 JB |
732 | mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0; |
733 | mode->vsync_end = mode->vsync_start + | |
734 | (dtd->part2.v_sync_off_width & 0xf); | |
735 | mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4; | |
736 | mode->vtotal = mode->vdisplay + dtd->part1.v_blank; | |
737 | mode->vtotal += (dtd->part1.v_high & 0xf) << 8; | |
738 | ||
739 | mode->clock = dtd->part1.clock * 10; | |
740 | ||
171a9e96 | 741 | mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); |
e2f0ba97 JB |
742 | if (dtd->part2.dtd_flags & 0x2) |
743 | mode->flags |= DRM_MODE_FLAG_PHSYNC; | |
744 | if (dtd->part2.dtd_flags & 0x4) | |
745 | mode->flags |= DRM_MODE_FLAG_PVSYNC; | |
746 | } | |
747 | ||
748 | static bool intel_sdvo_get_supp_encode(struct intel_output *output, | |
749 | struct intel_sdvo_encode *encode) | |
750 | { | |
751 | uint8_t status; | |
752 | ||
753 | intel_sdvo_write_cmd(output, SDVO_CMD_GET_SUPP_ENCODE, NULL, 0); | |
754 | status = intel_sdvo_read_response(output, encode, sizeof(*encode)); | |
755 | if (status != SDVO_CMD_STATUS_SUCCESS) { /* non-support means DVI */ | |
756 | memset(encode, 0, sizeof(*encode)); | |
757 | return false; | |
758 | } | |
759 | ||
760 | return true; | |
761 | } | |
762 | ||
763 | static bool intel_sdvo_set_encode(struct intel_output *output, uint8_t mode) | |
764 | { | |
765 | uint8_t status; | |
766 | ||
767 | intel_sdvo_write_cmd(output, SDVO_CMD_SET_ENCODE, &mode, 1); | |
768 | status = intel_sdvo_read_response(output, NULL, 0); | |
769 | ||
770 | return (status == SDVO_CMD_STATUS_SUCCESS); | |
771 | } | |
772 | ||
773 | static bool intel_sdvo_set_colorimetry(struct intel_output *output, | |
774 | uint8_t mode) | |
775 | { | |
776 | uint8_t status; | |
777 | ||
778 | intel_sdvo_write_cmd(output, SDVO_CMD_SET_COLORIMETRY, &mode, 1); | |
779 | status = intel_sdvo_read_response(output, NULL, 0); | |
780 | ||
781 | return (status == SDVO_CMD_STATUS_SUCCESS); | |
782 | } | |
783 | ||
784 | #if 0 | |
785 | static void intel_sdvo_dump_hdmi_buf(struct intel_output *output) | |
786 | { | |
787 | int i, j; | |
788 | uint8_t set_buf_index[2]; | |
789 | uint8_t av_split; | |
790 | uint8_t buf_size; | |
791 | uint8_t buf[48]; | |
792 | uint8_t *pos; | |
793 | ||
794 | intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_AV_SPLIT, NULL, 0); | |
795 | intel_sdvo_read_response(output, &av_split, 1); | |
796 | ||
797 | for (i = 0; i <= av_split; i++) { | |
798 | set_buf_index[0] = i; set_buf_index[1] = 0; | |
799 | intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_INDEX, | |
800 | set_buf_index, 2); | |
801 | intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_INFO, NULL, 0); | |
802 | intel_sdvo_read_response(output, &buf_size, 1); | |
803 | ||
804 | pos = buf; | |
805 | for (j = 0; j <= buf_size; j += 8) { | |
806 | intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_DATA, | |
807 | NULL, 0); | |
808 | intel_sdvo_read_response(output, pos, 8); | |
809 | pos += 8; | |
810 | } | |
811 | } | |
812 | } | |
813 | #endif | |
814 | ||
815 | static void intel_sdvo_set_hdmi_buf(struct intel_output *output, int index, | |
816 | uint8_t *data, int8_t size, uint8_t tx_rate) | |
817 | { | |
818 | uint8_t set_buf_index[2]; | |
819 | ||
820 | set_buf_index[0] = index; | |
821 | set_buf_index[1] = 0; | |
822 | ||
823 | intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_INDEX, set_buf_index, 2); | |
824 | ||
825 | for (; size > 0; size -= 8) { | |
826 | intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_DATA, data, 8); | |
827 | data += 8; | |
828 | } | |
829 | ||
830 | intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1); | |
831 | } | |
832 | ||
833 | static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size) | |
834 | { | |
835 | uint8_t csum = 0; | |
836 | int i; | |
837 | ||
838 | for (i = 0; i < size; i++) | |
839 | csum += data[i]; | |
840 | ||
841 | return 0x100 - csum; | |
842 | } | |
843 | ||
844 | #define DIP_TYPE_AVI 0x82 | |
845 | #define DIP_VERSION_AVI 0x2 | |
846 | #define DIP_LEN_AVI 13 | |
847 | ||
848 | struct dip_infoframe { | |
849 | uint8_t type; | |
850 | uint8_t version; | |
851 | uint8_t len; | |
852 | uint8_t checksum; | |
853 | union { | |
854 | struct { | |
855 | /* Packet Byte #1 */ | |
856 | uint8_t S:2; | |
857 | uint8_t B:2; | |
858 | uint8_t A:1; | |
859 | uint8_t Y:2; | |
860 | uint8_t rsvd1:1; | |
861 | /* Packet Byte #2 */ | |
862 | uint8_t R:4; | |
863 | uint8_t M:2; | |
864 | uint8_t C:2; | |
865 | /* Packet Byte #3 */ | |
866 | uint8_t SC:2; | |
867 | uint8_t Q:2; | |
868 | uint8_t EC:3; | |
869 | uint8_t ITC:1; | |
870 | /* Packet Byte #4 */ | |
871 | uint8_t VIC:7; | |
872 | uint8_t rsvd2:1; | |
873 | /* Packet Byte #5 */ | |
874 | uint8_t PR:4; | |
875 | uint8_t rsvd3:4; | |
876 | /* Packet Byte #6~13 */ | |
877 | uint16_t top_bar_end; | |
878 | uint16_t bottom_bar_start; | |
879 | uint16_t left_bar_end; | |
880 | uint16_t right_bar_start; | |
881 | } avi; | |
882 | struct { | |
883 | /* Packet Byte #1 */ | |
884 | uint8_t channel_count:3; | |
885 | uint8_t rsvd1:1; | |
886 | uint8_t coding_type:4; | |
887 | /* Packet Byte #2 */ | |
888 | uint8_t sample_size:2; /* SS0, SS1 */ | |
889 | uint8_t sample_frequency:3; | |
890 | uint8_t rsvd2:3; | |
891 | /* Packet Byte #3 */ | |
892 | uint8_t coding_type_private:5; | |
893 | uint8_t rsvd3:3; | |
894 | /* Packet Byte #4 */ | |
895 | uint8_t channel_allocation; | |
896 | /* Packet Byte #5 */ | |
897 | uint8_t rsvd4:3; | |
898 | uint8_t level_shift:4; | |
899 | uint8_t downmix_inhibit:1; | |
900 | } audio; | |
901 | uint8_t payload[28]; | |
902 | } __attribute__ ((packed)) u; | |
903 | } __attribute__((packed)); | |
904 | ||
905 | static void intel_sdvo_set_avi_infoframe(struct intel_output *output, | |
906 | struct drm_display_mode * mode) | |
907 | { | |
908 | struct dip_infoframe avi_if = { | |
909 | .type = DIP_TYPE_AVI, | |
910 | .version = DIP_VERSION_AVI, | |
911 | .len = DIP_LEN_AVI, | |
912 | }; | |
913 | ||
914 | avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if, | |
915 | 4 + avi_if.len); | |
916 | intel_sdvo_set_hdmi_buf(output, 1, (uint8_t *)&avi_if, 4 + avi_if.len, | |
917 | SDVO_HBUF_TX_VSYNC); | |
918 | } | |
919 | ||
7026d4ac ZW |
920 | static void intel_sdvo_set_tv_format(struct intel_output *output) |
921 | { | |
922 | struct intel_sdvo_priv *sdvo_priv = output->dev_priv; | |
923 | struct intel_sdvo_tv_format *format, unset; | |
924 | u8 status; | |
925 | ||
926 | format = &sdvo_priv->tv_format; | |
927 | memset(&unset, 0, sizeof(unset)); | |
928 | if (memcmp(format, &unset, sizeof(*format))) { | |
929 | DRM_DEBUG("%s: Choosing default TV format of NTSC-M\n", | |
930 | SDVO_NAME(sdvo_priv)); | |
931 | format->ntsc_m = 1; | |
932 | intel_sdvo_write_cmd(output, SDVO_CMD_SET_TV_FORMAT, format, | |
933 | sizeof(*format)); | |
934 | status = intel_sdvo_read_response(output, NULL, 0); | |
935 | if (status != SDVO_CMD_STATUS_SUCCESS) | |
936 | DRM_DEBUG("%s: Failed to set TV format\n", | |
937 | SDVO_NAME(sdvo_priv)); | |
938 | } | |
939 | } | |
940 | ||
e2f0ba97 JB |
941 | static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder, |
942 | struct drm_display_mode *mode, | |
943 | struct drm_display_mode *adjusted_mode) | |
944 | { | |
945 | struct intel_output *output = enc_to_intel_output(encoder); | |
946 | struct intel_sdvo_priv *dev_priv = output->dev_priv; | |
79e53945 | 947 | |
e2f0ba97 JB |
948 | if (!dev_priv->is_tv) { |
949 | /* Make the CRTC code factor in the SDVO pixel multiplier. The | |
950 | * SDVO device will be told of the multiplier during mode_set. | |
951 | */ | |
952 | adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode); | |
953 | } else { | |
954 | struct intel_sdvo_dtd output_dtd; | |
955 | bool success; | |
956 | ||
957 | /* We need to construct preferred input timings based on our | |
958 | * output timings. To do that, we have to set the output | |
959 | * timings, even though this isn't really the right place in | |
960 | * the sequence to do it. Oh well. | |
961 | */ | |
962 | ||
963 | ||
964 | /* Set output timings */ | |
965 | intel_sdvo_get_dtd_from_mode(&output_dtd, mode); | |
966 | intel_sdvo_set_target_output(output, | |
967 | dev_priv->controlled_output); | |
968 | intel_sdvo_set_output_timing(output, &output_dtd); | |
969 | ||
970 | /* Set the input timing to the screen. Assume always input 0. */ | |
971 | intel_sdvo_set_target_input(output, true, false); | |
972 | ||
973 | ||
974 | success = intel_sdvo_create_preferred_input_timing(output, | |
975 | mode->clock / 10, | |
976 | mode->hdisplay, | |
977 | mode->vdisplay); | |
978 | if (success) { | |
979 | struct intel_sdvo_dtd input_dtd; | |
79e53945 | 980 | |
e2f0ba97 JB |
981 | intel_sdvo_get_preferred_input_timing(output, |
982 | &input_dtd); | |
983 | intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); | |
984 | ||
7026d4ac ZW |
985 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
986 | ||
987 | mode->clock = adjusted_mode->clock; | |
988 | ||
989 | adjusted_mode->clock *= | |
990 | intel_sdvo_get_pixel_multiplier(mode); | |
e2f0ba97 JB |
991 | } else { |
992 | return false; | |
993 | } | |
994 | } | |
995 | return true; | |
996 | } | |
997 | ||
998 | static void intel_sdvo_mode_set(struct drm_encoder *encoder, | |
999 | struct drm_display_mode *mode, | |
1000 | struct drm_display_mode *adjusted_mode) | |
1001 | { | |
1002 | struct drm_device *dev = encoder->dev; | |
1003 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1004 | struct drm_crtc *crtc = encoder->crtc; | |
1005 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1006 | struct intel_output *output = enc_to_intel_output(encoder); | |
1007 | struct intel_sdvo_priv *sdvo_priv = output->dev_priv; | |
1008 | u32 sdvox = 0; | |
1009 | int sdvo_pixel_multiply; | |
1010 | struct intel_sdvo_in_out_map in_out; | |
1011 | struct intel_sdvo_dtd input_dtd; | |
1012 | u8 status; | |
1013 | ||
1014 | if (!mode) | |
1015 | return; | |
1016 | ||
1017 | /* First, set the input mapping for the first input to our controlled | |
1018 | * output. This is only correct if we're a single-input device, in | |
1019 | * which case the first input is the output from the appropriate SDVO | |
1020 | * channel on the motherboard. In a two-input device, the first input | |
1021 | * will be SDVOB and the second SDVOC. | |
1022 | */ | |
1023 | in_out.in0 = sdvo_priv->controlled_output; | |
1024 | in_out.in1 = 0; | |
1025 | ||
1026 | intel_sdvo_write_cmd(output, SDVO_CMD_SET_IN_OUT_MAP, | |
1027 | &in_out, sizeof(in_out)); | |
1028 | status = intel_sdvo_read_response(output, NULL, 0); | |
1029 | ||
1030 | if (sdvo_priv->is_hdmi) { | |
1031 | intel_sdvo_set_avi_infoframe(output, mode); | |
1032 | sdvox |= SDVO_AUDIO_ENABLE; | |
1033 | } | |
1034 | ||
7026d4ac ZW |
1035 | /* We have tried to get input timing in mode_fixup, and filled into |
1036 | adjusted_mode */ | |
1037 | if (sdvo_priv->is_tv) | |
1038 | intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode); | |
1039 | else | |
1040 | intel_sdvo_get_dtd_from_mode(&input_dtd, mode); | |
e2f0ba97 JB |
1041 | |
1042 | /* If it's a TV, we already set the output timing in mode_fixup. | |
1043 | * Otherwise, the output timing is equal to the input timing. | |
1044 | */ | |
1045 | if (!sdvo_priv->is_tv) { | |
1046 | /* Set the output timing to the screen */ | |
1047 | intel_sdvo_set_target_output(output, | |
1048 | sdvo_priv->controlled_output); | |
1049 | intel_sdvo_set_output_timing(output, &input_dtd); | |
1050 | } | |
79e53945 JB |
1051 | |
1052 | /* Set the input timing to the screen. Assume always input 0. */ | |
e2f0ba97 | 1053 | intel_sdvo_set_target_input(output, true, false); |
79e53945 | 1054 | |
7026d4ac ZW |
1055 | if (sdvo_priv->is_tv) |
1056 | intel_sdvo_set_tv_format(output); | |
1057 | ||
e2f0ba97 | 1058 | /* We would like to use intel_sdvo_create_preferred_input_timing() to |
79e53945 JB |
1059 | * provide the device with a timing it can support, if it supports that |
1060 | * feature. However, presumably we would need to adjust the CRTC to | |
1061 | * output the preferred timing, and we don't support that currently. | |
1062 | */ | |
e2f0ba97 JB |
1063 | #if 0 |
1064 | success = intel_sdvo_create_preferred_input_timing(output, clock, | |
1065 | width, height); | |
1066 | if (success) { | |
1067 | struct intel_sdvo_dtd *input_dtd; | |
1068 | ||
1069 | intel_sdvo_get_preferred_input_timing(output, &input_dtd); | |
1070 | intel_sdvo_set_input_timing(output, &input_dtd); | |
1071 | } | |
1072 | #else | |
1073 | intel_sdvo_set_input_timing(output, &input_dtd); | |
1074 | #endif | |
79e53945 JB |
1075 | |
1076 | switch (intel_sdvo_get_pixel_multiplier(mode)) { | |
1077 | case 1: | |
e2f0ba97 | 1078 | intel_sdvo_set_clock_rate_mult(output, |
79e53945 JB |
1079 | SDVO_CLOCK_RATE_MULT_1X); |
1080 | break; | |
1081 | case 2: | |
e2f0ba97 | 1082 | intel_sdvo_set_clock_rate_mult(output, |
79e53945 JB |
1083 | SDVO_CLOCK_RATE_MULT_2X); |
1084 | break; | |
1085 | case 4: | |
e2f0ba97 | 1086 | intel_sdvo_set_clock_rate_mult(output, |
79e53945 JB |
1087 | SDVO_CLOCK_RATE_MULT_4X); |
1088 | break; | |
1089 | } | |
1090 | ||
1091 | /* Set the SDVO control regs. */ | |
e2f0ba97 JB |
1092 | if (IS_I965G(dev)) { |
1093 | sdvox |= SDVO_BORDER_ENABLE | | |
1094 | SDVO_VSYNC_ACTIVE_HIGH | | |
1095 | SDVO_HSYNC_ACTIVE_HIGH; | |
1096 | } else { | |
1097 | sdvox |= I915_READ(sdvo_priv->output_device); | |
1098 | switch (sdvo_priv->output_device) { | |
1099 | case SDVOB: | |
1100 | sdvox &= SDVOB_PRESERVE_MASK; | |
1101 | break; | |
1102 | case SDVOC: | |
1103 | sdvox &= SDVOC_PRESERVE_MASK; | |
1104 | break; | |
1105 | } | |
1106 | sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; | |
1107 | } | |
79e53945 JB |
1108 | if (intel_crtc->pipe == 1) |
1109 | sdvox |= SDVO_PIPE_B_SELECT; | |
1110 | ||
1111 | sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode); | |
1112 | if (IS_I965G(dev)) { | |
e2f0ba97 JB |
1113 | /* done in crtc_mode_set as the dpll_md reg must be written early */ |
1114 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { | |
1115 | /* done in crtc_mode_set as it lives inside the dpll register */ | |
79e53945 JB |
1116 | } else { |
1117 | sdvox |= (sdvo_pixel_multiply - 1) << SDVO_PORT_MULTIPLY_SHIFT; | |
1118 | } | |
1119 | ||
e2f0ba97 | 1120 | intel_sdvo_write_sdvox(output, sdvox); |
79e53945 JB |
1121 | } |
1122 | ||
1123 | static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode) | |
1124 | { | |
1125 | struct drm_device *dev = encoder->dev; | |
1126 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1127 | struct intel_output *intel_output = enc_to_intel_output(encoder); | |
1128 | struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; | |
1129 | u32 temp; | |
1130 | ||
1131 | if (mode != DRM_MODE_DPMS_ON) { | |
1132 | intel_sdvo_set_active_outputs(intel_output, 0); | |
1133 | if (0) | |
1134 | intel_sdvo_set_encoder_power_state(intel_output, mode); | |
1135 | ||
1136 | if (mode == DRM_MODE_DPMS_OFF) { | |
1137 | temp = I915_READ(sdvo_priv->output_device); | |
1138 | if ((temp & SDVO_ENABLE) != 0) { | |
1139 | intel_sdvo_write_sdvox(intel_output, temp & ~SDVO_ENABLE); | |
1140 | } | |
1141 | } | |
1142 | } else { | |
1143 | bool input1, input2; | |
1144 | int i; | |
1145 | u8 status; | |
1146 | ||
1147 | temp = I915_READ(sdvo_priv->output_device); | |
1148 | if ((temp & SDVO_ENABLE) == 0) | |
1149 | intel_sdvo_write_sdvox(intel_output, temp | SDVO_ENABLE); | |
1150 | for (i = 0; i < 2; i++) | |
1151 | intel_wait_for_vblank(dev); | |
1152 | ||
1153 | status = intel_sdvo_get_trained_inputs(intel_output, &input1, | |
1154 | &input2); | |
1155 | ||
1156 | ||
1157 | /* Warn if the device reported failure to sync. | |
1158 | * A lot of SDVO devices fail to notify of sync, but it's | |
1159 | * a given it the status is a success, we succeeded. | |
1160 | */ | |
1161 | if (status == SDVO_CMD_STATUS_SUCCESS && !input1) { | |
1162 | DRM_DEBUG("First %s output reported failure to sync\n", | |
1163 | SDVO_NAME(sdvo_priv)); | |
1164 | } | |
1165 | ||
1166 | if (0) | |
1167 | intel_sdvo_set_encoder_power_state(intel_output, mode); | |
e2f0ba97 | 1168 | intel_sdvo_set_active_outputs(intel_output, sdvo_priv->controlled_output); |
79e53945 JB |
1169 | } |
1170 | return; | |
1171 | } | |
1172 | ||
1173 | static void intel_sdvo_save(struct drm_connector *connector) | |
1174 | { | |
1175 | struct drm_device *dev = connector->dev; | |
1176 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1177 | struct intel_output *intel_output = to_intel_output(connector); | |
1178 | struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; | |
1179 | int o; | |
1180 | ||
1181 | sdvo_priv->save_sdvo_mult = intel_sdvo_get_clock_rate_mult(intel_output); | |
1182 | intel_sdvo_get_active_outputs(intel_output, &sdvo_priv->save_active_outputs); | |
1183 | ||
1184 | if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) { | |
1185 | intel_sdvo_set_target_input(intel_output, true, false); | |
1186 | intel_sdvo_get_input_timing(intel_output, | |
1187 | &sdvo_priv->save_input_dtd_1); | |
1188 | } | |
1189 | ||
1190 | if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) { | |
1191 | intel_sdvo_set_target_input(intel_output, false, true); | |
1192 | intel_sdvo_get_input_timing(intel_output, | |
1193 | &sdvo_priv->save_input_dtd_2); | |
1194 | } | |
1195 | ||
1196 | for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++) | |
1197 | { | |
1198 | u16 this_output = (1 << o); | |
1199 | if (sdvo_priv->caps.output_flags & this_output) | |
1200 | { | |
1201 | intel_sdvo_set_target_output(intel_output, this_output); | |
1202 | intel_sdvo_get_output_timing(intel_output, | |
1203 | &sdvo_priv->save_output_dtd[o]); | |
1204 | } | |
1205 | } | |
e2f0ba97 JB |
1206 | if (sdvo_priv->is_tv) { |
1207 | /* XXX: Save TV format/enhancements. */ | |
1208 | } | |
79e53945 JB |
1209 | |
1210 | sdvo_priv->save_SDVOX = I915_READ(sdvo_priv->output_device); | |
1211 | } | |
1212 | ||
1213 | static void intel_sdvo_restore(struct drm_connector *connector) | |
1214 | { | |
1215 | struct drm_device *dev = connector->dev; | |
79e53945 JB |
1216 | struct intel_output *intel_output = to_intel_output(connector); |
1217 | struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; | |
1218 | int o; | |
1219 | int i; | |
1220 | bool input1, input2; | |
1221 | u8 status; | |
1222 | ||
1223 | intel_sdvo_set_active_outputs(intel_output, 0); | |
1224 | ||
1225 | for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++) | |
1226 | { | |
1227 | u16 this_output = (1 << o); | |
1228 | if (sdvo_priv->caps.output_flags & this_output) { | |
1229 | intel_sdvo_set_target_output(intel_output, this_output); | |
1230 | intel_sdvo_set_output_timing(intel_output, &sdvo_priv->save_output_dtd[o]); | |
1231 | } | |
1232 | } | |
1233 | ||
1234 | if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) { | |
1235 | intel_sdvo_set_target_input(intel_output, true, false); | |
1236 | intel_sdvo_set_input_timing(intel_output, &sdvo_priv->save_input_dtd_1); | |
1237 | } | |
1238 | ||
1239 | if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) { | |
1240 | intel_sdvo_set_target_input(intel_output, false, true); | |
1241 | intel_sdvo_set_input_timing(intel_output, &sdvo_priv->save_input_dtd_2); | |
1242 | } | |
1243 | ||
1244 | intel_sdvo_set_clock_rate_mult(intel_output, sdvo_priv->save_sdvo_mult); | |
1245 | ||
e2f0ba97 JB |
1246 | if (sdvo_priv->is_tv) { |
1247 | /* XXX: Restore TV format/enhancements. */ | |
1248 | } | |
1249 | ||
1250 | intel_sdvo_write_sdvox(intel_output, sdvo_priv->save_SDVOX); | |
79e53945 JB |
1251 | |
1252 | if (sdvo_priv->save_SDVOX & SDVO_ENABLE) | |
1253 | { | |
1254 | for (i = 0; i < 2; i++) | |
1255 | intel_wait_for_vblank(dev); | |
1256 | status = intel_sdvo_get_trained_inputs(intel_output, &input1, &input2); | |
1257 | if (status == SDVO_CMD_STATUS_SUCCESS && !input1) | |
1258 | DRM_DEBUG("First %s output reported failure to sync\n", | |
1259 | SDVO_NAME(sdvo_priv)); | |
1260 | } | |
1261 | ||
1262 | intel_sdvo_set_active_outputs(intel_output, sdvo_priv->save_active_outputs); | |
1263 | } | |
1264 | ||
1265 | static int intel_sdvo_mode_valid(struct drm_connector *connector, | |
1266 | struct drm_display_mode *mode) | |
1267 | { | |
1268 | struct intel_output *intel_output = to_intel_output(connector); | |
1269 | struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; | |
1270 | ||
1271 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
1272 | return MODE_NO_DBLESCAN; | |
1273 | ||
1274 | if (sdvo_priv->pixel_clock_min > mode->clock) | |
1275 | return MODE_CLOCK_LOW; | |
1276 | ||
1277 | if (sdvo_priv->pixel_clock_max < mode->clock) | |
1278 | return MODE_CLOCK_HIGH; | |
1279 | ||
1280 | return MODE_OK; | |
1281 | } | |
1282 | ||
1283 | static bool intel_sdvo_get_capabilities(struct intel_output *intel_output, struct intel_sdvo_caps *caps) | |
1284 | { | |
1285 | u8 status; | |
1286 | ||
1287 | intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_DEVICE_CAPS, NULL, 0); | |
1288 | status = intel_sdvo_read_response(intel_output, caps, sizeof(*caps)); | |
1289 | if (status != SDVO_CMD_STATUS_SUCCESS) | |
1290 | return false; | |
1291 | ||
1292 | return true; | |
1293 | } | |
1294 | ||
1295 | struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB) | |
1296 | { | |
1297 | struct drm_connector *connector = NULL; | |
1298 | struct intel_output *iout = NULL; | |
1299 | struct intel_sdvo_priv *sdvo; | |
1300 | ||
1301 | /* find the sdvo connector */ | |
1302 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1303 | iout = to_intel_output(connector); | |
1304 | ||
1305 | if (iout->type != INTEL_OUTPUT_SDVO) | |
1306 | continue; | |
1307 | ||
1308 | sdvo = iout->dev_priv; | |
1309 | ||
1310 | if (sdvo->output_device == SDVOB && sdvoB) | |
1311 | return connector; | |
1312 | ||
1313 | if (sdvo->output_device == SDVOC && !sdvoB) | |
1314 | return connector; | |
1315 | ||
1316 | } | |
1317 | ||
1318 | return NULL; | |
1319 | } | |
1320 | ||
1321 | int intel_sdvo_supports_hotplug(struct drm_connector *connector) | |
1322 | { | |
1323 | u8 response[2]; | |
1324 | u8 status; | |
1325 | struct intel_output *intel_output; | |
1326 | DRM_DEBUG("\n"); | |
1327 | ||
1328 | if (!connector) | |
1329 | return 0; | |
1330 | ||
1331 | intel_output = to_intel_output(connector); | |
1332 | ||
1333 | intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0); | |
1334 | status = intel_sdvo_read_response(intel_output, &response, 2); | |
1335 | ||
1336 | if (response[0] !=0) | |
1337 | return 1; | |
1338 | ||
1339 | return 0; | |
1340 | } | |
1341 | ||
1342 | void intel_sdvo_set_hotplug(struct drm_connector *connector, int on) | |
1343 | { | |
1344 | u8 response[2]; | |
1345 | u8 status; | |
1346 | struct intel_output *intel_output = to_intel_output(connector); | |
1347 | ||
1348 | intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0); | |
1349 | intel_sdvo_read_response(intel_output, &response, 2); | |
1350 | ||
1351 | if (on) { | |
1352 | intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0); | |
1353 | status = intel_sdvo_read_response(intel_output, &response, 2); | |
1354 | ||
1355 | intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2); | |
1356 | } else { | |
1357 | response[0] = 0; | |
1358 | response[1] = 0; | |
1359 | intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2); | |
1360 | } | |
1361 | ||
1362 | intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0); | |
1363 | intel_sdvo_read_response(intel_output, &response, 2); | |
1364 | } | |
1365 | ||
9dff6af8 ML |
1366 | static void |
1367 | intel_sdvo_hdmi_sink_detect(struct drm_connector *connector) | |
1368 | { | |
1369 | struct intel_output *intel_output = to_intel_output(connector); | |
1370 | struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; | |
1371 | struct edid *edid = NULL; | |
1372 | ||
1373 | intel_sdvo_set_control_bus_switch(intel_output, sdvo_priv->ddc_bus); | |
1374 | edid = drm_get_edid(&intel_output->base, | |
f9c10a9b | 1375 | intel_output->ddc_bus); |
9dff6af8 ML |
1376 | if (edid != NULL) { |
1377 | sdvo_priv->is_hdmi = drm_detect_hdmi_monitor(edid); | |
1378 | kfree(edid); | |
1379 | intel_output->base.display_info.raw_edid = NULL; | |
1380 | } | |
1381 | } | |
1382 | ||
79e53945 JB |
1383 | static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector) |
1384 | { | |
1385 | u8 response[2]; | |
1386 | u8 status; | |
1387 | struct intel_output *intel_output = to_intel_output(connector); | |
1388 | ||
1389 | intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0); | |
1390 | status = intel_sdvo_read_response(intel_output, &response, 2); | |
1391 | ||
1392 | DRM_DEBUG("SDVO response %d %d\n", response[0], response[1]); | |
e2f0ba97 JB |
1393 | |
1394 | if (status != SDVO_CMD_STATUS_SUCCESS) | |
1395 | return connector_status_unknown; | |
1396 | ||
9dff6af8 ML |
1397 | if ((response[0] != 0) || (response[1] != 0)) { |
1398 | intel_sdvo_hdmi_sink_detect(connector); | |
79e53945 | 1399 | return connector_status_connected; |
9dff6af8 | 1400 | } else |
79e53945 JB |
1401 | return connector_status_disconnected; |
1402 | } | |
1403 | ||
e2f0ba97 | 1404 | static void intel_sdvo_get_ddc_modes(struct drm_connector *connector) |
79e53945 JB |
1405 | { |
1406 | struct intel_output *intel_output = to_intel_output(connector); | |
1407 | ||
1408 | /* set the bus switch and get the modes */ | |
79e53945 JB |
1409 | intel_ddc_get_modes(intel_output); |
1410 | ||
e2f0ba97 JB |
1411 | #if 0 |
1412 | struct drm_device *dev = encoder->dev; | |
1413 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1414 | /* Mac mini hack. On this device, I get DDC through the analog, which | |
1415 | * load-detects as disconnected. I fail to DDC through the SDVO DDC, | |
1416 | * but it does load-detect as connected. So, just steal the DDC bits | |
1417 | * from analog when we fail at finding it the right way. | |
1418 | */ | |
1419 | crt = xf86_config->output[0]; | |
1420 | intel_output = crt->driver_private; | |
1421 | if (intel_output->type == I830_OUTPUT_ANALOG && | |
1422 | crt->funcs->detect(crt) == XF86OutputStatusDisconnected) { | |
1423 | I830I2CInit(pScrn, &intel_output->pDDCBus, GPIOA, "CRTDDC_A"); | |
1424 | edid_mon = xf86OutputGetEDID(crt, intel_output->pDDCBus); | |
1425 | xf86DestroyI2CBusRec(intel_output->pDDCBus, true, true); | |
1426 | } | |
1427 | if (edid_mon) { | |
1428 | xf86OutputSetEDID(output, edid_mon); | |
1429 | modes = xf86OutputGetEDIDModes(output); | |
1430 | } | |
1431 | #endif | |
1432 | } | |
1433 | ||
1434 | /** | |
1435 | * This function checks the current TV format, and chooses a default if | |
1436 | * it hasn't been set. | |
1437 | */ | |
1438 | static void | |
1439 | intel_sdvo_check_tv_format(struct intel_output *output) | |
1440 | { | |
1441 | struct intel_sdvo_priv *dev_priv = output->dev_priv; | |
7026d4ac | 1442 | struct intel_sdvo_tv_format format; |
e2f0ba97 JB |
1443 | uint8_t status; |
1444 | ||
1445 | intel_sdvo_write_cmd(output, SDVO_CMD_GET_TV_FORMAT, NULL, 0); | |
1446 | status = intel_sdvo_read_response(output, &format, sizeof(format)); | |
1447 | if (status != SDVO_CMD_STATUS_SUCCESS) | |
1448 | return; | |
1449 | ||
7026d4ac | 1450 | memcpy(&dev_priv->tv_format, &format, sizeof(format)); |
e2f0ba97 JB |
1451 | } |
1452 | ||
1453 | /* | |
1454 | * Set of SDVO TV modes. | |
1455 | * Note! This is in reply order (see loop in get_tv_modes). | |
1456 | * XXX: all 60Hz refresh? | |
1457 | */ | |
1458 | struct drm_display_mode sdvo_tv_modes[] = { | |
7026d4ac ZW |
1459 | { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384, |
1460 | 416, 0, 200, 201, 232, 233, 0, | |
e2f0ba97 | 1461 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1462 | { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384, |
1463 | 416, 0, 240, 241, 272, 273, 0, | |
e2f0ba97 | 1464 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1465 | { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464, |
1466 | 496, 0, 300, 301, 332, 333, 0, | |
e2f0ba97 | 1467 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1468 | { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704, |
1469 | 736, 0, 350, 351, 382, 383, 0, | |
e2f0ba97 | 1470 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1471 | { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704, |
1472 | 736, 0, 400, 401, 432, 433, 0, | |
e2f0ba97 | 1473 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1474 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704, |
1475 | 736, 0, 480, 481, 512, 513, 0, | |
e2f0ba97 | 1476 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1477 | { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768, |
1478 | 800, 0, 480, 481, 512, 513, 0, | |
e2f0ba97 | 1479 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1480 | { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768, |
1481 | 800, 0, 576, 577, 608, 609, 0, | |
e2f0ba97 | 1482 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1483 | { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784, |
1484 | 816, 0, 350, 351, 382, 383, 0, | |
e2f0ba97 | 1485 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1486 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784, |
1487 | 816, 0, 400, 401, 432, 433, 0, | |
e2f0ba97 | 1488 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1489 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784, |
1490 | 816, 0, 480, 481, 512, 513, 0, | |
e2f0ba97 | 1491 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1492 | { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784, |
1493 | 816, 0, 540, 541, 572, 573, 0, | |
e2f0ba97 | 1494 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1495 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784, |
1496 | 816, 0, 576, 577, 608, 609, 0, | |
e2f0ba97 | 1497 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1498 | { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832, |
1499 | 864, 0, 576, 577, 608, 609, 0, | |
e2f0ba97 | 1500 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1501 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864, |
1502 | 896, 0, 600, 601, 632, 633, 0, | |
e2f0ba97 | 1503 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1504 | { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896, |
1505 | 928, 0, 624, 625, 656, 657, 0, | |
e2f0ba97 | 1506 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1507 | { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984, |
1508 | 1016, 0, 766, 767, 798, 799, 0, | |
e2f0ba97 | 1509 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1510 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088, |
1511 | 1120, 0, 768, 769, 800, 801, 0, | |
e2f0ba97 | 1512 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1513 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344, |
1514 | 1376, 0, 1024, 1025, 1056, 1057, 0, | |
e2f0ba97 JB |
1515 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
1516 | }; | |
1517 | ||
1518 | static void intel_sdvo_get_tv_modes(struct drm_connector *connector) | |
1519 | { | |
1520 | struct intel_output *output = to_intel_output(connector); | |
7026d4ac ZW |
1521 | struct intel_sdvo_priv *sdvo_priv = output->dev_priv; |
1522 | struct intel_sdvo_sdtv_resolution_request tv_res; | |
e2f0ba97 JB |
1523 | uint32_t reply = 0; |
1524 | uint8_t status; | |
1525 | int i = 0; | |
1526 | ||
1527 | intel_sdvo_check_tv_format(output); | |
1528 | ||
1529 | /* Read the list of supported input resolutions for the selected TV | |
1530 | * format. | |
1531 | */ | |
7026d4ac ZW |
1532 | memset(&tv_res, 0, sizeof(tv_res)); |
1533 | memcpy(&tv_res, &sdvo_priv->tv_format, sizeof(tv_res)); | |
e2f0ba97 | 1534 | intel_sdvo_write_cmd(output, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, |
7026d4ac | 1535 | &tv_res, sizeof(tv_res)); |
e2f0ba97 JB |
1536 | status = intel_sdvo_read_response(output, &reply, 3); |
1537 | if (status != SDVO_CMD_STATUS_SUCCESS) | |
1538 | return; | |
1539 | ||
1540 | for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) | |
7026d4ac ZW |
1541 | if (reply & (1 << i)) { |
1542 | struct drm_display_mode *nmode; | |
1543 | nmode = drm_mode_duplicate(connector->dev, | |
1544 | &sdvo_tv_modes[i]); | |
1545 | if (nmode) | |
1546 | drm_mode_probed_add(connector, nmode); | |
1547 | } | |
e2f0ba97 JB |
1548 | } |
1549 | ||
7086c87f ML |
1550 | static void intel_sdvo_get_lvds_modes(struct drm_connector *connector) |
1551 | { | |
1552 | struct intel_output *intel_output = to_intel_output(connector); | |
1553 | struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; | |
1554 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
1555 | ||
1556 | /* | |
1557 | * Attempt to get the mode list from DDC. | |
1558 | * Assume that the preferred modes are | |
1559 | * arranged in priority order. | |
1560 | */ | |
1561 | /* set the bus switch and get the modes */ | |
1562 | intel_sdvo_set_control_bus_switch(intel_output, sdvo_priv->ddc_bus); | |
1563 | intel_ddc_get_modes(intel_output); | |
1564 | if (list_empty(&connector->probed_modes) == false) | |
1565 | return; | |
1566 | ||
1567 | /* Fetch modes from VBT */ | |
1568 | if (dev_priv->sdvo_lvds_vbt_mode != NULL) { | |
1569 | struct drm_display_mode *newmode; | |
1570 | newmode = drm_mode_duplicate(connector->dev, | |
1571 | dev_priv->sdvo_lvds_vbt_mode); | |
1572 | if (newmode != NULL) { | |
1573 | /* Guarantee the mode is preferred */ | |
1574 | newmode->type = (DRM_MODE_TYPE_PREFERRED | | |
1575 | DRM_MODE_TYPE_DRIVER); | |
1576 | drm_mode_probed_add(connector, newmode); | |
1577 | } | |
1578 | } | |
1579 | } | |
1580 | ||
e2f0ba97 JB |
1581 | static int intel_sdvo_get_modes(struct drm_connector *connector) |
1582 | { | |
1583 | struct intel_output *output = to_intel_output(connector); | |
1584 | struct intel_sdvo_priv *sdvo_priv = output->dev_priv; | |
1585 | ||
1586 | if (sdvo_priv->is_tv) | |
1587 | intel_sdvo_get_tv_modes(connector); | |
7086c87f ML |
1588 | else if (sdvo_priv->is_lvds == true) |
1589 | intel_sdvo_get_lvds_modes(connector); | |
e2f0ba97 JB |
1590 | else |
1591 | intel_sdvo_get_ddc_modes(connector); | |
1592 | ||
79e53945 JB |
1593 | if (list_empty(&connector->probed_modes)) |
1594 | return 0; | |
1595 | return 1; | |
1596 | } | |
1597 | ||
1598 | static void intel_sdvo_destroy(struct drm_connector *connector) | |
1599 | { | |
1600 | struct intel_output *intel_output = to_intel_output(connector); | |
1601 | ||
1602 | if (intel_output->i2c_bus) | |
1603 | intel_i2c_destroy(intel_output->i2c_bus); | |
619ac3b7 ML |
1604 | if (intel_output->ddc_bus) |
1605 | intel_i2c_destroy(intel_output->ddc_bus); | |
1606 | ||
79e53945 JB |
1607 | drm_sysfs_connector_remove(connector); |
1608 | drm_connector_cleanup(connector); | |
1609 | kfree(intel_output); | |
1610 | } | |
1611 | ||
1612 | static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = { | |
1613 | .dpms = intel_sdvo_dpms, | |
1614 | .mode_fixup = intel_sdvo_mode_fixup, | |
1615 | .prepare = intel_encoder_prepare, | |
1616 | .mode_set = intel_sdvo_mode_set, | |
1617 | .commit = intel_encoder_commit, | |
1618 | }; | |
1619 | ||
1620 | static const struct drm_connector_funcs intel_sdvo_connector_funcs = { | |
c9fb15f6 | 1621 | .dpms = drm_helper_connector_dpms, |
79e53945 JB |
1622 | .save = intel_sdvo_save, |
1623 | .restore = intel_sdvo_restore, | |
1624 | .detect = intel_sdvo_detect, | |
1625 | .fill_modes = drm_helper_probe_single_connector_modes, | |
1626 | .destroy = intel_sdvo_destroy, | |
1627 | }; | |
1628 | ||
1629 | static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = { | |
1630 | .get_modes = intel_sdvo_get_modes, | |
1631 | .mode_valid = intel_sdvo_mode_valid, | |
1632 | .best_encoder = intel_best_encoder, | |
1633 | }; | |
1634 | ||
b358d0a6 | 1635 | static void intel_sdvo_enc_destroy(struct drm_encoder *encoder) |
79e53945 JB |
1636 | { |
1637 | drm_encoder_cleanup(encoder); | |
1638 | } | |
1639 | ||
1640 | static const struct drm_encoder_funcs intel_sdvo_enc_funcs = { | |
1641 | .destroy = intel_sdvo_enc_destroy, | |
1642 | }; | |
1643 | ||
1644 | ||
e2f0ba97 JB |
1645 | /** |
1646 | * Choose the appropriate DDC bus for control bus switch command for this | |
1647 | * SDVO output based on the controlled output. | |
1648 | * | |
1649 | * DDC bus number assignment is in a priority order of RGB outputs, then TMDS | |
1650 | * outputs, then LVDS outputs. | |
1651 | */ | |
1652 | static void | |
1653 | intel_sdvo_select_ddc_bus(struct intel_sdvo_priv *dev_priv) | |
1654 | { | |
1655 | uint16_t mask = 0; | |
1656 | unsigned int num_bits; | |
1657 | ||
1658 | /* Make a mask of outputs less than or equal to our own priority in the | |
1659 | * list. | |
1660 | */ | |
1661 | switch (dev_priv->controlled_output) { | |
1662 | case SDVO_OUTPUT_LVDS1: | |
1663 | mask |= SDVO_OUTPUT_LVDS1; | |
1664 | case SDVO_OUTPUT_LVDS0: | |
1665 | mask |= SDVO_OUTPUT_LVDS0; | |
1666 | case SDVO_OUTPUT_TMDS1: | |
1667 | mask |= SDVO_OUTPUT_TMDS1; | |
1668 | case SDVO_OUTPUT_TMDS0: | |
1669 | mask |= SDVO_OUTPUT_TMDS0; | |
1670 | case SDVO_OUTPUT_RGB1: | |
1671 | mask |= SDVO_OUTPUT_RGB1; | |
1672 | case SDVO_OUTPUT_RGB0: | |
1673 | mask |= SDVO_OUTPUT_RGB0; | |
1674 | break; | |
1675 | } | |
1676 | ||
1677 | /* Count bits to find what number we are in the priority list. */ | |
1678 | mask &= dev_priv->caps.output_flags; | |
1679 | num_bits = hweight16(mask); | |
1680 | if (num_bits > 3) { | |
1681 | /* if more than 3 outputs, default to DDC bus 3 for now */ | |
1682 | num_bits = 3; | |
1683 | } | |
1684 | ||
1685 | /* Corresponds to SDVO_CONTROL_BUS_DDCx */ | |
1686 | dev_priv->ddc_bus = 1 << num_bits; | |
1687 | } | |
1688 | ||
1689 | static bool | |
1690 | intel_sdvo_get_digital_encoding_mode(struct intel_output *output) | |
1691 | { | |
1692 | struct intel_sdvo_priv *sdvo_priv = output->dev_priv; | |
1693 | uint8_t status; | |
1694 | ||
1695 | intel_sdvo_set_target_output(output, sdvo_priv->controlled_output); | |
1696 | ||
1697 | intel_sdvo_write_cmd(output, SDVO_CMD_GET_ENCODE, NULL, 0); | |
1698 | status = intel_sdvo_read_response(output, &sdvo_priv->is_hdmi, 1); | |
1699 | if (status != SDVO_CMD_STATUS_SUCCESS) | |
1700 | return false; | |
1701 | return true; | |
1702 | } | |
1703 | ||
619ac3b7 ML |
1704 | static struct intel_output * |
1705 | intel_sdvo_chan_to_intel_output(struct intel_i2c_chan *chan) | |
1706 | { | |
1707 | struct drm_device *dev = chan->drm_dev; | |
1708 | struct drm_connector *connector; | |
1709 | struct intel_output *intel_output = NULL; | |
1710 | ||
1711 | list_for_each_entry(connector, | |
1712 | &dev->mode_config.connector_list, head) { | |
f9c10a9b | 1713 | if (to_intel_output(connector)->ddc_bus == &chan->adapter) { |
619ac3b7 ML |
1714 | intel_output = to_intel_output(connector); |
1715 | break; | |
1716 | } | |
1717 | } | |
1718 | return intel_output; | |
1719 | } | |
1720 | ||
1721 | static int intel_sdvo_master_xfer(struct i2c_adapter *i2c_adap, | |
1722 | struct i2c_msg msgs[], int num) | |
1723 | { | |
1724 | struct intel_output *intel_output; | |
1725 | struct intel_sdvo_priv *sdvo_priv; | |
1726 | struct i2c_algo_bit_data *algo_data; | |
f9c10a9b | 1727 | const struct i2c_algorithm *algo; |
619ac3b7 ML |
1728 | |
1729 | algo_data = (struct i2c_algo_bit_data *)i2c_adap->algo_data; | |
1730 | intel_output = | |
1731 | intel_sdvo_chan_to_intel_output( | |
1732 | (struct intel_i2c_chan *)(algo_data->data)); | |
1733 | if (intel_output == NULL) | |
1734 | return -EINVAL; | |
1735 | ||
1736 | sdvo_priv = intel_output->dev_priv; | |
f9c10a9b | 1737 | algo = intel_output->i2c_bus->algo; |
619ac3b7 ML |
1738 | |
1739 | intel_sdvo_set_control_bus_switch(intel_output, sdvo_priv->ddc_bus); | |
1740 | return algo->master_xfer(i2c_adap, msgs, num); | |
1741 | } | |
1742 | ||
1743 | static struct i2c_algorithm intel_sdvo_i2c_bit_algo = { | |
1744 | .master_xfer = intel_sdvo_master_xfer, | |
1745 | }; | |
1746 | ||
714605e4 | 1747 | static u8 |
1748 | intel_sdvo_get_slave_addr(struct drm_device *dev, int output_device) | |
1749 | { | |
1750 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1751 | struct sdvo_device_mapping *my_mapping, *other_mapping; | |
1752 | ||
1753 | if (output_device == SDVOB) { | |
1754 | my_mapping = &dev_priv->sdvo_mappings[0]; | |
1755 | other_mapping = &dev_priv->sdvo_mappings[1]; | |
1756 | } else { | |
1757 | my_mapping = &dev_priv->sdvo_mappings[1]; | |
1758 | other_mapping = &dev_priv->sdvo_mappings[0]; | |
1759 | } | |
1760 | ||
1761 | /* If the BIOS described our SDVO device, take advantage of it. */ | |
1762 | if (my_mapping->slave_addr) | |
1763 | return my_mapping->slave_addr; | |
1764 | ||
1765 | /* If the BIOS only described a different SDVO device, use the | |
1766 | * address that it isn't using. | |
1767 | */ | |
1768 | if (other_mapping->slave_addr) { | |
1769 | if (other_mapping->slave_addr == 0x70) | |
1770 | return 0x72; | |
1771 | else | |
1772 | return 0x70; | |
1773 | } | |
1774 | ||
1775 | /* No SDVO device info is found for another DVO port, | |
1776 | * so use mapping assumption we had before BIOS parsing. | |
1777 | */ | |
1778 | if (output_device == SDVOB) | |
1779 | return 0x70; | |
1780 | else | |
1781 | return 0x72; | |
1782 | } | |
1783 | ||
7d57382e | 1784 | bool intel_sdvo_init(struct drm_device *dev, int output_device) |
79e53945 JB |
1785 | { |
1786 | struct drm_connector *connector; | |
1787 | struct intel_output *intel_output; | |
1788 | struct intel_sdvo_priv *sdvo_priv; | |
f9c10a9b KP |
1789 | struct i2c_adapter *i2cbus = NULL; |
1790 | struct i2c_adapter *ddcbus = NULL; | |
1791 | ||
79e53945 JB |
1792 | int connector_type; |
1793 | u8 ch[0x40]; | |
1794 | int i; | |
f9c10a9b | 1795 | int encoder_type; |
714605e4 | 1796 | u8 slave_addr; |
79e53945 JB |
1797 | |
1798 | intel_output = kcalloc(sizeof(struct intel_output)+sizeof(struct intel_sdvo_priv), 1, GFP_KERNEL); | |
1799 | if (!intel_output) { | |
7d57382e | 1800 | return false; |
79e53945 JB |
1801 | } |
1802 | ||
79e53945 JB |
1803 | sdvo_priv = (struct intel_sdvo_priv *)(intel_output + 1); |
1804 | intel_output->type = INTEL_OUTPUT_SDVO; | |
1805 | ||
79e53945 | 1806 | /* setup the DDC bus. */ |
f9c10a9b | 1807 | if (output_device == SDVOB) { |
79e53945 | 1808 | i2cbus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOB"); |
f9c10a9b KP |
1809 | slave_addr = 0x38; |
1810 | } else { | |
79e53945 | 1811 | i2cbus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOC"); |
f9c10a9b KP |
1812 | slave_addr = 0x39; |
1813 | } | |
1814 | ||
79e53945 | 1815 | if (!i2cbus) |
ad5b2a6d | 1816 | goto err_inteloutput; |
79e53945 | 1817 | |
714605e4 | 1818 | slave_addr = intel_sdvo_get_slave_addr(dev, output_device); |
79e53945 | 1819 | sdvo_priv->i2c_bus = i2cbus; |
f9c10a9b | 1820 | sdvo_priv->slave_addr = slave_addr; |
79e53945 | 1821 | |
79e53945 | 1822 | sdvo_priv->output_device = output_device; |
f9c10a9b | 1823 | intel_output->i2c_bus = sdvo_priv->i2c_bus; |
79e53945 JB |
1824 | intel_output->dev_priv = sdvo_priv; |
1825 | ||
79e53945 JB |
1826 | /* Read the regs to test if we can talk to the device */ |
1827 | for (i = 0; i < 0x40; i++) { | |
1828 | if (!intel_sdvo_read_byte(intel_output, i, &ch[i])) { | |
342dc382 | 1829 | DRM_DEBUG_KMS(I915_SDVO, |
1830 | "No SDVO device found on SDVO%c\n", | |
1831 | output_device == SDVOB ? 'B' : 'C'); | |
79e53945 JB |
1832 | goto err_i2c; |
1833 | } | |
1834 | } | |
1835 | ||
619ac3b7 ML |
1836 | /* setup the DDC bus. */ |
1837 | if (output_device == SDVOB) | |
1838 | ddcbus = intel_i2c_create(dev, GPIOE, "SDVOB DDC BUS"); | |
1839 | else | |
1840 | ddcbus = intel_i2c_create(dev, GPIOE, "SDVOC DDC BUS"); | |
1841 | ||
1842 | if (ddcbus == NULL) | |
1843 | goto err_i2c; | |
1844 | ||
1845 | intel_sdvo_i2c_bit_algo.functionality = | |
f9c10a9b KP |
1846 | intel_output->i2c_bus->algo->functionality; |
1847 | ddcbus->algo = &intel_sdvo_i2c_bit_algo; | |
619ac3b7 ML |
1848 | intel_output->ddc_bus = ddcbus; |
1849 | ||
7086c87f ML |
1850 | /* In defaut case sdvo lvds is false */ |
1851 | sdvo_priv->is_lvds = false; | |
79e53945 JB |
1852 | intel_sdvo_get_capabilities(intel_output, &sdvo_priv->caps); |
1853 | ||
e2f0ba97 JB |
1854 | if (sdvo_priv->caps.output_flags & |
1855 | (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) { | |
1856 | if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_TMDS0) | |
1857 | sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS0; | |
1858 | else | |
1859 | sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS1; | |
1860 | ||
e2f0ba97 JB |
1861 | encoder_type = DRM_MODE_ENCODER_TMDS; |
1862 | connector_type = DRM_MODE_CONNECTOR_DVID; | |
79e53945 | 1863 | |
e2f0ba97 JB |
1864 | if (intel_sdvo_get_supp_encode(intel_output, |
1865 | &sdvo_priv->encode) && | |
1866 | intel_sdvo_get_digital_encoding_mode(intel_output) && | |
1867 | sdvo_priv->is_hdmi) { | |
1868 | /* enable hdmi encoding mode if supported */ | |
1869 | intel_sdvo_set_encode(intel_output, SDVO_ENCODE_HDMI); | |
1870 | intel_sdvo_set_colorimetry(intel_output, | |
1871 | SDVO_COLORIMETRY_RGB256); | |
1872 | connector_type = DRM_MODE_CONNECTOR_HDMIA; | |
1873 | } | |
1874 | } | |
1875 | else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_SVID0) | |
79e53945 | 1876 | { |
e2f0ba97 | 1877 | sdvo_priv->controlled_output = SDVO_OUTPUT_SVID0; |
e2f0ba97 JB |
1878 | encoder_type = DRM_MODE_ENCODER_TVDAC; |
1879 | connector_type = DRM_MODE_CONNECTOR_SVIDEO; | |
1880 | sdvo_priv->is_tv = true; | |
1881 | intel_output->needs_tv_clock = true; | |
1882 | } | |
1883 | else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_RGB0) | |
1884 | { | |
1885 | sdvo_priv->controlled_output = SDVO_OUTPUT_RGB0; | |
79e53945 JB |
1886 | encoder_type = DRM_MODE_ENCODER_DAC; |
1887 | connector_type = DRM_MODE_CONNECTOR_VGA; | |
1888 | } | |
1889 | else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_RGB1) | |
1890 | { | |
e2f0ba97 | 1891 | sdvo_priv->controlled_output = SDVO_OUTPUT_RGB1; |
79e53945 JB |
1892 | encoder_type = DRM_MODE_ENCODER_DAC; |
1893 | connector_type = DRM_MODE_CONNECTOR_VGA; | |
1894 | } | |
e2f0ba97 | 1895 | else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_LVDS0) |
79e53945 | 1896 | { |
e2f0ba97 | 1897 | sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS0; |
e2f0ba97 JB |
1898 | encoder_type = DRM_MODE_ENCODER_LVDS; |
1899 | connector_type = DRM_MODE_CONNECTOR_LVDS; | |
7086c87f | 1900 | sdvo_priv->is_lvds = true; |
79e53945 | 1901 | } |
e2f0ba97 | 1902 | else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_LVDS1) |
79e53945 | 1903 | { |
e2f0ba97 | 1904 | sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS1; |
e2f0ba97 JB |
1905 | encoder_type = DRM_MODE_ENCODER_LVDS; |
1906 | connector_type = DRM_MODE_CONNECTOR_LVDS; | |
7086c87f | 1907 | sdvo_priv->is_lvds = true; |
79e53945 JB |
1908 | } |
1909 | else | |
1910 | { | |
1911 | unsigned char bytes[2]; | |
1912 | ||
e2f0ba97 | 1913 | sdvo_priv->controlled_output = 0; |
79e53945 | 1914 | memcpy (bytes, &sdvo_priv->caps.output_flags, 2); |
342dc382 | 1915 | DRM_DEBUG_KMS(I915_SDVO, |
1916 | "%s: Unknown SDVO output type (0x%02x%02x)\n", | |
1917 | SDVO_NAME(sdvo_priv), | |
1918 | bytes[0], bytes[1]); | |
e2f0ba97 JB |
1919 | encoder_type = DRM_MODE_ENCODER_NONE; |
1920 | connector_type = DRM_MODE_CONNECTOR_Unknown; | |
79e53945 JB |
1921 | goto err_i2c; |
1922 | } | |
1923 | ||
ad5b2a6d JB |
1924 | connector = &intel_output->base; |
1925 | drm_connector_init(dev, connector, &intel_sdvo_connector_funcs, | |
1926 | connector_type); | |
1927 | drm_connector_helper_add(connector, &intel_sdvo_connector_helper_funcs); | |
1928 | connector->interlace_allowed = 0; | |
1929 | connector->doublescan_allowed = 0; | |
1930 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; | |
1931 | ||
79e53945 JB |
1932 | drm_encoder_init(dev, &intel_output->enc, &intel_sdvo_enc_funcs, encoder_type); |
1933 | drm_encoder_helper_add(&intel_output->enc, &intel_sdvo_helper_funcs); | |
79e53945 JB |
1934 | |
1935 | drm_mode_connector_attach_encoder(&intel_output->base, &intel_output->enc); | |
1936 | drm_sysfs_connector_add(connector); | |
1937 | ||
e2f0ba97 JB |
1938 | intel_sdvo_select_ddc_bus(sdvo_priv); |
1939 | ||
79e53945 JB |
1940 | /* Set the input timing to the screen. Assume always input 0. */ |
1941 | intel_sdvo_set_target_input(intel_output, true, false); | |
1942 | ||
1943 | intel_sdvo_get_input_pixel_clock_range(intel_output, | |
1944 | &sdvo_priv->pixel_clock_min, | |
1945 | &sdvo_priv->pixel_clock_max); | |
1946 | ||
1947 | ||
342dc382 | 1948 | DRM_DEBUG_KMS(I915_SDVO, "%s device VID/DID: %02X:%02X.%02X, " |
1949 | "clock range %dMHz - %dMHz, " | |
1950 | "input 1: %c, input 2: %c, " | |
1951 | "output 1: %c, output 2: %c\n", | |
1952 | SDVO_NAME(sdvo_priv), | |
1953 | sdvo_priv->caps.vendor_id, sdvo_priv->caps.device_id, | |
1954 | sdvo_priv->caps.device_rev_id, | |
1955 | sdvo_priv->pixel_clock_min / 1000, | |
1956 | sdvo_priv->pixel_clock_max / 1000, | |
1957 | (sdvo_priv->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N', | |
1958 | (sdvo_priv->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N', | |
1959 | /* check currently supported outputs */ | |
1960 | sdvo_priv->caps.output_flags & | |
79e53945 | 1961 | (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N', |
342dc382 | 1962 | sdvo_priv->caps.output_flags & |
79e53945 JB |
1963 | (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N'); |
1964 | ||
7d57382e | 1965 | return true; |
79e53945 JB |
1966 | |
1967 | err_i2c: | |
619ac3b7 ML |
1968 | if (ddcbus != NULL) |
1969 | intel_i2c_destroy(intel_output->ddc_bus); | |
79e53945 | 1970 | intel_i2c_destroy(intel_output->i2c_bus); |
ad5b2a6d | 1971 | err_inteloutput: |
79e53945 JB |
1972 | kfree(intel_output); |
1973 | ||
7d57382e | 1974 | return false; |
79e53945 | 1975 | } |