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drm/i915: Add the brightness property for SDVO-LVDS
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
29#include <linux/delay.h>
30#include "drmP.h"
31#include "drm.h"
32#include "drm_crtc.h"
33#include "intel_drv.h"
2b8d33f7 34#include "drm_edid.h"
79e53945
JB		 35#include "i915_drm.h"
36#include "i915_drv.h"
37#include "intel_sdvo_regs.h"
38
39#undef SDVO_DEBUG
11670d3c 40
ce6feabd
ZY		 41static char *tv_format_names[] = {
42 "NTSC_M" , "NTSC_J" , "NTSC_443",
43 "PAL_B" , "PAL_D" , "PAL_G" ,
44 "PAL_H" , "PAL_I" , "PAL_M" ,
45 "PAL_N" , "PAL_NC" , "PAL_60" ,
46 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
47 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
48 "SECAM_60"
49};
50
51#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
52
79e53945 53struct intel_sdvo_priv {
f9c10a9b 54 u8 slave_addr;
e2f0ba97
JB		 55
56 /* Register for the SDVO device: SDVOB or SDVOC */
79e53945
JB		 57 int output_device;
58
e2f0ba97
JB		 59 /* Active outputs controlled by this SDVO output */
60 uint16_t controlled_output;
79e53945 61
e2f0ba97
JB		 62 /*
63 * Capabilities of the SDVO device returned by
64 * i830_sdvo_get_capabilities()
65 */
79e53945 66 struct intel_sdvo_caps caps;
e2f0ba97
JB		 67
68 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 69 int pixel_clock_min, pixel_clock_max;
70
fb7a46f3 71 /*
72 * For multiple function SDVO device,
73 * this is for current attached outputs.
74 */
75 uint16_t attached_output;
76
e2f0ba97
JB		 77 /**
78 * This is set if we're going to treat the device as TV-out.
79 *
80 * While we have these nice friendly flags for output types that ought
81 * to decide this for us, the S-Video output on our HDMI+S-Video card
82 * shows up as RGB1 (VGA).
83 */
84 bool is_tv;
85
ce6feabd
ZY		 86 /* This is for current tv format name */
87 char *tv_format_name;
88
89 /* This contains all current supported TV format */
90 char *tv_format_supported[TV_FORMAT_NUM];
91 int format_supported_num;
92 struct drm_property *tv_format_property;
93 struct drm_property *tv_format_name_property[TV_FORMAT_NUM];
94
e2f0ba97
JB		 95 /**
96 * This is set if we treat the device as HDMI, instead of DVI.
97 */
98 bool is_hdmi;
12682a97 99
7086c87f
ML		 100 /**
101 * This is set if we detect output of sdvo device as LVDS.
102 */
103 bool is_lvds;
e2f0ba97 104
12682a97 105 /**
106 * This is sdvo flags for input timing.
107 */
108 uint8_t sdvo_flags;
109
110 /**
111 * This is sdvo fixed pannel mode pointer
112 */
113 struct drm_display_mode *sdvo_lvds_fixed_mode;
114
e2f0ba97
JB		 115 /**
116 * Returned SDTV resolutions allowed for the current format, if the
117 * device reported it.
118 */
119 struct intel_sdvo_sdtv_resolution_reply sdtv_resolutions;
120
e2f0ba97
JB		 121 /*
122 * supported encoding mode, used to determine whether HDMI is
123 * supported
124 */
125 struct intel_sdvo_encode encode;
126
127 /* DDC bus used by this SDVO output */
128 uint8_t ddc_bus;
129
57cdaf90
KP		 130 /* Mac mini hack -- use the same DDC as the analog connector */
131 struct i2c_adapter *analog_ddc_bus;
132
79e53945
JB		 133 int save_sdvo_mult;
134 u16 save_active_outputs;
135 struct intel_sdvo_dtd save_input_dtd_1, save_input_dtd_2;
136 struct intel_sdvo_dtd save_output_dtd[16];
137 u32 save_SDVOX;
b9219c5e
ZY		 138 /* add the property for the SDVO-TV */
139 struct drm_property *left_property;
140 struct drm_property *right_property;
141 struct drm_property *top_property;
142 struct drm_property *bottom_property;
143 struct drm_property *hpos_property;
144 struct drm_property *vpos_property;
145
146 /* add the property for the SDVO-TV/LVDS */
147 struct drm_property *brightness_property;
148 struct drm_property *contrast_property;
149 struct drm_property *saturation_property;
150 struct drm_property *hue_property;
151
152 /* Add variable to record current setting for the above property */
153 u32 left_margin, right_margin, top_margin, bottom_margin;
154 /* this is to get the range of margin.*/
155 u32 max_hscan, max_vscan;
156 u32 max_hpos, cur_hpos;
157 u32 max_vpos, cur_vpos;
158 u32 cur_brightness, max_brightness;
159 u32 cur_contrast, max_contrast;
160 u32 cur_saturation, max_saturation;
161 u32 cur_hue, max_hue;
79e53945
JB		 162};
163
fb7a46f3 164static bool
165intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags);
166
79e53945
JB		 167/**
168 * Writes the SDVOB or SDVOC with the given value, but always writes both
169 * SDVOB and SDVOC to work around apparent hardware issues (according to
170 * comments in the BIOS).
171 */
b358d0a6 172static void intel_sdvo_write_sdvox(struct intel_output *intel_output, u32 val)
79e53945
JB		 173{
174 struct drm_device *dev = intel_output->base.dev;
175 struct drm_i915_private *dev_priv = dev->dev_private;
176 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
177 u32 bval = val, cval = val;
178 int i;
179
180 if (sdvo_priv->output_device == SDVOB) {
181 cval = I915_READ(SDVOC);
182 } else {
183 bval = I915_READ(SDVOB);
184 }
185 /*
186 * Write the registers twice for luck. Sometimes,
187 * writing them only once doesn't appear to 'stick'.
188 * The BIOS does this too. Yay, magic
189 */
190 for (i = 0; i < 2; i++)
191 {
192 I915_WRITE(SDVOB, bval);
193 I915_READ(SDVOB);
194 I915_WRITE(SDVOC, cval);
195 I915_READ(SDVOC);
196 }
197}
198
199static bool intel_sdvo_read_byte(struct intel_output *intel_output, u8 addr,
200 u8 *ch)
201{
202 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
203 u8 out_buf[2];
204 u8 buf[2];
205 int ret;
206
207 struct i2c_msg msgs[] = {
208 {
f9c10a9b 209 .addr = sdvo_priv->slave_addr >> 1,
79e53945
JB		 210 .flags = 0,
211 .len = 1,
212 .buf = out_buf,
213 },
214 {
f9c10a9b 215 .addr = sdvo_priv->slave_addr >> 1,
79e53945
JB		 216 .flags = I2C_M_RD,
217 .len = 1,
218 .buf = buf,
219 }
220 };
221
222 out_buf[0] = addr;
223 out_buf[1] = 0;
224
308cd3a2 225 if ((ret = i2c_transfer(intel_output->i2c_bus, msgs, 2)) == 2)
79e53945
JB		 226 {
227 *ch = buf[0];
228 return true;
229 }
230
8a4c47f3 231 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 232 return false;
233}
234
235static bool intel_sdvo_write_byte(struct intel_output *intel_output, int addr,
236 u8 ch)
237{
f9c10a9b 238 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
79e53945
JB		 239 u8 out_buf[2];
240 struct i2c_msg msgs[] = {
241 {
f9c10a9b 242 .addr = sdvo_priv->slave_addr >> 1,
79e53945
JB		 243 .flags = 0,
244 .len = 2,
245 .buf = out_buf,
246 }
247 };
248
249 out_buf[0] = addr;
250 out_buf[1] = ch;
251
f9c10a9b 252 if (i2c_transfer(intel_output->i2c_bus, msgs, 1) == 1)
79e53945
JB		 253 {
254 return true;
255 }
256 return false;
257}
258
259#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
260/** Mapping of command numbers to names, for debug output */
005568be 261static const struct _sdvo_cmd_name {
e2f0ba97
JB		 262 u8 cmd;
263 char *name;
79e53945
JB		 264} sdvo_cmd_names[] = {
265 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
266 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
267 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
268 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
269 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
270 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
271 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
272 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
273 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
274 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
275 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
276 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
277 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
278 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
279 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
280 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
281 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
282 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
283 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
284 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
285 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
286 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
287 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
288 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
289 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
290 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
291 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
292 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
293 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
294 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
295 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
296 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
297 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
e2f0ba97
JB		 300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
79e53945 304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
e2f0ba97
JB		 305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
b9219c5e
ZY		 308 /* Add the op code for SDVO enhancements */
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_POSITION_H),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POSITION_H),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_POSITION_H),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_POSITION_V),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POSITION_V),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_POSITION_V),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
e2f0ba97
JB		 333 /* HDMI op code */
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 354};
355
356#define SDVO_NAME(dev_priv) ((dev_priv)->output_device == SDVOB ? "SDVOB" : "SDVOC")
357#define SDVO_PRIV(output) ((struct intel_sdvo_priv *) (output)->dev_priv)
358
359#ifdef SDVO_DEBUG
360static void intel_sdvo_debug_write(struct intel_output *intel_output, u8 cmd,
361 void *args, int args_len)
362{
363 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
364 int i;
365
8a4c47f3 366 DRM_DEBUG_KMS("%s: W: %02X ",
342dc382 367 SDVO_NAME(sdvo_priv), cmd);
79e53945 368 for (i = 0; i < args_len; i++)
342dc382 369 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
79e53945 370 for (; i < 8; i++)
342dc382 371 DRM_LOG_KMS(" ");
79e53945
JB		 372 for (i = 0; i < sizeof(sdvo_cmd_names) / sizeof(sdvo_cmd_names[0]); i++) {
373 if (cmd == sdvo_cmd_names[i].cmd) {
342dc382 374 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 375 break;
376 }
377 }
378 if (i == sizeof(sdvo_cmd_names)/ sizeof(sdvo_cmd_names[0]))
342dc382 379 DRM_LOG_KMS("(%02X)", cmd);
380 DRM_LOG_KMS("\n");
79e53945
JB		 381}
382#else
383#define intel_sdvo_debug_write(o, c, a, l)
384#endif
385
386static void intel_sdvo_write_cmd(struct intel_output *intel_output, u8 cmd,
387 void *args, int args_len)
388{
389 int i;
390
391 intel_sdvo_debug_write(intel_output, cmd, args, args_len);
392
393 for (i = 0; i < args_len; i++) {
394 intel_sdvo_write_byte(intel_output, SDVO_I2C_ARG_0 - i,
395 ((u8*)args)[i]);
396 }
397
398 intel_sdvo_write_byte(intel_output, SDVO_I2C_OPCODE, cmd);
399}
400
401#ifdef SDVO_DEBUG
402static const char *cmd_status_names[] = {
403 "Power on",
404 "Success",
405 "Not supported",
406 "Invalid arg",
407 "Pending",
408 "Target not specified",
409 "Scaling not supported"
410};
411
412static void intel_sdvo_debug_response(struct intel_output *intel_output,
413 void *response, int response_len,
414 u8 status)
415{
416 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
33b52961 417 int i;
79e53945 418
8a4c47f3 419 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(sdvo_priv));
79e53945 420 for (i = 0; i < response_len; i++)
342dc382 421 DRM_LOG_KMS("%02X ", ((u8 *)response)[i]);
79e53945 422 for (; i < 8; i++)
342dc382 423 DRM_LOG_KMS(" ");
79e53945 424 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
342dc382 425 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
79e53945 426 else
342dc382 427 DRM_LOG_KMS("(??? %d)", status);
428 DRM_LOG_KMS("\n");
79e53945
JB		 429}
430#else
431#define intel_sdvo_debug_response(o, r, l, s)
432#endif
433
434static u8 intel_sdvo_read_response(struct intel_output *intel_output,
435 void *response, int response_len)
436{
437 int i;
438 u8 status;
439 u8 retry = 50;
440
441 while (retry--) {
442 /* Read the command response */
443 for (i = 0; i < response_len; i++) {
444 intel_sdvo_read_byte(intel_output,
445 SDVO_I2C_RETURN_0 + i,
446 &((u8 *)response)[i]);
447 }
448
449 /* read the return status */
450 intel_sdvo_read_byte(intel_output, SDVO_I2C_CMD_STATUS,
451 &status);
452
453 intel_sdvo_debug_response(intel_output, response, response_len,
454 status);
455 if (status != SDVO_CMD_STATUS_PENDING)
456 return status;
457
458 mdelay(50);
459 }
460
461 return status;
462}
463
b358d0a6 464static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
79e53945
JB		 465{
466 if (mode->clock >= 100000)
467 return 1;
468 else if (mode->clock >= 50000)
469 return 2;
470 else
471 return 4;
472}
473
474/**
475 * Don't check status code from this as it switches the bus back to the
476 * SDVO chips which defeats the purpose of doing a bus switch in the first
477 * place.
478 */
b358d0a6
HE		 479static void intel_sdvo_set_control_bus_switch(struct intel_output *intel_output,
480 u8 target)
79e53945
JB		 481{
482 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_CONTROL_BUS_SWITCH, &target, 1);
483}
484
485static bool intel_sdvo_set_target_input(struct intel_output *intel_output, bool target_0, bool target_1)
486{
487 struct intel_sdvo_set_target_input_args targets = {0};
488 u8 status;
489
490 if (target_0 && target_1)
491 return SDVO_CMD_STATUS_NOTSUPP;
492
493 if (target_1)
494 targets.target_1 = 1;
495
496 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_TARGET_INPUT, &targets,
497 sizeof(targets));
498
499 status = intel_sdvo_read_response(intel_output, NULL, 0);
500
501 return (status == SDVO_CMD_STATUS_SUCCESS);
502}
503
504/**
505 * Return whether each input is trained.
506 *
507 * This function is making an assumption about the layout of the response,
508 * which should be checked against the docs.
509 */
510static bool intel_sdvo_get_trained_inputs(struct intel_output *intel_output, bool *input_1, bool *input_2)
511{
512 struct intel_sdvo_get_trained_inputs_response response;
513 u8 status;
514
515 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_TRAINED_INPUTS, NULL, 0);
516 status = intel_sdvo_read_response(intel_output, &response, sizeof(response));
517 if (status != SDVO_CMD_STATUS_SUCCESS)
518 return false;
519
520 *input_1 = response.input0_trained;
521 *input_2 = response.input1_trained;
522 return true;
523}
524
525static bool intel_sdvo_get_active_outputs(struct intel_output *intel_output,
526 u16 *outputs)
527{
528 u8 status;
529
530 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_OUTPUTS, NULL, 0);
531 status = intel_sdvo_read_response(intel_output, outputs, sizeof(*outputs));
532
533 return (status == SDVO_CMD_STATUS_SUCCESS);
534}
535
536static bool intel_sdvo_set_active_outputs(struct intel_output *intel_output,
537 u16 outputs)
538{
539 u8 status;
540
541 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_OUTPUTS, &outputs,
542 sizeof(outputs));
543 status = intel_sdvo_read_response(intel_output, NULL, 0);
544 return (status == SDVO_CMD_STATUS_SUCCESS);
545}
546
547static bool intel_sdvo_set_encoder_power_state(struct intel_output *intel_output,
548 int mode)
549{
550 u8 status, state = SDVO_ENCODER_STATE_ON;
551
552 switch (mode) {
553 case DRM_MODE_DPMS_ON:
554 state = SDVO_ENCODER_STATE_ON;
555 break;
556 case DRM_MODE_DPMS_STANDBY:
557 state = SDVO_ENCODER_STATE_STANDBY;
558 break;
559 case DRM_MODE_DPMS_SUSPEND:
560 state = SDVO_ENCODER_STATE_SUSPEND;
561 break;
562 case DRM_MODE_DPMS_OFF:
563 state = SDVO_ENCODER_STATE_OFF;
564 break;
565 }
566
567 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ENCODER_POWER_STATE, &state,
568 sizeof(state));
569 status = intel_sdvo_read_response(intel_output, NULL, 0);
570
571 return (status == SDVO_CMD_STATUS_SUCCESS);
572}
573
574static bool intel_sdvo_get_input_pixel_clock_range(struct intel_output *intel_output,
575 int *clock_min,
576 int *clock_max)
577{
578 struct intel_sdvo_pixel_clock_range clocks;
579 u8 status;
580
581 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
582 NULL, 0);
583
584 status = intel_sdvo_read_response(intel_output, &clocks, sizeof(clocks));
585
586 if (status != SDVO_CMD_STATUS_SUCCESS)
587 return false;
588
589 /* Convert the values from units of 10 kHz to kHz. */
590 *clock_min = clocks.min * 10;
591 *clock_max = clocks.max * 10;
592
593 return true;
594}
595
596static bool intel_sdvo_set_target_output(struct intel_output *intel_output,
597 u16 outputs)
598{
599 u8 status;
600
601 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_TARGET_OUTPUT, &outputs,
602 sizeof(outputs));
603
604 status = intel_sdvo_read_response(intel_output, NULL, 0);
605 return (status == SDVO_CMD_STATUS_SUCCESS);
606}
607
608static bool intel_sdvo_get_timing(struct intel_output *intel_output, u8 cmd,
609 struct intel_sdvo_dtd *dtd)
610{
611 u8 status;
612
613 intel_sdvo_write_cmd(intel_output, cmd, NULL, 0);
614 status = intel_sdvo_read_response(intel_output, &dtd->part1,
615 sizeof(dtd->part1));
616 if (status != SDVO_CMD_STATUS_SUCCESS)
617 return false;
618
619 intel_sdvo_write_cmd(intel_output, cmd + 1, NULL, 0);
620 status = intel_sdvo_read_response(intel_output, &dtd->part2,
621 sizeof(dtd->part2));
622 if (status != SDVO_CMD_STATUS_SUCCESS)
623 return false;
624
625 return true;
626}
627
628static bool intel_sdvo_get_input_timing(struct intel_output *intel_output,
629 struct intel_sdvo_dtd *dtd)
630{
631 return intel_sdvo_get_timing(intel_output,
632 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
633}
634
635static bool intel_sdvo_get_output_timing(struct intel_output *intel_output,
636 struct intel_sdvo_dtd *dtd)
637{
638 return intel_sdvo_get_timing(intel_output,
639 SDVO_CMD_GET_OUTPUT_TIMINGS_PART1, dtd);
640}
641
642static bool intel_sdvo_set_timing(struct intel_output *intel_output, u8 cmd,
643 struct intel_sdvo_dtd *dtd)
644{
645 u8 status;
646
647 intel_sdvo_write_cmd(intel_output, cmd, &dtd->part1, sizeof(dtd->part1));
648 status = intel_sdvo_read_response(intel_output, NULL, 0);
649 if (status != SDVO_CMD_STATUS_SUCCESS)
650 return false;
651
652 intel_sdvo_write_cmd(intel_output, cmd + 1, &dtd->part2, sizeof(dtd->part2));
653 status = intel_sdvo_read_response(intel_output, NULL, 0);
654 if (status != SDVO_CMD_STATUS_SUCCESS)
655 return false;
656
657 return true;
658}
659
660static bool intel_sdvo_set_input_timing(struct intel_output *intel_output,
661 struct intel_sdvo_dtd *dtd)
662{
663 return intel_sdvo_set_timing(intel_output,
664 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
665}
666
667static bool intel_sdvo_set_output_timing(struct intel_output *intel_output,
668 struct intel_sdvo_dtd *dtd)
669{
670 return intel_sdvo_set_timing(intel_output,
671 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
672}
673
e2f0ba97
JB		 674static bool
675intel_sdvo_create_preferred_input_timing(struct intel_output *output,
676 uint16_t clock,
677 uint16_t width,
678 uint16_t height)
679{
680 struct intel_sdvo_preferred_input_timing_args args;
12682a97 681 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
e2f0ba97
JB		 682 uint8_t status;
683
e642c6f1 684 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 685 args.clock = clock;
686 args.width = width;
687 args.height = height;
e642c6f1 688 args.interlace = 0;
12682a97 689
690 if (sdvo_priv->is_lvds &&
691 (sdvo_priv->sdvo_lvds_fixed_mode->hdisplay != width ||
692 sdvo_priv->sdvo_lvds_fixed_mode->vdisplay != height))
693 args.scaled = 1;
694
e2f0ba97
JB		 695 intel_sdvo_write_cmd(output, SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
696 &args, sizeof(args));
697 status = intel_sdvo_read_response(output, NULL, 0);
698 if (status != SDVO_CMD_STATUS_SUCCESS)
699 return false;
700
701 return true;
702}
703
704static bool intel_sdvo_get_preferred_input_timing(struct intel_output *output,
705 struct intel_sdvo_dtd *dtd)
706{
707 bool status;
708
709 intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
710 NULL, 0);
711
712 status = intel_sdvo_read_response(output, &dtd->part1,
713 sizeof(dtd->part1));
714 if (status != SDVO_CMD_STATUS_SUCCESS)
715 return false;
716
717 intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
718 NULL, 0);
719
720 status = intel_sdvo_read_response(output, &dtd->part2,
721 sizeof(dtd->part2));
722 if (status != SDVO_CMD_STATUS_SUCCESS)
723 return false;
724
725 return false;
726}
79e53945
JB		 727
728static int intel_sdvo_get_clock_rate_mult(struct intel_output *intel_output)
729{
730 u8 response, status;
731
732 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_CLOCK_RATE_MULT, NULL, 0);
733 status = intel_sdvo_read_response(intel_output, &response, 1);
734
735 if (status != SDVO_CMD_STATUS_SUCCESS) {
8a4c47f3 736 DRM_DEBUG_KMS("Couldn't get SDVO clock rate multiplier\n");
79e53945
JB		 737 return SDVO_CLOCK_RATE_MULT_1X;
738 } else {
8a4c47f3 739 DRM_DEBUG_KMS("Current clock rate multiplier: %d\n", response);
79e53945
JB		 740 }
741
742 return response;
743}
744
745static bool intel_sdvo_set_clock_rate_mult(struct intel_output *intel_output, u8 val)
746{
747 u8 status;
748
749 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
750 status = intel_sdvo_read_response(intel_output, NULL, 0);
751 if (status != SDVO_CMD_STATUS_SUCCESS)
752 return false;
753
754 return true;
755}
756
e2f0ba97
JB		 757static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
758 struct drm_display_mode *mode)
79e53945 759{
e2f0ba97
JB		 760 uint16_t width, height;
761 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
762 uint16_t h_sync_offset, v_sync_offset;
79e53945
JB		 763
764 width = mode->crtc_hdisplay;
765 height = mode->crtc_vdisplay;
766
767 /* do some mode translations */
768 h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
769 h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
770
771 v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
772 v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
773
774 h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
775 v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
776
e2f0ba97
JB		 777 dtd->part1.clock = mode->clock / 10;
778 dtd->part1.h_active = width & 0xff;
779 dtd->part1.h_blank = h_blank_len & 0xff;
780 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 781 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 782 dtd->part1.v_active = height & 0xff;
783 dtd->part1.v_blank = v_blank_len & 0xff;
784 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 785 ((v_blank_len >> 8) & 0xf);
786
171a9e96 787 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 788 dtd->part2.h_sync_width = h_sync_len & 0xff;
789 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 790 (v_sync_len & 0xf);
e2f0ba97 791 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 792 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
793 ((v_sync_len & 0x30) >> 4);
794
e2f0ba97 795 dtd->part2.dtd_flags = 0x18;
79e53945 796 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
e2f0ba97 797 dtd->part2.dtd_flags |= 0x2;
79e53945 798 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
e2f0ba97
JB		 799 dtd->part2.dtd_flags |= 0x4;
800
801 dtd->part2.sdvo_flags = 0;
802 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
803 dtd->part2.reserved = 0;
804}
805
806static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
807 struct intel_sdvo_dtd *dtd)
808{
e2f0ba97
JB		 809 mode->hdisplay = dtd->part1.h_active;
810 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
811 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
171a9e96 812 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
e2f0ba97
JB		 813 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
814 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
815 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
816 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
817
818 mode->vdisplay = dtd->part1.v_active;
819 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
820 mode->vsync_start = mode->vdisplay;
821 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
171a9e96 822 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
e2f0ba97
JB		 823 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
824 mode->vsync_end = mode->vsync_start +
825 (dtd->part2.v_sync_off_width & 0xf);
826 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
827 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
828 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
829
830 mode->clock = dtd->part1.clock * 10;
831
171a9e96 832 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
e2f0ba97
JB		 833 if (dtd->part2.dtd_flags & 0x2)
834 mode->flags |= DRM_MODE_FLAG_PHSYNC;
835 if (dtd->part2.dtd_flags & 0x4)
836 mode->flags |= DRM_MODE_FLAG_PVSYNC;
837}
838
839static bool intel_sdvo_get_supp_encode(struct intel_output *output,
840 struct intel_sdvo_encode *encode)
841{
842 uint8_t status;
843
844 intel_sdvo_write_cmd(output, SDVO_CMD_GET_SUPP_ENCODE, NULL, 0);
845 status = intel_sdvo_read_response(output, encode, sizeof(*encode));
846 if (status != SDVO_CMD_STATUS_SUCCESS) { /* non-support means DVI */
847 memset(encode, 0, sizeof(*encode));
848 return false;
849 }
850
851 return true;
852}
853
854static bool intel_sdvo_set_encode(struct intel_output *output, uint8_t mode)
855{
856 uint8_t status;
857
858 intel_sdvo_write_cmd(output, SDVO_CMD_SET_ENCODE, &mode, 1);
859 status = intel_sdvo_read_response(output, NULL, 0);
860
861 return (status == SDVO_CMD_STATUS_SUCCESS);
862}
863
864static bool intel_sdvo_set_colorimetry(struct intel_output *output,
865 uint8_t mode)
866{
867 uint8_t status;
868
869 intel_sdvo_write_cmd(output, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
870 status = intel_sdvo_read_response(output, NULL, 0);
871
872 return (status == SDVO_CMD_STATUS_SUCCESS);
873}
874
875#if 0
876static void intel_sdvo_dump_hdmi_buf(struct intel_output *output)
877{
878 int i, j;
879 uint8_t set_buf_index[2];
880 uint8_t av_split;
881 uint8_t buf_size;
882 uint8_t buf[48];
883 uint8_t *pos;
884
885 intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_AV_SPLIT, NULL, 0);
886 intel_sdvo_read_response(output, &av_split, 1);
887
888 for (i = 0; i <= av_split; i++) {
889 set_buf_index[0] = i; set_buf_index[1] = 0;
890 intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_INDEX,
891 set_buf_index, 2);
892 intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
893 intel_sdvo_read_response(output, &buf_size, 1);
894
895 pos = buf;
896 for (j = 0; j <= buf_size; j += 8) {
897 intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_DATA,
898 NULL, 0);
899 intel_sdvo_read_response(output, pos, 8);
900 pos += 8;
901 }
902 }
903}
904#endif
905
906static void intel_sdvo_set_hdmi_buf(struct intel_output *output, int index,
907 uint8_t *data, int8_t size, uint8_t tx_rate)
908{
909 uint8_t set_buf_index[2];
910
911 set_buf_index[0] = index;
912 set_buf_index[1] = 0;
913
914 intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_INDEX, set_buf_index, 2);
915
916 for (; size > 0; size -= 8) {
917 intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_DATA, data, 8);
918 data += 8;
919 }
920
921 intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1);
922}
923
924static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size)
925{
926 uint8_t csum = 0;
927 int i;
928
929 for (i = 0; i < size; i++)
930 csum += data[i];
931
932 return 0x100 - csum;
933}
934
935#define DIP_TYPE_AVI 0x82
936#define DIP_VERSION_AVI 0x2
937#define DIP_LEN_AVI 13
938
939struct dip_infoframe {
940 uint8_t type;
941 uint8_t version;
942 uint8_t len;
943 uint8_t checksum;
944 union {
945 struct {
946 /* Packet Byte #1 */
947 uint8_t S:2;
948 uint8_t B:2;
949 uint8_t A:1;
950 uint8_t Y:2;
951 uint8_t rsvd1:1;
952 /* Packet Byte #2 */
953 uint8_t R:4;
954 uint8_t M:2;
955 uint8_t C:2;
956 /* Packet Byte #3 */
957 uint8_t SC:2;
958 uint8_t Q:2;
959 uint8_t EC:3;
960 uint8_t ITC:1;
961 /* Packet Byte #4 */
962 uint8_t VIC:7;
963 uint8_t rsvd2:1;
964 /* Packet Byte #5 */
965 uint8_t PR:4;
966 uint8_t rsvd3:4;
967 /* Packet Byte #6~13 */
968 uint16_t top_bar_end;
969 uint16_t bottom_bar_start;
970 uint16_t left_bar_end;
971 uint16_t right_bar_start;
972 } avi;
973 struct {
974 /* Packet Byte #1 */
975 uint8_t channel_count:3;
976 uint8_t rsvd1:1;
977 uint8_t coding_type:4;
978 /* Packet Byte #2 */
979 uint8_t sample_size:2; /* SS0, SS1 */
980 uint8_t sample_frequency:3;
981 uint8_t rsvd2:3;
982 /* Packet Byte #3 */
983 uint8_t coding_type_private:5;
984 uint8_t rsvd3:3;
985 /* Packet Byte #4 */
986 uint8_t channel_allocation;
987 /* Packet Byte #5 */
988 uint8_t rsvd4:3;
989 uint8_t level_shift:4;
990 uint8_t downmix_inhibit:1;
991 } audio;
992 uint8_t payload[28];
993 } __attribute__ ((packed)) u;
994} __attribute__((packed));
995
996static void intel_sdvo_set_avi_infoframe(struct intel_output *output,
997 struct drm_display_mode * mode)
998{
999 struct dip_infoframe avi_if = {
1000 .type = DIP_TYPE_AVI,
1001 .version = DIP_VERSION_AVI,
1002 .len = DIP_LEN_AVI,
1003 };
1004
1005 avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if,
1006 4 + avi_if.len);
1007 intel_sdvo_set_hdmi_buf(output, 1, (uint8_t *)&avi_if, 4 + avi_if.len,
1008 SDVO_HBUF_TX_VSYNC);
1009}
1010
7026d4ac
ZW		 1011static void intel_sdvo_set_tv_format(struct intel_output *output)
1012{
ce6feabd
ZY		 1013
1014 struct intel_sdvo_tv_format format;
7026d4ac 1015 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
ce6feabd
ZY		 1016 uint32_t format_map, i;
1017 uint8_t status;
7026d4ac 1018
ce6feabd
ZY		 1019 for (i = 0; i < TV_FORMAT_NUM; i++)
1020 if (tv_format_names[i] == sdvo_priv->tv_format_name)
1021 break;
1022
1023 format_map = 1 << i;
1024 memset(&format, 0, sizeof(format));
1025 memcpy(&format, &format_map, sizeof(format_map) > sizeof(format) ?
1026 sizeof(format) : sizeof(format_map));
1027
1028 intel_sdvo_write_cmd(output, SDVO_CMD_SET_TV_FORMAT, &format_map,
1029 sizeof(format));
1030
1031 status = intel_sdvo_read_response(output, NULL, 0);
1032 if (status != SDVO_CMD_STATUS_SUCCESS)
b9219c5e 1033 DRM_DEBUG_KMS("%s: Failed to set TV format\n",
ce6feabd 1034 SDVO_NAME(sdvo_priv));
7026d4ac
ZW		 1035}
1036
e2f0ba97
JB		 1037static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
1038 struct drm_display_mode *mode,
1039 struct drm_display_mode *adjusted_mode)
1040{
1041 struct intel_output *output = enc_to_intel_output(encoder);
1042 struct intel_sdvo_priv *dev_priv = output->dev_priv;
79e53945 1043
12682a97 1044 if (dev_priv->is_tv) {
e2f0ba97
JB		 1045 struct intel_sdvo_dtd output_dtd;
1046 bool success;
1047
1048 /* We need to construct preferred input timings based on our
1049 * output timings. To do that, we have to set the output
1050 * timings, even though this isn't really the right place in
1051 * the sequence to do it. Oh well.
1052 */
1053
1054
1055 /* Set output timings */
1056 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1057 intel_sdvo_set_target_output(output,
1058 dev_priv->controlled_output);
1059 intel_sdvo_set_output_timing(output, &output_dtd);
1060
1061 /* Set the input timing to the screen. Assume always input 0. */
1062 intel_sdvo_set_target_input(output, true, false);
1063
1064
1065 success = intel_sdvo_create_preferred_input_timing(output,
1066 mode->clock / 10,
1067 mode->hdisplay,
1068 mode->vdisplay);
1069 if (success) {
1070 struct intel_sdvo_dtd input_dtd;
79e53945 1071
e2f0ba97
JB		 1072 intel_sdvo_get_preferred_input_timing(output,
1073 &input_dtd);
1074 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
12682a97 1075 dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags;
1076
1077 drm_mode_set_crtcinfo(adjusted_mode, 0);
1078
1079 mode->clock = adjusted_mode->clock;
1080
1081 adjusted_mode->clock *=
1082 intel_sdvo_get_pixel_multiplier(mode);
1083 } else {
1084 return false;
1085 }
1086 } else if (dev_priv->is_lvds) {
1087 struct intel_sdvo_dtd output_dtd;
1088 bool success;
1089
1090 drm_mode_set_crtcinfo(dev_priv->sdvo_lvds_fixed_mode, 0);
1091 /* Set output timings */
1092 intel_sdvo_get_dtd_from_mode(&output_dtd,
1093 dev_priv->sdvo_lvds_fixed_mode);
1094
1095 intel_sdvo_set_target_output(output,
1096 dev_priv->controlled_output);
1097 intel_sdvo_set_output_timing(output, &output_dtd);
1098
1099 /* Set the input timing to the screen. Assume always input 0. */
1100 intel_sdvo_set_target_input(output, true, false);
1101
1102
1103 success = intel_sdvo_create_preferred_input_timing(
1104 output,
1105 mode->clock / 10,
1106 mode->hdisplay,
1107 mode->vdisplay);
1108
1109 if (success) {
1110 struct intel_sdvo_dtd input_dtd;
1111
1112 intel_sdvo_get_preferred_input_timing(output,
1113 &input_dtd);
1114 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1115 dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags;
e2f0ba97 1116
7026d4ac
ZW		 1117 drm_mode_set_crtcinfo(adjusted_mode, 0);
1118
1119 mode->clock = adjusted_mode->clock;
1120
1121 adjusted_mode->clock *=
1122 intel_sdvo_get_pixel_multiplier(mode);
e2f0ba97
JB		 1123 } else {
1124 return false;
1125 }
12682a97 1126
1127 } else {
1128 /* Make the CRTC code factor in the SDVO pixel multiplier. The
1129 * SDVO device will be told of the multiplier during mode_set.
1130 */
1131 adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode);
e2f0ba97
JB		 1132 }
1133 return true;
1134}
1135
1136static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1137 struct drm_display_mode *mode,
1138 struct drm_display_mode *adjusted_mode)
1139{
1140 struct drm_device *dev = encoder->dev;
1141 struct drm_i915_private *dev_priv = dev->dev_private;
1142 struct drm_crtc *crtc = encoder->crtc;
1143 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1144 struct intel_output *output = enc_to_intel_output(encoder);
1145 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1146 u32 sdvox = 0;
1147 int sdvo_pixel_multiply;
1148 struct intel_sdvo_in_out_map in_out;
1149 struct intel_sdvo_dtd input_dtd;
1150 u8 status;
1151
1152 if (!mode)
1153 return;
1154
1155 /* First, set the input mapping for the first input to our controlled
1156 * output. This is only correct if we're a single-input device, in
1157 * which case the first input is the output from the appropriate SDVO
1158 * channel on the motherboard. In a two-input device, the first input
1159 * will be SDVOB and the second SDVOC.
1160 */
1161 in_out.in0 = sdvo_priv->controlled_output;
1162 in_out.in1 = 0;
1163
1164 intel_sdvo_write_cmd(output, SDVO_CMD_SET_IN_OUT_MAP,
1165 &in_out, sizeof(in_out));
1166 status = intel_sdvo_read_response(output, NULL, 0);
1167
1168 if (sdvo_priv->is_hdmi) {
1169 intel_sdvo_set_avi_infoframe(output, mode);
1170 sdvox |= SDVO_AUDIO_ENABLE;
1171 }
1172
7026d4ac
ZW		 1173 /* We have tried to get input timing in mode_fixup, and filled into
1174 adjusted_mode */
12682a97 1175 if (sdvo_priv->is_tv || sdvo_priv->is_lvds) {
7026d4ac 1176 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
12682a97 1177 input_dtd.part2.sdvo_flags = sdvo_priv->sdvo_flags;
1178 } else
7026d4ac 1179 intel_sdvo_get_dtd_from_mode(&input_dtd, mode);
e2f0ba97
JB		 1180
1181 /* If it's a TV, we already set the output timing in mode_fixup.
1182 * Otherwise, the output timing is equal to the input timing.
1183 */
12682a97 1184 if (!sdvo_priv->is_tv && !sdvo_priv->is_lvds) {
e2f0ba97
JB		 1185 /* Set the output timing to the screen */
1186 intel_sdvo_set_target_output(output,
1187 sdvo_priv->controlled_output);
1188 intel_sdvo_set_output_timing(output, &input_dtd);
1189 }
79e53945
JB		 1190
1191 /* Set the input timing to the screen. Assume always input 0. */
e2f0ba97 1192 intel_sdvo_set_target_input(output, true, false);
79e53945 1193
7026d4ac
ZW		 1194 if (sdvo_priv->is_tv)
1195 intel_sdvo_set_tv_format(output);
1196
e2f0ba97 1197 /* We would like to use intel_sdvo_create_preferred_input_timing() to
79e53945
JB		 1198 * provide the device with a timing it can support, if it supports that
1199 * feature. However, presumably we would need to adjust the CRTC to
1200 * output the preferred timing, and we don't support that currently.
1201 */
e2f0ba97
JB		 1202#if 0
1203 success = intel_sdvo_create_preferred_input_timing(output, clock,
1204 width, height);
1205 if (success) {
1206 struct intel_sdvo_dtd *input_dtd;
1207
1208 intel_sdvo_get_preferred_input_timing(output, &input_dtd);
1209 intel_sdvo_set_input_timing(output, &input_dtd);
1210 }
1211#else
1212 intel_sdvo_set_input_timing(output, &input_dtd);
1213#endif
79e53945
JB		 1214
1215 switch (intel_sdvo_get_pixel_multiplier(mode)) {
1216 case 1:
e2f0ba97 1217 intel_sdvo_set_clock_rate_mult(output,
79e53945
JB		 1218 SDVO_CLOCK_RATE_MULT_1X);
1219 break;
1220 case 2:
e2f0ba97 1221 intel_sdvo_set_clock_rate_mult(output,
79e53945
JB		 1222 SDVO_CLOCK_RATE_MULT_2X);
1223 break;
1224 case 4:
e2f0ba97 1225 intel_sdvo_set_clock_rate_mult(output,
79e53945
JB		 1226 SDVO_CLOCK_RATE_MULT_4X);
1227 break;
1228 }
1229
1230 /* Set the SDVO control regs. */
e2f0ba97
JB		 1231 if (IS_I965G(dev)) {
1232 sdvox |= SDVO_BORDER_ENABLE |
1233 SDVO_VSYNC_ACTIVE_HIGH |
1234 SDVO_HSYNC_ACTIVE_HIGH;
1235 } else {
1236 sdvox |= I915_READ(sdvo_priv->output_device);
1237 switch (sdvo_priv->output_device) {
1238 case SDVOB:
1239 sdvox &= SDVOB_PRESERVE_MASK;
1240 break;
1241 case SDVOC:
1242 sdvox &= SDVOC_PRESERVE_MASK;
1243 break;
1244 }
1245 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1246 }
79e53945
JB		 1247 if (intel_crtc->pipe == 1)
1248 sdvox |= SDVO_PIPE_B_SELECT;
1249
1250 sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode);
1251 if (IS_I965G(dev)) {
e2f0ba97
JB		 1252 /* done in crtc_mode_set as the dpll_md reg must be written early */
1253 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1254 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945
JB		 1255 } else {
1256 sdvox |= (sdvo_pixel_multiply - 1) << SDVO_PORT_MULTIPLY_SHIFT;
1257 }
1258
12682a97 1259 if (sdvo_priv->sdvo_flags & SDVO_NEED_TO_STALL)
1260 sdvox |= SDVO_STALL_SELECT;
e2f0ba97 1261 intel_sdvo_write_sdvox(output, sdvox);
79e53945
JB		 1262}
1263
1264static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1265{
1266 struct drm_device *dev = encoder->dev;
1267 struct drm_i915_private *dev_priv = dev->dev_private;
1268 struct intel_output *intel_output = enc_to_intel_output(encoder);
1269 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1270 u32 temp;
1271
1272 if (mode != DRM_MODE_DPMS_ON) {
1273 intel_sdvo_set_active_outputs(intel_output, 0);
1274 if (0)
1275 intel_sdvo_set_encoder_power_state(intel_output, mode);
1276
1277 if (mode == DRM_MODE_DPMS_OFF) {
1278 temp = I915_READ(sdvo_priv->output_device);
1279 if ((temp & SDVO_ENABLE) != 0) {
1280 intel_sdvo_write_sdvox(intel_output, temp & ~SDVO_ENABLE);
1281 }
1282 }
1283 } else {
1284 bool input1, input2;
1285 int i;
1286 u8 status;
1287
1288 temp = I915_READ(sdvo_priv->output_device);
1289 if ((temp & SDVO_ENABLE) == 0)
1290 intel_sdvo_write_sdvox(intel_output, temp | SDVO_ENABLE);
1291 for (i = 0; i < 2; i++)
1292 intel_wait_for_vblank(dev);
1293
1294 status = intel_sdvo_get_trained_inputs(intel_output, &input1,
1295 &input2);
1296
1297
1298 /* Warn if the device reported failure to sync.
1299 * A lot of SDVO devices fail to notify of sync, but it's
1300 * a given it the status is a success, we succeeded.
1301 */
1302 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
8a4c47f3
ZY		 1303 DRM_DEBUG_KMS("First %s output reported failure to "
1304 "sync\n", SDVO_NAME(sdvo_priv));
79e53945
JB		 1305 }
1306
1307 if (0)
1308 intel_sdvo_set_encoder_power_state(intel_output, mode);
e2f0ba97 1309 intel_sdvo_set_active_outputs(intel_output, sdvo_priv->controlled_output);
79e53945
JB		 1310 }
1311 return;
1312}
1313
1314static void intel_sdvo_save(struct drm_connector *connector)
1315{
1316 struct drm_device *dev = connector->dev;
1317 struct drm_i915_private *dev_priv = dev->dev_private;
1318 struct intel_output *intel_output = to_intel_output(connector);
1319 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1320 int o;
1321
1322 sdvo_priv->save_sdvo_mult = intel_sdvo_get_clock_rate_mult(intel_output);
1323 intel_sdvo_get_active_outputs(intel_output, &sdvo_priv->save_active_outputs);
1324
1325 if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
1326 intel_sdvo_set_target_input(intel_output, true, false);
1327 intel_sdvo_get_input_timing(intel_output,
1328 &sdvo_priv->save_input_dtd_1);
1329 }
1330
1331 if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
1332 intel_sdvo_set_target_input(intel_output, false, true);
1333 intel_sdvo_get_input_timing(intel_output,
1334 &sdvo_priv->save_input_dtd_2);
1335 }
1336
1337 for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
1338 {
1339 u16 this_output = (1 << o);
1340 if (sdvo_priv->caps.output_flags & this_output)
1341 {
1342 intel_sdvo_set_target_output(intel_output, this_output);
1343 intel_sdvo_get_output_timing(intel_output,
1344 &sdvo_priv->save_output_dtd[o]);
1345 }
1346 }
e2f0ba97
JB		 1347 if (sdvo_priv->is_tv) {
1348 /* XXX: Save TV format/enhancements. */
1349 }
79e53945
JB		 1350
1351 sdvo_priv->save_SDVOX = I915_READ(sdvo_priv->output_device);
1352}
1353
1354static void intel_sdvo_restore(struct drm_connector *connector)
1355{
1356 struct drm_device *dev = connector->dev;
79e53945
JB		 1357 struct intel_output *intel_output = to_intel_output(connector);
1358 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1359 int o;
1360 int i;
1361 bool input1, input2;
1362 u8 status;
1363
1364 intel_sdvo_set_active_outputs(intel_output, 0);
1365
1366 for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
1367 {
1368 u16 this_output = (1 << o);
1369 if (sdvo_priv->caps.output_flags & this_output) {
1370 intel_sdvo_set_target_output(intel_output, this_output);
1371 intel_sdvo_set_output_timing(intel_output, &sdvo_priv->save_output_dtd[o]);
1372 }
1373 }
1374
1375 if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
1376 intel_sdvo_set_target_input(intel_output, true, false);
1377 intel_sdvo_set_input_timing(intel_output, &sdvo_priv->save_input_dtd_1);
1378 }
1379
1380 if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
1381 intel_sdvo_set_target_input(intel_output, false, true);
1382 intel_sdvo_set_input_timing(intel_output, &sdvo_priv->save_input_dtd_2);
1383 }
1384
1385 intel_sdvo_set_clock_rate_mult(intel_output, sdvo_priv->save_sdvo_mult);
1386
e2f0ba97
JB		 1387 if (sdvo_priv->is_tv) {
1388 /* XXX: Restore TV format/enhancements. */
1389 }
1390
1391 intel_sdvo_write_sdvox(intel_output, sdvo_priv->save_SDVOX);
79e53945
JB		 1392
1393 if (sdvo_priv->save_SDVOX & SDVO_ENABLE)
1394 {
1395 for (i = 0; i < 2; i++)
1396 intel_wait_for_vblank(dev);
1397 status = intel_sdvo_get_trained_inputs(intel_output, &input1, &input2);
1398 if (status == SDVO_CMD_STATUS_SUCCESS && !input1)
8a4c47f3
ZY		 1399 DRM_DEBUG_KMS("First %s output reported failure to "
1400 "sync\n", SDVO_NAME(sdvo_priv));
79e53945
JB		 1401 }
1402
1403 intel_sdvo_set_active_outputs(intel_output, sdvo_priv->save_active_outputs);
1404}
1405
1406static int intel_sdvo_mode_valid(struct drm_connector *connector,
1407 struct drm_display_mode *mode)
1408{
1409 struct intel_output *intel_output = to_intel_output(connector);
1410 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1411
1412 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1413 return MODE_NO_DBLESCAN;
1414
1415 if (sdvo_priv->pixel_clock_min > mode->clock)
1416 return MODE_CLOCK_LOW;
1417
1418 if (sdvo_priv->pixel_clock_max < mode->clock)
1419 return MODE_CLOCK_HIGH;
1420
12682a97 1421 if (sdvo_priv->is_lvds == true) {
1422 if (sdvo_priv->sdvo_lvds_fixed_mode == NULL)
1423 return MODE_PANEL;
1424
1425 if (mode->hdisplay > sdvo_priv->sdvo_lvds_fixed_mode->hdisplay)
1426 return MODE_PANEL;
1427
1428 if (mode->vdisplay > sdvo_priv->sdvo_lvds_fixed_mode->vdisplay)
1429 return MODE_PANEL;
1430 }
1431
79e53945
JB		 1432 return MODE_OK;
1433}
1434
1435static bool intel_sdvo_get_capabilities(struct intel_output *intel_output, struct intel_sdvo_caps *caps)
1436{
1437 u8 status;
1438
1439 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_DEVICE_CAPS, NULL, 0);
1440 status = intel_sdvo_read_response(intel_output, caps, sizeof(*caps));
1441 if (status != SDVO_CMD_STATUS_SUCCESS)
1442 return false;
1443
1444 return true;
1445}
1446
1447struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB)
1448{
1449 struct drm_connector *connector = NULL;
1450 struct intel_output *iout = NULL;
1451 struct intel_sdvo_priv *sdvo;
1452
1453 /* find the sdvo connector */
1454 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1455 iout = to_intel_output(connector);
1456
1457 if (iout->type != INTEL_OUTPUT_SDVO)
1458 continue;
1459
1460 sdvo = iout->dev_priv;
1461
1462 if (sdvo->output_device == SDVOB && sdvoB)
1463 return connector;
1464
1465 if (sdvo->output_device == SDVOC && !sdvoB)
1466 return connector;
1467
1468 }
1469
1470 return NULL;
1471}
1472
1473int intel_sdvo_supports_hotplug(struct drm_connector *connector)
1474{
1475 u8 response[2];
1476 u8 status;
1477 struct intel_output *intel_output;
8a4c47f3 1478 DRM_DEBUG_KMS("\n");
79e53945
JB		 1479
1480 if (!connector)
1481 return 0;
1482
1483 intel_output = to_intel_output(connector);
1484
1485 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1486 status = intel_sdvo_read_response(intel_output, &response, 2);
1487
1488 if (response[0] !=0)
1489 return 1;
1490
1491 return 0;
1492}
1493
1494void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
1495{
1496 u8 response[2];
1497 u8 status;
1498 struct intel_output *intel_output = to_intel_output(connector);
1499
1500 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1501 intel_sdvo_read_response(intel_output, &response, 2);
1502
1503 if (on) {
1504 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1505 status = intel_sdvo_read_response(intel_output, &response, 2);
1506
1507 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1508 } else {
1509 response[0] = 0;
1510 response[1] = 0;
1511 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1512 }
1513
1514 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1515 intel_sdvo_read_response(intel_output, &response, 2);
1516}
1517
fb7a46f3 1518static bool
1519intel_sdvo_multifunc_encoder(struct intel_output *intel_output)
1520{
1521 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1522 int caps = 0;
1523
1524 if (sdvo_priv->caps.output_flags &
1525 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1))
1526 caps++;
1527 if (sdvo_priv->caps.output_flags &
1528 (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1))
1529 caps++;
1530 if (sdvo_priv->caps.output_flags &
19e1f888 1531 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_SVID1))
fb7a46f3 1532 caps++;
1533 if (sdvo_priv->caps.output_flags &
1534 (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_CVBS1))
1535 caps++;
1536 if (sdvo_priv->caps.output_flags &
1537 (SDVO_OUTPUT_YPRPB0 | SDVO_OUTPUT_YPRPB1))
1538 caps++;
1539
1540 if (sdvo_priv->caps.output_flags &
1541 (SDVO_OUTPUT_SCART0 | SDVO_OUTPUT_SCART1))
1542 caps++;
1543
1544 if (sdvo_priv->caps.output_flags &
1545 (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1))
1546 caps++;
1547
1548 return (caps > 1);
1549}
1550
57cdaf90
KP		 1551static struct drm_connector *
1552intel_find_analog_connector(struct drm_device *dev)
1553{
1554 struct drm_connector *connector;
1555 struct intel_output *intel_output;
1556
1557 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1558 intel_output = to_intel_output(connector);
1559 if (intel_output->type == INTEL_OUTPUT_ANALOG)
1560 return connector;
1561 }
1562 return NULL;
1563}
1564
1565static int
1566intel_analog_is_connected(struct drm_device *dev)
1567{
1568 struct drm_connector *analog_connector;
1569 analog_connector = intel_find_analog_connector(dev);
1570
1571 if (!analog_connector)
1572 return false;
1573
1574 if (analog_connector->funcs->detect(analog_connector) ==
1575 connector_status_disconnected)
1576 return false;
1577
1578 return true;
1579}
1580
2b8d33f7 1581enum drm_connector_status
1582intel_sdvo_hdmi_sink_detect(struct drm_connector *connector, u16 response)
9dff6af8
ML		 1583{
1584 struct intel_output *intel_output = to_intel_output(connector);
1585 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
2b8d33f7 1586 enum drm_connector_status status = connector_status_connected;
9dff6af8
ML		 1587 struct edid *edid = NULL;
1588
9dff6af8 1589 edid = drm_get_edid(&intel_output->base,
f9c10a9b 1590 intel_output->ddc_bus);
57cdaf90
KP		 1591
1592 /* when there is no edid and no monitor is connected with VGA
1593 * port, try to use the CRT ddc to read the EDID for DVI-connector
1594 */
1595 if (edid == NULL &&
1596 sdvo_priv->analog_ddc_bus &&
1597 !intel_analog_is_connected(intel_output->base.dev))
1598 edid = drm_get_edid(&intel_output->base,
1599 sdvo_priv->analog_ddc_bus);
9dff6af8 1600 if (edid != NULL) {
2b8d33f7 1601 /* Don't report the output as connected if it's a DVI-I
1602 * connector with a non-digital EDID coming out.
1603 */
1604 if (response & (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) {
1605 if (edid->input & DRM_EDID_INPUT_DIGITAL)
1606 sdvo_priv->is_hdmi =
1607 drm_detect_hdmi_monitor(edid);
1608 else
1609 status = connector_status_disconnected;
1610 }
1611
9dff6af8
ML		 1612 kfree(edid);
1613 intel_output->base.display_info.raw_edid = NULL;
2b8d33f7 1614
1615 } else if (response & (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1))
1616 status = connector_status_disconnected;
1617
1618 return status;
9dff6af8
ML		 1619}
1620
79e53945
JB		 1621static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector)
1622{
fb7a46f3 1623 uint16_t response;
79e53945
JB		 1624 u8 status;
1625 struct intel_output *intel_output = to_intel_output(connector);
fb7a46f3 1626 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
79e53945 1627
ce6feabd
ZY		 1628 intel_sdvo_write_cmd(intel_output,
1629 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0);
79e53945
JB		 1630 status = intel_sdvo_read_response(intel_output, &response, 2);
1631
51c8b407 1632 DRM_DEBUG_KMS("SDVO response %d %d\n", response & 0xff, response >> 8);
e2f0ba97
JB		 1633
1634 if (status != SDVO_CMD_STATUS_SUCCESS)
1635 return connector_status_unknown;
1636
fb7a46f3 1637 if (response == 0)
79e53945 1638 return connector_status_disconnected;
fb7a46f3 1639
1640 if (intel_sdvo_multifunc_encoder(intel_output) &&
1641 sdvo_priv->attached_output != response) {
1642 if (sdvo_priv->controlled_output != response &&
1643 intel_sdvo_output_setup(intel_output, response) != true)
1644 return connector_status_unknown;
1645 sdvo_priv->attached_output = response;
1646 }
2b8d33f7 1647 return intel_sdvo_hdmi_sink_detect(connector, response);
79e53945
JB		 1648}
1649
e2f0ba97 1650static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945
JB		 1651{
1652 struct intel_output *intel_output = to_intel_output(connector);
57cdaf90
KP		 1653 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1654 int num_modes;
79e53945
JB		 1655
1656 /* set the bus switch and get the modes */
57cdaf90 1657 num_modes = intel_ddc_get_modes(intel_output);
79e53945 1658
57cdaf90
KP		 1659 /*
1660 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1661 * link between analog and digital outputs. So, if the regular SDVO
1662 * DDC fails, check to see if the analog output is disconnected, in
1663 * which case we'll look there for the digital DDC data.
e2f0ba97 1664 */
57cdaf90
KP		 1665 if (num_modes == 0 &&
1666 sdvo_priv->analog_ddc_bus &&
1667 !intel_analog_is_connected(intel_output->base.dev)) {
1668 struct i2c_adapter *digital_ddc_bus;
e2f0ba97 1669
57cdaf90
KP		 1670 /* Switch to the analog ddc bus and try that
1671 */
1672 digital_ddc_bus = intel_output->ddc_bus;
1673 intel_output->ddc_bus = sdvo_priv->analog_ddc_bus;
e2f0ba97 1674
57cdaf90 1675 (void) intel_ddc_get_modes(intel_output);
e2f0ba97 1676
57cdaf90 1677 intel_output->ddc_bus = digital_ddc_bus;
e2f0ba97 1678 }
e2f0ba97
JB		 1679}
1680
1681/*
1682 * Set of SDVO TV modes.
1683 * Note! This is in reply order (see loop in get_tv_modes).
1684 * XXX: all 60Hz refresh?
1685 */
1686struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1687 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1688 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1689 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1690 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1691 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1692 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1693 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1694 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1695 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1696 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1697 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1698 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1699 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1700 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1701 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1702 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1703 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1704 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1705 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1706 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1707 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1708 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1709 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1710 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1711 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1712 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1713 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1714 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1715 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1716 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1717 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1718 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1719 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1720 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1721 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1722 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1723 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1724 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1725 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1726 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1727 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1728 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1729 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1730 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1731 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1732 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1733 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1734 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1735 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1736 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1737 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1738 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1739 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1740 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1741 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1742 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1743 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1744};
1745
1746static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1747{
1748 struct intel_output *output = to_intel_output(connector);
7026d4ac
ZW		 1749 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1750 struct intel_sdvo_sdtv_resolution_request tv_res;
ce6feabd
ZY		 1751 uint32_t reply = 0, format_map = 0;
1752 int i;
e2f0ba97 1753 uint8_t status;
e2f0ba97 1754
e2f0ba97
JB		 1755
1756 /* Read the list of supported input resolutions for the selected TV
1757 * format.
1758 */
ce6feabd
ZY		 1759 for (i = 0; i < TV_FORMAT_NUM; i++)
1760 if (tv_format_names[i] == sdvo_priv->tv_format_name)
1761 break;
1762
1763 format_map = (1 << i);
1764 memcpy(&tv_res, &format_map,
1765 sizeof(struct intel_sdvo_sdtv_resolution_request) >
1766 sizeof(format_map) ? sizeof(format_map) :
1767 sizeof(struct intel_sdvo_sdtv_resolution_request));
1768
1769 intel_sdvo_set_target_output(output, sdvo_priv->controlled_output);
1770
e2f0ba97 1771 intel_sdvo_write_cmd(output, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
7026d4ac 1772 &tv_res, sizeof(tv_res));
e2f0ba97
JB		 1773 status = intel_sdvo_read_response(output, &reply, 3);
1774 if (status != SDVO_CMD_STATUS_SUCCESS)
1775 return;
1776
1777 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 1778 if (reply & (1 << i)) {
1779 struct drm_display_mode *nmode;
1780 nmode = drm_mode_duplicate(connector->dev,
1781 &sdvo_tv_modes[i]);
1782 if (nmode)
1783 drm_mode_probed_add(connector, nmode);
1784 }
ce6feabd 1785
e2f0ba97
JB		 1786}
1787
7086c87f
ML		 1788static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1789{
1790 struct intel_output *intel_output = to_intel_output(connector);
7086c87f 1791 struct drm_i915_private *dev_priv = connector->dev->dev_private;
12682a97 1792 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1793 struct drm_display_mode *newmode;
7086c87f
ML		 1794
1795 /*
1796 * Attempt to get the mode list from DDC.
1797 * Assume that the preferred modes are
1798 * arranged in priority order.
1799 */
7086c87f
ML		 1800 intel_ddc_get_modes(intel_output);
1801 if (list_empty(&connector->probed_modes) == false)
12682a97 1802 goto end;
7086c87f
ML		 1803
1804 /* Fetch modes from VBT */
1805 if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
7086c87f
ML		 1806 newmode = drm_mode_duplicate(connector->dev,
1807 dev_priv->sdvo_lvds_vbt_mode);
1808 if (newmode != NULL) {
1809 /* Guarantee the mode is preferred */
1810 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1811 DRM_MODE_TYPE_DRIVER);
1812 drm_mode_probed_add(connector, newmode);
1813 }
1814 }
12682a97 1815
1816end:
1817 list_for_each_entry(newmode, &connector->probed_modes, head) {
1818 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1819 sdvo_priv->sdvo_lvds_fixed_mode =
1820 drm_mode_duplicate(connector->dev, newmode);
1821 break;
1822 }
1823 }
1824
7086c87f
ML		 1825}
1826
e2f0ba97
JB		 1827static int intel_sdvo_get_modes(struct drm_connector *connector)
1828{
1829 struct intel_output *output = to_intel_output(connector);
1830 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1831
1832 if (sdvo_priv->is_tv)
1833 intel_sdvo_get_tv_modes(connector);
7086c87f
ML		 1834 else if (sdvo_priv->is_lvds == true)
1835 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 1836 else
1837 intel_sdvo_get_ddc_modes(connector);
1838
79e53945
JB		 1839 if (list_empty(&connector->probed_modes))
1840 return 0;
1841 return 1;
1842}
1843
b9219c5e
ZY		 1844static
1845void intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
1846{
1847 struct intel_output *intel_output = to_intel_output(connector);
1848 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1849 struct drm_device *dev = connector->dev;
1850
1851 if (sdvo_priv->is_tv) {
1852 if (sdvo_priv->left_property)
1853 drm_property_destroy(dev, sdvo_priv->left_property);
1854 if (sdvo_priv->right_property)
1855 drm_property_destroy(dev, sdvo_priv->right_property);
1856 if (sdvo_priv->top_property)
1857 drm_property_destroy(dev, sdvo_priv->top_property);
1858 if (sdvo_priv->bottom_property)
1859 drm_property_destroy(dev, sdvo_priv->bottom_property);
1860 if (sdvo_priv->hpos_property)
1861 drm_property_destroy(dev, sdvo_priv->hpos_property);
1862 if (sdvo_priv->vpos_property)
1863 drm_property_destroy(dev, sdvo_priv->vpos_property);
1864 }
1865 if (sdvo_priv->is_tv) {
1866 if (sdvo_priv->saturation_property)
1867 drm_property_destroy(dev,
1868 sdvo_priv->saturation_property);
1869 if (sdvo_priv->contrast_property)
1870 drm_property_destroy(dev,
1871 sdvo_priv->contrast_property);
1872 if (sdvo_priv->hue_property)
1873 drm_property_destroy(dev, sdvo_priv->hue_property);
1874 }
d0cbde93 1875 if (sdvo_priv->is_tv || sdvo_priv->is_lvds) {
b9219c5e
ZY		 1876 if (sdvo_priv->brightness_property)
1877 drm_property_destroy(dev,
1878 sdvo_priv->brightness_property);
1879 }
1880 return;
1881}
1882
79e53945
JB		 1883static void intel_sdvo_destroy(struct drm_connector *connector)
1884{
1885 struct intel_output *intel_output = to_intel_output(connector);
12682a97 1886 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
79e53945
JB		 1887
1888 if (intel_output->i2c_bus)
1889 intel_i2c_destroy(intel_output->i2c_bus);
619ac3b7
ML		 1890 if (intel_output->ddc_bus)
1891 intel_i2c_destroy(intel_output->ddc_bus);
57cdaf90
KP		 1892 if (sdvo_priv->analog_ddc_bus)
1893 intel_i2c_destroy(sdvo_priv->analog_ddc_bus);
619ac3b7 1894
12682a97 1895 if (sdvo_priv->sdvo_lvds_fixed_mode != NULL)
1896 drm_mode_destroy(connector->dev,
1897 sdvo_priv->sdvo_lvds_fixed_mode);
1898
ce6feabd
ZY		 1899 if (sdvo_priv->tv_format_property)
1900 drm_property_destroy(connector->dev,
1901 sdvo_priv->tv_format_property);
1902
d0cbde93 1903 if (sdvo_priv->is_tv || sdvo_priv->is_lvds)
b9219c5e
ZY		 1904 intel_sdvo_destroy_enhance_property(connector);
1905
79e53945
JB		 1906 drm_sysfs_connector_remove(connector);
1907 drm_connector_cleanup(connector);
12682a97 1908
79e53945
JB		 1909 kfree(intel_output);
1910}
1911
ce6feabd
ZY		 1912static int
1913intel_sdvo_set_property(struct drm_connector *connector,
1914 struct drm_property *property,
1915 uint64_t val)
1916{
1917 struct intel_output *intel_output = to_intel_output(connector);
1918 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1919 struct drm_encoder *encoder = &intel_output->enc;
1920 struct drm_crtc *crtc = encoder->crtc;
1921 int ret = 0;
1922 bool changed = false;
b9219c5e
ZY		 1923 uint8_t cmd, status;
1924 uint16_t temp_value;
ce6feabd
ZY		 1925
1926 ret = drm_connector_property_set_value(connector, property, val);
1927 if (ret < 0)
1928 goto out;
1929
1930 if (property == sdvo_priv->tv_format_property) {
1931 if (val >= TV_FORMAT_NUM) {
1932 ret = -EINVAL;
1933 goto out;
1934 }
1935 if (sdvo_priv->tv_format_name ==
1936 sdvo_priv->tv_format_supported[val])
1937 goto out;
1938
1939 sdvo_priv->tv_format_name = sdvo_priv->tv_format_supported[val];
1940 changed = true;
ce6feabd
ZY		 1941 }
1942
d0cbde93 1943 if (sdvo_priv->is_tv || sdvo_priv->is_lvds) {
b9219c5e
ZY		 1944 cmd = 0;
1945 temp_value = val;
1946 if (sdvo_priv->left_property == property) {
1947 drm_connector_property_set_value(connector,
1948 sdvo_priv->right_property, val);
1949 if (sdvo_priv->left_margin == temp_value)
1950 goto out;
1951
1952 sdvo_priv->left_margin = temp_value;
1953 sdvo_priv->right_margin = temp_value;
1954 temp_value = sdvo_priv->max_hscan -
1955 sdvo_priv->left_margin;
1956 cmd = SDVO_CMD_SET_OVERSCAN_H;
1957 } else if (sdvo_priv->right_property == property) {
1958 drm_connector_property_set_value(connector,
1959 sdvo_priv->left_property, val);
1960 if (sdvo_priv->right_margin == temp_value)
1961 goto out;
1962
1963 sdvo_priv->left_margin = temp_value;
1964 sdvo_priv->right_margin = temp_value;
1965 temp_value = sdvo_priv->max_hscan -
1966 sdvo_priv->left_margin;
1967 cmd = SDVO_CMD_SET_OVERSCAN_H;
1968 } else if (sdvo_priv->top_property == property) {
1969 drm_connector_property_set_value(connector,
1970 sdvo_priv->bottom_property, val);
1971 if (sdvo_priv->top_margin == temp_value)
1972 goto out;
1973
1974 sdvo_priv->top_margin = temp_value;
1975 sdvo_priv->bottom_margin = temp_value;
1976 temp_value = sdvo_priv->max_vscan -
1977 sdvo_priv->top_margin;
1978 cmd = SDVO_CMD_SET_OVERSCAN_V;
1979 } else if (sdvo_priv->bottom_property == property) {
1980 drm_connector_property_set_value(connector,
1981 sdvo_priv->top_property, val);
1982 if (sdvo_priv->bottom_margin == temp_value)
1983 goto out;
1984 sdvo_priv->top_margin = temp_value;
1985 sdvo_priv->bottom_margin = temp_value;
1986 temp_value = sdvo_priv->max_vscan -
1987 sdvo_priv->top_margin;
1988 cmd = SDVO_CMD_SET_OVERSCAN_V;
1989 } else if (sdvo_priv->hpos_property == property) {
1990 if (sdvo_priv->cur_hpos == temp_value)
1991 goto out;
1992
1993 cmd = SDVO_CMD_SET_POSITION_H;
1994 sdvo_priv->cur_hpos = temp_value;
1995 } else if (sdvo_priv->vpos_property == property) {
1996 if (sdvo_priv->cur_vpos == temp_value)
1997 goto out;
1998
1999 cmd = SDVO_CMD_SET_POSITION_V;
2000 sdvo_priv->cur_vpos = temp_value;
2001 } else if (sdvo_priv->saturation_property == property) {
2002 if (sdvo_priv->cur_saturation == temp_value)
2003 goto out;
2004
2005 cmd = SDVO_CMD_SET_SATURATION;
2006 sdvo_priv->cur_saturation = temp_value;
2007 } else if (sdvo_priv->contrast_property == property) {
2008 if (sdvo_priv->cur_contrast == temp_value)
2009 goto out;
2010
2011 cmd = SDVO_CMD_SET_CONTRAST;
2012 sdvo_priv->cur_contrast = temp_value;
2013 } else if (sdvo_priv->hue_property == property) {
2014 if (sdvo_priv->cur_hue == temp_value)
2015 goto out;
2016
2017 cmd = SDVO_CMD_SET_HUE;
2018 sdvo_priv->cur_hue = temp_value;
2019 } else if (sdvo_priv->brightness_property == property) {
2020 if (sdvo_priv->cur_brightness == temp_value)
2021 goto out;
2022
2023 cmd = SDVO_CMD_SET_BRIGHTNESS;
2024 sdvo_priv->cur_brightness = temp_value;
2025 }
2026 if (cmd) {
2027 intel_sdvo_write_cmd(intel_output, cmd, &temp_value, 2);
2028 status = intel_sdvo_read_response(intel_output,
2029 NULL, 0);
2030 if (status != SDVO_CMD_STATUS_SUCCESS) {
2031 DRM_DEBUG_KMS("Incorrect SDVO command \n");
2032 return -EINVAL;
2033 }
2034 changed = true;
2035 }
2036 }
ce6feabd
ZY		 2037 if (changed && crtc)
2038 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
2039 crtc->y, crtc->fb);
2040out:
2041 return ret;
2042}
2043
79e53945
JB		 2044static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
2045 .dpms = intel_sdvo_dpms,
2046 .mode_fixup = intel_sdvo_mode_fixup,
2047 .prepare = intel_encoder_prepare,
2048 .mode_set = intel_sdvo_mode_set,
2049 .commit = intel_encoder_commit,
2050};
2051
2052static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
c9fb15f6 2053 .dpms = drm_helper_connector_dpms,
79e53945
JB		 2054 .save = intel_sdvo_save,
2055 .restore = intel_sdvo_restore,
2056 .detect = intel_sdvo_detect,
2057 .fill_modes = drm_helper_probe_single_connector_modes,
ce6feabd 2058 .set_property = intel_sdvo_set_property,
79e53945
JB		 2059 .destroy = intel_sdvo_destroy,
2060};
2061
2062static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
2063 .get_modes = intel_sdvo_get_modes,
2064 .mode_valid = intel_sdvo_mode_valid,
2065 .best_encoder = intel_best_encoder,
2066};
2067
b358d0a6 2068static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945
JB		 2069{
2070 drm_encoder_cleanup(encoder);
2071}
2072
2073static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
2074 .destroy = intel_sdvo_enc_destroy,
2075};
2076
2077
e2f0ba97
JB		 2078/**
2079 * Choose the appropriate DDC bus for control bus switch command for this
2080 * SDVO output based on the controlled output.
2081 *
2082 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
2083 * outputs, then LVDS outputs.
2084 */
2085static void
2086intel_sdvo_select_ddc_bus(struct intel_sdvo_priv *dev_priv)
2087{
2088 uint16_t mask = 0;
2089 unsigned int num_bits;
2090
2091 /* Make a mask of outputs less than or equal to our own priority in the
2092 * list.
2093 */
2094 switch (dev_priv->controlled_output) {
2095 case SDVO_OUTPUT_LVDS1:
2096 mask |= SDVO_OUTPUT_LVDS1;
2097 case SDVO_OUTPUT_LVDS0:
2098 mask |= SDVO_OUTPUT_LVDS0;
2099 case SDVO_OUTPUT_TMDS1:
2100 mask |= SDVO_OUTPUT_TMDS1;
2101 case SDVO_OUTPUT_TMDS0:
2102 mask |= SDVO_OUTPUT_TMDS0;
2103 case SDVO_OUTPUT_RGB1:
2104 mask |= SDVO_OUTPUT_RGB1;
2105 case SDVO_OUTPUT_RGB0:
2106 mask |= SDVO_OUTPUT_RGB0;
2107 break;
2108 }
2109
2110 /* Count bits to find what number we are in the priority list. */
2111 mask &= dev_priv->caps.output_flags;
2112 num_bits = hweight16(mask);
2113 if (num_bits > 3) {
2114 /* if more than 3 outputs, default to DDC bus 3 for now */
2115 num_bits = 3;
2116 }
2117
2118 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
2119 dev_priv->ddc_bus = 1 << num_bits;
2120}
2121
2122static bool
2123intel_sdvo_get_digital_encoding_mode(struct intel_output *output)
2124{
2125 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
2126 uint8_t status;
2127
2128 intel_sdvo_set_target_output(output, sdvo_priv->controlled_output);
2129
2130 intel_sdvo_write_cmd(output, SDVO_CMD_GET_ENCODE, NULL, 0);
2131 status = intel_sdvo_read_response(output, &sdvo_priv->is_hdmi, 1);
2132 if (status != SDVO_CMD_STATUS_SUCCESS)
2133 return false;
2134 return true;
2135}
2136
619ac3b7
ML		 2137static struct intel_output *
2138intel_sdvo_chan_to_intel_output(struct intel_i2c_chan *chan)
2139{
2140 struct drm_device *dev = chan->drm_dev;
2141 struct drm_connector *connector;
2142 struct intel_output *intel_output = NULL;
2143
2144 list_for_each_entry(connector,
2145 &dev->mode_config.connector_list, head) {
f9c10a9b 2146 if (to_intel_output(connector)->ddc_bus == &chan->adapter) {
619ac3b7
ML		 2147 intel_output = to_intel_output(connector);
2148 break;
2149 }
2150 }
2151 return intel_output;
2152}
2153
2154static int intel_sdvo_master_xfer(struct i2c_adapter *i2c_adap,
2155 struct i2c_msg msgs[], int num)
2156{
2157 struct intel_output *intel_output;
2158 struct intel_sdvo_priv *sdvo_priv;
2159 struct i2c_algo_bit_data *algo_data;
f9c10a9b 2160 const struct i2c_algorithm *algo;
619ac3b7
ML		 2161
2162 algo_data = (struct i2c_algo_bit_data *)i2c_adap->algo_data;
2163 intel_output =
2164 intel_sdvo_chan_to_intel_output(
2165 (struct intel_i2c_chan *)(algo_data->data));
2166 if (intel_output == NULL)
2167 return -EINVAL;
2168
2169 sdvo_priv = intel_output->dev_priv;
f9c10a9b 2170 algo = intel_output->i2c_bus->algo;
619ac3b7
ML		 2171
2172 intel_sdvo_set_control_bus_switch(intel_output, sdvo_priv->ddc_bus);
2173 return algo->master_xfer(i2c_adap, msgs, num);
2174}
2175
2176static struct i2c_algorithm intel_sdvo_i2c_bit_algo = {
2177 .master_xfer = intel_sdvo_master_xfer,
2178};
2179
714605e4 2180static u8
2181intel_sdvo_get_slave_addr(struct drm_device *dev, int output_device)
2182{
2183 struct drm_i915_private *dev_priv = dev->dev_private;
2184 struct sdvo_device_mapping *my_mapping, *other_mapping;
2185
2186 if (output_device == SDVOB) {
2187 my_mapping = &dev_priv->sdvo_mappings[0];
2188 other_mapping = &dev_priv->sdvo_mappings[1];
2189 } else {
2190 my_mapping = &dev_priv->sdvo_mappings[1];
2191 other_mapping = &dev_priv->sdvo_mappings[0];
2192 }
2193
2194 /* If the BIOS described our SDVO device, take advantage of it. */
2195 if (my_mapping->slave_addr)
2196 return my_mapping->slave_addr;
2197
2198 /* If the BIOS only described a different SDVO device, use the
2199 * address that it isn't using.
2200 */
2201 if (other_mapping->slave_addr) {
2202 if (other_mapping->slave_addr == 0x70)
2203 return 0x72;
2204 else
2205 return 0x70;
2206 }
2207
2208 /* No SDVO device info is found for another DVO port,
2209 * so use mapping assumption we had before BIOS parsing.
2210 */
2211 if (output_device == SDVOB)
2212 return 0x70;
2213 else
2214 return 0x72;
2215}
2216
fb7a46f3 2217static bool
2218intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags)
2219{
2220 struct drm_connector *connector = &intel_output->base;
2221 struct drm_encoder *encoder = &intel_output->enc;
2222 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
2223 bool ret = true, registered = false;
2224
2225 sdvo_priv->is_tv = false;
2226 intel_output->needs_tv_clock = false;
2227 sdvo_priv->is_lvds = false;
2228
2229 if (device_is_registered(&connector->kdev)) {
2230 drm_sysfs_connector_remove(connector);
2231 registered = true;
2232 }
2233
2234 if (flags &
2235 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) {
2236 if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_TMDS0)
2237 sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS0;
2238 else
2239 sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS1;
2240
2241 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2242 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2243
2244 if (intel_sdvo_get_supp_encode(intel_output,
2245 &sdvo_priv->encode) &&
2246 intel_sdvo_get_digital_encoding_mode(intel_output) &&
2247 sdvo_priv->is_hdmi) {
2248 /* enable hdmi encoding mode if supported */
2249 intel_sdvo_set_encode(intel_output, SDVO_ENCODE_HDMI);
2250 intel_sdvo_set_colorimetry(intel_output,
2251 SDVO_COLORIMETRY_RGB256);
2252 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
f8aed700
ML		 2253 intel_output->clone_mask =
2254 (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2255 (1 << INTEL_ANALOG_CLONE_BIT);
fb7a46f3 2256 }
2257 } else if (flags & SDVO_OUTPUT_SVID0) {
2258
2259 sdvo_priv->controlled_output = SDVO_OUTPUT_SVID0;
2260 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2261 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
2262 sdvo_priv->is_tv = true;
2263 intel_output->needs_tv_clock = true;
f8aed700 2264 intel_output->clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
fb7a46f3 2265 } else if (flags & SDVO_OUTPUT_RGB0) {
2266
2267 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB0;
2268 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2269 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
f8aed700
ML		 2270 intel_output->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2271 (1 << INTEL_ANALOG_CLONE_BIT);
fb7a46f3 2272 } else if (flags & SDVO_OUTPUT_RGB1) {
2273
2274 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB1;
2275 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2276 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2277 } else if (flags & SDVO_OUTPUT_LVDS0) {
2278
2279 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS0;
2280 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2281 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2282 sdvo_priv->is_lvds = true;
f8aed700
ML		 2283 intel_output->clone_mask = (1 << INTEL_ANALOG_CLONE_BIT) |
2284 (1 << INTEL_SDVO_LVDS_CLONE_BIT);
fb7a46f3 2285 } else if (flags & SDVO_OUTPUT_LVDS1) {
2286
2287 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS1;
2288 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2289 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2290 sdvo_priv->is_lvds = true;
f8aed700
ML		 2291 intel_output->clone_mask = (1 << INTEL_ANALOG_CLONE_BIT) |
2292 (1 << INTEL_SDVO_LVDS_CLONE_BIT);
fb7a46f3 2293 } else {
2294
2295 unsigned char bytes[2];
2296
2297 sdvo_priv->controlled_output = 0;
2298 memcpy(bytes, &sdvo_priv->caps.output_flags, 2);
51c8b407
DA		 2299 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
2300 SDVO_NAME(sdvo_priv),
2301 bytes[0], bytes[1]);
fb7a46f3 2302 ret = false;
2303 }
f8aed700 2304 intel_output->crtc_mask = (1 << 0) | (1 << 1);
fb7a46f3 2305
2306 if (ret && registered)
2307 ret = drm_sysfs_connector_add(connector) == 0 ? true : false;
2308
2309
2310 return ret;
2311
2312}
2313
ce6feabd
ZY		 2314static void intel_sdvo_tv_create_property(struct drm_connector *connector)
2315{
2316 struct intel_output *intel_output = to_intel_output(connector);
2317 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
2318 struct intel_sdvo_tv_format format;
2319 uint32_t format_map, i;
2320 uint8_t status;
2321
2322 intel_sdvo_set_target_output(intel_output,
2323 sdvo_priv->controlled_output);
2324
2325 intel_sdvo_write_cmd(intel_output,
2326 SDVO_CMD_GET_SUPPORTED_TV_FORMATS, NULL, 0);
2327 status = intel_sdvo_read_response(intel_output,
2328 &format, sizeof(format));
2329 if (status != SDVO_CMD_STATUS_SUCCESS)
2330 return;
2331
2332 memcpy(&format_map, &format, sizeof(format) > sizeof(format_map) ?
2333 sizeof(format_map) : sizeof(format));
2334
2335 if (format_map == 0)
2336 return;
2337
2338 sdvo_priv->format_supported_num = 0;
2339 for (i = 0 ; i < TV_FORMAT_NUM; i++)
2340 if (format_map & (1 << i)) {
2341 sdvo_priv->tv_format_supported
2342 [sdvo_priv->format_supported_num++] =
2343 tv_format_names[i];
2344 }
2345
2346
2347 sdvo_priv->tv_format_property =
2348 drm_property_create(
2349 connector->dev, DRM_MODE_PROP_ENUM,
2350 "mode", sdvo_priv->format_supported_num);
2351
2352 for (i = 0; i < sdvo_priv->format_supported_num; i++)
2353 drm_property_add_enum(
2354 sdvo_priv->tv_format_property, i,
2355 i, sdvo_priv->tv_format_supported[i]);
2356
2357 sdvo_priv->tv_format_name = sdvo_priv->tv_format_supported[0];
2358 drm_connector_attach_property(
2359 connector, sdvo_priv->tv_format_property, 0);
2360
2361}
2362
b9219c5e
ZY		 2363static void intel_sdvo_create_enhance_property(struct drm_connector *connector)
2364{
2365 struct intel_output *intel_output = to_intel_output(connector);
2366 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
2367 struct intel_sdvo_enhancements_reply sdvo_data;
2368 struct drm_device *dev = connector->dev;
2369 uint8_t status;
2370 uint16_t response, data_value[2];
2371
2372 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2373 NULL, 0);
2374 status = intel_sdvo_read_response(intel_output, &sdvo_data,
2375 sizeof(sdvo_data));
2376 if (status != SDVO_CMD_STATUS_SUCCESS) {
2377 DRM_DEBUG_KMS(" incorrect response is returned\n");
2378 return;
2379 }
2380 response = *((uint16_t *)&sdvo_data);
2381 if (!response) {
2382 DRM_DEBUG_KMS("No enhancement is supported\n");
2383 return;
2384 }
2385 if (sdvo_priv->is_tv) {
2386 /* when horizontal overscan is supported, Add the left/right
2387 * property
2388 */
2389 if (sdvo_data.overscan_h) {
2390 intel_sdvo_write_cmd(intel_output,
2391 SDVO_CMD_GET_MAX_OVERSCAN_H, NULL, 0);
2392 status = intel_sdvo_read_response(intel_output,
2393 &data_value, 4);
2394 if (status != SDVO_CMD_STATUS_SUCCESS) {
2395 DRM_DEBUG_KMS("Incorrect SDVO max "
2396 "h_overscan\n");
2397 return;
2398 }
2399 intel_sdvo_write_cmd(intel_output,
2400 SDVO_CMD_GET_OVERSCAN_H, NULL, 0);
2401 status = intel_sdvo_read_response(intel_output,
2402 &response, 2);
2403 if (status != SDVO_CMD_STATUS_SUCCESS) {
2404 DRM_DEBUG_KMS("Incorrect SDVO h_overscan\n");
2405 return;
2406 }
2407 sdvo_priv->max_hscan = data_value[0];
2408 sdvo_priv->left_margin = data_value[0] - response;
2409 sdvo_priv->right_margin = sdvo_priv->left_margin;
2410 sdvo_priv->left_property =
2411 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2412 "left_margin", 2);
2413 sdvo_priv->left_property->values[0] = 0;
2414 sdvo_priv->left_property->values[1] = data_value[0];
2415 drm_connector_attach_property(connector,
2416 sdvo_priv->left_property,
2417 sdvo_priv->left_margin);
2418 sdvo_priv->right_property =
2419 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2420 "right_margin", 2);
2421 sdvo_priv->right_property->values[0] = 0;
2422 sdvo_priv->right_property->values[1] = data_value[0];
2423 drm_connector_attach_property(connector,
2424 sdvo_priv->right_property,
2425 sdvo_priv->right_margin);
2426 DRM_DEBUG_KMS("h_overscan: max %d, "
2427 "default %d, current %d\n",
2428 data_value[0], data_value[1], response);
2429 }
2430 if (sdvo_data.overscan_v) {
2431 intel_sdvo_write_cmd(intel_output,
2432 SDVO_CMD_GET_MAX_OVERSCAN_V, NULL, 0);
2433 status = intel_sdvo_read_response(intel_output,
2434 &data_value, 4);
2435 if (status != SDVO_CMD_STATUS_SUCCESS) {
2436 DRM_DEBUG_KMS("Incorrect SDVO max "
2437 "v_overscan\n");
2438 return;
2439 }
2440 intel_sdvo_write_cmd(intel_output,
2441 SDVO_CMD_GET_OVERSCAN_V, NULL, 0);
2442 status = intel_sdvo_read_response(intel_output,
2443 &response, 2);
2444 if (status != SDVO_CMD_STATUS_SUCCESS) {
2445 DRM_DEBUG_KMS("Incorrect SDVO v_overscan\n");
2446 return;
2447 }
2448 sdvo_priv->max_vscan = data_value[0];
2449 sdvo_priv->top_margin = data_value[0] - response;
2450 sdvo_priv->bottom_margin = sdvo_priv->top_margin;
2451 sdvo_priv->top_property =
2452 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2453 "top_margin", 2);
2454 sdvo_priv->top_property->values[0] = 0;
2455 sdvo_priv->top_property->values[1] = data_value[0];
2456 drm_connector_attach_property(connector,
2457 sdvo_priv->top_property,
2458 sdvo_priv->top_margin);
2459 sdvo_priv->bottom_property =
2460 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2461 "bottom_margin", 2);
2462 sdvo_priv->bottom_property->values[0] = 0;
2463 sdvo_priv->bottom_property->values[1] = data_value[0];
2464 drm_connector_attach_property(connector,
2465 sdvo_priv->bottom_property,
2466 sdvo_priv->bottom_margin);
2467 DRM_DEBUG_KMS("v_overscan: max %d, "
2468 "default %d, current %d\n",
2469 data_value[0], data_value[1], response);
2470 }
2471 if (sdvo_data.position_h) {
2472 intel_sdvo_write_cmd(intel_output,
2473 SDVO_CMD_GET_MAX_POSITION_H, NULL, 0);
2474 status = intel_sdvo_read_response(intel_output,
2475 &data_value, 4);
2476 if (status != SDVO_CMD_STATUS_SUCCESS) {
2477 DRM_DEBUG_KMS("Incorrect SDVO Max h_pos\n");
2478 return;
2479 }
2480 intel_sdvo_write_cmd(intel_output,
2481 SDVO_CMD_GET_POSITION_H, NULL, 0);
2482 status = intel_sdvo_read_response(intel_output,
2483 &response, 2);
2484 if (status != SDVO_CMD_STATUS_SUCCESS) {
2485 DRM_DEBUG_KMS("Incorrect SDVO get h_postion\n");
2486 return;
2487 }
2488 sdvo_priv->max_hpos = data_value[0];
2489 sdvo_priv->cur_hpos = response;
2490 sdvo_priv->hpos_property =
2491 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2492 "hpos", 2);
2493 sdvo_priv->hpos_property->values[0] = 0;
2494 sdvo_priv->hpos_property->values[1] = data_value[0];
2495 drm_connector_attach_property(connector,
2496 sdvo_priv->hpos_property,
2497 sdvo_priv->cur_hpos);
2498 DRM_DEBUG_KMS("h_position: max %d, "
2499 "default %d, current %d\n",
2500 data_value[0], data_value[1], response);
2501 }
2502 if (sdvo_data.position_v) {
2503 intel_sdvo_write_cmd(intel_output,
2504 SDVO_CMD_GET_MAX_POSITION_V, NULL, 0);
2505 status = intel_sdvo_read_response(intel_output,
2506 &data_value, 4);
2507 if (status != SDVO_CMD_STATUS_SUCCESS) {
2508 DRM_DEBUG_KMS("Incorrect SDVO Max v_pos\n");
2509 return;
2510 }
2511 intel_sdvo_write_cmd(intel_output,
2512 SDVO_CMD_GET_POSITION_V, NULL, 0);
2513 status = intel_sdvo_read_response(intel_output,
2514 &response, 2);
2515 if (status != SDVO_CMD_STATUS_SUCCESS) {
2516 DRM_DEBUG_KMS("Incorrect SDVO get v_postion\n");
2517 return;
2518 }
2519 sdvo_priv->max_vpos = data_value[0];
2520 sdvo_priv->cur_vpos = response;
2521 sdvo_priv->vpos_property =
2522 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2523 "vpos", 2);
2524 sdvo_priv->vpos_property->values[0] = 0;
2525 sdvo_priv->vpos_property->values[1] = data_value[0];
2526 drm_connector_attach_property(connector,
2527 sdvo_priv->vpos_property,
2528 sdvo_priv->cur_vpos);
2529 DRM_DEBUG_KMS("v_position: max %d, "
2530 "default %d, current %d\n",
2531 data_value[0], data_value[1], response);
2532 }
2533 }
2534 if (sdvo_priv->is_tv) {
2535 if (sdvo_data.saturation) {
2536 intel_sdvo_write_cmd(intel_output,
2537 SDVO_CMD_GET_MAX_SATURATION, NULL, 0);
2538 status = intel_sdvo_read_response(intel_output,
2539 &data_value, 4);
2540 if (status != SDVO_CMD_STATUS_SUCCESS) {
2541 DRM_DEBUG_KMS("Incorrect SDVO Max sat\n");
2542 return;
2543 }
2544 intel_sdvo_write_cmd(intel_output,
2545 SDVO_CMD_GET_SATURATION, NULL, 0);
2546 status = intel_sdvo_read_response(intel_output,
2547 &response, 2);
2548 if (status != SDVO_CMD_STATUS_SUCCESS) {
2549 DRM_DEBUG_KMS("Incorrect SDVO get sat\n");
2550 return;
2551 }
2552 sdvo_priv->max_saturation = data_value[0];
2553 sdvo_priv->cur_saturation = response;
2554 sdvo_priv->saturation_property =
2555 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2556 "saturation", 2);
2557 sdvo_priv->saturation_property->values[0] = 0;
2558 sdvo_priv->saturation_property->values[1] =
2559 data_value[0];
2560 drm_connector_attach_property(connector,
2561 sdvo_priv->saturation_property,
2562 sdvo_priv->cur_saturation);
2563 DRM_DEBUG_KMS("saturation: max %d, "
2564 "default %d, current %d\n",
2565 data_value[0], data_value[1], response);
2566 }
2567 if (sdvo_data.contrast) {
2568 intel_sdvo_write_cmd(intel_output,
2569 SDVO_CMD_GET_MAX_CONTRAST, NULL, 0);
2570 status = intel_sdvo_read_response(intel_output,
2571 &data_value, 4);
2572 if (status != SDVO_CMD_STATUS_SUCCESS) {
2573 DRM_DEBUG_KMS("Incorrect SDVO Max contrast\n");
2574 return;
2575 }
2576 intel_sdvo_write_cmd(intel_output,
2577 SDVO_CMD_GET_CONTRAST, NULL, 0);
2578 status = intel_sdvo_read_response(intel_output,
2579 &response, 2);
2580 if (status != SDVO_CMD_STATUS_SUCCESS) {
2581 DRM_DEBUG_KMS("Incorrect SDVO get contrast\n");
2582 return;
2583 }
2584 sdvo_priv->max_contrast = data_value[0];
2585 sdvo_priv->cur_contrast = response;
2586 sdvo_priv->contrast_property =
2587 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2588 "contrast", 2);
2589 sdvo_priv->contrast_property->values[0] = 0;
2590 sdvo_priv->contrast_property->values[1] = data_value[0];
2591 drm_connector_attach_property(connector,
2592 sdvo_priv->contrast_property,
2593 sdvo_priv->cur_contrast);
2594 DRM_DEBUG_KMS("contrast: max %d, "
2595 "default %d, current %d\n",
2596 data_value[0], data_value[1], response);
2597 }
2598 if (sdvo_data.hue) {
2599 intel_sdvo_write_cmd(intel_output,
2600 SDVO_CMD_GET_MAX_HUE, NULL, 0);
2601 status = intel_sdvo_read_response(intel_output,
2602 &data_value, 4);
2603 if (status != SDVO_CMD_STATUS_SUCCESS) {
2604 DRM_DEBUG_KMS("Incorrect SDVO Max hue\n");
2605 return;
2606 }
2607 intel_sdvo_write_cmd(intel_output,
2608 SDVO_CMD_GET_HUE, NULL, 0);
2609 status = intel_sdvo_read_response(intel_output,
2610 &response, 2);
2611 if (status != SDVO_CMD_STATUS_SUCCESS) {
2612 DRM_DEBUG_KMS("Incorrect SDVO get hue\n");
2613 return;
2614 }
2615 sdvo_priv->max_hue = data_value[0];
2616 sdvo_priv->cur_hue = response;
2617 sdvo_priv->hue_property =
2618 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2619 "hue", 2);
2620 sdvo_priv->hue_property->values[0] = 0;
2621 sdvo_priv->hue_property->values[1] =
2622 data_value[0];
2623 drm_connector_attach_property(connector,
2624 sdvo_priv->hue_property,
2625 sdvo_priv->cur_hue);
2626 DRM_DEBUG_KMS("hue: max %d, default %d, current %d\n",
2627 data_value[0], data_value[1], response);
2628 }
2629 }
d0cbde93 2630 if (sdvo_priv->is_tv || sdvo_priv->is_lvds) {
b9219c5e
ZY		 2631 if (sdvo_data.brightness) {
2632 intel_sdvo_write_cmd(intel_output,
2633 SDVO_CMD_GET_MAX_BRIGHTNESS, NULL, 0);
2634 status = intel_sdvo_read_response(intel_output,
2635 &data_value, 4);
2636 if (status != SDVO_CMD_STATUS_SUCCESS) {
2637 DRM_DEBUG_KMS("Incorrect SDVO Max bright\n");
2638 return;
2639 }
2640 intel_sdvo_write_cmd(intel_output,
2641 SDVO_CMD_GET_BRIGHTNESS, NULL, 0);
2642 status = intel_sdvo_read_response(intel_output,
2643 &response, 2);
2644 if (status != SDVO_CMD_STATUS_SUCCESS) {
2645 DRM_DEBUG_KMS("Incorrect SDVO get brigh\n");
2646 return;
2647 }
2648 sdvo_priv->max_brightness = data_value[0];
2649 sdvo_priv->cur_brightness = response;
2650 sdvo_priv->brightness_property =
2651 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2652 "brightness", 2);
2653 sdvo_priv->brightness_property->values[0] = 0;
2654 sdvo_priv->brightness_property->values[1] =
2655 data_value[0];
2656 drm_connector_attach_property(connector,
2657 sdvo_priv->brightness_property,
2658 sdvo_priv->cur_brightness);
2659 DRM_DEBUG_KMS("brightness: max %d, "
2660 "default %d, current %d\n",
2661 data_value[0], data_value[1], response);
2662 }
2663 }
2664 return;
2665}
2666
7d57382e 2667bool intel_sdvo_init(struct drm_device *dev, int output_device)
79e53945
JB		 2668{
2669 struct drm_connector *connector;
2670 struct intel_output *intel_output;
2671 struct intel_sdvo_priv *sdvo_priv;
f9c10a9b 2672
79e53945
JB		 2673 u8 ch[0x40];
2674 int i;
79e53945
JB		 2675
2676 intel_output = kcalloc(sizeof(struct intel_output)+sizeof(struct intel_sdvo_priv), 1, GFP_KERNEL);
2677 if (!intel_output) {
7d57382e 2678 return false;
79e53945
JB		 2679 }
2680
79e53945 2681 sdvo_priv = (struct intel_sdvo_priv *)(intel_output + 1);
308cd3a2
KP		 2682 sdvo_priv->output_device = output_device;
2683
2684 intel_output->dev_priv = sdvo_priv;
79e53945
JB		 2685 intel_output->type = INTEL_OUTPUT_SDVO;
2686
79e53945 2687 /* setup the DDC bus. */
308cd3a2
KP		 2688 if (output_device == SDVOB)
2689 intel_output->i2c_bus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOB");
2690 else
2691 intel_output->i2c_bus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOC");
2692
2693 if (!intel_output->i2c_bus)
ad5b2a6d 2694 goto err_inteloutput;
79e53945 2695
308cd3a2 2696 sdvo_priv->slave_addr = intel_sdvo_get_slave_addr(dev, output_device);
79e53945 2697
308cd3a2
KP		 2698 /* Save the bit-banging i2c functionality for use by the DDC wrapper */
2699 intel_sdvo_i2c_bit_algo.functionality = intel_output->i2c_bus->algo->functionality;
79e53945 2700
79e53945
JB		 2701 /* Read the regs to test if we can talk to the device */
2702 for (i = 0; i < 0x40; i++) {
2703 if (!intel_sdvo_read_byte(intel_output, i, &ch[i])) {
8a4c47f3 2704 DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",
342dc382 2705 output_device == SDVOB ? 'B' : 'C');
79e53945
JB		 2706 goto err_i2c;
2707 }
2708 }
2709
619ac3b7 2710 /* setup the DDC bus. */
57cdaf90 2711 if (output_device == SDVOB) {
308cd3a2 2712 intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOB DDC BUS");
57cdaf90
KP		 2713 sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA,
2714 "SDVOB/VGA DDC BUS");
2715 } else {
308cd3a2 2716 intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOC DDC BUS");
57cdaf90
KP		 2717 sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA,
2718 "SDVOC/VGA DDC BUS");
2719 }
619ac3b7 2720
308cd3a2 2721 if (intel_output->ddc_bus == NULL)
619ac3b7
ML		 2722 goto err_i2c;
2723
308cd3a2
KP		 2724 /* Wrap with our custom algo which switches to DDC mode */
2725 intel_output->ddc_bus->algo = &intel_sdvo_i2c_bit_algo;
619ac3b7 2726
7086c87f 2727 /* In defaut case sdvo lvds is false */
79e53945
JB		 2728 intel_sdvo_get_capabilities(intel_output, &sdvo_priv->caps);
2729
fb7a46f3 2730 if (intel_sdvo_output_setup(intel_output,
2731 sdvo_priv->caps.output_flags) != true) {
51c8b407 2732 DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
fb7a46f3 2733 output_device == SDVOB ? 'B' : 'C');
79e53945
JB		 2734 goto err_i2c;
2735 }
2736
fb7a46f3 2737
ad5b2a6d
JB		 2738 connector = &intel_output->base;
2739 drm_connector_init(dev, connector, &intel_sdvo_connector_funcs,
fb7a46f3 2740 connector->connector_type);
2741
ad5b2a6d
JB		 2742 drm_connector_helper_add(connector, &intel_sdvo_connector_helper_funcs);
2743 connector->interlace_allowed = 0;
2744 connector->doublescan_allowed = 0;
2745 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
2746
fb7a46f3 2747 drm_encoder_init(dev, &intel_output->enc,
2748 &intel_sdvo_enc_funcs, intel_output->enc.encoder_type);
2749
79e53945 2750 drm_encoder_helper_add(&intel_output->enc, &intel_sdvo_helper_funcs);
79e53945
JB		 2751
2752 drm_mode_connector_attach_encoder(&intel_output->base, &intel_output->enc);
d0cbde93 2753 if (sdvo_priv->is_tv)
ce6feabd 2754 intel_sdvo_tv_create_property(connector);
d0cbde93
ZY		 2755
2756 if (sdvo_priv->is_tv || sdvo_priv->is_lvds)
b9219c5e 2757 intel_sdvo_create_enhance_property(connector);
d0cbde93 2758
79e53945
JB		 2759 drm_sysfs_connector_add(connector);
2760
e2f0ba97
JB		 2761 intel_sdvo_select_ddc_bus(sdvo_priv);
2762
79e53945
JB		 2763 /* Set the input timing to the screen. Assume always input 0. */
2764 intel_sdvo_set_target_input(intel_output, true, false);
2765
2766 intel_sdvo_get_input_pixel_clock_range(intel_output,
2767 &sdvo_priv->pixel_clock_min,
2768 &sdvo_priv->pixel_clock_max);
2769
2770
8a4c47f3 2771 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
342dc382 2772 "clock range %dMHz - %dMHz, "
2773 "input 1: %c, input 2: %c, "
2774 "output 1: %c, output 2: %c\n",
2775 SDVO_NAME(sdvo_priv),
2776 sdvo_priv->caps.vendor_id, sdvo_priv->caps.device_id,
2777 sdvo_priv->caps.device_rev_id,
2778 sdvo_priv->pixel_clock_min / 1000,
2779 sdvo_priv->pixel_clock_max / 1000,
2780 (sdvo_priv->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2781 (sdvo_priv->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
2782 /* check currently supported outputs */
2783 sdvo_priv->caps.output_flags &
79e53945 2784 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
342dc382 2785 sdvo_priv->caps.output_flags &
79e53945
JB		 2786 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
2787
7d57382e 2788 return true;
79e53945
JB		 2789
2790err_i2c:
57cdaf90
KP		 2791 if (sdvo_priv->analog_ddc_bus != NULL)
2792 intel_i2c_destroy(sdvo_priv->analog_ddc_bus);
308cd3a2 2793 if (intel_output->ddc_bus != NULL)
619ac3b7 2794 intel_i2c_destroy(intel_output->ddc_bus);
308cd3a2
KP		 2795 if (intel_output->i2c_bus != NULL)
2796 intel_i2c_destroy(intel_output->i2c_bus);
ad5b2a6d 2797err_inteloutput:
79e53945
JB		 2798 kfree(intel_output);
2799
7d57382e 2800 return false;
79e53945 2801}
Linux 6.x block layer and io_uring tree(s)