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drm: drop _mode_ from update_edit_property()
[linux-block.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
79e53945 30#include <linux/delay.h>
2d1a8a48 31#include <linux/export.h>
760285e7 32#include <drm/drmP.h>
c6f95f27 33#include <drm/drm_atomic_helper.h>
760285e7
DH		 34#include <drm/drm_crtc.h>
35#include <drm/drm_edid.h>
ea5b213a 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945
JB		 38#include "i915_drv.h"
39#include "intel_sdvo_regs.h"
40
14571b4c
ZW		 41#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
42#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
43#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
a0b1c7a5 44#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
14571b4c
ZW		 45
46#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
0206e353 47 SDVO_TV_MASK)
14571b4c
ZW		 48
49#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
13946743 50#define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
14571b4c 51#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
32aad86f 52#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
52220085 53#define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
14571b4c 54
79e53945 55
4d9194de 56static const char * const tv_format_names[] = {
ce6feabd
ZY		 57 "NTSC_M" , "NTSC_J" , "NTSC_443",
58 "PAL_B" , "PAL_D" , "PAL_G" ,
59 "PAL_H" , "PAL_I" , "PAL_M" ,
60 "PAL_N" , "PAL_NC" , "PAL_60" ,
61 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
62 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
63 "SECAM_60"
64};
65
53abb679 66#define TV_FORMAT_NUM ARRAY_SIZE(tv_format_names)
ce6feabd 67
ea5b213a
CW		 68struct intel_sdvo {
69 struct intel_encoder base;
70
f899fc64 71 struct i2c_adapter *i2c;
f9c10a9b 72 u8 slave_addr;
e2f0ba97 73
e957d772
CW		 74 struct i2c_adapter ddc;
75
e2f0ba97 76 /* Register for the SDVO device: SDVOB or SDVOC */
f0f59a00 77 i915_reg_t sdvo_reg;
79e53945 78
e2f0ba97
JB		 79 /* Active outputs controlled by this SDVO output */
80 uint16_t controlled_output;
79e53945 81
e2f0ba97
JB		 82 /*
83 * Capabilities of the SDVO device returned by
19d415a2 84 * intel_sdvo_get_capabilities()
e2f0ba97 85 */
79e53945 86 struct intel_sdvo_caps caps;
e2f0ba97
JB		 87
88 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 89 int pixel_clock_min, pixel_clock_max;
90
fb7a46f3 91 /*
92 * For multiple function SDVO device,
93 * this is for current attached outputs.
94 */
95 uint16_t attached_output;
96
cc68c81a
SF		 97 /*
98 * Hotplug activation bits for this device
99 */
5fa7ac9c 100 uint16_t hotplug_active;
cc68c81a 101
e2f0ba97
JB		 102 /**
103 * This is set if we're going to treat the device as TV-out.
104 *
105 * While we have these nice friendly flags for output types that ought
106 * to decide this for us, the S-Video output on our HDMI+S-Video card
107 * shows up as RGB1 (VGA).
108 */
109 bool is_tv;
110
2a5c0832 111 enum port port;
eef4eacb 112
e2f0ba97
JB		 113 /**
114 * This is set if we treat the device as HDMI, instead of DVI.
115 */
116 bool is_hdmi;
da79de97
CW		 117 bool has_hdmi_monitor;
118 bool has_hdmi_audio;
abedc077 119 bool rgb_quant_range_selectable;
12682a97 120
7086c87f 121 /**
6c9547ff
CW		 122 * This is set if we detect output of sdvo device as LVDS and
123 * have a valid fixed mode to use with the panel.
7086c87f
ML		 124 */
125 bool is_lvds;
e2f0ba97 126
12682a97 127 /**
128 * This is sdvo fixed pannel mode pointer
129 */
130 struct drm_display_mode *sdvo_lvds_fixed_mode;
131
c751ce4f 132 /* DDC bus used by this SDVO encoder */
e2f0ba97 133 uint8_t ddc_bus;
e751823d
EE		 134
135 /*
136 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd
137 */
138 uint8_t dtd_sdvo_flags;
14571b4c
ZW		 139};
140
141struct intel_sdvo_connector {
615fb93f
CW		 142 struct intel_connector base;
143
14571b4c
ZW		 144 /* Mark the type of connector */
145 uint16_t output_flag;
146
147 /* This contains all current supported TV format */
40039750 148 u8 tv_format_supported[TV_FORMAT_NUM];
14571b4c 149 int format_supported_num;
c5521706 150 struct drm_property *tv_format;
14571b4c 151
b9219c5e 152 /* add the property for the SDVO-TV */
c5521706
CW		 153 struct drm_property *left;
154 struct drm_property *right;
155 struct drm_property *top;
156 struct drm_property *bottom;
157 struct drm_property *hpos;
158 struct drm_property *vpos;
159 struct drm_property *contrast;
160 struct drm_property *saturation;
161 struct drm_property *hue;
162 struct drm_property *sharpness;
163 struct drm_property *flicker_filter;
164 struct drm_property *flicker_filter_adaptive;
165 struct drm_property *flicker_filter_2d;
166 struct drm_property *tv_chroma_filter;
167 struct drm_property *tv_luma_filter;
e044218a 168 struct drm_property *dot_crawl;
b9219c5e
ZY		 169
170 /* add the property for the SDVO-TV/LVDS */
c5521706 171 struct drm_property *brightness;
b9219c5e 172
b9219c5e 173 /* this is to get the range of margin.*/
630d30a4
ML		 174 u32 max_hscan, max_vscan;
175};
176
177struct intel_sdvo_connector_state {
178 /* base.base: tv.saturation/contrast/hue/brightness */
179 struct intel_digital_connector_state base;
180
181 struct {
182 unsigned overscan_h, overscan_v, hpos, vpos, sharpness;
183 unsigned flicker_filter, flicker_filter_2d, flicker_filter_adaptive;
184 unsigned chroma_filter, luma_filter, dot_crawl;
185 } tv;
79e53945
JB		 186};
187
8aca63aa 188static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder)
ea5b213a 189{
8aca63aa 190 return container_of(encoder, struct intel_sdvo, base);
ea5b213a
CW		 191}
192
df0e9248
CW		 193static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
194{
8aca63aa 195 return to_sdvo(intel_attached_encoder(connector));
df0e9248
CW		 196}
197
630d30a4
ML		 198static struct intel_sdvo_connector *
199to_intel_sdvo_connector(struct drm_connector *connector)
200{
201 return container_of(connector, struct intel_sdvo_connector, base.base);
202}
203
5f88a9c6
VS		 204#define to_intel_sdvo_connector_state(conn_state) \
205 container_of((conn_state), struct intel_sdvo_connector_state, base.base)
615fb93f 206
fb7a46f3 207static bool
ea5b213a 208intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
32aad86f
CW		 209static bool
210intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
211 struct intel_sdvo_connector *intel_sdvo_connector,
212 int type);
213static bool
214intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
215 struct intel_sdvo_connector *intel_sdvo_connector);
fb7a46f3 216
c16336b9 217/*
79e53945
JB		 218 * Writes the SDVOB or SDVOC with the given value, but always writes both
219 * SDVOB and SDVOC to work around apparent hardware issues (according to
220 * comments in the BIOS).
221 */
ea5b213a 222static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
79e53945 223{
4ef69c7a 224 struct drm_device *dev = intel_sdvo->base.base.dev;
fac5e23e 225 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945
JB		 226 u32 bval = val, cval = val;
227 int i;
228
2a5c0832 229 if (HAS_PCH_SPLIT(dev_priv)) {
ea5b213a 230 I915_WRITE(intel_sdvo->sdvo_reg, val);
abab6311 231 POSTING_READ(intel_sdvo->sdvo_reg);
e8504ee2
VS		 232 /*
233 * HW workaround, need to write this twice for issue
234 * that may result in first write getting masked.
235 */
6e266956 236 if (HAS_PCH_IBX(dev_priv)) {
e8504ee2
VS		 237 I915_WRITE(intel_sdvo->sdvo_reg, val);
238 POSTING_READ(intel_sdvo->sdvo_reg);
239 }
461ed3ca
ZY		 240 return;
241 }
242
2a5c0832 243 if (intel_sdvo->port == PORT_B)
e2debe91
PZ		 244 cval = I915_READ(GEN3_SDVOC);
245 else
246 bval = I915_READ(GEN3_SDVOB);
247
79e53945
JB		 248 /*
249 * Write the registers twice for luck. Sometimes,
250 * writing them only once doesn't appear to 'stick'.
251 * The BIOS does this too. Yay, magic
252 */
c16336b9 253 for (i = 0; i < 2; i++) {
e2debe91 254 I915_WRITE(GEN3_SDVOB, bval);
abab6311 255 POSTING_READ(GEN3_SDVOB);
c16336b9 256
e2debe91 257 I915_WRITE(GEN3_SDVOC, cval);
abab6311 258 POSTING_READ(GEN3_SDVOC);
79e53945
JB		 259 }
260}
261
32aad86f 262static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
79e53945 263{
79e53945
JB		 264 struct i2c_msg msgs[] = {
265 {
e957d772 266 .addr = intel_sdvo->slave_addr,
79e53945
JB		 267 .flags = 0,
268 .len = 1,
e957d772 269 .buf = &addr,
79e53945
JB		 270 },
271 {
e957d772 272 .addr = intel_sdvo->slave_addr,
79e53945
JB		 273 .flags = I2C_M_RD,
274 .len = 1,
e957d772 275 .buf = ch,
79e53945
JB		 276 }
277 };
32aad86f 278 int ret;
79e53945 279
f899fc64 280 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
79e53945 281 return true;
79e53945 282
8a4c47f3 283 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 284 return false;
285}
286
79e53945
JB		 287#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
288/** Mapping of command numbers to names, for debug output */
005568be 289static const struct _sdvo_cmd_name {
e2f0ba97 290 u8 cmd;
2e88e40b 291 const char *name;
579627ea 292} __attribute__ ((packed)) sdvo_cmd_names[] = {
0206e353
AJ		 293 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
294 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
295 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
296 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
297 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
336
337 /* Add the op code for SDVO enhancements */
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
382
383 /* HDMI op code */
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 404};
405
2a5c0832 406#define SDVO_NAME(svdo) ((svdo)->port == PORT_B ? "SDVOB" : "SDVOC")
79e53945 407
ea5b213a 408static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
32aad86f 409 const void *args, int args_len)
79e53945 410{
84fcb469
DV		 411 int i, pos = 0;
412#define BUF_LEN 256
413 char buffer[BUF_LEN];
414
415#define BUF_PRINT(args...) \
416 pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args)
417
79e53945 418
84fcb469
DV		 419 for (i = 0; i < args_len; i++) {
420 BUF_PRINT("%02X ", ((u8 *)args)[i]);
421 }
422 for (; i < 8; i++) {
423 BUF_PRINT(" ");
424 }
04ad327f 425 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
79e53945 426 if (cmd == sdvo_cmd_names[i].cmd) {
84fcb469 427 BUF_PRINT("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 428 break;
429 }
430 }
84fcb469
DV		 431 if (i == ARRAY_SIZE(sdvo_cmd_names)) {
432 BUF_PRINT("(%02X)", cmd);
433 }
434 BUG_ON(pos >= BUF_LEN - 1);
435#undef BUF_PRINT
436#undef BUF_LEN
437
438 DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer);
79e53945 439}
79e53945 440
4d9194de 441static const char * const cmd_status_names[] = {
e957d772
CW		 442 "Power on",
443 "Success",
444 "Not supported",
445 "Invalid arg",
446 "Pending",
447 "Target not specified",
448 "Scaling not supported"
449};
450
a8506684
DV		 451static bool __intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
452 const void *args, int args_len,
453 bool unlocked)
79e53945 454{
3bf3f452
BW		 455 u8 *buf, status;
456 struct i2c_msg *msgs;
457 int i, ret = true;
458
a8506684 459 /* Would be simpler to allocate both in one go ? */
5c67eeb6 460 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL);
3bf3f452
BW		 461 if (!buf)
462 return false;
463
464 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
0274df3e 465 if (!msgs) {
a8506684 466 kfree(buf);
3bf3f452 467 return false;
a8506684 468 }
79e53945 469
ea5b213a 470 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
79e53945
JB		 471
472 for (i = 0; i < args_len; i++) {
e957d772
CW		 473 msgs[i].addr = intel_sdvo->slave_addr;
474 msgs[i].flags = 0;
475 msgs[i].len = 2;
476 msgs[i].buf = buf + 2 *i;
477 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
478 buf[2*i + 1] = ((u8*)args)[i];
479 }
480 msgs[i].addr = intel_sdvo->slave_addr;
481 msgs[i].flags = 0;
482 msgs[i].len = 2;
483 msgs[i].buf = buf + 2*i;
484 buf[2*i + 0] = SDVO_I2C_OPCODE;
485 buf[2*i + 1] = cmd;
486
487 /* the following two are to read the response */
488 status = SDVO_I2C_CMD_STATUS;
489 msgs[i+1].addr = intel_sdvo->slave_addr;
490 msgs[i+1].flags = 0;
491 msgs[i+1].len = 1;
492 msgs[i+1].buf = &status;
493
494 msgs[i+2].addr = intel_sdvo->slave_addr;
495 msgs[i+2].flags = I2C_M_RD;
496 msgs[i+2].len = 1;
497 msgs[i+2].buf = &status;
498
a8506684
DV		 499 if (unlocked)
500 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
501 else
502 ret = __i2c_transfer(intel_sdvo->i2c, msgs, i+3);
e957d772
CW		 503 if (ret < 0) {
504 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
3bf3f452
BW		 505 ret = false;
506 goto out;
e957d772
CW		 507 }
508 if (ret != i+3) {
509 /* failure in I2C transfer */
510 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
3bf3f452 511 ret = false;
e957d772
CW		 512 }
513
3bf3f452
BW		 514out:
515 kfree(msgs);
516 kfree(buf);
517 return ret;
79e53945
JB		 518}
519
a8506684
DV		 520static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
521 const void *args, int args_len)
522{
523 return __intel_sdvo_write_cmd(intel_sdvo, cmd, args, args_len, true);
524}
525
b5c616a7
CW		 526static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
527 void *response, int response_len)
79e53945 528{
fc37381c 529 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
b5c616a7 530 u8 status;
84fcb469
DV		 531 int i, pos = 0;
532#define BUF_LEN 256
533 char buffer[BUF_LEN];
79e53945 534
d121a5d2 535
b5c616a7
CW		 536 /*
537 * The documentation states that all commands will be
538 * processed within 15µs, and that we need only poll
539 * the status byte a maximum of 3 times in order for the
540 * command to be complete.
541 *
542 * Check 5 times in case the hardware failed to read the docs.
fc37381c
CW		 543 *
544 * Also beware that the first response by many devices is to
545 * reply PENDING and stall for time. TVs are notorious for
546 * requiring longer than specified to complete their replies.
547 * Originally (in the DDX long ago), the delay was only ever 15ms
548 * with an additional delay of 30ms applied for TVs added later after
549 * many experiments. To accommodate both sets of delays, we do a
550 * sequence of slow checks if the device is falling behind and fails
551 * to reply within 5*15µs.
b5c616a7 552 */
d121a5d2
CW		 553 if (!intel_sdvo_read_byte(intel_sdvo,
554 SDVO_I2C_CMD_STATUS,
555 &status))
556 goto log_fail;
557
1ad87e72 558 while ((status == SDVO_CMD_STATUS_PENDING ||
46a3f4a3 559 status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) {
fc37381c
CW		 560 if (retry < 10)
561 msleep(15);
562 else
563 udelay(15);
564
b5c616a7
CW		 565 if (!intel_sdvo_read_byte(intel_sdvo,
566 SDVO_I2C_CMD_STATUS,
567 &status))
d121a5d2
CW		 568 goto log_fail;
569 }
b5c616a7 570
84fcb469
DV		 571#define BUF_PRINT(args...) \
572 pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args)
573
79e53945 574 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
84fcb469 575 BUF_PRINT("(%s)", cmd_status_names[status]);
79e53945 576 else
84fcb469 577 BUF_PRINT("(??? %d)", status);
79e53945 578
b5c616a7
CW		 579 if (status != SDVO_CMD_STATUS_SUCCESS)
580 goto log_fail;
79e53945 581
b5c616a7
CW		 582 /* Read the command response */
583 for (i = 0; i < response_len; i++) {
584 if (!intel_sdvo_read_byte(intel_sdvo,
585 SDVO_I2C_RETURN_0 + i,
586 &((u8 *)response)[i]))
587 goto log_fail;
84fcb469 588 BUF_PRINT(" %02X", ((u8 *)response)[i]);
b5c616a7 589 }
84fcb469
DV		 590 BUG_ON(pos >= BUF_LEN - 1);
591#undef BUF_PRINT
592#undef BUF_LEN
593
594 DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer);
b5c616a7 595 return true;
79e53945 596
b5c616a7 597log_fail:
84fcb469 598 DRM_DEBUG_KMS("%s: R: ... failed\n", SDVO_NAME(intel_sdvo));
b5c616a7 599 return false;
79e53945
JB		 600}
601
5e7234c9 602static int intel_sdvo_get_pixel_multiplier(const struct drm_display_mode *adjusted_mode)
79e53945 603{
aad941d5 604 if (adjusted_mode->crtc_clock >= 100000)
79e53945 605 return 1;
aad941d5 606 else if (adjusted_mode->crtc_clock >= 50000)
79e53945
JB		 607 return 2;
608 else
609 return 4;
610}
611
a8506684
DV		 612static bool __intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
613 u8 ddc_bus)
79e53945 614{
d121a5d2 615 /* This must be the immediately preceding write before the i2c xfer */
a8506684
DV		 616 return __intel_sdvo_write_cmd(intel_sdvo,
617 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
618 &ddc_bus, 1, false);
79e53945
JB		 619}
620
32aad86f 621static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
79e53945 622{
d121a5d2
CW		 623 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
624 return false;
625
626 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
32aad86f 627}
79e53945 628
32aad86f
CW		 629static bool
630intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
631{
632 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
633 return false;
79e53945 634
32aad86f
CW		 635 return intel_sdvo_read_response(intel_sdvo, value, len);
636}
79e53945 637
32aad86f
CW		 638static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
639{
640 struct intel_sdvo_set_target_input_args targets = {0};
641 return intel_sdvo_set_value(intel_sdvo,
642 SDVO_CMD_SET_TARGET_INPUT,
643 &targets, sizeof(targets));
79e53945
JB		 644}
645
c16336b9 646/*
79e53945
JB		 647 * Return whether each input is trained.
648 *
649 * This function is making an assumption about the layout of the response,
650 * which should be checked against the docs.
651 */
ea5b213a 652static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
79e53945
JB		 653{
654 struct intel_sdvo_get_trained_inputs_response response;
79e53945 655
1a3665c8 656 BUILD_BUG_ON(sizeof(response) != 1);
32aad86f
CW		 657 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
658 &response, sizeof(response)))
79e53945
JB		 659 return false;
660
661 *input_1 = response.input0_trained;
662 *input_2 = response.input1_trained;
663 return true;
664}
665
ea5b213a 666static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
79e53945
JB		 667 u16 outputs)
668{
32aad86f
CW		 669 return intel_sdvo_set_value(intel_sdvo,
670 SDVO_CMD_SET_ACTIVE_OUTPUTS,
671 &outputs, sizeof(outputs));
79e53945
JB		 672}
673
4ac41f47
DV		 674static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo,
675 u16 *outputs)
676{
677 return intel_sdvo_get_value(intel_sdvo,
678 SDVO_CMD_GET_ACTIVE_OUTPUTS,
679 outputs, sizeof(*outputs));
680}
681
ea5b213a 682static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
79e53945
JB		 683 int mode)
684{
32aad86f 685 u8 state = SDVO_ENCODER_STATE_ON;
79e53945
JB		 686
687 switch (mode) {
688 case DRM_MODE_DPMS_ON:
689 state = SDVO_ENCODER_STATE_ON;
690 break;
691 case DRM_MODE_DPMS_STANDBY:
692 state = SDVO_ENCODER_STATE_STANDBY;
693 break;
694 case DRM_MODE_DPMS_SUSPEND:
695 state = SDVO_ENCODER_STATE_SUSPEND;
696 break;
697 case DRM_MODE_DPMS_OFF:
698 state = SDVO_ENCODER_STATE_OFF;
699 break;
700 }
701
32aad86f
CW		 702 return intel_sdvo_set_value(intel_sdvo,
703 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
79e53945
JB		 704}
705
ea5b213a 706static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
79e53945
JB		 707 int *clock_min,
708 int *clock_max)
709{
710 struct intel_sdvo_pixel_clock_range clocks;
79e53945 711
1a3665c8 712 BUILD_BUG_ON(sizeof(clocks) != 4);
32aad86f
CW		 713 if (!intel_sdvo_get_value(intel_sdvo,
714 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
715 &clocks, sizeof(clocks)))
79e53945
JB		 716 return false;
717
718 /* Convert the values from units of 10 kHz to kHz. */
719 *clock_min = clocks.min * 10;
720 *clock_max = clocks.max * 10;
79e53945
JB		 721 return true;
722}
723
ea5b213a 724static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
79e53945
JB		 725 u16 outputs)
726{
32aad86f
CW		 727 return intel_sdvo_set_value(intel_sdvo,
728 SDVO_CMD_SET_TARGET_OUTPUT,
729 &outputs, sizeof(outputs));
79e53945
JB		 730}
731
ea5b213a 732static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
79e53945
JB		 733 struct intel_sdvo_dtd *dtd)
734{
32aad86f
CW		 735 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
736 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
79e53945
JB		 737}
738
045ac3b5
JB		 739static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
740 struct intel_sdvo_dtd *dtd)
741{
742 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
743 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
744}
745
ea5b213a 746static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 747 struct intel_sdvo_dtd *dtd)
748{
ea5b213a 749 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 750 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
751}
752
ea5b213a 753static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 754 struct intel_sdvo_dtd *dtd)
755{
ea5b213a 756 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 757 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
758}
759
045ac3b5
JB		 760static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo,
761 struct intel_sdvo_dtd *dtd)
762{
763 return intel_sdvo_get_timing(intel_sdvo,
764 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
765}
766
e2f0ba97 767static bool
ea5b213a 768intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 769 uint16_t clock,
770 uint16_t width,
771 uint16_t height)
772{
773 struct intel_sdvo_preferred_input_timing_args args;
e2f0ba97 774
e642c6f1 775 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 776 args.clock = clock;
777 args.width = width;
778 args.height = height;
e642c6f1 779 args.interlace = 0;
12682a97 780
ea5b213a
CW		 781 if (intel_sdvo->is_lvds &&
782 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
783 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
12682a97 784 args.scaled = 1;
785
32aad86f
CW		 786 return intel_sdvo_set_value(intel_sdvo,
787 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
788 &args, sizeof(args));
e2f0ba97
JB		 789}
790
ea5b213a 791static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 792 struct intel_sdvo_dtd *dtd)
793{
1a3665c8
CW		 794 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
795 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
32aad86f
CW		 796 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
797 &dtd->part1, sizeof(dtd->part1)) &&
798 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
799 &dtd->part2, sizeof(dtd->part2));
e2f0ba97 800}
79e53945 801
ea5b213a 802static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
79e53945 803{
32aad86f 804 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
79e53945
JB		 805}
806
e2f0ba97 807static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
32aad86f 808 const struct drm_display_mode *mode)
79e53945 809{
e2f0ba97
JB		 810 uint16_t width, height;
811 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
812 uint16_t h_sync_offset, v_sync_offset;
6651819b 813 int mode_clock;
79e53945 814
1c4a814e
DV		 815 memset(dtd, 0, sizeof(*dtd));
816
c6ebd4c0
DV		 817 width = mode->hdisplay;
818 height = mode->vdisplay;
79e53945
JB		 819
820 /* do some mode translations */
c6ebd4c0
DV		 821 h_blank_len = mode->htotal - mode->hdisplay;
822 h_sync_len = mode->hsync_end - mode->hsync_start;
79e53945 823
c6ebd4c0
DV		 824 v_blank_len = mode->vtotal - mode->vdisplay;
825 v_sync_len = mode->vsync_end - mode->vsync_start;
79e53945 826
c6ebd4c0
DV		 827 h_sync_offset = mode->hsync_start - mode->hdisplay;
828 v_sync_offset = mode->vsync_start - mode->vdisplay;
79e53945 829
6651819b 830 mode_clock = mode->clock;
6651819b
DV		 831 mode_clock /= 10;
832 dtd->part1.clock = mode_clock;
833
e2f0ba97
JB		 834 dtd->part1.h_active = width & 0xff;
835 dtd->part1.h_blank = h_blank_len & 0xff;
836 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 837 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 838 dtd->part1.v_active = height & 0xff;
839 dtd->part1.v_blank = v_blank_len & 0xff;
840 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 841 ((v_blank_len >> 8) & 0xf);
842
171a9e96 843 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 844 dtd->part2.h_sync_width = h_sync_len & 0xff;
845 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 846 (v_sync_len & 0xf);
e2f0ba97 847 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 848 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
849 ((v_sync_len & 0x30) >> 4);
850
e2f0ba97 851 dtd->part2.dtd_flags = 0x18;
59d92bfa
DV		 852 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
853 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
79e53945 854 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
59d92bfa 855 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
79e53945 856 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
59d92bfa 857 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
e2f0ba97 858
e2f0ba97 859 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
e2f0ba97
JB		 860}
861
1c4a814e 862static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode,
32aad86f 863 const struct intel_sdvo_dtd *dtd)
e2f0ba97 864{
1c4a814e
DV		 865 struct drm_display_mode mode = {};
866
867 mode.hdisplay = dtd->part1.h_active;
868 mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
869 mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off;
870 mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
871 mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width;
872 mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
873 mode.htotal = mode.hdisplay + dtd->part1.h_blank;
874 mode.htotal += (dtd->part1.h_high & 0xf) << 8;
875
876 mode.vdisplay = dtd->part1.v_active;
877 mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
878 mode.vsync_start = mode.vdisplay;
879 mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
880 mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
881 mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0;
882 mode.vsync_end = mode.vsync_start +
e2f0ba97 883 (dtd->part2.v_sync_off_width & 0xf);
1c4a814e
DV		 884 mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
885 mode.vtotal = mode.vdisplay + dtd->part1.v_blank;
886 mode.vtotal += (dtd->part1.v_high & 0xf) << 8;
e2f0ba97 887
1c4a814e 888 mode.clock = dtd->part1.clock * 10;
e2f0ba97 889
59d92bfa 890 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
1c4a814e 891 mode.flags |= DRM_MODE_FLAG_INTERLACE;
59d92bfa 892 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
1c4a814e 893 mode.flags |= DRM_MODE_FLAG_PHSYNC;
3cea210f 894 else
1c4a814e 895 mode.flags |= DRM_MODE_FLAG_NHSYNC;
59d92bfa 896 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
1c4a814e 897 mode.flags |= DRM_MODE_FLAG_PVSYNC;
3cea210f 898 else
1c4a814e
DV		 899 mode.flags |= DRM_MODE_FLAG_NVSYNC;
900
901 drm_mode_set_crtcinfo(&mode, 0);
902
903 drm_mode_copy(pmode, &mode);
e2f0ba97
JB		 904}
905
e27d8538 906static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
e2f0ba97 907{
e27d8538 908 struct intel_sdvo_encode encode;
e2f0ba97 909
1a3665c8 910 BUILD_BUG_ON(sizeof(encode) != 2);
e27d8538
CW		 911 return intel_sdvo_get_value(intel_sdvo,
912 SDVO_CMD_GET_SUPP_ENCODE,
913 &encode, sizeof(encode));
e2f0ba97
JB		 914}
915
ea5b213a 916static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
c751ce4f 917 uint8_t mode)
e2f0ba97 918{
32aad86f 919 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
e2f0ba97
JB		 920}
921
ea5b213a 922static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 923 uint8_t mode)
924{
32aad86f 925 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
e2f0ba97
JB		 926}
927
928#if 0
ea5b213a 929static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 930{
931 int i, j;
932 uint8_t set_buf_index[2];
933 uint8_t av_split;
934 uint8_t buf_size;
935 uint8_t buf[48];
936 uint8_t *pos;
937
32aad86f 938 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
e2f0ba97
JB		 939
940 for (i = 0; i <= av_split; i++) {
941 set_buf_index[0] = i; set_buf_index[1] = 0;
c751ce4f 942 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
e2f0ba97 943 set_buf_index, 2);
c751ce4f
EA		 944 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
945 intel_sdvo_read_response(encoder, &buf_size, 1);
e2f0ba97
JB		 946
947 pos = buf;
948 for (j = 0; j <= buf_size; j += 8) {
c751ce4f 949 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
e2f0ba97 950 NULL, 0);
c751ce4f 951 intel_sdvo_read_response(encoder, pos, 8);
e2f0ba97
JB		 952 pos += 8;
953 }
954 }
955}
956#endif
957
b6e0e543
DV		 958static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
959 unsigned if_index, uint8_t tx_rate,
fff63867 960 const uint8_t *data, unsigned length)
b6e0e543
DV		 961{
962 uint8_t set_buf_index[2] = { if_index, 0 };
963 uint8_t hbuf_size, tmp[8];
964 int i;
965
966 if (!intel_sdvo_set_value(intel_sdvo,
967 SDVO_CMD_SET_HBUF_INDEX,
968 set_buf_index, 2))
969 return false;
970
971 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
972 &hbuf_size, 1))
973 return false;
974
975 /* Buffer size is 0 based, hooray! */
976 hbuf_size++;
977
978 DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
979 if_index, length, hbuf_size);
980
981 for (i = 0; i < hbuf_size; i += 8) {
982 memset(tmp, 0, 8);
983 if (i < length)
984 memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
985
986 if (!intel_sdvo_set_value(intel_sdvo,
987 SDVO_CMD_SET_HBUF_DATA,
988 tmp, 8))
989 return false;
990 }
991
992 return intel_sdvo_set_value(intel_sdvo,
993 SDVO_CMD_SET_HBUF_TXRATE,
994 &tx_rate, 1);
995}
996
abedc077 997static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
5f88a9c6 998 const struct intel_crtc_state *pipe_config)
e2f0ba97 999{
15dcd350 1000 uint8_t sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
15dcd350
DL		 1001 union hdmi_infoframe frame;
1002 int ret;
1003 ssize_t len;
1004
1005 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
0c1f528c
SS		 1006 &pipe_config->base.adjusted_mode,
1007 false);
15dcd350
DL		 1008 if (ret < 0) {
1009 DRM_ERROR("couldn't fill AVI infoframe\n");
1010 return false;
1011 }
3c17fe4b 1012
abedc077 1013 if (intel_sdvo->rgb_quant_range_selectable) {
f9fe0530 1014 if (pipe_config->limited_color_range)
15dcd350
DL		 1015 frame.avi.quantization_range =
1016 HDMI_QUANTIZATION_RANGE_LIMITED;
abedc077 1017 else
15dcd350
DL		 1018 frame.avi.quantization_range =
1019 HDMI_QUANTIZATION_RANGE_FULL;
abedc077
VS		 1020 }
1021
15dcd350
DL		 1022 len = hdmi_infoframe_pack(&frame, sdvo_data, sizeof(sdvo_data));
1023 if (len < 0)
1024 return false;
81014b9d 1025
b6e0e543
DV		 1026 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
1027 SDVO_HBUF_TX_VSYNC,
1028 sdvo_data, sizeof(sdvo_data));
e2f0ba97
JB		 1029}
1030
630d30a4 1031static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo,
5f88a9c6 1032 const struct drm_connector_state *conn_state)
7026d4ac 1033{
ce6feabd 1034 struct intel_sdvo_tv_format format;
40039750 1035 uint32_t format_map;
ce6feabd 1036
630d30a4 1037 format_map = 1 << conn_state->tv.mode;
ce6feabd 1038 memset(&format, 0, sizeof(format));
32aad86f 1039 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
ce6feabd 1040
32aad86f
CW		 1041 BUILD_BUG_ON(sizeof(format) != 6);
1042 return intel_sdvo_set_value(intel_sdvo,
1043 SDVO_CMD_SET_TV_FORMAT,
1044 &format, sizeof(format));
7026d4ac
ZW		 1045}
1046
32aad86f
CW		 1047static bool
1048intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
e811f5ae 1049 const struct drm_display_mode *mode)
e2f0ba97 1050{
32aad86f 1051 struct intel_sdvo_dtd output_dtd;
79e53945 1052
32aad86f
CW		 1053 if (!intel_sdvo_set_target_output(intel_sdvo,
1054 intel_sdvo->attached_output))
1055 return false;
e2f0ba97 1056
32aad86f
CW		 1057 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1058 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1059 return false;
e2f0ba97 1060
32aad86f
CW		 1061 return true;
1062}
1063
c16336b9
CW		 1064/*
1065 * Asks the sdvo controller for the preferred input mode given the output mode.
1066 * Unfortunately we have to set up the full output mode to do that.
1067 */
32aad86f 1068static bool
c9a29698 1069intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
e811f5ae 1070 const struct drm_display_mode *mode,
c9a29698 1071 struct drm_display_mode *adjusted_mode)
32aad86f 1072{
c9a29698
DV		 1073 struct intel_sdvo_dtd input_dtd;
1074
32aad86f
CW		 1075 /* Reset the input timing to the screen. Assume always input 0. */
1076 if (!intel_sdvo_set_target_input(intel_sdvo))
1077 return false;
e2f0ba97 1078
32aad86f
CW		 1079 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
1080 mode->clock / 10,
1081 mode->hdisplay,
1082 mode->vdisplay))
1083 return false;
e2f0ba97 1084
32aad86f 1085 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
c9a29698 1086 &input_dtd))
32aad86f 1087 return false;
e2f0ba97 1088
c9a29698 1089 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
e751823d 1090 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags;
79e53945 1091
32aad86f
CW		 1092 return true;
1093}
12682a97 1094
5cec258b 1095static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config)
70484559 1096{
3c52f4eb 1097 unsigned dotclock = pipe_config->port_clock;
70484559
DV		 1098 struct dpll *clock = &pipe_config->dpll;
1099
c16336b9
CW		 1100 /*
1101 * SDVO TV has fixed PLL values depend on its clock range,
1102 * this mirrors vbios setting.
1103 */
70484559
DV		 1104 if (dotclock >= 100000 && dotclock < 140500) {
1105 clock->p1 = 2;
1106 clock->p2 = 10;
1107 clock->n = 3;
1108 clock->m1 = 16;
1109 clock->m2 = 8;
1110 } else if (dotclock >= 140500 && dotclock <= 200000) {
1111 clock->p1 = 1;
1112 clock->p2 = 10;
1113 clock->n = 6;
1114 clock->m1 = 12;
1115 clock->m2 = 8;
1116 } else {
1117 WARN(1, "SDVO TV clock out of range: %i\n", dotclock);
1118 }
1119
1120 pipe_config->clock_set = true;
1121}
1122
6cc5f341 1123static bool intel_sdvo_compute_config(struct intel_encoder *encoder,
0a478c27
ML		 1124 struct intel_crtc_state *pipe_config,
1125 struct drm_connector_state *conn_state)
32aad86f 1126{
8aca63aa 1127 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
630d30a4
ML		 1128 struct intel_sdvo_connector_state *intel_sdvo_state =
1129 to_intel_sdvo_connector_state(conn_state);
2d112de7
ACO		 1130 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1131 struct drm_display_mode *mode = &pipe_config->base.mode;
12682a97 1132
5d2d38dd
DV		 1133 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
1134 pipe_config->pipe_bpp = 8*3;
1135
6e266956 1136 if (HAS_PCH_SPLIT(to_i915(encoder->base.dev)))
5bfe2ac0
DV		 1137 pipe_config->has_pch_encoder = true;
1138
c16336b9
CW		 1139 /*
1140 * We need to construct preferred input timings based on our
32aad86f
CW		 1141 * output timings. To do that, we have to set the output
1142 * timings, even though this isn't really the right place in
1143 * the sequence to do it. Oh well.
1144 */
1145 if (intel_sdvo->is_tv) {
1146 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
1147 return false;
12682a97 1148
c9a29698
DV		 1149 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1150 mode,
1151 adjusted_mode);
09ede541 1152 pipe_config->sdvo_tv_clock = true;
ea5b213a 1153 } else if (intel_sdvo->is_lvds) {
32aad86f 1154 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
6c9547ff 1155 intel_sdvo->sdvo_lvds_fixed_mode))
e2f0ba97 1156 return false;
12682a97 1157
c9a29698
DV		 1158 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1159 mode,
1160 adjusted_mode);
e2f0ba97 1161 }
32aad86f 1162
e4dd27aa
VS		 1163 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
1164 return false;
1165
c16336b9
CW		 1166 /*
1167 * Make the CRTC code factor in the SDVO pixel multiplier. The
6c9547ff 1168 * SDVO device will factor out the multiplier during mode_set.
32aad86f 1169 */
6cc5f341
DV		 1170 pipe_config->pixel_multiplier =
1171 intel_sdvo_get_pixel_multiplier(adjusted_mode);
32aad86f 1172
630d30a4 1173 if (intel_sdvo_state->base.force_audio != HDMI_AUDIO_OFF_DVI)
b32962f8
ML		 1174 pipe_config->has_hdmi_sink = intel_sdvo->has_hdmi_monitor;
1175
630d30a4
ML		 1176 if (intel_sdvo_state->base.force_audio == HDMI_AUDIO_ON ||
1177 (intel_sdvo_state->base.force_audio == HDMI_AUDIO_AUTO && intel_sdvo->has_hdmi_audio))
b32962f8 1178 pipe_config->has_audio = true;
9f04003e 1179
630d30a4 1180 if (intel_sdvo_state->base.broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
c16336b9
CW		 1181 /*
1182 * See CEA-861-E - 5.1 Default Encoding Parameters
1183 *
1184 * FIXME: This bit is only valid when using TMDS encoding and 8
1185 * bit per color mode.
1186 */
9f04003e 1187 if (pipe_config->has_hdmi_sink &&
18316c8c 1188 drm_match_cea_mode(adjusted_mode) > 1)
69f5acc8
DV		 1189 pipe_config->limited_color_range = true;
1190 } else {
9f04003e 1191 if (pipe_config->has_hdmi_sink &&
630d30a4 1192 intel_sdvo_state->base.broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED)
69f5acc8 1193 pipe_config->limited_color_range = true;
55bc60db
VS		 1194 }
1195
70484559
DV		 1196 /* Clock computation needs to happen after pixel multiplier. */
1197 if (intel_sdvo->is_tv)
1198 i9xx_adjust_sdvo_tv_clock(pipe_config);
1199
7949dd47
VS		 1200 /* Set user selected PAR to incoming mode's member */
1201 if (intel_sdvo->is_hdmi)
0e9f25d0 1202 adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio;
7949dd47 1203
e2f0ba97
JB		 1204 return true;
1205}
1206
630d30a4
ML		 1207#define UPDATE_PROPERTY(input, NAME) \
1208 do { \
1209 val = input; \
1210 intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_##NAME, &val, sizeof(val)); \
1211 } while (0)
1212
1213static void intel_sdvo_update_props(struct intel_sdvo *intel_sdvo,
5f88a9c6 1214 const struct intel_sdvo_connector_state *sdvo_state)
630d30a4 1215{
5f88a9c6 1216 const struct drm_connector_state *conn_state = &sdvo_state->base.base;
630d30a4
ML		 1217 struct intel_sdvo_connector *intel_sdvo_conn =
1218 to_intel_sdvo_connector(conn_state->connector);
1219 uint16_t val;
1220
1221 if (intel_sdvo_conn->left)
1222 UPDATE_PROPERTY(sdvo_state->tv.overscan_h, OVERSCAN_H);
1223
1224 if (intel_sdvo_conn->top)
1225 UPDATE_PROPERTY(sdvo_state->tv.overscan_v, OVERSCAN_V);
1226
1227 if (intel_sdvo_conn->hpos)
1228 UPDATE_PROPERTY(sdvo_state->tv.hpos, HPOS);
1229
1230 if (intel_sdvo_conn->vpos)
1231 UPDATE_PROPERTY(sdvo_state->tv.vpos, VPOS);
1232
1233 if (intel_sdvo_conn->saturation)
1234 UPDATE_PROPERTY(conn_state->tv.saturation, SATURATION);
1235
1236 if (intel_sdvo_conn->contrast)
1237 UPDATE_PROPERTY(conn_state->tv.contrast, CONTRAST);
1238
1239 if (intel_sdvo_conn->hue)
1240 UPDATE_PROPERTY(conn_state->tv.hue, HUE);
1241
1242 if (intel_sdvo_conn->brightness)
1243 UPDATE_PROPERTY(conn_state->tv.brightness, BRIGHTNESS);
1244
1245 if (intel_sdvo_conn->sharpness)
1246 UPDATE_PROPERTY(sdvo_state->tv.sharpness, SHARPNESS);
1247
1248 if (intel_sdvo_conn->flicker_filter)
1249 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter, FLICKER_FILTER);
1250
1251 if (intel_sdvo_conn->flicker_filter_2d)
1252 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_2d, FLICKER_FILTER_2D);
1253
1254 if (intel_sdvo_conn->flicker_filter_adaptive)
1255 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
1256
1257 if (intel_sdvo_conn->tv_chroma_filter)
1258 UPDATE_PROPERTY(sdvo_state->tv.chroma_filter, TV_CHROMA_FILTER);
1259
1260 if (intel_sdvo_conn->tv_luma_filter)
1261 UPDATE_PROPERTY(sdvo_state->tv.luma_filter, TV_LUMA_FILTER);
1262
1263 if (intel_sdvo_conn->dot_crawl)
1264 UPDATE_PROPERTY(sdvo_state->tv.dot_crawl, DOT_CRAWL);
1265
1266#undef UPDATE_PROPERTY
1267}
1268
fd6bbda9 1269static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
5f88a9c6
VS		 1270 const struct intel_crtc_state *crtc_state,
1271 const struct drm_connector_state *conn_state)
e2f0ba97 1272{
66478475 1273 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
f9fe0530
ML		 1274 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1275 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
5f88a9c6
VS		 1276 const struct intel_sdvo_connector_state *sdvo_state =
1277 to_intel_sdvo_connector_state(conn_state);
1278 const struct drm_display_mode *mode = &crtc_state->base.mode;
8aca63aa 1279 struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder);
6c9547ff 1280 u32 sdvox;
e2f0ba97 1281 struct intel_sdvo_in_out_map in_out;
6651819b 1282 struct intel_sdvo_dtd input_dtd, output_dtd;
6c9547ff 1283 int rate;
e2f0ba97 1284
630d30a4
ML		 1285 intel_sdvo_update_props(intel_sdvo, sdvo_state);
1286
c16336b9
CW		 1287 /*
1288 * First, set the input mapping for the first input to our controlled
e2f0ba97
JB		 1289 * output. This is only correct if we're a single-input device, in
1290 * which case the first input is the output from the appropriate SDVO
1291 * channel on the motherboard. In a two-input device, the first input
1292 * will be SDVOB and the second SDVOC.
1293 */
ea5b213a 1294 in_out.in0 = intel_sdvo->attached_output;
e2f0ba97
JB		 1295 in_out.in1 = 0;
1296
c74696b9
PR		 1297 intel_sdvo_set_value(intel_sdvo,
1298 SDVO_CMD_SET_IN_OUT_MAP,
1299 &in_out, sizeof(in_out));
e2f0ba97 1300
6c9547ff
CW		 1301 /* Set the output timings to the screen */
1302 if (!intel_sdvo_set_target_output(intel_sdvo,
1303 intel_sdvo->attached_output))
1304 return;
e2f0ba97 1305
6651819b
DV		 1306 /* lvds has a special fixed output timing. */
1307 if (intel_sdvo->is_lvds)
1308 intel_sdvo_get_dtd_from_mode(&output_dtd,
1309 intel_sdvo->sdvo_lvds_fixed_mode);
1310 else
1311 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
c8d4bb54
DV		 1312 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1313 DRM_INFO("Setting output timings on %s failed\n",
1314 SDVO_NAME(intel_sdvo));
79e53945
JB		 1315
1316 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 1317 if (!intel_sdvo_set_target_input(intel_sdvo))
1318 return;
79e53945 1319
f9fe0530 1320 if (crtc_state->has_hdmi_sink) {
97aaf910
CW		 1321 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1322 intel_sdvo_set_colorimetry(intel_sdvo,
1323 SDVO_COLORIMETRY_RGB256);
f9fe0530 1324 intel_sdvo_set_avi_infoframe(intel_sdvo, crtc_state);
97aaf910
CW		 1325 } else
1326 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
7026d4ac 1327
6c9547ff 1328 if (intel_sdvo->is_tv &&
630d30a4 1329 !intel_sdvo_set_tv_format(intel_sdvo, conn_state))
6c9547ff 1330 return;
e2f0ba97 1331
6651819b 1332 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
eeb47937 1333
e751823d
EE		 1334 if (intel_sdvo->is_tv || intel_sdvo->is_lvds)
1335 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
c8d4bb54
DV		 1336 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
1337 DRM_INFO("Setting input timings on %s failed\n",
1338 SDVO_NAME(intel_sdvo));
79e53945 1339
f9fe0530 1340 switch (crtc_state->pixel_multiplier) {
6c9547ff 1341 default:
fd0753cf 1342 WARN(1, "unknown pixel multiplier specified\n");
32aad86f
CW		 1343 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1344 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1345 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
79e53945 1346 }
32aad86f
CW		 1347 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1348 return;
79e53945
JB		 1349
1350 /* Set the SDVO control regs. */
66478475 1351 if (INTEL_GEN(dev_priv) >= 4) {
ba68e086
PZ		 1352 /* The real mode polarity is set by the SDVO commands, using
1353 * struct intel_sdvo_dtd. */
1354 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
6e266956 1355 if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
69f5acc8 1356 sdvox |= HDMI_COLOR_RANGE_16_235;
66478475 1357 if (INTEL_GEN(dev_priv) < 5)
6714afb1 1358 sdvox |= SDVO_BORDER_ENABLE;
e2f0ba97 1359 } else {
6c9547ff 1360 sdvox = I915_READ(intel_sdvo->sdvo_reg);
2a5c0832 1361 if (intel_sdvo->port == PORT_B)
e2f0ba97 1362 sdvox &= SDVOB_PRESERVE_MASK;
2a5c0832 1363 else
e2f0ba97 1364 sdvox &= SDVOC_PRESERVE_MASK;
e2f0ba97
JB		 1365 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1366 }
3573c410 1367
b9eb89b2 1368 if (HAS_PCH_CPT(dev_priv))
eeb47937 1369 sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe);
3573c410 1370 else
eeb47937 1371 sdvox |= SDVO_PIPE_SEL(crtc->pipe);
3573c410 1372
de44e256
DV		 1373 if (crtc_state->has_audio) {
1374 WARN_ON_ONCE(INTEL_GEN(dev_priv) < 4);
6c9547ff 1375 sdvox |= SDVO_AUDIO_ENABLE;
de44e256 1376 }
79e53945 1377
66478475 1378 if (INTEL_GEN(dev_priv) >= 4) {
e2f0ba97 1379 /* done in crtc_mode_set as the dpll_md reg must be written early */
50a0bc90 1380 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
73f67aa8 1381 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
e2f0ba97 1382 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945 1383 } else {
f9fe0530 1384 sdvox |= (crtc_state->pixel_multiplier - 1)
6cc5f341 1385 << SDVO_PORT_MULTIPLY_SHIFT;
79e53945
JB		 1386 }
1387
6714afb1 1388 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
66478475 1389 INTEL_GEN(dev_priv) < 5)
12682a97 1390 sdvox |= SDVO_STALL_SELECT;
ea5b213a 1391 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
79e53945
JB		 1392}
1393
4ac41f47 1394static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
79e53945 1395{
4ac41f47
DV		 1396 struct intel_sdvo_connector *intel_sdvo_connector =
1397 to_intel_sdvo_connector(&connector->base);
1398 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base);
2f28c50b 1399 u16 active_outputs = 0;
4ac41f47
DV		 1400
1401 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1402
1403 if (active_outputs & intel_sdvo_connector->output_flag)
1404 return true;
1405 else
1406 return false;
1407}
1408
76203467
VS		 1409bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv,
1410 i915_reg_t sdvo_reg, enum pipe *pipe)
1411{
1412 u32 val;
1413
1414 val = I915_READ(sdvo_reg);
1415
1416 /* asserts want to know the pipe even if the port is disabled */
1417 if (HAS_PCH_CPT(dev_priv))
1418 *pipe = (val & SDVO_PIPE_SEL_MASK_CPT) >> SDVO_PIPE_SEL_SHIFT_CPT;
1419 else if (IS_CHERRYVIEW(dev_priv))
1420 *pipe = (val & SDVO_PIPE_SEL_MASK_CHV) >> SDVO_PIPE_SEL_SHIFT_CHV;
1421 else
1422 *pipe = (val & SDVO_PIPE_SEL_MASK) >> SDVO_PIPE_SEL_SHIFT;
1423
1424 return val & SDVO_ENABLE;
1425}
1426
4ac41f47
DV		 1427static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
1428 enum pipe *pipe)
1429{
76203467 1430 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
8aca63aa 1431 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
2f28c50b 1432 u16 active_outputs = 0;
76203467 1433 bool ret;
4ac41f47 1434
7a7d1fb7 1435 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
4ac41f47 1436
76203467 1437 ret = intel_sdvo_port_enabled(dev_priv, intel_sdvo->sdvo_reg, pipe);
4ac41f47 1438
76203467 1439 return ret || active_outputs;
4ac41f47
DV		 1440}
1441
045ac3b5 1442static void intel_sdvo_get_config(struct intel_encoder *encoder,
5cec258b 1443 struct intel_crtc_state *pipe_config)
045ac3b5 1444{
6c49f241 1445 struct drm_device *dev = encoder->base.dev;
fac5e23e 1446 struct drm_i915_private *dev_priv = to_i915(dev);
8aca63aa 1447 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
045ac3b5 1448 struct intel_sdvo_dtd dtd;
6c49f241 1449 int encoder_pixel_multiplier = 0;
18442d08 1450 int dotclock;
6c49f241
DV		 1451 u32 flags = 0, sdvox;
1452 u8 val;
045ac3b5
JB		 1453 bool ret;
1454
e1214b95
VS		 1455 pipe_config->output_types |= BIT(INTEL_OUTPUT_SDVO);
1456
b5a9fa09
DV		 1457 sdvox = I915_READ(intel_sdvo->sdvo_reg);
1458
045ac3b5
JB		 1459 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd);
1460 if (!ret) {
c16336b9
CW		 1461 /*
1462 * Some sdvo encoders are not spec compliant and don't
1463 * implement the mandatory get_timings function.
1464 */
045ac3b5 1465 DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n");
bb760063
DV		 1466 pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS;
1467 } else {
1468 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
1469 flags |= DRM_MODE_FLAG_PHSYNC;
1470 else
1471 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1472
bb760063
DV		 1473 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
1474 flags |= DRM_MODE_FLAG_PVSYNC;
1475 else
1476 flags |= DRM_MODE_FLAG_NVSYNC;
045ac3b5
JB		 1477 }
1478
2d112de7 1479 pipe_config->base.adjusted_mode.flags |= flags;
045ac3b5 1480
fdafa9e2
DV		 1481 /*
1482 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in
1483 * the sdvo port register, on all other platforms it is part of the dpll
1484 * state. Since the general pipe state readout happens before the
1485 * encoder->get_config we so already have a valid pixel multplier on all
1486 * other platfroms.
1487 */
50a0bc90 1488 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
6c49f241
DV		 1489 pipe_config->pixel_multiplier =
1490 ((sdvox & SDVO_PORT_MULTIPLY_MASK)
1491 >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
1492 }
045ac3b5 1493
2b85886a 1494 dotclock = pipe_config->port_clock;
e3b247da 1495
2b85886a
VS		 1496 if (pipe_config->pixel_multiplier)
1497 dotclock /= pipe_config->pixel_multiplier;
18442d08 1498
2d112de7 1499 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
18442d08 1500
6c49f241 1501 /* Cross check the port pixel multiplier with the sdvo encoder state. */
53b91408
DL		 1502 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT,
1503 &val, 1)) {
1504 switch (val) {
1505 case SDVO_CLOCK_RATE_MULT_1X:
1506 encoder_pixel_multiplier = 1;
1507 break;
1508 case SDVO_CLOCK_RATE_MULT_2X:
1509 encoder_pixel_multiplier = 2;
1510 break;
1511 case SDVO_CLOCK_RATE_MULT_4X:
1512 encoder_pixel_multiplier = 4;
1513 break;
1514 }
6c49f241 1515 }
fdafa9e2 1516
b5a9fa09
DV		 1517 if (sdvox & HDMI_COLOR_RANGE_16_235)
1518 pipe_config->limited_color_range = true;
1519
de44e256
DV		 1520 if (sdvox & SDVO_AUDIO_ENABLE)
1521 pipe_config->has_audio = true;
1522
9f04003e
DV		 1523 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE,
1524 &val, 1)) {
1525 if (val == SDVO_ENCODE_HDMI)
1526 pipe_config->has_hdmi_sink = true;
1527 }
1528
6c49f241
DV		 1529 WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier,
1530 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
1531 pipe_config->pixel_multiplier, encoder_pixel_multiplier);
045ac3b5
JB		 1532}
1533
fd6bbda9 1534static void intel_disable_sdvo(struct intel_encoder *encoder,
5f88a9c6
VS		 1535 const struct intel_crtc_state *old_crtc_state,
1536 const struct drm_connector_state *conn_state)
ce22c320 1537{
fac5e23e 1538 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
8aca63aa 1539 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
463320ae 1540 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
ce22c320
DV		 1541 u32 temp;
1542
1543 intel_sdvo_set_active_outputs(intel_sdvo, 0);
1544 if (0)
1545 intel_sdvo_set_encoder_power_state(intel_sdvo,
1546 DRM_MODE_DPMS_OFF);
1547
1548 temp = I915_READ(intel_sdvo->sdvo_reg);
776ca7cf 1549
1612c8bd
VS		 1550 temp &= ~SDVO_ENABLE;
1551 intel_sdvo_write_sdvox(intel_sdvo, temp);
1552
1553 /*
1554 * HW workaround for IBX, we need to move the port
1555 * to transcoder A after disabling it to allow the
1556 * matching DP port to be enabled on transcoder A.
1557 */
1558 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
0c241d5b
VS		 1559 /*
1560 * We get CPU/PCH FIFO underruns on the other pipe when
1561 * doing the workaround. Sweep them under the rug.
1562 */
1563 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1564 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1565
76203467
VS		 1566 temp &= ~SDVO_PIPE_SEL_MASK;
1567 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
1612c8bd
VS		 1568 intel_sdvo_write_sdvox(intel_sdvo, temp);
1569
1570 temp &= ~SDVO_ENABLE;
1571 intel_sdvo_write_sdvox(intel_sdvo, temp);
0c241d5b 1572
0f0f74bc 1573 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
0c241d5b
VS		 1574 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1575 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
ce22c320
DV		 1576 }
1577}
1578
fd6bbda9 1579static void pch_disable_sdvo(struct intel_encoder *encoder,
5f88a9c6
VS		 1580 const struct intel_crtc_state *old_crtc_state,
1581 const struct drm_connector_state *old_conn_state)
3c65d1d1
VS		 1582{
1583}
1584
fd6bbda9 1585static void pch_post_disable_sdvo(struct intel_encoder *encoder,
5f88a9c6
VS		 1586 const struct intel_crtc_state *old_crtc_state,
1587 const struct drm_connector_state *old_conn_state)
3c65d1d1 1588{
fd6bbda9 1589 intel_disable_sdvo(encoder, old_crtc_state, old_conn_state);
3c65d1d1
VS		 1590}
1591
fd6bbda9 1592static void intel_enable_sdvo(struct intel_encoder *encoder,
5f88a9c6
VS		 1593 const struct intel_crtc_state *pipe_config,
1594 const struct drm_connector_state *conn_state)
ce22c320
DV		 1595{
1596 struct drm_device *dev = encoder->base.dev;
fac5e23e 1597 struct drm_i915_private *dev_priv = to_i915(dev);
8aca63aa 1598 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
463320ae 1599 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
79e53945 1600 u32 temp;
ce22c320
DV		 1601 bool input1, input2;
1602 int i;
d0a7b6de 1603 bool success;
ce22c320
DV		 1604
1605 temp = I915_READ(intel_sdvo->sdvo_reg);
3c65d1d1
VS		 1606 temp |= SDVO_ENABLE;
1607 intel_sdvo_write_sdvox(intel_sdvo, temp);
776ca7cf 1608
ce22c320 1609 for (i = 0; i < 2; i++)
0f0f74bc 1610 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
ce22c320 1611
d0a7b6de 1612 success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
c16336b9
CW		 1613 /*
1614 * Warn if the device reported failure to sync.
1615 *
ce22c320
DV		 1616 * A lot of SDVO devices fail to notify of sync, but it's
1617 * a given it the status is a success, we succeeded.
1618 */
d0a7b6de 1619 if (success && !input1) {
ce22c320
DV		 1620 DRM_DEBUG_KMS("First %s output reported failure to "
1621 "sync\n", SDVO_NAME(intel_sdvo));
1622 }
1623
1624 if (0)
1625 intel_sdvo_set_encoder_power_state(intel_sdvo,
1626 DRM_MODE_DPMS_ON);
1627 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
1628}
1629
c19de8eb
DL		 1630static enum drm_mode_status
1631intel_sdvo_mode_valid(struct drm_connector *connector,
1632 struct drm_display_mode *mode)
79e53945 1633{
df0e9248 1634 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
24b23882 1635 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
79e53945 1636
e4dd27aa
VS		 1637 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1638 return MODE_NO_DBLESCAN;
1639
ea5b213a 1640 if (intel_sdvo->pixel_clock_min > mode->clock)
79e53945
JB		 1641 return MODE_CLOCK_LOW;
1642
ea5b213a 1643 if (intel_sdvo->pixel_clock_max < mode->clock)
79e53945
JB		 1644 return MODE_CLOCK_HIGH;
1645
24b23882
MK		 1646 if (mode->clock > max_dotclk)
1647 return MODE_CLOCK_HIGH;
1648
8545423a 1649 if (intel_sdvo->is_lvds) {
ea5b213a 1650 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
12682a97 1651 return MODE_PANEL;
1652
ea5b213a 1653 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
12682a97 1654 return MODE_PANEL;
1655 }
1656
79e53945
JB		 1657 return MODE_OK;
1658}
1659
ea5b213a 1660static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
79e53945 1661{
1a3665c8 1662 BUILD_BUG_ON(sizeof(*caps) != 8);
e957d772
CW		 1663 if (!intel_sdvo_get_value(intel_sdvo,
1664 SDVO_CMD_GET_DEVICE_CAPS,
1665 caps, sizeof(*caps)))
1666 return false;
1667
1668 DRM_DEBUG_KMS("SDVO capabilities:\n"
1669 " vendor_id: %d\n"
1670 " device_id: %d\n"
1671 " device_rev_id: %d\n"
1672 " sdvo_version_major: %d\n"
1673 " sdvo_version_minor: %d\n"
1674 " sdvo_inputs_mask: %d\n"
1675 " smooth_scaling: %d\n"
1676 " sharp_scaling: %d\n"
1677 " up_scaling: %d\n"
1678 " down_scaling: %d\n"
1679 " stall_support: %d\n"
1680 " output_flags: %d\n",
1681 caps->vendor_id,
1682 caps->device_id,
1683 caps->device_rev_id,
1684 caps->sdvo_version_major,
1685 caps->sdvo_version_minor,
1686 caps->sdvo_inputs_mask,
1687 caps->smooth_scaling,
1688 caps->sharp_scaling,
1689 caps->up_scaling,
1690 caps->down_scaling,
1691 caps->stall_support,
1692 caps->output_flags);
1693
1694 return true;
79e53945
JB		 1695}
1696
5fa7ac9c 1697static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
79e53945 1698{
50a0bc90 1699 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
5fa7ac9c 1700 uint16_t hotplug;
79e53945 1701
50a0bc90 1702 if (!I915_HAS_HOTPLUG(dev_priv))
1d83d957
VS		 1703 return 0;
1704
c16336b9
CW		 1705 /*
1706 * HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
1707 * on the line.
1708 */
50a0bc90 1709 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
5fa7ac9c 1710 return 0;
768b107e 1711
5fa7ac9c
JN		 1712 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1713 &hotplug, sizeof(hotplug)))
1714 return 0;
768b107e 1715
5fa7ac9c 1716 return hotplug;
79e53945
JB		 1717}
1718
cc68c81a 1719static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
79e53945 1720{
8aca63aa 1721 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
79e53945 1722
5fa7ac9c 1723 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG,
1b2cb026
VS		 1724 &intel_sdvo->hotplug_active, 2);
1725}
1726
1727static bool intel_sdvo_hotplug(struct intel_encoder *encoder,
1728 struct intel_connector *connector)
1729{
1730 intel_sdvo_enable_hotplug(encoder);
1731
1732 return intel_encoder_hotplug(encoder, connector);
79e53945
JB		 1733}
1734
fb7a46f3 1735static bool
ea5b213a 1736intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
fb7a46f3 1737{
bc65212c 1738 /* Is there more than one type of output? */
2294488d 1739 return hweight16(intel_sdvo->caps.output_flags) > 1;
fb7a46f3 1740}
1741
f899fc64 1742static struct edid *
e957d772 1743intel_sdvo_get_edid(struct drm_connector *connector)
f899fc64 1744{
e957d772
CW		 1745 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1746 return drm_get_edid(connector, &sdvo->ddc);
f899fc64
CW		 1747}
1748
ff482d83
CW		 1749/* Mac mini hack -- use the same DDC as the analog connector */
1750static struct edid *
1751intel_sdvo_get_analog_edid(struct drm_connector *connector)
1752{
fac5e23e 1753 struct drm_i915_private *dev_priv = to_i915(connector->dev);
ff482d83 1754
0c1dab89 1755 return drm_get_edid(connector,
3bd7d909 1756 intel_gmbus_get_adapter(dev_priv,
41aa3448 1757 dev_priv->vbt.crt_ddc_pin));
ff482d83
CW		 1758}
1759
c43b5634 1760static enum drm_connector_status
8bf38485 1761intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
9dff6af8 1762{
df0e9248 1763 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
9d1a903d
CW		 1764 enum drm_connector_status status;
1765 struct edid *edid;
9dff6af8 1766
e957d772 1767 edid = intel_sdvo_get_edid(connector);
57cdaf90 1768
ea5b213a 1769 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
e957d772 1770 u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
9d1a903d 1771
7c3f0a27
ZY		 1772 /*
1773 * Don't use the 1 as the argument of DDC bus switch to get
1774 * the EDID. It is used for SDVO SPD ROM.
1775 */
9d1a903d 1776 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
e957d772
CW		 1777 intel_sdvo->ddc_bus = ddc;
1778 edid = intel_sdvo_get_edid(connector);
1779 if (edid)
7c3f0a27 1780 break;
7c3f0a27 1781 }
e957d772
CW		 1782 /*
1783 * If we found the EDID on the other bus,
1784 * assume that is the correct DDC bus.
1785 */
1786 if (edid == NULL)
1787 intel_sdvo->ddc_bus = saved_ddc;
7c3f0a27 1788 }
9d1a903d
CW		 1789
1790 /*
1791 * When there is no edid and no monitor is connected with VGA
1792 * port, try to use the CRT ddc to read the EDID for DVI-connector.
57cdaf90 1793 */
ff482d83
CW		 1794 if (edid == NULL)
1795 edid = intel_sdvo_get_analog_edid(connector);
149c36a3 1796
2f551c84 1797 status = connector_status_unknown;
9dff6af8 1798 if (edid != NULL) {
149c36a3 1799 /* DDC bus is shared, match EDID to connector type */
9d1a903d
CW		 1800 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1801 status = connector_status_connected;
da79de97
CW		 1802 if (intel_sdvo->is_hdmi) {
1803 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
1804 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
abedc077
VS		 1805 intel_sdvo->rgb_quant_range_selectable =
1806 drm_rgb_quant_range_selectable(edid);
da79de97 1807 }
13946743
CW		 1808 } else
1809 status = connector_status_disconnected;
9d1a903d
CW		 1810 kfree(edid);
1811 }
7f36e7ed 1812
2b8d33f7 1813 return status;
9dff6af8
ML		 1814}
1815
52220085
CW		 1816static bool
1817intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
1818 struct edid *edid)
1819{
1820 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1821 bool connector_is_digital = !!IS_DIGITAL(sdvo);
1822
1823 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
1824 connector_is_digital, monitor_is_digital);
1825 return connector_is_digital == monitor_is_digital;
1826}
1827
7b334fcb 1828static enum drm_connector_status
930a9e28 1829intel_sdvo_detect(struct drm_connector *connector, bool force)
79e53945 1830{
fb7a46f3 1831 uint16_t response;
df0e9248 1832 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1833 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
14571b4c 1834 enum drm_connector_status ret;
79e53945 1835
164c8598 1836 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 1837 connector->base.id, connector->name);
164c8598 1838
fc37381c
CW		 1839 if (!intel_sdvo_get_value(intel_sdvo,
1840 SDVO_CMD_GET_ATTACHED_DISPLAYS,
1841 &response, 2))
32aad86f 1842 return connector_status_unknown;
79e53945 1843
e957d772
CW		 1844 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
1845 response & 0xff, response >> 8,
1846 intel_sdvo_connector->output_flag);
e2f0ba97 1847
fb7a46f3 1848 if (response == 0)
79e53945 1849 return connector_status_disconnected;
fb7a46f3 1850
ea5b213a 1851 intel_sdvo->attached_output = response;
14571b4c 1852
97aaf910
CW		 1853 intel_sdvo->has_hdmi_monitor = false;
1854 intel_sdvo->has_hdmi_audio = false;
abedc077 1855 intel_sdvo->rgb_quant_range_selectable = false;
97aaf910 1856
615fb93f 1857 if ((intel_sdvo_connector->output_flag & response) == 0)
14571b4c 1858 ret = connector_status_disconnected;
13946743 1859 else if (IS_TMDS(intel_sdvo_connector))
8bf38485 1860 ret = intel_sdvo_tmds_sink_detect(connector);
13946743
CW		 1861 else {
1862 struct edid *edid;
1863
1864 /* if we have an edid check it matches the connection */
1865 edid = intel_sdvo_get_edid(connector);
1866 if (edid == NULL)
1867 edid = intel_sdvo_get_analog_edid(connector);
1868 if (edid != NULL) {
52220085
CW		 1869 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
1870 edid))
13946743 1871 ret = connector_status_connected;
52220085
CW		 1872 else
1873 ret = connector_status_disconnected;
1874
13946743
CW		 1875 kfree(edid);
1876 } else
1877 ret = connector_status_connected;
1878 }
14571b4c
ZW		 1879
1880 /* May update encoder flag for like clock for SDVO TV, etc.*/
1881 if (ret == connector_status_connected) {
ea5b213a
CW		 1882 intel_sdvo->is_tv = false;
1883 intel_sdvo->is_lvds = false;
14571b4c 1884
09ede541 1885 if (response & SDVO_TV_MASK)
ea5b213a 1886 intel_sdvo->is_tv = true;
14571b4c 1887 if (response & SDVO_LVDS_MASK)
8545423a 1888 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
fb7a46f3 1889 }
14571b4c
ZW		 1890
1891 return ret;
79e53945
JB		 1892}
1893
e2f0ba97 1894static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945 1895{
ff482d83 1896 struct edid *edid;
79e53945 1897
46a3f4a3 1898 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 1899 connector->base.id, connector->name);
46a3f4a3 1900
79e53945 1901 /* set the bus switch and get the modes */
e957d772 1902 edid = intel_sdvo_get_edid(connector);
79e53945 1903
57cdaf90
KP		 1904 /*
1905 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1906 * link between analog and digital outputs. So, if the regular SDVO
1907 * DDC fails, check to see if the analog output is disconnected, in
1908 * which case we'll look there for the digital DDC data.
e2f0ba97 1909 */
f899fc64
CW		 1910 if (edid == NULL)
1911 edid = intel_sdvo_get_analog_edid(connector);
1912
ff482d83 1913 if (edid != NULL) {
52220085
CW		 1914 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
1915 edid)) {
c555f023 1916 drm_connector_update_edid_property(connector, edid);
0c1dab89
CW		 1917 drm_add_edid_modes(connector, edid);
1918 }
13946743 1919
ff482d83 1920 kfree(edid);
e2f0ba97 1921 }
e2f0ba97
JB		 1922}
1923
1924/*
1925 * Set of SDVO TV modes.
1926 * Note! This is in reply order (see loop in get_tv_modes).
1927 * XXX: all 60Hz refresh?
1928 */
b1f559ec 1929static const struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1930 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1931 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1932 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1933 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1934 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1935 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1936 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1937 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1938 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1939 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1940 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1941 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1942 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1943 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1944 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1945 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1946 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1947 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1948 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1949 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1950 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1951 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1952 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1953 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1954 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1955 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1956 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1957 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1958 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1959 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1960 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1961 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1962 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1963 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1964 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1965 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1966 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1967 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1968 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1969 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1970 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1971 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1972 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1973 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1974 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1975 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1976 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1977 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1978 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1979 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1980 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1981 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1982 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1983 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1984 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1985 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1986 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1987};
1988
1989static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1990{
df0e9248 1991 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
630d30a4 1992 const struct drm_connector_state *conn_state = connector->state;
7026d4ac 1993 struct intel_sdvo_sdtv_resolution_request tv_res;
ce6feabd
ZY		 1994 uint32_t reply = 0, format_map = 0;
1995 int i;
e2f0ba97 1996
46a3f4a3 1997 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 1998 connector->base.id, connector->name);
46a3f4a3 1999
c16336b9
CW		 2000 /*
2001 * Read the list of supported input resolutions for the selected TV
e2f0ba97
JB		 2002 * format.
2003 */
630d30a4 2004 format_map = 1 << conn_state->tv.mode;
ce6feabd 2005 memcpy(&tv_res, &format_map,
32aad86f 2006 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
ce6feabd 2007
32aad86f
CW		 2008 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
2009 return;
ce6feabd 2010
32aad86f 2011 BUILD_BUG_ON(sizeof(tv_res) != 3);
e957d772
CW		 2012 if (!intel_sdvo_write_cmd(intel_sdvo,
2013 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
32aad86f
CW		 2014 &tv_res, sizeof(tv_res)))
2015 return;
2016 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
e2f0ba97
JB		 2017 return;
2018
2019 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 2020 if (reply & (1 << i)) {
2021 struct drm_display_mode *nmode;
2022 nmode = drm_mode_duplicate(connector->dev,
32aad86f 2023 &sdvo_tv_modes[i]);
7026d4ac
ZW		 2024 if (nmode)
2025 drm_mode_probed_add(connector, nmode);
2026 }
e2f0ba97
JB		 2027}
2028
7086c87f
ML		 2029static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
2030{
df0e9248 2031 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
fac5e23e 2032 struct drm_i915_private *dev_priv = to_i915(connector->dev);
12682a97 2033 struct drm_display_mode *newmode;
7086c87f 2034
46a3f4a3 2035 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 2036 connector->base.id, connector->name);
46a3f4a3 2037
7086c87f 2038 /*
c3456fb3 2039 * Fetch modes from VBT. For SDVO prefer the VBT mode since some
4300a0f8 2040 * SDVO->LVDS transcoders can't cope with the EDID mode.
7086c87f 2041 */
41aa3448 2042 if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) {
7086c87f 2043 newmode = drm_mode_duplicate(connector->dev,
41aa3448 2044 dev_priv->vbt.sdvo_lvds_vbt_mode);
7086c87f
ML		 2045 if (newmode != NULL) {
2046 /* Guarantee the mode is preferred */
2047 newmode->type = (DRM_MODE_TYPE_PREFERRED |
2048 DRM_MODE_TYPE_DRIVER);
2049 drm_mode_probed_add(connector, newmode);
2050 }
2051 }
12682a97 2052
4300a0f8
DA		 2053 /*
2054 * Attempt to get the mode list from DDC.
2055 * Assume that the preferred modes are
2056 * arranged in priority order.
2057 */
2058 intel_ddc_get_modes(connector, &intel_sdvo->ddc);
2059
12682a97 2060 list_for_each_entry(newmode, &connector->probed_modes, head) {
2061 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
ea5b213a 2062 intel_sdvo->sdvo_lvds_fixed_mode =
12682a97 2063 drm_mode_duplicate(connector->dev, newmode);
6c9547ff 2064
8545423a 2065 intel_sdvo->is_lvds = true;
12682a97 2066 break;
2067 }
2068 }
7086c87f
ML		 2069}
2070
e2f0ba97
JB		 2071static int intel_sdvo_get_modes(struct drm_connector *connector)
2072{
615fb93f 2073 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e2f0ba97 2074
615fb93f 2075 if (IS_TV(intel_sdvo_connector))
e2f0ba97 2076 intel_sdvo_get_tv_modes(connector);
615fb93f 2077 else if (IS_LVDS(intel_sdvo_connector))
7086c87f 2078 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 2079 else
2080 intel_sdvo_get_ddc_modes(connector);
2081
32aad86f 2082 return !list_empty(&connector->probed_modes);
79e53945
JB		 2083}
2084
2085static void intel_sdvo_destroy(struct drm_connector *connector)
2086{
615fb93f 2087 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
79e53945 2088
79e53945 2089 drm_connector_cleanup(connector);
4b745b1e 2090 kfree(intel_sdvo_connector);
79e53945
JB		 2091}
2092
ce6feabd 2093static int
630d30a4
ML		 2094intel_sdvo_connector_atomic_get_property(struct drm_connector *connector,
2095 const struct drm_connector_state *state,
2096 struct drm_property *property,
2097 uint64_t *val)
ce6feabd 2098{
615fb93f 2099 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
630d30a4 2100 const struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state((void *)state);
c5521706
CW		 2101
2102 if (property == intel_sdvo_connector->tv_format) {
630d30a4 2103 int i;
b9219c5e 2104
630d30a4
ML		 2105 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
2106 if (state->tv.mode == intel_sdvo_connector->tv_format_supported[i]) {
2107 *val = i;
b9219c5e 2108
32aad86f 2109 return 0;
630d30a4 2110 }
b9219c5e 2111
630d30a4
ML		 2112 WARN_ON(1);
2113 *val = 0;
2114 } else if (property == intel_sdvo_connector->top ||
2115 property == intel_sdvo_connector->bottom)
2116 *val = intel_sdvo_connector->max_vscan - sdvo_state->tv.overscan_v;
2117 else if (property == intel_sdvo_connector->left ||
2118 property == intel_sdvo_connector->right)
2119 *val = intel_sdvo_connector->max_hscan - sdvo_state->tv.overscan_h;
2120 else if (property == intel_sdvo_connector->hpos)
2121 *val = sdvo_state->tv.hpos;
2122 else if (property == intel_sdvo_connector->vpos)
2123 *val = sdvo_state->tv.vpos;
2124 else if (property == intel_sdvo_connector->saturation)
2125 *val = state->tv.saturation;
2126 else if (property == intel_sdvo_connector->contrast)
2127 *val = state->tv.contrast;
2128 else if (property == intel_sdvo_connector->hue)
2129 *val = state->tv.hue;
2130 else if (property == intel_sdvo_connector->brightness)
2131 *val = state->tv.brightness;
2132 else if (property == intel_sdvo_connector->sharpness)
2133 *val = sdvo_state->tv.sharpness;
2134 else if (property == intel_sdvo_connector->flicker_filter)
2135 *val = sdvo_state->tv.flicker_filter;
2136 else if (property == intel_sdvo_connector->flicker_filter_2d)
2137 *val = sdvo_state->tv.flicker_filter_2d;
2138 else if (property == intel_sdvo_connector->flicker_filter_adaptive)
2139 *val = sdvo_state->tv.flicker_filter_adaptive;
2140 else if (property == intel_sdvo_connector->tv_chroma_filter)
2141 *val = sdvo_state->tv.chroma_filter;
2142 else if (property == intel_sdvo_connector->tv_luma_filter)
2143 *val = sdvo_state->tv.luma_filter;
2144 else if (property == intel_sdvo_connector->dot_crawl)
2145 *val = sdvo_state->tv.dot_crawl;
2146 else
2147 return intel_digital_connector_atomic_get_property(connector, state, property, val);
32aad86f 2148
630d30a4
ML		 2149 return 0;
2150}
b9219c5e 2151
630d30a4
ML		 2152static int
2153intel_sdvo_connector_atomic_set_property(struct drm_connector *connector,
2154 struct drm_connector_state *state,
2155 struct drm_property *property,
2156 uint64_t val)
2157{
2158 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2159 struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state(state);
b9219c5e 2160
630d30a4
ML		 2161 if (property == intel_sdvo_connector->tv_format) {
2162 state->tv.mode = intel_sdvo_connector->tv_format_supported[val];
b9219c5e 2163
630d30a4
ML		 2164 if (state->crtc) {
2165 struct drm_crtc_state *crtc_state =
2166 drm_atomic_get_new_crtc_state(state->state, state->crtc);
b9219c5e 2167
630d30a4
ML		 2168 crtc_state->connectors_changed = true;
2169 }
2170 } else if (property == intel_sdvo_connector->top ||
2171 property == intel_sdvo_connector->bottom)
2172 /* Cannot set these independent from each other */
2173 sdvo_state->tv.overscan_v = intel_sdvo_connector->max_vscan - val;
2174 else if (property == intel_sdvo_connector->left ||
2175 property == intel_sdvo_connector->right)
2176 /* Cannot set these independent from each other */
2177 sdvo_state->tv.overscan_h = intel_sdvo_connector->max_hscan - val;
2178 else if (property == intel_sdvo_connector->hpos)
2179 sdvo_state->tv.hpos = val;
2180 else if (property == intel_sdvo_connector->vpos)
2181 sdvo_state->tv.vpos = val;
2182 else if (property == intel_sdvo_connector->saturation)
2183 state->tv.saturation = val;
2184 else if (property == intel_sdvo_connector->contrast)
2185 state->tv.contrast = val;
2186 else if (property == intel_sdvo_connector->hue)
2187 state->tv.hue = val;
2188 else if (property == intel_sdvo_connector->brightness)
2189 state->tv.brightness = val;
2190 else if (property == intel_sdvo_connector->sharpness)
2191 sdvo_state->tv.sharpness = val;
2192 else if (property == intel_sdvo_connector->flicker_filter)
2193 sdvo_state->tv.flicker_filter = val;
2194 else if (property == intel_sdvo_connector->flicker_filter_2d)
2195 sdvo_state->tv.flicker_filter_2d = val;
2196 else if (property == intel_sdvo_connector->flicker_filter_adaptive)
2197 sdvo_state->tv.flicker_filter_adaptive = val;
2198 else if (property == intel_sdvo_connector->tv_chroma_filter)
2199 sdvo_state->tv.chroma_filter = val;
2200 else if (property == intel_sdvo_connector->tv_luma_filter)
2201 sdvo_state->tv.luma_filter = val;
2202 else if (property == intel_sdvo_connector->dot_crawl)
2203 sdvo_state->tv.dot_crawl = val;
2204 else
2205 return intel_digital_connector_atomic_set_property(connector, state, property, val);
c5521706 2206
32aad86f 2207 return 0;
ce6feabd
ZY		 2208}
2209
7a418e34
CW		 2210static int
2211intel_sdvo_connector_register(struct drm_connector *connector)
2212{
2213 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1ebaa0b9
CW		 2214 int ret;
2215
2216 ret = intel_connector_register(connector);
2217 if (ret)
2218 return ret;
7a418e34
CW		 2219
2220 return sysfs_create_link(&connector->kdev->kobj,
2221 &sdvo->ddc.dev.kobj,
2222 sdvo->ddc.dev.kobj.name);
2223}
2224
c191eca1
CW		 2225static void
2226intel_sdvo_connector_unregister(struct drm_connector *connector)
2227{
2228 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
2229
2230 sysfs_remove_link(&connector->kdev->kobj,
2231 sdvo->ddc.dev.kobj.name);
2232 intel_connector_unregister(connector);
2233}
2234
630d30a4
ML		 2235static struct drm_connector_state *
2236intel_sdvo_connector_duplicate_state(struct drm_connector *connector)
2237{
2238 struct intel_sdvo_connector_state *state;
2239
2240 state = kmemdup(connector->state, sizeof(*state), GFP_KERNEL);
2241 if (!state)
2242 return NULL;
2243
2244 __drm_atomic_helper_connector_duplicate_state(connector, &state->base.base);
2245 return &state->base.base;
2246}
2247
79e53945 2248static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
79e53945
JB		 2249 .detect = intel_sdvo_detect,
2250 .fill_modes = drm_helper_probe_single_connector_modes,
630d30a4
ML		 2251 .atomic_get_property = intel_sdvo_connector_atomic_get_property,
2252 .atomic_set_property = intel_sdvo_connector_atomic_set_property,
7a418e34 2253 .late_register = intel_sdvo_connector_register,
c191eca1 2254 .early_unregister = intel_sdvo_connector_unregister,
79e53945 2255 .destroy = intel_sdvo_destroy,
c6f95f27 2256 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
630d30a4 2257 .atomic_duplicate_state = intel_sdvo_connector_duplicate_state,
79e53945
JB		 2258};
2259
630d30a4
ML		 2260static int intel_sdvo_atomic_check(struct drm_connector *conn,
2261 struct drm_connector_state *new_conn_state)
2262{
2263 struct drm_atomic_state *state = new_conn_state->state;
2264 struct drm_connector_state *old_conn_state =
2265 drm_atomic_get_old_connector_state(state, conn);
2266 struct intel_sdvo_connector_state *old_state =
2267 to_intel_sdvo_connector_state(old_conn_state);
2268 struct intel_sdvo_connector_state *new_state =
2269 to_intel_sdvo_connector_state(new_conn_state);
2270
2271 if (new_conn_state->crtc &&
2272 (memcmp(&old_state->tv, &new_state->tv, sizeof(old_state->tv)) ||
2273 memcmp(&old_conn_state->tv, &new_conn_state->tv, sizeof(old_conn_state->tv)))) {
2274 struct drm_crtc_state *crtc_state =
2275 drm_atomic_get_new_crtc_state(new_conn_state->state,
2276 new_conn_state->crtc);
2277
2278 crtc_state->connectors_changed = true;
2279 }
2280
2281 return intel_digital_connector_atomic_check(conn, new_conn_state);
2282}
2283
79e53945
JB		 2284static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
2285 .get_modes = intel_sdvo_get_modes,
2286 .mode_valid = intel_sdvo_mode_valid,
630d30a4 2287 .atomic_check = intel_sdvo_atomic_check,
79e53945
JB		 2288};
2289
b358d0a6 2290static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945 2291{
8aca63aa 2292 struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder));
d2a82a6f 2293
ea5b213a 2294 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
d2a82a6f 2295 drm_mode_destroy(encoder->dev,
ea5b213a 2296 intel_sdvo->sdvo_lvds_fixed_mode);
d2a82a6f 2297
e957d772 2298 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 2299 intel_encoder_destroy(encoder);
79e53945
JB		 2300}
2301
2302static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
2303 .destroy = intel_sdvo_enc_destroy,
2304};
2305
b66d8424
CW		 2306static void
2307intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
2308{
2309 uint16_t mask = 0;
2310 unsigned int num_bits;
2311
c16336b9
CW		 2312 /*
2313 * Make a mask of outputs less than or equal to our own priority in the
b66d8424
CW		 2314 * list.
2315 */
2316 switch (sdvo->controlled_output) {
2317 case SDVO_OUTPUT_LVDS1:
2318 mask |= SDVO_OUTPUT_LVDS1;
2319 case SDVO_OUTPUT_LVDS0:
2320 mask |= SDVO_OUTPUT_LVDS0;
2321 case SDVO_OUTPUT_TMDS1:
2322 mask |= SDVO_OUTPUT_TMDS1;
2323 case SDVO_OUTPUT_TMDS0:
2324 mask |= SDVO_OUTPUT_TMDS0;
2325 case SDVO_OUTPUT_RGB1:
2326 mask |= SDVO_OUTPUT_RGB1;
2327 case SDVO_OUTPUT_RGB0:
2328 mask |= SDVO_OUTPUT_RGB0;
2329 break;
2330 }
2331
2332 /* Count bits to find what number we are in the priority list. */
2333 mask &= sdvo->caps.output_flags;
2334 num_bits = hweight16(mask);
2335 /* If more than 3 outputs, default to DDC bus 3 for now. */
2336 if (num_bits > 3)
2337 num_bits = 3;
2338
2339 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
2340 sdvo->ddc_bus = 1 << num_bits;
2341}
79e53945 2342
c16336b9 2343/*
e2f0ba97
JB		 2344 * Choose the appropriate DDC bus for control bus switch command for this
2345 * SDVO output based on the controlled output.
2346 *
2347 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
2348 * outputs, then LVDS outputs.
2349 */
2350static void
b1083333 2351intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
8bd864b8 2352 struct intel_sdvo *sdvo)
e2f0ba97 2353{
b1083333 2354 struct sdvo_device_mapping *mapping;
e2f0ba97 2355
2a5c0832 2356 if (sdvo->port == PORT_B)
9d6c875d 2357 mapping = &dev_priv->vbt.sdvo_mappings[0];
b1083333 2358 else
9d6c875d 2359 mapping = &dev_priv->vbt.sdvo_mappings[1];
e2f0ba97 2360
b66d8424
CW		 2361 if (mapping->initialized)
2362 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
2363 else
2364 intel_sdvo_guess_ddc_bus(sdvo);
e2f0ba97
JB		 2365}
2366
e957d772
CW		 2367static void
2368intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
8bd864b8 2369 struct intel_sdvo *sdvo)
e957d772
CW		 2370{
2371 struct sdvo_device_mapping *mapping;
46eb3036 2372 u8 pin;
e957d772 2373
2a5c0832 2374 if (sdvo->port == PORT_B)
9d6c875d 2375 mapping = &dev_priv->vbt.sdvo_mappings[0];
e957d772 2376 else
9d6c875d 2377 mapping = &dev_priv->vbt.sdvo_mappings[1];
e957d772 2378
88ac7939
JN		 2379 if (mapping->initialized &&
2380 intel_gmbus_is_valid_pin(dev_priv, mapping->i2c_pin))
e957d772 2381 pin = mapping->i2c_pin;
6cb1612a 2382 else
988c7015 2383 pin = GMBUS_PIN_DPB;
e957d772 2384
6cb1612a
JN		 2385 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
2386
c16336b9
CW		 2387 /*
2388 * With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow
6cb1612a 2389 * our code totally fails once we start using gmbus. Hence fall back to
c16336b9
CW		 2390 * bit banging for now.
2391 */
6cb1612a 2392 intel_gmbus_force_bit(sdvo->i2c, true);
e957d772
CW		 2393}
2394
fbfcc4f3
JN		 2395/* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */
2396static void
2397intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo)
2398{
2399 intel_gmbus_force_bit(sdvo->i2c, false);
e957d772
CW		 2400}
2401
e2f0ba97 2402static bool
e27d8538 2403intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
e2f0ba97 2404{
97aaf910 2405 return intel_sdvo_check_supp_encode(intel_sdvo);
e2f0ba97
JB		 2406}
2407
714605e4 2408static u8
c39055b0
ACO		 2409intel_sdvo_get_slave_addr(struct drm_i915_private *dev_priv,
2410 struct intel_sdvo *sdvo)
714605e4 2411{
714605e4 2412 struct sdvo_device_mapping *my_mapping, *other_mapping;
2413
2a5c0832 2414 if (sdvo->port == PORT_B) {
9d6c875d
JN		 2415 my_mapping = &dev_priv->vbt.sdvo_mappings[0];
2416 other_mapping = &dev_priv->vbt.sdvo_mappings[1];
714605e4 2417 } else {
9d6c875d
JN		 2418 my_mapping = &dev_priv->vbt.sdvo_mappings[1];
2419 other_mapping = &dev_priv->vbt.sdvo_mappings[0];
714605e4 2420 }
2421
2422 /* If the BIOS described our SDVO device, take advantage of it. */
2423 if (my_mapping->slave_addr)
2424 return my_mapping->slave_addr;
2425
c16336b9
CW		 2426 /*
2427 * If the BIOS only described a different SDVO device, use the
714605e4 2428 * address that it isn't using.
2429 */
2430 if (other_mapping->slave_addr) {
2431 if (other_mapping->slave_addr == 0x70)
2432 return 0x72;
2433 else
2434 return 0x70;
2435 }
2436
c16336b9
CW		 2437 /*
2438 * No SDVO device info is found for another DVO port,
714605e4 2439 * so use mapping assumption we had before BIOS parsing.
2440 */
2a5c0832 2441 if (sdvo->port == PORT_B)
714605e4 2442 return 0x70;
2443 else
2444 return 0x72;
2445}
2446
c393454d 2447static int
df0e9248
CW		 2448intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
2449 struct intel_sdvo *encoder)
14571b4c 2450{
c393454d
ID		 2451 struct drm_connector *drm_connector;
2452 int ret;
2453
2454 drm_connector = &connector->base.base;
2455 ret = drm_connector_init(encoder->base.base.dev,
2456 drm_connector,
df0e9248
CW		 2457 &intel_sdvo_connector_funcs,
2458 connector->base.base.connector_type);
c393454d
ID		 2459 if (ret < 0)
2460 return ret;
6070a4a9 2461
c393454d 2462 drm_connector_helper_add(drm_connector,
df0e9248 2463 &intel_sdvo_connector_helper_funcs);
14571b4c 2464
8f4839e2 2465 connector->base.base.interlace_allowed = 1;
df0e9248
CW		 2466 connector->base.base.doublescan_allowed = 0;
2467 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
4ac41f47 2468 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
14571b4c 2469
df0e9248 2470 intel_connector_attach_encoder(&connector->base, &encoder->base);
c393454d
ID		 2471
2472 return 0;
14571b4c 2473}
6070a4a9 2474
7f36e7ed 2475static void
55bc60db
VS		 2476intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
2477 struct intel_sdvo_connector *connector)
7f36e7ed 2478{
646d5772 2479 struct drm_i915_private *dev_priv = to_i915(connector->base.base.dev);
7f36e7ed 2480
3f43c48d 2481 intel_attach_force_audio_property(&connector->base.base);
646d5772 2482 if (INTEL_GEN(dev_priv) >= 4 && IS_MOBILE(dev_priv)) {
e953fd7b 2483 intel_attach_broadcast_rgb_property(&connector->base.base);
55bc60db 2484 }
7949dd47 2485 intel_attach_aspect_ratio_property(&connector->base.base);
0e9f25d0 2486 connector->base.base.state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
7f36e7ed
CW		 2487}
2488
08d9bc92
ACO		 2489static struct intel_sdvo_connector *intel_sdvo_connector_alloc(void)
2490{
2491 struct intel_sdvo_connector *sdvo_connector;
630d30a4 2492 struct intel_sdvo_connector_state *conn_state;
08d9bc92
ACO		 2493
2494 sdvo_connector = kzalloc(sizeof(*sdvo_connector), GFP_KERNEL);
2495 if (!sdvo_connector)
2496 return NULL;
2497
630d30a4
ML		 2498 conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL);
2499 if (!conn_state) {
08d9bc92
ACO		 2500 kfree(sdvo_connector);
2501 return NULL;
2502 }
2503
630d30a4
ML		 2504 __drm_atomic_helper_connector_reset(&sdvo_connector->base.base,
2505 &conn_state->base.base);
2506
08d9bc92
ACO		 2507 return sdvo_connector;
2508}
2509
fb7a46f3 2510static bool
ea5b213a 2511intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
fb7a46f3 2512{
4ef69c7a 2513 struct drm_encoder *encoder = &intel_sdvo->base.base;
de44e256 2514 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
14571b4c 2515 struct drm_connector *connector;
cc68c81a 2516 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
14571b4c 2517 struct intel_connector *intel_connector;
615fb93f 2518 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2519
46a3f4a3
CW		 2520 DRM_DEBUG_KMS("initialising DVI device %d\n", device);
2521
08d9bc92 2522 intel_sdvo_connector = intel_sdvo_connector_alloc();
615fb93f 2523 if (!intel_sdvo_connector)
14571b4c
ZW		 2524 return false;
2525
14571b4c 2526 if (device == 0) {
ea5b213a 2527 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
615fb93f 2528 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
14571b4c 2529 } else if (device == 1) {
ea5b213a 2530 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
615fb93f 2531 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
14571b4c
ZW		 2532 }
2533
615fb93f 2534 intel_connector = &intel_sdvo_connector->base;
14571b4c 2535 connector = &intel_connector->base;
5fa7ac9c
JN		 2536 if (intel_sdvo_get_hotplug_support(intel_sdvo) &
2537 intel_sdvo_connector->output_flag) {
5fa7ac9c 2538 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag;
c16336b9
CW		 2539 /*
2540 * Some SDVO devices have one-shot hotplug interrupts.
cc68c81a
SF		 2541 * Ensure that they get re-enabled when an interrupt happens.
2542 */
1b2cb026 2543 intel_encoder->hotplug = intel_sdvo_hotplug;
3a2fb2c3 2544 intel_sdvo_enable_hotplug(intel_encoder);
5fa7ac9c 2545 } else {
821450c6 2546 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
5fa7ac9c 2547 }
14571b4c
ZW		 2548 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2549 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2550
de44e256
DV		 2551 /* gen3 doesn't do the hdmi bits in the SDVO register */
2552 if (INTEL_GEN(dev_priv) >= 4 &&
2553 intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
14571b4c 2554 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
e27d8538 2555 intel_sdvo->is_hdmi = true;
14571b4c 2556 }
14571b4c 2557
c393454d
ID		 2558 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2559 kfree(intel_sdvo_connector);
2560 return false;
2561 }
2562
f797d221 2563 if (intel_sdvo->is_hdmi)
55bc60db 2564 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector);
14571b4c
ZW		 2565
2566 return true;
2567}
2568
2569static bool
ea5b213a 2570intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
14571b4c 2571{
4ef69c7a
CW		 2572 struct drm_encoder *encoder = &intel_sdvo->base.base;
2573 struct drm_connector *connector;
2574 struct intel_connector *intel_connector;
2575 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2576
46a3f4a3
CW		 2577 DRM_DEBUG_KMS("initialising TV type %d\n", type);
2578
08d9bc92 2579 intel_sdvo_connector = intel_sdvo_connector_alloc();
615fb93f
CW		 2580 if (!intel_sdvo_connector)
2581 return false;
14571b4c 2582
615fb93f 2583 intel_connector = &intel_sdvo_connector->base;
4ef69c7a
CW		 2584 connector = &intel_connector->base;
2585 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2586 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
14571b4c 2587
4ef69c7a
CW		 2588 intel_sdvo->controlled_output |= type;
2589 intel_sdvo_connector->output_flag = type;
14571b4c 2590
4ef69c7a 2591 intel_sdvo->is_tv = true;
14571b4c 2592
c393454d
ID		 2593 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2594 kfree(intel_sdvo_connector);
2595 return false;
2596 }
14571b4c 2597
4ef69c7a 2598 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
32aad86f 2599 goto err;
14571b4c 2600
4ef69c7a 2601 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f 2602 goto err;
14571b4c 2603
4ef69c7a 2604 return true;
32aad86f
CW		 2605
2606err:
123d5c01 2607 intel_sdvo_destroy(connector);
32aad86f 2608 return false;
14571b4c
ZW		 2609}
2610
2611static bool
ea5b213a 2612intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2613{
4ef69c7a
CW		 2614 struct drm_encoder *encoder = &intel_sdvo->base.base;
2615 struct drm_connector *connector;
2616 struct intel_connector *intel_connector;
2617 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2618
46a3f4a3
CW		 2619 DRM_DEBUG_KMS("initialising analog device %d\n", device);
2620
8ce7da47 2621 intel_sdvo_connector = intel_sdvo_connector_alloc();
615fb93f
CW		 2622 if (!intel_sdvo_connector)
2623 return false;
14571b4c 2624
615fb93f 2625 intel_connector = &intel_sdvo_connector->base;
4ef69c7a 2626 connector = &intel_connector->base;
821450c6 2627 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
4ef69c7a
CW		 2628 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2629 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2630
2631 if (device == 0) {
2632 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2633 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2634 } else if (device == 1) {
2635 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2636 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2637 }
2638
c393454d
ID		 2639 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2640 kfree(intel_sdvo_connector);
2641 return false;
2642 }
2643
4ef69c7a 2644 return true;
14571b4c
ZW		 2645}
2646
2647static bool
ea5b213a 2648intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2649{
4ef69c7a
CW		 2650 struct drm_encoder *encoder = &intel_sdvo->base.base;
2651 struct drm_connector *connector;
2652 struct intel_connector *intel_connector;
2653 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2654
46a3f4a3
CW		 2655 DRM_DEBUG_KMS("initialising LVDS device %d\n", device);
2656
08d9bc92 2657 intel_sdvo_connector = intel_sdvo_connector_alloc();
615fb93f
CW		 2658 if (!intel_sdvo_connector)
2659 return false;
14571b4c 2660
615fb93f
CW		 2661 intel_connector = &intel_sdvo_connector->base;
2662 connector = &intel_connector->base;
4ef69c7a
CW		 2663 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2664 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2665
2666 if (device == 0) {
2667 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2668 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2669 } else if (device == 1) {
2670 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2671 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2672 }
2673
c393454d
ID		 2674 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2675 kfree(intel_sdvo_connector);
2676 return false;
2677 }
2678
4ef69c7a 2679 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f
CW		 2680 goto err;
2681
2682 return true;
2683
2684err:
123d5c01 2685 intel_sdvo_destroy(connector);
32aad86f 2686 return false;
14571b4c
ZW		 2687}
2688
2689static bool
ea5b213a 2690intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
14571b4c 2691{
ea5b213a 2692 intel_sdvo->is_tv = false;
ea5b213a 2693 intel_sdvo->is_lvds = false;
fb7a46f3 2694
14571b4c 2695 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
fb7a46f3 2696
14571b4c 2697 if (flags & SDVO_OUTPUT_TMDS0)
ea5b213a 2698 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
14571b4c
ZW		 2699 return false;
2700
2701 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
ea5b213a 2702 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
14571b4c
ZW		 2703 return false;
2704
2705 /* TV has no XXX1 function block */
a1f4b7ff 2706 if (flags & SDVO_OUTPUT_SVID0)
ea5b213a 2707 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
14571b4c
ZW		 2708 return false;
2709
2710 if (flags & SDVO_OUTPUT_CVBS0)
ea5b213a 2711 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
14571b4c 2712 return false;
fb7a46f3 2713
a0b1c7a5
CW		 2714 if (flags & SDVO_OUTPUT_YPRPB0)
2715 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
2716 return false;
2717
14571b4c 2718 if (flags & SDVO_OUTPUT_RGB0)
ea5b213a 2719 if (!intel_sdvo_analog_init(intel_sdvo, 0))
14571b4c
ZW		 2720 return false;
2721
2722 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
ea5b213a 2723 if (!intel_sdvo_analog_init(intel_sdvo, 1))
14571b4c
ZW		 2724 return false;
2725
2726 if (flags & SDVO_OUTPUT_LVDS0)
ea5b213a 2727 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
14571b4c
ZW		 2728 return false;
2729
2730 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
ea5b213a 2731 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
14571b4c 2732 return false;
fb7a46f3 2733
14571b4c 2734 if ((flags & SDVO_OUTPUT_MASK) == 0) {
fb7a46f3 2735 unsigned char bytes[2];
2736
ea5b213a
CW		 2737 intel_sdvo->controlled_output = 0;
2738 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
51c8b407 2739 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
ea5b213a 2740 SDVO_NAME(intel_sdvo),
51c8b407 2741 bytes[0], bytes[1]);
14571b4c 2742 return false;
fb7a46f3 2743 }
27f8227b 2744 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
fb7a46f3 2745
14571b4c 2746 return true;
fb7a46f3 2747}
2748
d0ddfbd3
JN		 2749static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)
2750{
2751 struct drm_device *dev = intel_sdvo->base.base.dev;
2752 struct drm_connector *connector, *tmp;
2753
2754 list_for_each_entry_safe(connector, tmp,
2755 &dev->mode_config.connector_list, head) {
d9255d57 2756 if (intel_attached_encoder(connector) == &intel_sdvo->base) {
34ea3d38 2757 drm_connector_unregister(connector);
d0ddfbd3 2758 intel_sdvo_destroy(connector);
d9255d57 2759 }
d0ddfbd3
JN		 2760 }
2761}
2762
32aad86f
CW		 2763static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2764 struct intel_sdvo_connector *intel_sdvo_connector,
2765 int type)
ce6feabd 2766{
4ef69c7a 2767 struct drm_device *dev = intel_sdvo->base.base.dev;
ce6feabd
ZY		 2768 struct intel_sdvo_tv_format format;
2769 uint32_t format_map, i;
ce6feabd 2770
32aad86f
CW		 2771 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2772 return false;
ce6feabd 2773
1a3665c8 2774 BUILD_BUG_ON(sizeof(format) != 6);
32aad86f
CW		 2775 if (!intel_sdvo_get_value(intel_sdvo,
2776 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2777 &format, sizeof(format)))
2778 return false;
ce6feabd 2779
32aad86f 2780 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
ce6feabd
ZY		 2781
2782 if (format_map == 0)
32aad86f 2783 return false;
ce6feabd 2784
615fb93f 2785 intel_sdvo_connector->format_supported_num = 0;
ce6feabd 2786 for (i = 0 ; i < TV_FORMAT_NUM; i++)
40039750
CW		 2787 if (format_map & (1 << i))
2788 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
ce6feabd
ZY		 2789
2790
c5521706 2791 intel_sdvo_connector->tv_format =
32aad86f
CW		 2792 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2793 "mode", intel_sdvo_connector->format_supported_num);
c5521706 2794 if (!intel_sdvo_connector->tv_format)
fcc8d672 2795 return false;
ce6feabd 2796
615fb93f 2797 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
30e9db6d
VS		 2798 drm_property_add_enum(intel_sdvo_connector->tv_format, i,
2799 tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
ce6feabd 2800
630d30a4 2801 intel_sdvo_connector->base.base.state->tv.mode = intel_sdvo_connector->tv_format_supported[0];
10223df2
VS		 2802 drm_object_attach_property(&intel_sdvo_connector->base.base.base,
2803 intel_sdvo_connector->tv_format, 0);
32aad86f 2804 return true;
ce6feabd
ZY		 2805
2806}
2807
630d30a4 2808#define _ENHANCEMENT(state_assignment, name, NAME) do { \
c5521706
CW		 2809 if (enhancements.name) { \
2810 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2811 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2812 return false; \
c5521706 2813 intel_sdvo_connector->name = \
d9bc3c02 2814 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
c5521706 2815 if (!intel_sdvo_connector->name) return false; \
630d30a4 2816 state_assignment = response; \
662595df 2817 drm_object_attach_property(&connector->base, \
630d30a4 2818 intel_sdvo_connector->name, 0); \
c5521706
CW		 2819 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2820 data_value[0], data_value[1], response); \
2821 } \
0206e353 2822} while (0)
c5521706 2823
630d30a4
ML		 2824#define ENHANCEMENT(state, name, NAME) _ENHANCEMENT((state)->name, name, NAME)
2825
c5521706
CW		 2826static bool
2827intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2828 struct intel_sdvo_connector *intel_sdvo_connector,
2829 struct intel_sdvo_enhancements_reply enhancements)
b9219c5e 2830{
4ef69c7a 2831 struct drm_device *dev = intel_sdvo->base.base.dev;
32aad86f 2832 struct drm_connector *connector = &intel_sdvo_connector->base.base;
630d30a4
ML		 2833 struct drm_connector_state *conn_state = connector->state;
2834 struct intel_sdvo_connector_state *sdvo_state =
2835 to_intel_sdvo_connector_state(conn_state);
b9219c5e
ZY		 2836 uint16_t response, data_value[2];
2837
c16336b9 2838 /* when horizontal overscan is supported, Add the left/right property */
c5521706
CW		 2839 if (enhancements.overscan_h) {
2840 if (!intel_sdvo_get_value(intel_sdvo,
2841 SDVO_CMD_GET_MAX_OVERSCAN_H,
2842 &data_value, 4))
2843 return false;
32aad86f 2844
c5521706
CW		 2845 if (!intel_sdvo_get_value(intel_sdvo,
2846 SDVO_CMD_GET_OVERSCAN_H,
2847 &response, 2))
2848 return false;
fcc8d672 2849
630d30a4
ML		 2850 sdvo_state->tv.overscan_h = response;
2851
c5521706 2852 intel_sdvo_connector->max_hscan = data_value[0];
c5521706 2853 intel_sdvo_connector->left =
d9bc3c02 2854 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
c5521706
CW		 2855 if (!intel_sdvo_connector->left)
2856 return false;
fcc8d672 2857
662595df 2858 drm_object_attach_property(&connector->base,
630d30a4 2859 intel_sdvo_connector->left, 0);
fcc8d672 2860
c5521706 2861 intel_sdvo_connector->right =
d9bc3c02 2862 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
c5521706
CW		 2863 if (!intel_sdvo_connector->right)
2864 return false;
32aad86f 2865
662595df 2866 drm_object_attach_property(&connector->base,
630d30a4 2867 intel_sdvo_connector->right, 0);
c5521706
CW		 2868 DRM_DEBUG_KMS("h_overscan: max %d, "
2869 "default %d, current %d\n",
2870 data_value[0], data_value[1], response);
2871 }
32aad86f 2872
c5521706
CW		 2873 if (enhancements.overscan_v) {
2874 if (!intel_sdvo_get_value(intel_sdvo,
2875 SDVO_CMD_GET_MAX_OVERSCAN_V,
2876 &data_value, 4))
2877 return false;
fcc8d672 2878
c5521706
CW		 2879 if (!intel_sdvo_get_value(intel_sdvo,
2880 SDVO_CMD_GET_OVERSCAN_V,
2881 &response, 2))
2882 return false;
32aad86f 2883
630d30a4
ML		 2884 sdvo_state->tv.overscan_v = response;
2885
c5521706 2886 intel_sdvo_connector->max_vscan = data_value[0];
c5521706 2887 intel_sdvo_connector->top =
d9bc3c02
SH		 2888 drm_property_create_range(dev, 0,
2889 "top_margin", 0, data_value[0]);
c5521706
CW		 2890 if (!intel_sdvo_connector->top)
2891 return false;
32aad86f 2892
662595df 2893 drm_object_attach_property(&connector->base,
630d30a4 2894 intel_sdvo_connector->top, 0);
fcc8d672 2895
c5521706 2896 intel_sdvo_connector->bottom =
d9bc3c02
SH		 2897 drm_property_create_range(dev, 0,
2898 "bottom_margin", 0, data_value[0]);
c5521706
CW		 2899 if (!intel_sdvo_connector->bottom)
2900 return false;
32aad86f 2901
662595df 2902 drm_object_attach_property(&connector->base,
630d30a4 2903 intel_sdvo_connector->bottom, 0);
c5521706
CW		 2904 DRM_DEBUG_KMS("v_overscan: max %d, "
2905 "default %d, current %d\n",
2906 data_value[0], data_value[1], response);
2907 }
32aad86f 2908
630d30a4
ML		 2909 ENHANCEMENT(&sdvo_state->tv, hpos, HPOS);
2910 ENHANCEMENT(&sdvo_state->tv, vpos, VPOS);
2911 ENHANCEMENT(&conn_state->tv, saturation, SATURATION);
2912 ENHANCEMENT(&conn_state->tv, contrast, CONTRAST);
2913 ENHANCEMENT(&conn_state->tv, hue, HUE);
2914 ENHANCEMENT(&conn_state->tv, brightness, BRIGHTNESS);
2915 ENHANCEMENT(&sdvo_state->tv, sharpness, SHARPNESS);
2916 ENHANCEMENT(&sdvo_state->tv, flicker_filter, FLICKER_FILTER);
2917 ENHANCEMENT(&sdvo_state->tv, flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2918 ENHANCEMENT(&sdvo_state->tv, flicker_filter_2d, FLICKER_FILTER_2D);
2919 _ENHANCEMENT(sdvo_state->tv.chroma_filter, tv_chroma_filter, TV_CHROMA_FILTER);
2920 _ENHANCEMENT(sdvo_state->tv.luma_filter, tv_luma_filter, TV_LUMA_FILTER);
fcc8d672 2921
e044218a
CW		 2922 if (enhancements.dot_crawl) {
2923 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2924 return false;
2925
630d30a4 2926 sdvo_state->tv.dot_crawl = response & 0x1;
e044218a 2927 intel_sdvo_connector->dot_crawl =
d9bc3c02 2928 drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
e044218a
CW		 2929 if (!intel_sdvo_connector->dot_crawl)
2930 return false;
2931
662595df 2932 drm_object_attach_property(&connector->base,
630d30a4 2933 intel_sdvo_connector->dot_crawl, 0);
e044218a
CW		 2934 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2935 }
2936
c5521706
CW		 2937 return true;
2938}
32aad86f 2939
c5521706
CW		 2940static bool
2941intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2942 struct intel_sdvo_connector *intel_sdvo_connector,
2943 struct intel_sdvo_enhancements_reply enhancements)
2944{
4ef69c7a 2945 struct drm_device *dev = intel_sdvo->base.base.dev;
c5521706
CW		 2946 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2947 uint16_t response, data_value[2];
32aad86f 2948
630d30a4 2949 ENHANCEMENT(&connector->state->tv, brightness, BRIGHTNESS);
fcc8d672 2950
c5521706
CW		 2951 return true;
2952}
2953#undef ENHANCEMENT
630d30a4 2954#undef _ENHANCEMENT
32aad86f 2955
c5521706
CW		 2956static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2957 struct intel_sdvo_connector *intel_sdvo_connector)
2958{
2959 union {
2960 struct intel_sdvo_enhancements_reply reply;
2961 uint16_t response;
2962 } enhancements;
32aad86f 2963
1a3665c8
CW		 2964 BUILD_BUG_ON(sizeof(enhancements) != 2);
2965
99016646
ID		 2966 if (!intel_sdvo_get_value(intel_sdvo,
2967 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2968 &enhancements, sizeof(enhancements)) ||
2969 enhancements.response == 0) {
c5521706
CW		 2970 DRM_DEBUG_KMS("No enhancement is supported\n");
2971 return true;
b9219c5e 2972 }
32aad86f 2973
c5521706
CW		 2974 if (IS_TV(intel_sdvo_connector))
2975 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
0206e353 2976 else if (IS_LVDS(intel_sdvo_connector))
c5521706
CW		 2977 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2978 else
2979 return true;
e957d772
CW		 2980}
2981
2982static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
2983 struct i2c_msg *msgs,
2984 int num)
2985{
2986 struct intel_sdvo *sdvo = adapter->algo_data;
fcc8d672 2987
a8506684 2988 if (!__intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
e957d772
CW		 2989 return -EIO;
2990
2991 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
2992}
2993
2994static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
2995{
2996 struct intel_sdvo *sdvo = adapter->algo_data;
2997 return sdvo->i2c->algo->functionality(sdvo->i2c);
2998}
2999
3000static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
3001 .master_xfer = intel_sdvo_ddc_proxy_xfer,
3002 .functionality = intel_sdvo_ddc_proxy_func
3003};
3004
a8506684
DV		 3005static void proxy_lock_bus(struct i2c_adapter *adapter,
3006 unsigned int flags)
3007{
3008 struct intel_sdvo *sdvo = adapter->algo_data;
3009 sdvo->i2c->lock_ops->lock_bus(sdvo->i2c, flags);
3010}
3011
3012static int proxy_trylock_bus(struct i2c_adapter *adapter,
3013 unsigned int flags)
3014{
3015 struct intel_sdvo *sdvo = adapter->algo_data;
3016 return sdvo->i2c->lock_ops->trylock_bus(sdvo->i2c, flags);
3017}
3018
3019static void proxy_unlock_bus(struct i2c_adapter *adapter,
3020 unsigned int flags)
3021{
3022 struct intel_sdvo *sdvo = adapter->algo_data;
3023 sdvo->i2c->lock_ops->unlock_bus(sdvo->i2c, flags);
3024}
3025
0db1aa42 3026static const struct i2c_lock_operations proxy_lock_ops = {
a8506684
DV		 3027 .lock_bus = proxy_lock_bus,
3028 .trylock_bus = proxy_trylock_bus,
3029 .unlock_bus = proxy_unlock_bus,
3030};
3031
e957d772
CW		 3032static bool
3033intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
c39055b0 3034 struct drm_i915_private *dev_priv)
e957d772 3035{
c39055b0 3036 struct pci_dev *pdev = dev_priv->drm.pdev;
52a05c30 3037
e957d772
CW		 3038 sdvo->ddc.owner = THIS_MODULE;
3039 sdvo->ddc.class = I2C_CLASS_DDC;
3040 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
52a05c30 3041 sdvo->ddc.dev.parent = &pdev->dev;
e957d772
CW		 3042 sdvo->ddc.algo_data = sdvo;
3043 sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
a8506684 3044 sdvo->ddc.lock_ops = &proxy_lock_ops;
e957d772
CW		 3045
3046 return i2c_add_adapter(&sdvo->ddc) == 0;
b9219c5e
ZY		 3047}
3048
2a5c0832
VS		 3049static void assert_sdvo_port_valid(const struct drm_i915_private *dev_priv,
3050 enum port port)
3051{
3052 if (HAS_PCH_SPLIT(dev_priv))
3053 WARN_ON(port != PORT_B);
3054 else
3055 WARN_ON(port != PORT_B && port != PORT_C);
3056}
3057
c39055b0 3058bool intel_sdvo_init(struct drm_i915_private *dev_priv,
f0f59a00 3059 i915_reg_t sdvo_reg, enum port port)
79e53945 3060{
21d40d37 3061 struct intel_encoder *intel_encoder;
ea5b213a 3062 struct intel_sdvo *intel_sdvo;
79e53945 3063 int i;
2a5c0832
VS		 3064
3065 assert_sdvo_port_valid(dev_priv, port);
3066
b14c5679 3067 intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL);
ea5b213a 3068 if (!intel_sdvo)
7d57382e 3069 return false;
79e53945 3070
56184e3d 3071 intel_sdvo->sdvo_reg = sdvo_reg;
2a5c0832 3072 intel_sdvo->port = port;
c39055b0
ACO		 3073 intel_sdvo->slave_addr =
3074 intel_sdvo_get_slave_addr(dev_priv, intel_sdvo) >> 1;
8bd864b8 3075 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo);
c39055b0 3076 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev_priv))
fbfcc4f3 3077 goto err_i2c_bus;
e957d772 3078
56184e3d 3079 /* encoder type will be decided later */
ea5b213a 3080 intel_encoder = &intel_sdvo->base;
21d40d37 3081 intel_encoder->type = INTEL_OUTPUT_SDVO;
79f255a0 3082 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
03cdc1d4 3083 intel_encoder->port = port;
c39055b0
ACO		 3084 drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
3085 &intel_sdvo_enc_funcs, 0,
580d8ed5 3086 "SDVO %c", port_name(port));
79e53945 3087
79e53945
JB		 3088 /* Read the regs to test if we can talk to the device */
3089 for (i = 0; i < 0x40; i++) {
f899fc64
CW		 3090 u8 byte;
3091
3092 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
eef4eacb
DV		 3093 DRM_DEBUG_KMS("No SDVO device found on %s\n",
3094 SDVO_NAME(intel_sdvo));
f899fc64 3095 goto err;
79e53945
JB		 3096 }
3097 }
3098
6cc5f341 3099 intel_encoder->compute_config = intel_sdvo_compute_config;
6e266956 3100 if (HAS_PCH_SPLIT(dev_priv)) {
3c65d1d1
VS		 3101 intel_encoder->disable = pch_disable_sdvo;
3102 intel_encoder->post_disable = pch_post_disable_sdvo;
3103 } else {
3104 intel_encoder->disable = intel_disable_sdvo;
3105 }
192d47a6 3106 intel_encoder->pre_enable = intel_sdvo_pre_enable;
ce22c320 3107 intel_encoder->enable = intel_enable_sdvo;
4ac41f47 3108 intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
045ac3b5 3109 intel_encoder->get_config = intel_sdvo_get_config;
ce22c320 3110
af901ca1 3111 /* In default case sdvo lvds is false */
32aad86f 3112 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
f899fc64 3113 goto err;
79e53945 3114
ea5b213a
CW		 3115 if (intel_sdvo_output_setup(intel_sdvo,
3116 intel_sdvo->caps.output_flags) != true) {
eef4eacb
DV		 3117 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
3118 SDVO_NAME(intel_sdvo));
d0ddfbd3
JN		 3119 /* Output_setup can leave behind connectors! */
3120 goto err_output;
79e53945
JB		 3121 }
3122
c16336b9
CW		 3123 /*
3124 * Only enable the hotplug irq if we need it, to work around noisy
7ba220ce
CW		 3125 * hotplug lines.
3126 */
3127 if (intel_sdvo->hotplug_active) {
2a5c0832
VS		 3128 if (intel_sdvo->port == PORT_B)
3129 intel_encoder->hpd_pin = HPD_SDVO_B;
3130 else
3131 intel_encoder->hpd_pin = HPD_SDVO_C;
7ba220ce
CW		 3132 }
3133
e506d6fd
DV		 3134 /*
3135 * Cloning SDVO with anything is often impossible, since the SDVO
3136 * encoder can request a special input timing mode. And even if that's
3137 * not the case we have evidence that cloning a plain unscaled mode with
3138 * VGA doesn't really work. Furthermore the cloning flags are way too
3139 * simplistic anyway to express such constraints, so just give up on
3140 * cloning for SDVO encoders.
3141 */
bc079e8b 3142 intel_sdvo->base.cloneable = 0;
e506d6fd 3143
8bd864b8 3144 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo);
e2f0ba97 3145
79e53945 3146 /* Set the input timing to the screen. Assume always input 0. */
32aad86f 3147 if (!intel_sdvo_set_target_input(intel_sdvo))
d0ddfbd3 3148 goto err_output;
79e53945 3149
32aad86f
CW		 3150 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
3151 &intel_sdvo->pixel_clock_min,
3152 &intel_sdvo->pixel_clock_max))
d0ddfbd3 3153 goto err_output;
79e53945 3154
8a4c47f3 3155 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
342dc382 3156 "clock range %dMHz - %dMHz, "
3157 "input 1: %c, input 2: %c, "
3158 "output 1: %c, output 2: %c\n",
ea5b213a
CW		 3159 SDVO_NAME(intel_sdvo),
3160 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
3161 intel_sdvo->caps.device_rev_id,
3162 intel_sdvo->pixel_clock_min / 1000,
3163 intel_sdvo->pixel_clock_max / 1000,
3164 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
3165 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
342dc382 3166 /* check currently supported outputs */
ea5b213a 3167 intel_sdvo->caps.output_flags &
79e53945 3168 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
ea5b213a 3169 intel_sdvo->caps.output_flags &
79e53945 3170 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
7d57382e 3171 return true;
79e53945 3172
d0ddfbd3
JN		 3173err_output:
3174 intel_sdvo_output_cleanup(intel_sdvo);
3175
f899fc64 3176err:
373a3cf7 3177 drm_encoder_cleanup(&intel_encoder->base);
e957d772 3178 i2c_del_adapter(&intel_sdvo->ddc);
fbfcc4f3
JN		 3179err_i2c_bus:
3180 intel_sdvo_unselect_i2c_bus(intel_sdvo);
ea5b213a 3181 kfree(intel_sdvo);
79e53945 3182
7d57382e 3183 return false;
79e53945 3184}
Linux 6.x block layer and io_uring tree(s)