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79e53945 JB |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2007 Intel Corporation | |
4 | * Jesse Barnes <jesse.barnes@intel.com> | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
23 | * DEALINGS IN THE SOFTWARE. | |
24 | * | |
25 | * Authors: | |
26 | * Eric Anholt <eric@anholt.net> | |
27 | */ | |
28 | #include <linux/i2c.h> | |
29 | #include <linux/delay.h> | |
30 | #include "drmP.h" | |
31 | #include "drm.h" | |
32 | #include "drm_crtc.h" | |
33 | #include "intel_drv.h" | |
2b8d33f7 | 34 | #include "drm_edid.h" |
79e53945 JB |
35 | #include "i915_drm.h" |
36 | #include "i915_drv.h" | |
37 | #include "intel_sdvo_regs.h" | |
38 | ||
ce6feabd ZY |
39 | static char *tv_format_names[] = { |
40 | "NTSC_M" , "NTSC_J" , "NTSC_443", | |
41 | "PAL_B" , "PAL_D" , "PAL_G" , | |
42 | "PAL_H" , "PAL_I" , "PAL_M" , | |
43 | "PAL_N" , "PAL_NC" , "PAL_60" , | |
44 | "SECAM_B" , "SECAM_D" , "SECAM_G" , | |
45 | "SECAM_K" , "SECAM_K1", "SECAM_L" , | |
46 | "SECAM_60" | |
47 | }; | |
48 | ||
49 | #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names)) | |
50 | ||
79e53945 | 51 | struct intel_sdvo_priv { |
f9c10a9b | 52 | u8 slave_addr; |
e2f0ba97 JB |
53 | |
54 | /* Register for the SDVO device: SDVOB or SDVOC */ | |
79e53945 JB |
55 | int output_device; |
56 | ||
e2f0ba97 JB |
57 | /* Active outputs controlled by this SDVO output */ |
58 | uint16_t controlled_output; | |
79e53945 | 59 | |
e2f0ba97 JB |
60 | /* |
61 | * Capabilities of the SDVO device returned by | |
62 | * i830_sdvo_get_capabilities() | |
63 | */ | |
79e53945 | 64 | struct intel_sdvo_caps caps; |
e2f0ba97 JB |
65 | |
66 | /* Pixel clock limitations reported by the SDVO device, in kHz */ | |
79e53945 JB |
67 | int pixel_clock_min, pixel_clock_max; |
68 | ||
fb7a46f3 | 69 | /* |
70 | * For multiple function SDVO device, | |
71 | * this is for current attached outputs. | |
72 | */ | |
73 | uint16_t attached_output; | |
74 | ||
e2f0ba97 JB |
75 | /** |
76 | * This is set if we're going to treat the device as TV-out. | |
77 | * | |
78 | * While we have these nice friendly flags for output types that ought | |
79 | * to decide this for us, the S-Video output on our HDMI+S-Video card | |
80 | * shows up as RGB1 (VGA). | |
81 | */ | |
82 | bool is_tv; | |
83 | ||
ce6feabd ZY |
84 | /* This is for current tv format name */ |
85 | char *tv_format_name; | |
86 | ||
87 | /* This contains all current supported TV format */ | |
88 | char *tv_format_supported[TV_FORMAT_NUM]; | |
89 | int format_supported_num; | |
90 | struct drm_property *tv_format_property; | |
91 | struct drm_property *tv_format_name_property[TV_FORMAT_NUM]; | |
92 | ||
e2f0ba97 JB |
93 | /** |
94 | * This is set if we treat the device as HDMI, instead of DVI. | |
95 | */ | |
96 | bool is_hdmi; | |
12682a97 | 97 | |
7086c87f ML |
98 | /** |
99 | * This is set if we detect output of sdvo device as LVDS. | |
100 | */ | |
101 | bool is_lvds; | |
e2f0ba97 | 102 | |
12682a97 | 103 | /** |
104 | * This is sdvo flags for input timing. | |
105 | */ | |
106 | uint8_t sdvo_flags; | |
107 | ||
108 | /** | |
109 | * This is sdvo fixed pannel mode pointer | |
110 | */ | |
111 | struct drm_display_mode *sdvo_lvds_fixed_mode; | |
112 | ||
e2f0ba97 JB |
113 | /** |
114 | * Returned SDTV resolutions allowed for the current format, if the | |
115 | * device reported it. | |
116 | */ | |
117 | struct intel_sdvo_sdtv_resolution_reply sdtv_resolutions; | |
118 | ||
e2f0ba97 JB |
119 | /* |
120 | * supported encoding mode, used to determine whether HDMI is | |
121 | * supported | |
122 | */ | |
123 | struct intel_sdvo_encode encode; | |
124 | ||
125 | /* DDC bus used by this SDVO output */ | |
126 | uint8_t ddc_bus; | |
127 | ||
57cdaf90 KP |
128 | /* Mac mini hack -- use the same DDC as the analog connector */ |
129 | struct i2c_adapter *analog_ddc_bus; | |
130 | ||
79e53945 JB |
131 | int save_sdvo_mult; |
132 | u16 save_active_outputs; | |
133 | struct intel_sdvo_dtd save_input_dtd_1, save_input_dtd_2; | |
134 | struct intel_sdvo_dtd save_output_dtd[16]; | |
135 | u32 save_SDVOX; | |
b9219c5e ZY |
136 | /* add the property for the SDVO-TV */ |
137 | struct drm_property *left_property; | |
138 | struct drm_property *right_property; | |
139 | struct drm_property *top_property; | |
140 | struct drm_property *bottom_property; | |
141 | struct drm_property *hpos_property; | |
142 | struct drm_property *vpos_property; | |
143 | ||
144 | /* add the property for the SDVO-TV/LVDS */ | |
145 | struct drm_property *brightness_property; | |
146 | struct drm_property *contrast_property; | |
147 | struct drm_property *saturation_property; | |
148 | struct drm_property *hue_property; | |
149 | ||
150 | /* Add variable to record current setting for the above property */ | |
151 | u32 left_margin, right_margin, top_margin, bottom_margin; | |
152 | /* this is to get the range of margin.*/ | |
153 | u32 max_hscan, max_vscan; | |
154 | u32 max_hpos, cur_hpos; | |
155 | u32 max_vpos, cur_vpos; | |
156 | u32 cur_brightness, max_brightness; | |
157 | u32 cur_contrast, max_contrast; | |
158 | u32 cur_saturation, max_saturation; | |
159 | u32 cur_hue, max_hue; | |
79e53945 JB |
160 | }; |
161 | ||
fb7a46f3 | 162 | static bool |
163 | intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags); | |
164 | ||
79e53945 JB |
165 | /** |
166 | * Writes the SDVOB or SDVOC with the given value, but always writes both | |
167 | * SDVOB and SDVOC to work around apparent hardware issues (according to | |
168 | * comments in the BIOS). | |
169 | */ | |
b358d0a6 | 170 | static void intel_sdvo_write_sdvox(struct intel_output *intel_output, u32 val) |
79e53945 JB |
171 | { |
172 | struct drm_device *dev = intel_output->base.dev; | |
173 | struct drm_i915_private *dev_priv = dev->dev_private; | |
174 | struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; | |
175 | u32 bval = val, cval = val; | |
176 | int i; | |
177 | ||
178 | if (sdvo_priv->output_device == SDVOB) { | |
179 | cval = I915_READ(SDVOC); | |
180 | } else { | |
181 | bval = I915_READ(SDVOB); | |
182 | } | |
183 | /* | |
184 | * Write the registers twice for luck. Sometimes, | |
185 | * writing them only once doesn't appear to 'stick'. | |
186 | * The BIOS does this too. Yay, magic | |
187 | */ | |
188 | for (i = 0; i < 2; i++) | |
189 | { | |
190 | I915_WRITE(SDVOB, bval); | |
191 | I915_READ(SDVOB); | |
192 | I915_WRITE(SDVOC, cval); | |
193 | I915_READ(SDVOC); | |
194 | } | |
195 | } | |
196 | ||
197 | static bool intel_sdvo_read_byte(struct intel_output *intel_output, u8 addr, | |
198 | u8 *ch) | |
199 | { | |
200 | struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; | |
201 | u8 out_buf[2]; | |
202 | u8 buf[2]; | |
203 | int ret; | |
204 | ||
205 | struct i2c_msg msgs[] = { | |
206 | { | |
f9c10a9b | 207 | .addr = sdvo_priv->slave_addr >> 1, |
79e53945 JB |
208 | .flags = 0, |
209 | .len = 1, | |
210 | .buf = out_buf, | |
211 | }, | |
212 | { | |
f9c10a9b | 213 | .addr = sdvo_priv->slave_addr >> 1, |
79e53945 JB |
214 | .flags = I2C_M_RD, |
215 | .len = 1, | |
216 | .buf = buf, | |
217 | } | |
218 | }; | |
219 | ||
220 | out_buf[0] = addr; | |
221 | out_buf[1] = 0; | |
222 | ||
308cd3a2 | 223 | if ((ret = i2c_transfer(intel_output->i2c_bus, msgs, 2)) == 2) |
79e53945 JB |
224 | { |
225 | *ch = buf[0]; | |
226 | return true; | |
227 | } | |
228 | ||
8a4c47f3 | 229 | DRM_DEBUG_KMS("i2c transfer returned %d\n", ret); |
79e53945 JB |
230 | return false; |
231 | } | |
232 | ||
233 | static bool intel_sdvo_write_byte(struct intel_output *intel_output, int addr, | |
234 | u8 ch) | |
235 | { | |
f9c10a9b | 236 | struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; |
79e53945 JB |
237 | u8 out_buf[2]; |
238 | struct i2c_msg msgs[] = { | |
239 | { | |
f9c10a9b | 240 | .addr = sdvo_priv->slave_addr >> 1, |
79e53945 JB |
241 | .flags = 0, |
242 | .len = 2, | |
243 | .buf = out_buf, | |
244 | } | |
245 | }; | |
246 | ||
247 | out_buf[0] = addr; | |
248 | out_buf[1] = ch; | |
249 | ||
f9c10a9b | 250 | if (i2c_transfer(intel_output->i2c_bus, msgs, 1) == 1) |
79e53945 JB |
251 | { |
252 | return true; | |
253 | } | |
254 | return false; | |
255 | } | |
256 | ||
257 | #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd} | |
258 | /** Mapping of command numbers to names, for debug output */ | |
005568be | 259 | static const struct _sdvo_cmd_name { |
e2f0ba97 JB |
260 | u8 cmd; |
261 | char *name; | |
79e53945 JB |
262 | } sdvo_cmd_names[] = { |
263 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET), | |
264 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS), | |
265 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV), | |
266 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS), | |
267 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS), | |
268 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS), | |
269 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP), | |
270 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP), | |
271 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS), | |
272 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT), | |
273 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG), | |
274 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG), | |
275 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE), | |
276 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT), | |
277 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT), | |
278 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1), | |
279 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2), | |
280 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), | |
281 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2), | |
282 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), | |
283 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1), | |
284 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2), | |
285 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1), | |
286 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2), | |
287 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING), | |
288 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1), | |
289 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2), | |
290 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE), | |
291 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE), | |
292 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS), | |
293 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT), | |
294 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT), | |
295 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS), | |
296 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT), | |
297 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT), | |
e2f0ba97 JB |
298 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES), |
299 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE), | |
300 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE), | |
301 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE), | |
79e53945 | 302 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH), |
e2f0ba97 JB |
303 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT), |
304 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT), | |
305 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS), | |
b9219c5e ZY |
306 | /* Add the op code for SDVO enhancements */ |
307 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_POSITION_H), | |
308 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POSITION_H), | |
309 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_POSITION_H), | |
310 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_POSITION_V), | |
311 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POSITION_V), | |
312 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_POSITION_V), | |
313 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION), | |
314 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION), | |
315 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION), | |
316 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE), | |
317 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE), | |
318 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE), | |
319 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST), | |
320 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST), | |
321 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST), | |
322 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS), | |
323 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS), | |
324 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS), | |
325 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H), | |
326 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H), | |
327 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H), | |
328 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V), | |
329 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V), | |
330 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V), | |
e2f0ba97 JB |
331 | /* HDMI op code */ |
332 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE), | |
333 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE), | |
334 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE), | |
335 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI), | |
336 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI), | |
337 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP), | |
338 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY), | |
339 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY), | |
340 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER), | |
341 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT), | |
342 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT), | |
343 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX), | |
344 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX), | |
345 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO), | |
346 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT), | |
347 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT), | |
348 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE), | |
349 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE), | |
350 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA), | |
351 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA), | |
79e53945 JB |
352 | }; |
353 | ||
354 | #define SDVO_NAME(dev_priv) ((dev_priv)->output_device == SDVOB ? "SDVOB" : "SDVOC") | |
355 | #define SDVO_PRIV(output) ((struct intel_sdvo_priv *) (output)->dev_priv) | |
356 | ||
79e53945 JB |
357 | static void intel_sdvo_debug_write(struct intel_output *intel_output, u8 cmd, |
358 | void *args, int args_len) | |
359 | { | |
360 | struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; | |
361 | int i; | |
362 | ||
8a4c47f3 | 363 | DRM_DEBUG_KMS("%s: W: %02X ", |
342dc382 | 364 | SDVO_NAME(sdvo_priv), cmd); |
79e53945 | 365 | for (i = 0; i < args_len; i++) |
342dc382 | 366 | DRM_LOG_KMS("%02X ", ((u8 *)args)[i]); |
79e53945 | 367 | for (; i < 8; i++) |
342dc382 | 368 | DRM_LOG_KMS(" "); |
79e53945 JB |
369 | for (i = 0; i < sizeof(sdvo_cmd_names) / sizeof(sdvo_cmd_names[0]); i++) { |
370 | if (cmd == sdvo_cmd_names[i].cmd) { | |
342dc382 | 371 | DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name); |
79e53945 JB |
372 | break; |
373 | } | |
374 | } | |
375 | if (i == sizeof(sdvo_cmd_names)/ sizeof(sdvo_cmd_names[0])) | |
342dc382 | 376 | DRM_LOG_KMS("(%02X)", cmd); |
377 | DRM_LOG_KMS("\n"); | |
79e53945 | 378 | } |
79e53945 JB |
379 | |
380 | static void intel_sdvo_write_cmd(struct intel_output *intel_output, u8 cmd, | |
381 | void *args, int args_len) | |
382 | { | |
383 | int i; | |
384 | ||
385 | intel_sdvo_debug_write(intel_output, cmd, args, args_len); | |
386 | ||
387 | for (i = 0; i < args_len; i++) { | |
388 | intel_sdvo_write_byte(intel_output, SDVO_I2C_ARG_0 - i, | |
389 | ((u8*)args)[i]); | |
390 | } | |
391 | ||
392 | intel_sdvo_write_byte(intel_output, SDVO_I2C_OPCODE, cmd); | |
393 | } | |
394 | ||
79e53945 JB |
395 | static const char *cmd_status_names[] = { |
396 | "Power on", | |
397 | "Success", | |
398 | "Not supported", | |
399 | "Invalid arg", | |
400 | "Pending", | |
401 | "Target not specified", | |
402 | "Scaling not supported" | |
403 | }; | |
404 | ||
405 | static void intel_sdvo_debug_response(struct intel_output *intel_output, | |
406 | void *response, int response_len, | |
407 | u8 status) | |
408 | { | |
409 | struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; | |
33b52961 | 410 | int i; |
79e53945 | 411 | |
8a4c47f3 | 412 | DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(sdvo_priv)); |
79e53945 | 413 | for (i = 0; i < response_len; i++) |
342dc382 | 414 | DRM_LOG_KMS("%02X ", ((u8 *)response)[i]); |
79e53945 | 415 | for (; i < 8; i++) |
342dc382 | 416 | DRM_LOG_KMS(" "); |
79e53945 | 417 | if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP) |
342dc382 | 418 | DRM_LOG_KMS("(%s)", cmd_status_names[status]); |
79e53945 | 419 | else |
342dc382 | 420 | DRM_LOG_KMS("(??? %d)", status); |
421 | DRM_LOG_KMS("\n"); | |
79e53945 | 422 | } |
79e53945 JB |
423 | |
424 | static u8 intel_sdvo_read_response(struct intel_output *intel_output, | |
425 | void *response, int response_len) | |
426 | { | |
427 | int i; | |
428 | u8 status; | |
429 | u8 retry = 50; | |
430 | ||
431 | while (retry--) { | |
432 | /* Read the command response */ | |
433 | for (i = 0; i < response_len; i++) { | |
434 | intel_sdvo_read_byte(intel_output, | |
435 | SDVO_I2C_RETURN_0 + i, | |
436 | &((u8 *)response)[i]); | |
437 | } | |
438 | ||
439 | /* read the return status */ | |
440 | intel_sdvo_read_byte(intel_output, SDVO_I2C_CMD_STATUS, | |
441 | &status); | |
442 | ||
443 | intel_sdvo_debug_response(intel_output, response, response_len, | |
444 | status); | |
445 | if (status != SDVO_CMD_STATUS_PENDING) | |
446 | return status; | |
447 | ||
448 | mdelay(50); | |
449 | } | |
450 | ||
451 | return status; | |
452 | } | |
453 | ||
b358d0a6 | 454 | static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode) |
79e53945 JB |
455 | { |
456 | if (mode->clock >= 100000) | |
457 | return 1; | |
458 | else if (mode->clock >= 50000) | |
459 | return 2; | |
460 | else | |
461 | return 4; | |
462 | } | |
463 | ||
464 | /** | |
6a304caf ZY |
465 | * Try to read the response after issuie the DDC switch command. But it |
466 | * is noted that we must do the action of reading response and issuing DDC | |
467 | * switch command in one I2C transaction. Otherwise when we try to start | |
468 | * another I2C transaction after issuing the DDC bus switch, it will be | |
469 | * switched to the internal SDVO register. | |
79e53945 | 470 | */ |
b358d0a6 HE |
471 | static void intel_sdvo_set_control_bus_switch(struct intel_output *intel_output, |
472 | u8 target) | |
79e53945 | 473 | { |
6a304caf ZY |
474 | struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; |
475 | u8 out_buf[2], cmd_buf[2], ret_value[2], ret; | |
476 | struct i2c_msg msgs[] = { | |
477 | { | |
478 | .addr = sdvo_priv->slave_addr >> 1, | |
479 | .flags = 0, | |
480 | .len = 2, | |
481 | .buf = out_buf, | |
482 | }, | |
483 | /* the following two are to read the response */ | |
484 | { | |
485 | .addr = sdvo_priv->slave_addr >> 1, | |
486 | .flags = 0, | |
487 | .len = 1, | |
488 | .buf = cmd_buf, | |
489 | }, | |
490 | { | |
491 | .addr = sdvo_priv->slave_addr >> 1, | |
492 | .flags = I2C_M_RD, | |
493 | .len = 1, | |
494 | .buf = ret_value, | |
495 | }, | |
496 | }; | |
497 | ||
498 | intel_sdvo_debug_write(intel_output, SDVO_CMD_SET_CONTROL_BUS_SWITCH, | |
499 | &target, 1); | |
500 | /* write the DDC switch command argument */ | |
501 | intel_sdvo_write_byte(intel_output, SDVO_I2C_ARG_0, target); | |
502 | ||
503 | out_buf[0] = SDVO_I2C_OPCODE; | |
504 | out_buf[1] = SDVO_CMD_SET_CONTROL_BUS_SWITCH; | |
505 | cmd_buf[0] = SDVO_I2C_CMD_STATUS; | |
506 | cmd_buf[1] = 0; | |
507 | ret_value[0] = 0; | |
508 | ret_value[1] = 0; | |
509 | ||
510 | ret = i2c_transfer(intel_output->i2c_bus, msgs, 3); | |
511 | if (ret != 3) { | |
512 | /* failure in I2C transfer */ | |
513 | DRM_DEBUG_KMS("I2c transfer returned %d\n", ret); | |
514 | return; | |
515 | } | |
516 | if (ret_value[0] != SDVO_CMD_STATUS_SUCCESS) { | |
517 | DRM_DEBUG_KMS("DDC switch command returns response %d\n", | |
518 | ret_value[0]); | |
519 | return; | |
520 | } | |
521 | return; | |
79e53945 JB |
522 | } |
523 | ||
524 | static bool intel_sdvo_set_target_input(struct intel_output *intel_output, bool target_0, bool target_1) | |
525 | { | |
526 | struct intel_sdvo_set_target_input_args targets = {0}; | |
527 | u8 status; | |
528 | ||
529 | if (target_0 && target_1) | |
530 | return SDVO_CMD_STATUS_NOTSUPP; | |
531 | ||
532 | if (target_1) | |
533 | targets.target_1 = 1; | |
534 | ||
535 | intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_TARGET_INPUT, &targets, | |
536 | sizeof(targets)); | |
537 | ||
538 | status = intel_sdvo_read_response(intel_output, NULL, 0); | |
539 | ||
540 | return (status == SDVO_CMD_STATUS_SUCCESS); | |
541 | } | |
542 | ||
543 | /** | |
544 | * Return whether each input is trained. | |
545 | * | |
546 | * This function is making an assumption about the layout of the response, | |
547 | * which should be checked against the docs. | |
548 | */ | |
549 | static bool intel_sdvo_get_trained_inputs(struct intel_output *intel_output, bool *input_1, bool *input_2) | |
550 | { | |
551 | struct intel_sdvo_get_trained_inputs_response response; | |
552 | u8 status; | |
553 | ||
554 | intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_TRAINED_INPUTS, NULL, 0); | |
555 | status = intel_sdvo_read_response(intel_output, &response, sizeof(response)); | |
556 | if (status != SDVO_CMD_STATUS_SUCCESS) | |
557 | return false; | |
558 | ||
559 | *input_1 = response.input0_trained; | |
560 | *input_2 = response.input1_trained; | |
561 | return true; | |
562 | } | |
563 | ||
564 | static bool intel_sdvo_get_active_outputs(struct intel_output *intel_output, | |
565 | u16 *outputs) | |
566 | { | |
567 | u8 status; | |
568 | ||
569 | intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_OUTPUTS, NULL, 0); | |
570 | status = intel_sdvo_read_response(intel_output, outputs, sizeof(*outputs)); | |
571 | ||
572 | return (status == SDVO_CMD_STATUS_SUCCESS); | |
573 | } | |
574 | ||
575 | static bool intel_sdvo_set_active_outputs(struct intel_output *intel_output, | |
576 | u16 outputs) | |
577 | { | |
578 | u8 status; | |
579 | ||
580 | intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_OUTPUTS, &outputs, | |
581 | sizeof(outputs)); | |
582 | status = intel_sdvo_read_response(intel_output, NULL, 0); | |
583 | return (status == SDVO_CMD_STATUS_SUCCESS); | |
584 | } | |
585 | ||
586 | static bool intel_sdvo_set_encoder_power_state(struct intel_output *intel_output, | |
587 | int mode) | |
588 | { | |
589 | u8 status, state = SDVO_ENCODER_STATE_ON; | |
590 | ||
591 | switch (mode) { | |
592 | case DRM_MODE_DPMS_ON: | |
593 | state = SDVO_ENCODER_STATE_ON; | |
594 | break; | |
595 | case DRM_MODE_DPMS_STANDBY: | |
596 | state = SDVO_ENCODER_STATE_STANDBY; | |
597 | break; | |
598 | case DRM_MODE_DPMS_SUSPEND: | |
599 | state = SDVO_ENCODER_STATE_SUSPEND; | |
600 | break; | |
601 | case DRM_MODE_DPMS_OFF: | |
602 | state = SDVO_ENCODER_STATE_OFF; | |
603 | break; | |
604 | } | |
605 | ||
606 | intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ENCODER_POWER_STATE, &state, | |
607 | sizeof(state)); | |
608 | status = intel_sdvo_read_response(intel_output, NULL, 0); | |
609 | ||
610 | return (status == SDVO_CMD_STATUS_SUCCESS); | |
611 | } | |
612 | ||
613 | static bool intel_sdvo_get_input_pixel_clock_range(struct intel_output *intel_output, | |
614 | int *clock_min, | |
615 | int *clock_max) | |
616 | { | |
617 | struct intel_sdvo_pixel_clock_range clocks; | |
618 | u8 status; | |
619 | ||
620 | intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, | |
621 | NULL, 0); | |
622 | ||
623 | status = intel_sdvo_read_response(intel_output, &clocks, sizeof(clocks)); | |
624 | ||
625 | if (status != SDVO_CMD_STATUS_SUCCESS) | |
626 | return false; | |
627 | ||
628 | /* Convert the values from units of 10 kHz to kHz. */ | |
629 | *clock_min = clocks.min * 10; | |
630 | *clock_max = clocks.max * 10; | |
631 | ||
632 | return true; | |
633 | } | |
634 | ||
635 | static bool intel_sdvo_set_target_output(struct intel_output *intel_output, | |
636 | u16 outputs) | |
637 | { | |
638 | u8 status; | |
639 | ||
640 | intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_TARGET_OUTPUT, &outputs, | |
641 | sizeof(outputs)); | |
642 | ||
643 | status = intel_sdvo_read_response(intel_output, NULL, 0); | |
644 | return (status == SDVO_CMD_STATUS_SUCCESS); | |
645 | } | |
646 | ||
647 | static bool intel_sdvo_get_timing(struct intel_output *intel_output, u8 cmd, | |
648 | struct intel_sdvo_dtd *dtd) | |
649 | { | |
650 | u8 status; | |
651 | ||
652 | intel_sdvo_write_cmd(intel_output, cmd, NULL, 0); | |
653 | status = intel_sdvo_read_response(intel_output, &dtd->part1, | |
654 | sizeof(dtd->part1)); | |
655 | if (status != SDVO_CMD_STATUS_SUCCESS) | |
656 | return false; | |
657 | ||
658 | intel_sdvo_write_cmd(intel_output, cmd + 1, NULL, 0); | |
659 | status = intel_sdvo_read_response(intel_output, &dtd->part2, | |
660 | sizeof(dtd->part2)); | |
661 | if (status != SDVO_CMD_STATUS_SUCCESS) | |
662 | return false; | |
663 | ||
664 | return true; | |
665 | } | |
666 | ||
667 | static bool intel_sdvo_get_input_timing(struct intel_output *intel_output, | |
668 | struct intel_sdvo_dtd *dtd) | |
669 | { | |
670 | return intel_sdvo_get_timing(intel_output, | |
671 | SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd); | |
672 | } | |
673 | ||
674 | static bool intel_sdvo_get_output_timing(struct intel_output *intel_output, | |
675 | struct intel_sdvo_dtd *dtd) | |
676 | { | |
677 | return intel_sdvo_get_timing(intel_output, | |
678 | SDVO_CMD_GET_OUTPUT_TIMINGS_PART1, dtd); | |
679 | } | |
680 | ||
681 | static bool intel_sdvo_set_timing(struct intel_output *intel_output, u8 cmd, | |
682 | struct intel_sdvo_dtd *dtd) | |
683 | { | |
684 | u8 status; | |
685 | ||
686 | intel_sdvo_write_cmd(intel_output, cmd, &dtd->part1, sizeof(dtd->part1)); | |
687 | status = intel_sdvo_read_response(intel_output, NULL, 0); | |
688 | if (status != SDVO_CMD_STATUS_SUCCESS) | |
689 | return false; | |
690 | ||
691 | intel_sdvo_write_cmd(intel_output, cmd + 1, &dtd->part2, sizeof(dtd->part2)); | |
692 | status = intel_sdvo_read_response(intel_output, NULL, 0); | |
693 | if (status != SDVO_CMD_STATUS_SUCCESS) | |
694 | return false; | |
695 | ||
696 | return true; | |
697 | } | |
698 | ||
699 | static bool intel_sdvo_set_input_timing(struct intel_output *intel_output, | |
700 | struct intel_sdvo_dtd *dtd) | |
701 | { | |
702 | return intel_sdvo_set_timing(intel_output, | |
703 | SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); | |
704 | } | |
705 | ||
706 | static bool intel_sdvo_set_output_timing(struct intel_output *intel_output, | |
707 | struct intel_sdvo_dtd *dtd) | |
708 | { | |
709 | return intel_sdvo_set_timing(intel_output, | |
710 | SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); | |
711 | } | |
712 | ||
e2f0ba97 JB |
713 | static bool |
714 | intel_sdvo_create_preferred_input_timing(struct intel_output *output, | |
715 | uint16_t clock, | |
716 | uint16_t width, | |
717 | uint16_t height) | |
718 | { | |
719 | struct intel_sdvo_preferred_input_timing_args args; | |
12682a97 | 720 | struct intel_sdvo_priv *sdvo_priv = output->dev_priv; |
e2f0ba97 JB |
721 | uint8_t status; |
722 | ||
e642c6f1 | 723 | memset(&args, 0, sizeof(args)); |
e2f0ba97 JB |
724 | args.clock = clock; |
725 | args.width = width; | |
726 | args.height = height; | |
e642c6f1 | 727 | args.interlace = 0; |
12682a97 | 728 | |
729 | if (sdvo_priv->is_lvds && | |
730 | (sdvo_priv->sdvo_lvds_fixed_mode->hdisplay != width || | |
731 | sdvo_priv->sdvo_lvds_fixed_mode->vdisplay != height)) | |
732 | args.scaled = 1; | |
733 | ||
e2f0ba97 JB |
734 | intel_sdvo_write_cmd(output, SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, |
735 | &args, sizeof(args)); | |
736 | status = intel_sdvo_read_response(output, NULL, 0); | |
737 | if (status != SDVO_CMD_STATUS_SUCCESS) | |
738 | return false; | |
739 | ||
740 | return true; | |
741 | } | |
742 | ||
743 | static bool intel_sdvo_get_preferred_input_timing(struct intel_output *output, | |
744 | struct intel_sdvo_dtd *dtd) | |
745 | { | |
746 | bool status; | |
747 | ||
748 | intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, | |
749 | NULL, 0); | |
750 | ||
751 | status = intel_sdvo_read_response(output, &dtd->part1, | |
752 | sizeof(dtd->part1)); | |
753 | if (status != SDVO_CMD_STATUS_SUCCESS) | |
754 | return false; | |
755 | ||
756 | intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, | |
757 | NULL, 0); | |
758 | ||
759 | status = intel_sdvo_read_response(output, &dtd->part2, | |
760 | sizeof(dtd->part2)); | |
761 | if (status != SDVO_CMD_STATUS_SUCCESS) | |
762 | return false; | |
763 | ||
764 | return false; | |
765 | } | |
79e53945 JB |
766 | |
767 | static int intel_sdvo_get_clock_rate_mult(struct intel_output *intel_output) | |
768 | { | |
769 | u8 response, status; | |
770 | ||
771 | intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_CLOCK_RATE_MULT, NULL, 0); | |
772 | status = intel_sdvo_read_response(intel_output, &response, 1); | |
773 | ||
774 | if (status != SDVO_CMD_STATUS_SUCCESS) { | |
8a4c47f3 | 775 | DRM_DEBUG_KMS("Couldn't get SDVO clock rate multiplier\n"); |
79e53945 JB |
776 | return SDVO_CLOCK_RATE_MULT_1X; |
777 | } else { | |
8a4c47f3 | 778 | DRM_DEBUG_KMS("Current clock rate multiplier: %d\n", response); |
79e53945 JB |
779 | } |
780 | ||
781 | return response; | |
782 | } | |
783 | ||
784 | static bool intel_sdvo_set_clock_rate_mult(struct intel_output *intel_output, u8 val) | |
785 | { | |
786 | u8 status; | |
787 | ||
788 | intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); | |
789 | status = intel_sdvo_read_response(intel_output, NULL, 0); | |
790 | if (status != SDVO_CMD_STATUS_SUCCESS) | |
791 | return false; | |
792 | ||
793 | return true; | |
794 | } | |
795 | ||
e2f0ba97 JB |
796 | static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, |
797 | struct drm_display_mode *mode) | |
79e53945 | 798 | { |
e2f0ba97 JB |
799 | uint16_t width, height; |
800 | uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len; | |
801 | uint16_t h_sync_offset, v_sync_offset; | |
79e53945 JB |
802 | |
803 | width = mode->crtc_hdisplay; | |
804 | height = mode->crtc_vdisplay; | |
805 | ||
806 | /* do some mode translations */ | |
807 | h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start; | |
808 | h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; | |
809 | ||
810 | v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start; | |
811 | v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; | |
812 | ||
813 | h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start; | |
814 | v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start; | |
815 | ||
e2f0ba97 JB |
816 | dtd->part1.clock = mode->clock / 10; |
817 | dtd->part1.h_active = width & 0xff; | |
818 | dtd->part1.h_blank = h_blank_len & 0xff; | |
819 | dtd->part1.h_high = (((width >> 8) & 0xf) << 4) | | |
79e53945 | 820 | ((h_blank_len >> 8) & 0xf); |
e2f0ba97 JB |
821 | dtd->part1.v_active = height & 0xff; |
822 | dtd->part1.v_blank = v_blank_len & 0xff; | |
823 | dtd->part1.v_high = (((height >> 8) & 0xf) << 4) | | |
79e53945 JB |
824 | ((v_blank_len >> 8) & 0xf); |
825 | ||
171a9e96 | 826 | dtd->part2.h_sync_off = h_sync_offset & 0xff; |
e2f0ba97 JB |
827 | dtd->part2.h_sync_width = h_sync_len & 0xff; |
828 | dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 | | |
79e53945 | 829 | (v_sync_len & 0xf); |
e2f0ba97 | 830 | dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) | |
79e53945 JB |
831 | ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) | |
832 | ((v_sync_len & 0x30) >> 4); | |
833 | ||
e2f0ba97 | 834 | dtd->part2.dtd_flags = 0x18; |
79e53945 | 835 | if (mode->flags & DRM_MODE_FLAG_PHSYNC) |
e2f0ba97 | 836 | dtd->part2.dtd_flags |= 0x2; |
79e53945 | 837 | if (mode->flags & DRM_MODE_FLAG_PVSYNC) |
e2f0ba97 JB |
838 | dtd->part2.dtd_flags |= 0x4; |
839 | ||
840 | dtd->part2.sdvo_flags = 0; | |
841 | dtd->part2.v_sync_off_high = v_sync_offset & 0xc0; | |
842 | dtd->part2.reserved = 0; | |
843 | } | |
844 | ||
845 | static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode, | |
846 | struct intel_sdvo_dtd *dtd) | |
847 | { | |
e2f0ba97 JB |
848 | mode->hdisplay = dtd->part1.h_active; |
849 | mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; | |
850 | mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off; | |
171a9e96 | 851 | mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2; |
e2f0ba97 JB |
852 | mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width; |
853 | mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4; | |
854 | mode->htotal = mode->hdisplay + dtd->part1.h_blank; | |
855 | mode->htotal += (dtd->part1.h_high & 0xf) << 8; | |
856 | ||
857 | mode->vdisplay = dtd->part1.v_active; | |
858 | mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8; | |
859 | mode->vsync_start = mode->vdisplay; | |
860 | mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf; | |
171a9e96 | 861 | mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2; |
e2f0ba97 JB |
862 | mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0; |
863 | mode->vsync_end = mode->vsync_start + | |
864 | (dtd->part2.v_sync_off_width & 0xf); | |
865 | mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4; | |
866 | mode->vtotal = mode->vdisplay + dtd->part1.v_blank; | |
867 | mode->vtotal += (dtd->part1.v_high & 0xf) << 8; | |
868 | ||
869 | mode->clock = dtd->part1.clock * 10; | |
870 | ||
171a9e96 | 871 | mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); |
e2f0ba97 JB |
872 | if (dtd->part2.dtd_flags & 0x2) |
873 | mode->flags |= DRM_MODE_FLAG_PHSYNC; | |
874 | if (dtd->part2.dtd_flags & 0x4) | |
875 | mode->flags |= DRM_MODE_FLAG_PVSYNC; | |
876 | } | |
877 | ||
878 | static bool intel_sdvo_get_supp_encode(struct intel_output *output, | |
879 | struct intel_sdvo_encode *encode) | |
880 | { | |
881 | uint8_t status; | |
882 | ||
883 | intel_sdvo_write_cmd(output, SDVO_CMD_GET_SUPP_ENCODE, NULL, 0); | |
884 | status = intel_sdvo_read_response(output, encode, sizeof(*encode)); | |
885 | if (status != SDVO_CMD_STATUS_SUCCESS) { /* non-support means DVI */ | |
886 | memset(encode, 0, sizeof(*encode)); | |
887 | return false; | |
888 | } | |
889 | ||
890 | return true; | |
891 | } | |
892 | ||
893 | static bool intel_sdvo_set_encode(struct intel_output *output, uint8_t mode) | |
894 | { | |
895 | uint8_t status; | |
896 | ||
897 | intel_sdvo_write_cmd(output, SDVO_CMD_SET_ENCODE, &mode, 1); | |
898 | status = intel_sdvo_read_response(output, NULL, 0); | |
899 | ||
900 | return (status == SDVO_CMD_STATUS_SUCCESS); | |
901 | } | |
902 | ||
903 | static bool intel_sdvo_set_colorimetry(struct intel_output *output, | |
904 | uint8_t mode) | |
905 | { | |
906 | uint8_t status; | |
907 | ||
908 | intel_sdvo_write_cmd(output, SDVO_CMD_SET_COLORIMETRY, &mode, 1); | |
909 | status = intel_sdvo_read_response(output, NULL, 0); | |
910 | ||
911 | return (status == SDVO_CMD_STATUS_SUCCESS); | |
912 | } | |
913 | ||
914 | #if 0 | |
915 | static void intel_sdvo_dump_hdmi_buf(struct intel_output *output) | |
916 | { | |
917 | int i, j; | |
918 | uint8_t set_buf_index[2]; | |
919 | uint8_t av_split; | |
920 | uint8_t buf_size; | |
921 | uint8_t buf[48]; | |
922 | uint8_t *pos; | |
923 | ||
924 | intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_AV_SPLIT, NULL, 0); | |
925 | intel_sdvo_read_response(output, &av_split, 1); | |
926 | ||
927 | for (i = 0; i <= av_split; i++) { | |
928 | set_buf_index[0] = i; set_buf_index[1] = 0; | |
929 | intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_INDEX, | |
930 | set_buf_index, 2); | |
931 | intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_INFO, NULL, 0); | |
932 | intel_sdvo_read_response(output, &buf_size, 1); | |
933 | ||
934 | pos = buf; | |
935 | for (j = 0; j <= buf_size; j += 8) { | |
936 | intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_DATA, | |
937 | NULL, 0); | |
938 | intel_sdvo_read_response(output, pos, 8); | |
939 | pos += 8; | |
940 | } | |
941 | } | |
942 | } | |
943 | #endif | |
944 | ||
945 | static void intel_sdvo_set_hdmi_buf(struct intel_output *output, int index, | |
946 | uint8_t *data, int8_t size, uint8_t tx_rate) | |
947 | { | |
948 | uint8_t set_buf_index[2]; | |
949 | ||
950 | set_buf_index[0] = index; | |
951 | set_buf_index[1] = 0; | |
952 | ||
953 | intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_INDEX, set_buf_index, 2); | |
954 | ||
955 | for (; size > 0; size -= 8) { | |
956 | intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_DATA, data, 8); | |
957 | data += 8; | |
958 | } | |
959 | ||
960 | intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1); | |
961 | } | |
962 | ||
963 | static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size) | |
964 | { | |
965 | uint8_t csum = 0; | |
966 | int i; | |
967 | ||
968 | for (i = 0; i < size; i++) | |
969 | csum += data[i]; | |
970 | ||
971 | return 0x100 - csum; | |
972 | } | |
973 | ||
974 | #define DIP_TYPE_AVI 0x82 | |
975 | #define DIP_VERSION_AVI 0x2 | |
976 | #define DIP_LEN_AVI 13 | |
977 | ||
978 | struct dip_infoframe { | |
979 | uint8_t type; | |
980 | uint8_t version; | |
981 | uint8_t len; | |
982 | uint8_t checksum; | |
983 | union { | |
984 | struct { | |
985 | /* Packet Byte #1 */ | |
986 | uint8_t S:2; | |
987 | uint8_t B:2; | |
988 | uint8_t A:1; | |
989 | uint8_t Y:2; | |
990 | uint8_t rsvd1:1; | |
991 | /* Packet Byte #2 */ | |
992 | uint8_t R:4; | |
993 | uint8_t M:2; | |
994 | uint8_t C:2; | |
995 | /* Packet Byte #3 */ | |
996 | uint8_t SC:2; | |
997 | uint8_t Q:2; | |
998 | uint8_t EC:3; | |
999 | uint8_t ITC:1; | |
1000 | /* Packet Byte #4 */ | |
1001 | uint8_t VIC:7; | |
1002 | uint8_t rsvd2:1; | |
1003 | /* Packet Byte #5 */ | |
1004 | uint8_t PR:4; | |
1005 | uint8_t rsvd3:4; | |
1006 | /* Packet Byte #6~13 */ | |
1007 | uint16_t top_bar_end; | |
1008 | uint16_t bottom_bar_start; | |
1009 | uint16_t left_bar_end; | |
1010 | uint16_t right_bar_start; | |
1011 | } avi; | |
1012 | struct { | |
1013 | /* Packet Byte #1 */ | |
1014 | uint8_t channel_count:3; | |
1015 | uint8_t rsvd1:1; | |
1016 | uint8_t coding_type:4; | |
1017 | /* Packet Byte #2 */ | |
1018 | uint8_t sample_size:2; /* SS0, SS1 */ | |
1019 | uint8_t sample_frequency:3; | |
1020 | uint8_t rsvd2:3; | |
1021 | /* Packet Byte #3 */ | |
1022 | uint8_t coding_type_private:5; | |
1023 | uint8_t rsvd3:3; | |
1024 | /* Packet Byte #4 */ | |
1025 | uint8_t channel_allocation; | |
1026 | /* Packet Byte #5 */ | |
1027 | uint8_t rsvd4:3; | |
1028 | uint8_t level_shift:4; | |
1029 | uint8_t downmix_inhibit:1; | |
1030 | } audio; | |
1031 | uint8_t payload[28]; | |
1032 | } __attribute__ ((packed)) u; | |
1033 | } __attribute__((packed)); | |
1034 | ||
1035 | static void intel_sdvo_set_avi_infoframe(struct intel_output *output, | |
1036 | struct drm_display_mode * mode) | |
1037 | { | |
1038 | struct dip_infoframe avi_if = { | |
1039 | .type = DIP_TYPE_AVI, | |
1040 | .version = DIP_VERSION_AVI, | |
1041 | .len = DIP_LEN_AVI, | |
1042 | }; | |
1043 | ||
1044 | avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if, | |
1045 | 4 + avi_if.len); | |
1046 | intel_sdvo_set_hdmi_buf(output, 1, (uint8_t *)&avi_if, 4 + avi_if.len, | |
1047 | SDVO_HBUF_TX_VSYNC); | |
1048 | } | |
1049 | ||
7026d4ac ZW |
1050 | static void intel_sdvo_set_tv_format(struct intel_output *output) |
1051 | { | |
ce6feabd ZY |
1052 | |
1053 | struct intel_sdvo_tv_format format; | |
7026d4ac | 1054 | struct intel_sdvo_priv *sdvo_priv = output->dev_priv; |
ce6feabd ZY |
1055 | uint32_t format_map, i; |
1056 | uint8_t status; | |
7026d4ac | 1057 | |
ce6feabd ZY |
1058 | for (i = 0; i < TV_FORMAT_NUM; i++) |
1059 | if (tv_format_names[i] == sdvo_priv->tv_format_name) | |
1060 | break; | |
1061 | ||
1062 | format_map = 1 << i; | |
1063 | memset(&format, 0, sizeof(format)); | |
1064 | memcpy(&format, &format_map, sizeof(format_map) > sizeof(format) ? | |
1065 | sizeof(format) : sizeof(format_map)); | |
1066 | ||
1067 | intel_sdvo_write_cmd(output, SDVO_CMD_SET_TV_FORMAT, &format_map, | |
1068 | sizeof(format)); | |
1069 | ||
1070 | status = intel_sdvo_read_response(output, NULL, 0); | |
1071 | if (status != SDVO_CMD_STATUS_SUCCESS) | |
b9219c5e | 1072 | DRM_DEBUG_KMS("%s: Failed to set TV format\n", |
ce6feabd | 1073 | SDVO_NAME(sdvo_priv)); |
7026d4ac ZW |
1074 | } |
1075 | ||
e2f0ba97 JB |
1076 | static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder, |
1077 | struct drm_display_mode *mode, | |
1078 | struct drm_display_mode *adjusted_mode) | |
1079 | { | |
1080 | struct intel_output *output = enc_to_intel_output(encoder); | |
1081 | struct intel_sdvo_priv *dev_priv = output->dev_priv; | |
79e53945 | 1082 | |
12682a97 | 1083 | if (dev_priv->is_tv) { |
e2f0ba97 JB |
1084 | struct intel_sdvo_dtd output_dtd; |
1085 | bool success; | |
1086 | ||
1087 | /* We need to construct preferred input timings based on our | |
1088 | * output timings. To do that, we have to set the output | |
1089 | * timings, even though this isn't really the right place in | |
1090 | * the sequence to do it. Oh well. | |
1091 | */ | |
1092 | ||
1093 | ||
1094 | /* Set output timings */ | |
1095 | intel_sdvo_get_dtd_from_mode(&output_dtd, mode); | |
1096 | intel_sdvo_set_target_output(output, | |
1097 | dev_priv->controlled_output); | |
1098 | intel_sdvo_set_output_timing(output, &output_dtd); | |
1099 | ||
1100 | /* Set the input timing to the screen. Assume always input 0. */ | |
1101 | intel_sdvo_set_target_input(output, true, false); | |
1102 | ||
1103 | ||
1104 | success = intel_sdvo_create_preferred_input_timing(output, | |
1105 | mode->clock / 10, | |
1106 | mode->hdisplay, | |
1107 | mode->vdisplay); | |
1108 | if (success) { | |
1109 | struct intel_sdvo_dtd input_dtd; | |
79e53945 | 1110 | |
e2f0ba97 JB |
1111 | intel_sdvo_get_preferred_input_timing(output, |
1112 | &input_dtd); | |
1113 | intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); | |
12682a97 | 1114 | dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags; |
1115 | ||
1116 | drm_mode_set_crtcinfo(adjusted_mode, 0); | |
1117 | ||
1118 | mode->clock = adjusted_mode->clock; | |
1119 | ||
1120 | adjusted_mode->clock *= | |
1121 | intel_sdvo_get_pixel_multiplier(mode); | |
1122 | } else { | |
1123 | return false; | |
1124 | } | |
1125 | } else if (dev_priv->is_lvds) { | |
1126 | struct intel_sdvo_dtd output_dtd; | |
1127 | bool success; | |
1128 | ||
1129 | drm_mode_set_crtcinfo(dev_priv->sdvo_lvds_fixed_mode, 0); | |
1130 | /* Set output timings */ | |
1131 | intel_sdvo_get_dtd_from_mode(&output_dtd, | |
1132 | dev_priv->sdvo_lvds_fixed_mode); | |
1133 | ||
1134 | intel_sdvo_set_target_output(output, | |
1135 | dev_priv->controlled_output); | |
1136 | intel_sdvo_set_output_timing(output, &output_dtd); | |
1137 | ||
1138 | /* Set the input timing to the screen. Assume always input 0. */ | |
1139 | intel_sdvo_set_target_input(output, true, false); | |
1140 | ||
1141 | ||
1142 | success = intel_sdvo_create_preferred_input_timing( | |
1143 | output, | |
1144 | mode->clock / 10, | |
1145 | mode->hdisplay, | |
1146 | mode->vdisplay); | |
1147 | ||
1148 | if (success) { | |
1149 | struct intel_sdvo_dtd input_dtd; | |
1150 | ||
1151 | intel_sdvo_get_preferred_input_timing(output, | |
1152 | &input_dtd); | |
1153 | intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); | |
1154 | dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags; | |
e2f0ba97 | 1155 | |
7026d4ac ZW |
1156 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
1157 | ||
1158 | mode->clock = adjusted_mode->clock; | |
1159 | ||
1160 | adjusted_mode->clock *= | |
1161 | intel_sdvo_get_pixel_multiplier(mode); | |
e2f0ba97 JB |
1162 | } else { |
1163 | return false; | |
1164 | } | |
12682a97 | 1165 | |
1166 | } else { | |
1167 | /* Make the CRTC code factor in the SDVO pixel multiplier. The | |
1168 | * SDVO device will be told of the multiplier during mode_set. | |
1169 | */ | |
1170 | adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode); | |
e2f0ba97 JB |
1171 | } |
1172 | return true; | |
1173 | } | |
1174 | ||
1175 | static void intel_sdvo_mode_set(struct drm_encoder *encoder, | |
1176 | struct drm_display_mode *mode, | |
1177 | struct drm_display_mode *adjusted_mode) | |
1178 | { | |
1179 | struct drm_device *dev = encoder->dev; | |
1180 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1181 | struct drm_crtc *crtc = encoder->crtc; | |
1182 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1183 | struct intel_output *output = enc_to_intel_output(encoder); | |
1184 | struct intel_sdvo_priv *sdvo_priv = output->dev_priv; | |
1185 | u32 sdvox = 0; | |
1186 | int sdvo_pixel_multiply; | |
1187 | struct intel_sdvo_in_out_map in_out; | |
1188 | struct intel_sdvo_dtd input_dtd; | |
1189 | u8 status; | |
1190 | ||
1191 | if (!mode) | |
1192 | return; | |
1193 | ||
1194 | /* First, set the input mapping for the first input to our controlled | |
1195 | * output. This is only correct if we're a single-input device, in | |
1196 | * which case the first input is the output from the appropriate SDVO | |
1197 | * channel on the motherboard. In a two-input device, the first input | |
1198 | * will be SDVOB and the second SDVOC. | |
1199 | */ | |
1200 | in_out.in0 = sdvo_priv->controlled_output; | |
1201 | in_out.in1 = 0; | |
1202 | ||
1203 | intel_sdvo_write_cmd(output, SDVO_CMD_SET_IN_OUT_MAP, | |
1204 | &in_out, sizeof(in_out)); | |
1205 | status = intel_sdvo_read_response(output, NULL, 0); | |
1206 | ||
1207 | if (sdvo_priv->is_hdmi) { | |
1208 | intel_sdvo_set_avi_infoframe(output, mode); | |
1209 | sdvox |= SDVO_AUDIO_ENABLE; | |
1210 | } | |
1211 | ||
7026d4ac ZW |
1212 | /* We have tried to get input timing in mode_fixup, and filled into |
1213 | adjusted_mode */ | |
12682a97 | 1214 | if (sdvo_priv->is_tv || sdvo_priv->is_lvds) { |
7026d4ac | 1215 | intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode); |
12682a97 | 1216 | input_dtd.part2.sdvo_flags = sdvo_priv->sdvo_flags; |
1217 | } else | |
7026d4ac | 1218 | intel_sdvo_get_dtd_from_mode(&input_dtd, mode); |
e2f0ba97 JB |
1219 | |
1220 | /* If it's a TV, we already set the output timing in mode_fixup. | |
1221 | * Otherwise, the output timing is equal to the input timing. | |
1222 | */ | |
12682a97 | 1223 | if (!sdvo_priv->is_tv && !sdvo_priv->is_lvds) { |
e2f0ba97 JB |
1224 | /* Set the output timing to the screen */ |
1225 | intel_sdvo_set_target_output(output, | |
1226 | sdvo_priv->controlled_output); | |
1227 | intel_sdvo_set_output_timing(output, &input_dtd); | |
1228 | } | |
79e53945 JB |
1229 | |
1230 | /* Set the input timing to the screen. Assume always input 0. */ | |
e2f0ba97 | 1231 | intel_sdvo_set_target_input(output, true, false); |
79e53945 | 1232 | |
7026d4ac ZW |
1233 | if (sdvo_priv->is_tv) |
1234 | intel_sdvo_set_tv_format(output); | |
1235 | ||
e2f0ba97 | 1236 | /* We would like to use intel_sdvo_create_preferred_input_timing() to |
79e53945 JB |
1237 | * provide the device with a timing it can support, if it supports that |
1238 | * feature. However, presumably we would need to adjust the CRTC to | |
1239 | * output the preferred timing, and we don't support that currently. | |
1240 | */ | |
e2f0ba97 JB |
1241 | #if 0 |
1242 | success = intel_sdvo_create_preferred_input_timing(output, clock, | |
1243 | width, height); | |
1244 | if (success) { | |
1245 | struct intel_sdvo_dtd *input_dtd; | |
1246 | ||
1247 | intel_sdvo_get_preferred_input_timing(output, &input_dtd); | |
1248 | intel_sdvo_set_input_timing(output, &input_dtd); | |
1249 | } | |
1250 | #else | |
1251 | intel_sdvo_set_input_timing(output, &input_dtd); | |
1252 | #endif | |
79e53945 JB |
1253 | |
1254 | switch (intel_sdvo_get_pixel_multiplier(mode)) { | |
1255 | case 1: | |
e2f0ba97 | 1256 | intel_sdvo_set_clock_rate_mult(output, |
79e53945 JB |
1257 | SDVO_CLOCK_RATE_MULT_1X); |
1258 | break; | |
1259 | case 2: | |
e2f0ba97 | 1260 | intel_sdvo_set_clock_rate_mult(output, |
79e53945 JB |
1261 | SDVO_CLOCK_RATE_MULT_2X); |
1262 | break; | |
1263 | case 4: | |
e2f0ba97 | 1264 | intel_sdvo_set_clock_rate_mult(output, |
79e53945 JB |
1265 | SDVO_CLOCK_RATE_MULT_4X); |
1266 | break; | |
1267 | } | |
1268 | ||
1269 | /* Set the SDVO control regs. */ | |
e2f0ba97 JB |
1270 | if (IS_I965G(dev)) { |
1271 | sdvox |= SDVO_BORDER_ENABLE | | |
1272 | SDVO_VSYNC_ACTIVE_HIGH | | |
1273 | SDVO_HSYNC_ACTIVE_HIGH; | |
1274 | } else { | |
1275 | sdvox |= I915_READ(sdvo_priv->output_device); | |
1276 | switch (sdvo_priv->output_device) { | |
1277 | case SDVOB: | |
1278 | sdvox &= SDVOB_PRESERVE_MASK; | |
1279 | break; | |
1280 | case SDVOC: | |
1281 | sdvox &= SDVOC_PRESERVE_MASK; | |
1282 | break; | |
1283 | } | |
1284 | sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; | |
1285 | } | |
79e53945 JB |
1286 | if (intel_crtc->pipe == 1) |
1287 | sdvox |= SDVO_PIPE_B_SELECT; | |
1288 | ||
1289 | sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode); | |
1290 | if (IS_I965G(dev)) { | |
e2f0ba97 JB |
1291 | /* done in crtc_mode_set as the dpll_md reg must be written early */ |
1292 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { | |
1293 | /* done in crtc_mode_set as it lives inside the dpll register */ | |
79e53945 JB |
1294 | } else { |
1295 | sdvox |= (sdvo_pixel_multiply - 1) << SDVO_PORT_MULTIPLY_SHIFT; | |
1296 | } | |
1297 | ||
12682a97 | 1298 | if (sdvo_priv->sdvo_flags & SDVO_NEED_TO_STALL) |
1299 | sdvox |= SDVO_STALL_SELECT; | |
e2f0ba97 | 1300 | intel_sdvo_write_sdvox(output, sdvox); |
79e53945 JB |
1301 | } |
1302 | ||
1303 | static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode) | |
1304 | { | |
1305 | struct drm_device *dev = encoder->dev; | |
1306 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1307 | struct intel_output *intel_output = enc_to_intel_output(encoder); | |
1308 | struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; | |
1309 | u32 temp; | |
1310 | ||
1311 | if (mode != DRM_MODE_DPMS_ON) { | |
1312 | intel_sdvo_set_active_outputs(intel_output, 0); | |
1313 | if (0) | |
1314 | intel_sdvo_set_encoder_power_state(intel_output, mode); | |
1315 | ||
1316 | if (mode == DRM_MODE_DPMS_OFF) { | |
1317 | temp = I915_READ(sdvo_priv->output_device); | |
1318 | if ((temp & SDVO_ENABLE) != 0) { | |
1319 | intel_sdvo_write_sdvox(intel_output, temp & ~SDVO_ENABLE); | |
1320 | } | |
1321 | } | |
1322 | } else { | |
1323 | bool input1, input2; | |
1324 | int i; | |
1325 | u8 status; | |
1326 | ||
1327 | temp = I915_READ(sdvo_priv->output_device); | |
1328 | if ((temp & SDVO_ENABLE) == 0) | |
1329 | intel_sdvo_write_sdvox(intel_output, temp | SDVO_ENABLE); | |
1330 | for (i = 0; i < 2; i++) | |
1331 | intel_wait_for_vblank(dev); | |
1332 | ||
1333 | status = intel_sdvo_get_trained_inputs(intel_output, &input1, | |
1334 | &input2); | |
1335 | ||
1336 | ||
1337 | /* Warn if the device reported failure to sync. | |
1338 | * A lot of SDVO devices fail to notify of sync, but it's | |
1339 | * a given it the status is a success, we succeeded. | |
1340 | */ | |
1341 | if (status == SDVO_CMD_STATUS_SUCCESS && !input1) { | |
8a4c47f3 ZY |
1342 | DRM_DEBUG_KMS("First %s output reported failure to " |
1343 | "sync\n", SDVO_NAME(sdvo_priv)); | |
79e53945 JB |
1344 | } |
1345 | ||
1346 | if (0) | |
1347 | intel_sdvo_set_encoder_power_state(intel_output, mode); | |
e2f0ba97 | 1348 | intel_sdvo_set_active_outputs(intel_output, sdvo_priv->controlled_output); |
79e53945 JB |
1349 | } |
1350 | return; | |
1351 | } | |
1352 | ||
1353 | static void intel_sdvo_save(struct drm_connector *connector) | |
1354 | { | |
1355 | struct drm_device *dev = connector->dev; | |
1356 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1357 | struct intel_output *intel_output = to_intel_output(connector); | |
1358 | struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; | |
1359 | int o; | |
1360 | ||
1361 | sdvo_priv->save_sdvo_mult = intel_sdvo_get_clock_rate_mult(intel_output); | |
1362 | intel_sdvo_get_active_outputs(intel_output, &sdvo_priv->save_active_outputs); | |
1363 | ||
1364 | if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) { | |
1365 | intel_sdvo_set_target_input(intel_output, true, false); | |
1366 | intel_sdvo_get_input_timing(intel_output, | |
1367 | &sdvo_priv->save_input_dtd_1); | |
1368 | } | |
1369 | ||
1370 | if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) { | |
1371 | intel_sdvo_set_target_input(intel_output, false, true); | |
1372 | intel_sdvo_get_input_timing(intel_output, | |
1373 | &sdvo_priv->save_input_dtd_2); | |
1374 | } | |
1375 | ||
1376 | for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++) | |
1377 | { | |
1378 | u16 this_output = (1 << o); | |
1379 | if (sdvo_priv->caps.output_flags & this_output) | |
1380 | { | |
1381 | intel_sdvo_set_target_output(intel_output, this_output); | |
1382 | intel_sdvo_get_output_timing(intel_output, | |
1383 | &sdvo_priv->save_output_dtd[o]); | |
1384 | } | |
1385 | } | |
e2f0ba97 JB |
1386 | if (sdvo_priv->is_tv) { |
1387 | /* XXX: Save TV format/enhancements. */ | |
1388 | } | |
79e53945 JB |
1389 | |
1390 | sdvo_priv->save_SDVOX = I915_READ(sdvo_priv->output_device); | |
1391 | } | |
1392 | ||
1393 | static void intel_sdvo_restore(struct drm_connector *connector) | |
1394 | { | |
1395 | struct drm_device *dev = connector->dev; | |
79e53945 JB |
1396 | struct intel_output *intel_output = to_intel_output(connector); |
1397 | struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; | |
1398 | int o; | |
1399 | int i; | |
1400 | bool input1, input2; | |
1401 | u8 status; | |
1402 | ||
1403 | intel_sdvo_set_active_outputs(intel_output, 0); | |
1404 | ||
1405 | for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++) | |
1406 | { | |
1407 | u16 this_output = (1 << o); | |
1408 | if (sdvo_priv->caps.output_flags & this_output) { | |
1409 | intel_sdvo_set_target_output(intel_output, this_output); | |
1410 | intel_sdvo_set_output_timing(intel_output, &sdvo_priv->save_output_dtd[o]); | |
1411 | } | |
1412 | } | |
1413 | ||
1414 | if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) { | |
1415 | intel_sdvo_set_target_input(intel_output, true, false); | |
1416 | intel_sdvo_set_input_timing(intel_output, &sdvo_priv->save_input_dtd_1); | |
1417 | } | |
1418 | ||
1419 | if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) { | |
1420 | intel_sdvo_set_target_input(intel_output, false, true); | |
1421 | intel_sdvo_set_input_timing(intel_output, &sdvo_priv->save_input_dtd_2); | |
1422 | } | |
1423 | ||
1424 | intel_sdvo_set_clock_rate_mult(intel_output, sdvo_priv->save_sdvo_mult); | |
1425 | ||
e2f0ba97 JB |
1426 | if (sdvo_priv->is_tv) { |
1427 | /* XXX: Restore TV format/enhancements. */ | |
1428 | } | |
1429 | ||
1430 | intel_sdvo_write_sdvox(intel_output, sdvo_priv->save_SDVOX); | |
79e53945 JB |
1431 | |
1432 | if (sdvo_priv->save_SDVOX & SDVO_ENABLE) | |
1433 | { | |
1434 | for (i = 0; i < 2; i++) | |
1435 | intel_wait_for_vblank(dev); | |
1436 | status = intel_sdvo_get_trained_inputs(intel_output, &input1, &input2); | |
1437 | if (status == SDVO_CMD_STATUS_SUCCESS && !input1) | |
8a4c47f3 ZY |
1438 | DRM_DEBUG_KMS("First %s output reported failure to " |
1439 | "sync\n", SDVO_NAME(sdvo_priv)); | |
79e53945 JB |
1440 | } |
1441 | ||
1442 | intel_sdvo_set_active_outputs(intel_output, sdvo_priv->save_active_outputs); | |
1443 | } | |
1444 | ||
1445 | static int intel_sdvo_mode_valid(struct drm_connector *connector, | |
1446 | struct drm_display_mode *mode) | |
1447 | { | |
1448 | struct intel_output *intel_output = to_intel_output(connector); | |
1449 | struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; | |
1450 | ||
1451 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
1452 | return MODE_NO_DBLESCAN; | |
1453 | ||
1454 | if (sdvo_priv->pixel_clock_min > mode->clock) | |
1455 | return MODE_CLOCK_LOW; | |
1456 | ||
1457 | if (sdvo_priv->pixel_clock_max < mode->clock) | |
1458 | return MODE_CLOCK_HIGH; | |
1459 | ||
12682a97 | 1460 | if (sdvo_priv->is_lvds == true) { |
1461 | if (sdvo_priv->sdvo_lvds_fixed_mode == NULL) | |
1462 | return MODE_PANEL; | |
1463 | ||
1464 | if (mode->hdisplay > sdvo_priv->sdvo_lvds_fixed_mode->hdisplay) | |
1465 | return MODE_PANEL; | |
1466 | ||
1467 | if (mode->vdisplay > sdvo_priv->sdvo_lvds_fixed_mode->vdisplay) | |
1468 | return MODE_PANEL; | |
1469 | } | |
1470 | ||
79e53945 JB |
1471 | return MODE_OK; |
1472 | } | |
1473 | ||
1474 | static bool intel_sdvo_get_capabilities(struct intel_output *intel_output, struct intel_sdvo_caps *caps) | |
1475 | { | |
1476 | u8 status; | |
1477 | ||
1478 | intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_DEVICE_CAPS, NULL, 0); | |
1479 | status = intel_sdvo_read_response(intel_output, caps, sizeof(*caps)); | |
1480 | if (status != SDVO_CMD_STATUS_SUCCESS) | |
1481 | return false; | |
1482 | ||
1483 | return true; | |
1484 | } | |
1485 | ||
1486 | struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB) | |
1487 | { | |
1488 | struct drm_connector *connector = NULL; | |
1489 | struct intel_output *iout = NULL; | |
1490 | struct intel_sdvo_priv *sdvo; | |
1491 | ||
1492 | /* find the sdvo connector */ | |
1493 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1494 | iout = to_intel_output(connector); | |
1495 | ||
1496 | if (iout->type != INTEL_OUTPUT_SDVO) | |
1497 | continue; | |
1498 | ||
1499 | sdvo = iout->dev_priv; | |
1500 | ||
1501 | if (sdvo->output_device == SDVOB && sdvoB) | |
1502 | return connector; | |
1503 | ||
1504 | if (sdvo->output_device == SDVOC && !sdvoB) | |
1505 | return connector; | |
1506 | ||
1507 | } | |
1508 | ||
1509 | return NULL; | |
1510 | } | |
1511 | ||
1512 | int intel_sdvo_supports_hotplug(struct drm_connector *connector) | |
1513 | { | |
1514 | u8 response[2]; | |
1515 | u8 status; | |
1516 | struct intel_output *intel_output; | |
8a4c47f3 | 1517 | DRM_DEBUG_KMS("\n"); |
79e53945 JB |
1518 | |
1519 | if (!connector) | |
1520 | return 0; | |
1521 | ||
1522 | intel_output = to_intel_output(connector); | |
1523 | ||
1524 | intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0); | |
1525 | status = intel_sdvo_read_response(intel_output, &response, 2); | |
1526 | ||
1527 | if (response[0] !=0) | |
1528 | return 1; | |
1529 | ||
1530 | return 0; | |
1531 | } | |
1532 | ||
1533 | void intel_sdvo_set_hotplug(struct drm_connector *connector, int on) | |
1534 | { | |
1535 | u8 response[2]; | |
1536 | u8 status; | |
1537 | struct intel_output *intel_output = to_intel_output(connector); | |
1538 | ||
1539 | intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0); | |
1540 | intel_sdvo_read_response(intel_output, &response, 2); | |
1541 | ||
1542 | if (on) { | |
1543 | intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0); | |
1544 | status = intel_sdvo_read_response(intel_output, &response, 2); | |
1545 | ||
1546 | intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2); | |
1547 | } else { | |
1548 | response[0] = 0; | |
1549 | response[1] = 0; | |
1550 | intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2); | |
1551 | } | |
1552 | ||
1553 | intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0); | |
1554 | intel_sdvo_read_response(intel_output, &response, 2); | |
1555 | } | |
1556 | ||
fb7a46f3 | 1557 | static bool |
1558 | intel_sdvo_multifunc_encoder(struct intel_output *intel_output) | |
1559 | { | |
1560 | struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; | |
1561 | int caps = 0; | |
1562 | ||
1563 | if (sdvo_priv->caps.output_flags & | |
1564 | (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) | |
1565 | caps++; | |
1566 | if (sdvo_priv->caps.output_flags & | |
1567 | (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)) | |
1568 | caps++; | |
1569 | if (sdvo_priv->caps.output_flags & | |
19e1f888 | 1570 | (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_SVID1)) |
fb7a46f3 | 1571 | caps++; |
1572 | if (sdvo_priv->caps.output_flags & | |
1573 | (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_CVBS1)) | |
1574 | caps++; | |
1575 | if (sdvo_priv->caps.output_flags & | |
1576 | (SDVO_OUTPUT_YPRPB0 | SDVO_OUTPUT_YPRPB1)) | |
1577 | caps++; | |
1578 | ||
1579 | if (sdvo_priv->caps.output_flags & | |
1580 | (SDVO_OUTPUT_SCART0 | SDVO_OUTPUT_SCART1)) | |
1581 | caps++; | |
1582 | ||
1583 | if (sdvo_priv->caps.output_flags & | |
1584 | (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)) | |
1585 | caps++; | |
1586 | ||
1587 | return (caps > 1); | |
1588 | } | |
1589 | ||
57cdaf90 KP |
1590 | static struct drm_connector * |
1591 | intel_find_analog_connector(struct drm_device *dev) | |
1592 | { | |
1593 | struct drm_connector *connector; | |
1594 | struct intel_output *intel_output; | |
1595 | ||
1596 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1597 | intel_output = to_intel_output(connector); | |
1598 | if (intel_output->type == INTEL_OUTPUT_ANALOG) | |
1599 | return connector; | |
1600 | } | |
1601 | return NULL; | |
1602 | } | |
1603 | ||
1604 | static int | |
1605 | intel_analog_is_connected(struct drm_device *dev) | |
1606 | { | |
1607 | struct drm_connector *analog_connector; | |
1608 | analog_connector = intel_find_analog_connector(dev); | |
1609 | ||
1610 | if (!analog_connector) | |
1611 | return false; | |
1612 | ||
1613 | if (analog_connector->funcs->detect(analog_connector) == | |
1614 | connector_status_disconnected) | |
1615 | return false; | |
1616 | ||
1617 | return true; | |
1618 | } | |
1619 | ||
2b8d33f7 | 1620 | enum drm_connector_status |
1621 | intel_sdvo_hdmi_sink_detect(struct drm_connector *connector, u16 response) | |
9dff6af8 ML |
1622 | { |
1623 | struct intel_output *intel_output = to_intel_output(connector); | |
1624 | struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; | |
2b8d33f7 | 1625 | enum drm_connector_status status = connector_status_connected; |
9dff6af8 ML |
1626 | struct edid *edid = NULL; |
1627 | ||
9dff6af8 | 1628 | edid = drm_get_edid(&intel_output->base, |
f9c10a9b | 1629 | intel_output->ddc_bus); |
57cdaf90 | 1630 | |
7c3f0a27 ZY |
1631 | /* This is only applied to SDVO cards with multiple outputs */ |
1632 | if (edid == NULL && intel_sdvo_multifunc_encoder(intel_output)) { | |
1633 | uint8_t saved_ddc, temp_ddc; | |
1634 | saved_ddc = sdvo_priv->ddc_bus; | |
1635 | temp_ddc = sdvo_priv->ddc_bus >> 1; | |
1636 | /* | |
1637 | * Don't use the 1 as the argument of DDC bus switch to get | |
1638 | * the EDID. It is used for SDVO SPD ROM. | |
1639 | */ | |
1640 | while(temp_ddc > 1) { | |
1641 | sdvo_priv->ddc_bus = temp_ddc; | |
1642 | edid = drm_get_edid(&intel_output->base, | |
1643 | intel_output->ddc_bus); | |
1644 | if (edid) { | |
1645 | /* | |
1646 | * When we can get the EDID, maybe it is the | |
1647 | * correct DDC bus. Update it. | |
1648 | */ | |
1649 | sdvo_priv->ddc_bus = temp_ddc; | |
1650 | break; | |
1651 | } | |
1652 | temp_ddc >>= 1; | |
1653 | } | |
1654 | if (edid == NULL) | |
1655 | sdvo_priv->ddc_bus = saved_ddc; | |
1656 | } | |
57cdaf90 KP |
1657 | /* when there is no edid and no monitor is connected with VGA |
1658 | * port, try to use the CRT ddc to read the EDID for DVI-connector | |
1659 | */ | |
1660 | if (edid == NULL && | |
1661 | sdvo_priv->analog_ddc_bus && | |
1662 | !intel_analog_is_connected(intel_output->base.dev)) | |
1663 | edid = drm_get_edid(&intel_output->base, | |
1664 | sdvo_priv->analog_ddc_bus); | |
9dff6af8 | 1665 | if (edid != NULL) { |
2b8d33f7 | 1666 | /* Don't report the output as connected if it's a DVI-I |
1667 | * connector with a non-digital EDID coming out. | |
1668 | */ | |
1669 | if (response & (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) { | |
1670 | if (edid->input & DRM_EDID_INPUT_DIGITAL) | |
1671 | sdvo_priv->is_hdmi = | |
1672 | drm_detect_hdmi_monitor(edid); | |
1673 | else | |
1674 | status = connector_status_disconnected; | |
1675 | } | |
1676 | ||
9dff6af8 ML |
1677 | kfree(edid); |
1678 | intel_output->base.display_info.raw_edid = NULL; | |
2b8d33f7 | 1679 | |
1680 | } else if (response & (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) | |
1681 | status = connector_status_disconnected; | |
1682 | ||
1683 | return status; | |
9dff6af8 ML |
1684 | } |
1685 | ||
79e53945 JB |
1686 | static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector) |
1687 | { | |
fb7a46f3 | 1688 | uint16_t response; |
79e53945 JB |
1689 | u8 status; |
1690 | struct intel_output *intel_output = to_intel_output(connector); | |
fb7a46f3 | 1691 | struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; |
79e53945 | 1692 | |
ce6feabd ZY |
1693 | intel_sdvo_write_cmd(intel_output, |
1694 | SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0); | |
d09c23de ZY |
1695 | if (sdvo_priv->is_tv) { |
1696 | /* add 30ms delay when the output type is SDVO-TV */ | |
1697 | mdelay(30); | |
1698 | } | |
79e53945 JB |
1699 | status = intel_sdvo_read_response(intel_output, &response, 2); |
1700 | ||
51c8b407 | 1701 | DRM_DEBUG_KMS("SDVO response %d %d\n", response & 0xff, response >> 8); |
e2f0ba97 JB |
1702 | |
1703 | if (status != SDVO_CMD_STATUS_SUCCESS) | |
1704 | return connector_status_unknown; | |
1705 | ||
fb7a46f3 | 1706 | if (response == 0) |
79e53945 | 1707 | return connector_status_disconnected; |
fb7a46f3 | 1708 | |
1709 | if (intel_sdvo_multifunc_encoder(intel_output) && | |
1710 | sdvo_priv->attached_output != response) { | |
1711 | if (sdvo_priv->controlled_output != response && | |
1712 | intel_sdvo_output_setup(intel_output, response) != true) | |
1713 | return connector_status_unknown; | |
1714 | sdvo_priv->attached_output = response; | |
1715 | } | |
2b8d33f7 | 1716 | return intel_sdvo_hdmi_sink_detect(connector, response); |
79e53945 JB |
1717 | } |
1718 | ||
e2f0ba97 | 1719 | static void intel_sdvo_get_ddc_modes(struct drm_connector *connector) |
79e53945 JB |
1720 | { |
1721 | struct intel_output *intel_output = to_intel_output(connector); | |
57cdaf90 KP |
1722 | struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; |
1723 | int num_modes; | |
79e53945 JB |
1724 | |
1725 | /* set the bus switch and get the modes */ | |
57cdaf90 | 1726 | num_modes = intel_ddc_get_modes(intel_output); |
79e53945 | 1727 | |
57cdaf90 KP |
1728 | /* |
1729 | * Mac mini hack. On this device, the DVI-I connector shares one DDC | |
1730 | * link between analog and digital outputs. So, if the regular SDVO | |
1731 | * DDC fails, check to see if the analog output is disconnected, in | |
1732 | * which case we'll look there for the digital DDC data. | |
e2f0ba97 | 1733 | */ |
57cdaf90 KP |
1734 | if (num_modes == 0 && |
1735 | sdvo_priv->analog_ddc_bus && | |
1736 | !intel_analog_is_connected(intel_output->base.dev)) { | |
1737 | struct i2c_adapter *digital_ddc_bus; | |
e2f0ba97 | 1738 | |
57cdaf90 KP |
1739 | /* Switch to the analog ddc bus and try that |
1740 | */ | |
1741 | digital_ddc_bus = intel_output->ddc_bus; | |
1742 | intel_output->ddc_bus = sdvo_priv->analog_ddc_bus; | |
e2f0ba97 | 1743 | |
57cdaf90 | 1744 | (void) intel_ddc_get_modes(intel_output); |
e2f0ba97 | 1745 | |
57cdaf90 | 1746 | intel_output->ddc_bus = digital_ddc_bus; |
e2f0ba97 | 1747 | } |
e2f0ba97 JB |
1748 | } |
1749 | ||
1750 | /* | |
1751 | * Set of SDVO TV modes. | |
1752 | * Note! This is in reply order (see loop in get_tv_modes). | |
1753 | * XXX: all 60Hz refresh? | |
1754 | */ | |
1755 | struct drm_display_mode sdvo_tv_modes[] = { | |
7026d4ac ZW |
1756 | { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384, |
1757 | 416, 0, 200, 201, 232, 233, 0, | |
e2f0ba97 | 1758 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1759 | { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384, |
1760 | 416, 0, 240, 241, 272, 273, 0, | |
e2f0ba97 | 1761 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1762 | { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464, |
1763 | 496, 0, 300, 301, 332, 333, 0, | |
e2f0ba97 | 1764 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1765 | { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704, |
1766 | 736, 0, 350, 351, 382, 383, 0, | |
e2f0ba97 | 1767 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1768 | { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704, |
1769 | 736, 0, 400, 401, 432, 433, 0, | |
e2f0ba97 | 1770 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1771 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704, |
1772 | 736, 0, 480, 481, 512, 513, 0, | |
e2f0ba97 | 1773 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1774 | { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768, |
1775 | 800, 0, 480, 481, 512, 513, 0, | |
e2f0ba97 | 1776 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1777 | { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768, |
1778 | 800, 0, 576, 577, 608, 609, 0, | |
e2f0ba97 | 1779 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1780 | { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784, |
1781 | 816, 0, 350, 351, 382, 383, 0, | |
e2f0ba97 | 1782 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1783 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784, |
1784 | 816, 0, 400, 401, 432, 433, 0, | |
e2f0ba97 | 1785 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1786 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784, |
1787 | 816, 0, 480, 481, 512, 513, 0, | |
e2f0ba97 | 1788 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1789 | { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784, |
1790 | 816, 0, 540, 541, 572, 573, 0, | |
e2f0ba97 | 1791 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1792 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784, |
1793 | 816, 0, 576, 577, 608, 609, 0, | |
e2f0ba97 | 1794 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1795 | { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832, |
1796 | 864, 0, 576, 577, 608, 609, 0, | |
e2f0ba97 | 1797 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1798 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864, |
1799 | 896, 0, 600, 601, 632, 633, 0, | |
e2f0ba97 | 1800 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1801 | { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896, |
1802 | 928, 0, 624, 625, 656, 657, 0, | |
e2f0ba97 | 1803 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1804 | { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984, |
1805 | 1016, 0, 766, 767, 798, 799, 0, | |
e2f0ba97 | 1806 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1807 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088, |
1808 | 1120, 0, 768, 769, 800, 801, 0, | |
e2f0ba97 | 1809 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1810 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344, |
1811 | 1376, 0, 1024, 1025, 1056, 1057, 0, | |
e2f0ba97 JB |
1812 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
1813 | }; | |
1814 | ||
1815 | static void intel_sdvo_get_tv_modes(struct drm_connector *connector) | |
1816 | { | |
1817 | struct intel_output *output = to_intel_output(connector); | |
7026d4ac ZW |
1818 | struct intel_sdvo_priv *sdvo_priv = output->dev_priv; |
1819 | struct intel_sdvo_sdtv_resolution_request tv_res; | |
ce6feabd ZY |
1820 | uint32_t reply = 0, format_map = 0; |
1821 | int i; | |
e2f0ba97 | 1822 | uint8_t status; |
e2f0ba97 | 1823 | |
e2f0ba97 JB |
1824 | |
1825 | /* Read the list of supported input resolutions for the selected TV | |
1826 | * format. | |
1827 | */ | |
ce6feabd ZY |
1828 | for (i = 0; i < TV_FORMAT_NUM; i++) |
1829 | if (tv_format_names[i] == sdvo_priv->tv_format_name) | |
1830 | break; | |
1831 | ||
1832 | format_map = (1 << i); | |
1833 | memcpy(&tv_res, &format_map, | |
1834 | sizeof(struct intel_sdvo_sdtv_resolution_request) > | |
1835 | sizeof(format_map) ? sizeof(format_map) : | |
1836 | sizeof(struct intel_sdvo_sdtv_resolution_request)); | |
1837 | ||
1838 | intel_sdvo_set_target_output(output, sdvo_priv->controlled_output); | |
1839 | ||
e2f0ba97 | 1840 | intel_sdvo_write_cmd(output, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, |
7026d4ac | 1841 | &tv_res, sizeof(tv_res)); |
e2f0ba97 JB |
1842 | status = intel_sdvo_read_response(output, &reply, 3); |
1843 | if (status != SDVO_CMD_STATUS_SUCCESS) | |
1844 | return; | |
1845 | ||
1846 | for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) | |
7026d4ac ZW |
1847 | if (reply & (1 << i)) { |
1848 | struct drm_display_mode *nmode; | |
1849 | nmode = drm_mode_duplicate(connector->dev, | |
1850 | &sdvo_tv_modes[i]); | |
1851 | if (nmode) | |
1852 | drm_mode_probed_add(connector, nmode); | |
1853 | } | |
ce6feabd | 1854 | |
e2f0ba97 JB |
1855 | } |
1856 | ||
7086c87f ML |
1857 | static void intel_sdvo_get_lvds_modes(struct drm_connector *connector) |
1858 | { | |
1859 | struct intel_output *intel_output = to_intel_output(connector); | |
7086c87f | 1860 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
12682a97 | 1861 | struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; |
1862 | struct drm_display_mode *newmode; | |
7086c87f ML |
1863 | |
1864 | /* | |
1865 | * Attempt to get the mode list from DDC. | |
1866 | * Assume that the preferred modes are | |
1867 | * arranged in priority order. | |
1868 | */ | |
7086c87f ML |
1869 | intel_ddc_get_modes(intel_output); |
1870 | if (list_empty(&connector->probed_modes) == false) | |
12682a97 | 1871 | goto end; |
7086c87f ML |
1872 | |
1873 | /* Fetch modes from VBT */ | |
1874 | if (dev_priv->sdvo_lvds_vbt_mode != NULL) { | |
7086c87f ML |
1875 | newmode = drm_mode_duplicate(connector->dev, |
1876 | dev_priv->sdvo_lvds_vbt_mode); | |
1877 | if (newmode != NULL) { | |
1878 | /* Guarantee the mode is preferred */ | |
1879 | newmode->type = (DRM_MODE_TYPE_PREFERRED | | |
1880 | DRM_MODE_TYPE_DRIVER); | |
1881 | drm_mode_probed_add(connector, newmode); | |
1882 | } | |
1883 | } | |
12682a97 | 1884 | |
1885 | end: | |
1886 | list_for_each_entry(newmode, &connector->probed_modes, head) { | |
1887 | if (newmode->type & DRM_MODE_TYPE_PREFERRED) { | |
1888 | sdvo_priv->sdvo_lvds_fixed_mode = | |
1889 | drm_mode_duplicate(connector->dev, newmode); | |
1890 | break; | |
1891 | } | |
1892 | } | |
1893 | ||
7086c87f ML |
1894 | } |
1895 | ||
e2f0ba97 JB |
1896 | static int intel_sdvo_get_modes(struct drm_connector *connector) |
1897 | { | |
1898 | struct intel_output *output = to_intel_output(connector); | |
1899 | struct intel_sdvo_priv *sdvo_priv = output->dev_priv; | |
1900 | ||
1901 | if (sdvo_priv->is_tv) | |
1902 | intel_sdvo_get_tv_modes(connector); | |
7086c87f ML |
1903 | else if (sdvo_priv->is_lvds == true) |
1904 | intel_sdvo_get_lvds_modes(connector); | |
e2f0ba97 JB |
1905 | else |
1906 | intel_sdvo_get_ddc_modes(connector); | |
1907 | ||
79e53945 JB |
1908 | if (list_empty(&connector->probed_modes)) |
1909 | return 0; | |
1910 | return 1; | |
1911 | } | |
1912 | ||
b9219c5e ZY |
1913 | static |
1914 | void intel_sdvo_destroy_enhance_property(struct drm_connector *connector) | |
1915 | { | |
1916 | struct intel_output *intel_output = to_intel_output(connector); | |
1917 | struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; | |
1918 | struct drm_device *dev = connector->dev; | |
1919 | ||
1920 | if (sdvo_priv->is_tv) { | |
1921 | if (sdvo_priv->left_property) | |
1922 | drm_property_destroy(dev, sdvo_priv->left_property); | |
1923 | if (sdvo_priv->right_property) | |
1924 | drm_property_destroy(dev, sdvo_priv->right_property); | |
1925 | if (sdvo_priv->top_property) | |
1926 | drm_property_destroy(dev, sdvo_priv->top_property); | |
1927 | if (sdvo_priv->bottom_property) | |
1928 | drm_property_destroy(dev, sdvo_priv->bottom_property); | |
1929 | if (sdvo_priv->hpos_property) | |
1930 | drm_property_destroy(dev, sdvo_priv->hpos_property); | |
1931 | if (sdvo_priv->vpos_property) | |
1932 | drm_property_destroy(dev, sdvo_priv->vpos_property); | |
1933 | } | |
1934 | if (sdvo_priv->is_tv) { | |
1935 | if (sdvo_priv->saturation_property) | |
1936 | drm_property_destroy(dev, | |
1937 | sdvo_priv->saturation_property); | |
1938 | if (sdvo_priv->contrast_property) | |
1939 | drm_property_destroy(dev, | |
1940 | sdvo_priv->contrast_property); | |
1941 | if (sdvo_priv->hue_property) | |
1942 | drm_property_destroy(dev, sdvo_priv->hue_property); | |
1943 | } | |
d0cbde93 | 1944 | if (sdvo_priv->is_tv || sdvo_priv->is_lvds) { |
b9219c5e ZY |
1945 | if (sdvo_priv->brightness_property) |
1946 | drm_property_destroy(dev, | |
1947 | sdvo_priv->brightness_property); | |
1948 | } | |
1949 | return; | |
1950 | } | |
1951 | ||
79e53945 JB |
1952 | static void intel_sdvo_destroy(struct drm_connector *connector) |
1953 | { | |
1954 | struct intel_output *intel_output = to_intel_output(connector); | |
12682a97 | 1955 | struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; |
79e53945 JB |
1956 | |
1957 | if (intel_output->i2c_bus) | |
1958 | intel_i2c_destroy(intel_output->i2c_bus); | |
619ac3b7 ML |
1959 | if (intel_output->ddc_bus) |
1960 | intel_i2c_destroy(intel_output->ddc_bus); | |
57cdaf90 KP |
1961 | if (sdvo_priv->analog_ddc_bus) |
1962 | intel_i2c_destroy(sdvo_priv->analog_ddc_bus); | |
619ac3b7 | 1963 | |
12682a97 | 1964 | if (sdvo_priv->sdvo_lvds_fixed_mode != NULL) |
1965 | drm_mode_destroy(connector->dev, | |
1966 | sdvo_priv->sdvo_lvds_fixed_mode); | |
1967 | ||
ce6feabd ZY |
1968 | if (sdvo_priv->tv_format_property) |
1969 | drm_property_destroy(connector->dev, | |
1970 | sdvo_priv->tv_format_property); | |
1971 | ||
d0cbde93 | 1972 | if (sdvo_priv->is_tv || sdvo_priv->is_lvds) |
b9219c5e ZY |
1973 | intel_sdvo_destroy_enhance_property(connector); |
1974 | ||
79e53945 JB |
1975 | drm_sysfs_connector_remove(connector); |
1976 | drm_connector_cleanup(connector); | |
12682a97 | 1977 | |
79e53945 JB |
1978 | kfree(intel_output); |
1979 | } | |
1980 | ||
ce6feabd ZY |
1981 | static int |
1982 | intel_sdvo_set_property(struct drm_connector *connector, | |
1983 | struct drm_property *property, | |
1984 | uint64_t val) | |
1985 | { | |
1986 | struct intel_output *intel_output = to_intel_output(connector); | |
1987 | struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; | |
1988 | struct drm_encoder *encoder = &intel_output->enc; | |
1989 | struct drm_crtc *crtc = encoder->crtc; | |
1990 | int ret = 0; | |
1991 | bool changed = false; | |
b9219c5e ZY |
1992 | uint8_t cmd, status; |
1993 | uint16_t temp_value; | |
ce6feabd ZY |
1994 | |
1995 | ret = drm_connector_property_set_value(connector, property, val); | |
1996 | if (ret < 0) | |
1997 | goto out; | |
1998 | ||
1999 | if (property == sdvo_priv->tv_format_property) { | |
2000 | if (val >= TV_FORMAT_NUM) { | |
2001 | ret = -EINVAL; | |
2002 | goto out; | |
2003 | } | |
2004 | if (sdvo_priv->tv_format_name == | |
2005 | sdvo_priv->tv_format_supported[val]) | |
2006 | goto out; | |
2007 | ||
2008 | sdvo_priv->tv_format_name = sdvo_priv->tv_format_supported[val]; | |
2009 | changed = true; | |
ce6feabd ZY |
2010 | } |
2011 | ||
d0cbde93 | 2012 | if (sdvo_priv->is_tv || sdvo_priv->is_lvds) { |
b9219c5e ZY |
2013 | cmd = 0; |
2014 | temp_value = val; | |
2015 | if (sdvo_priv->left_property == property) { | |
2016 | drm_connector_property_set_value(connector, | |
2017 | sdvo_priv->right_property, val); | |
2018 | if (sdvo_priv->left_margin == temp_value) | |
2019 | goto out; | |
2020 | ||
2021 | sdvo_priv->left_margin = temp_value; | |
2022 | sdvo_priv->right_margin = temp_value; | |
2023 | temp_value = sdvo_priv->max_hscan - | |
2024 | sdvo_priv->left_margin; | |
2025 | cmd = SDVO_CMD_SET_OVERSCAN_H; | |
2026 | } else if (sdvo_priv->right_property == property) { | |
2027 | drm_connector_property_set_value(connector, | |
2028 | sdvo_priv->left_property, val); | |
2029 | if (sdvo_priv->right_margin == temp_value) | |
2030 | goto out; | |
2031 | ||
2032 | sdvo_priv->left_margin = temp_value; | |
2033 | sdvo_priv->right_margin = temp_value; | |
2034 | temp_value = sdvo_priv->max_hscan - | |
2035 | sdvo_priv->left_margin; | |
2036 | cmd = SDVO_CMD_SET_OVERSCAN_H; | |
2037 | } else if (sdvo_priv->top_property == property) { | |
2038 | drm_connector_property_set_value(connector, | |
2039 | sdvo_priv->bottom_property, val); | |
2040 | if (sdvo_priv->top_margin == temp_value) | |
2041 | goto out; | |
2042 | ||
2043 | sdvo_priv->top_margin = temp_value; | |
2044 | sdvo_priv->bottom_margin = temp_value; | |
2045 | temp_value = sdvo_priv->max_vscan - | |
2046 | sdvo_priv->top_margin; | |
2047 | cmd = SDVO_CMD_SET_OVERSCAN_V; | |
2048 | } else if (sdvo_priv->bottom_property == property) { | |
2049 | drm_connector_property_set_value(connector, | |
2050 | sdvo_priv->top_property, val); | |
2051 | if (sdvo_priv->bottom_margin == temp_value) | |
2052 | goto out; | |
2053 | sdvo_priv->top_margin = temp_value; | |
2054 | sdvo_priv->bottom_margin = temp_value; | |
2055 | temp_value = sdvo_priv->max_vscan - | |
2056 | sdvo_priv->top_margin; | |
2057 | cmd = SDVO_CMD_SET_OVERSCAN_V; | |
2058 | } else if (sdvo_priv->hpos_property == property) { | |
2059 | if (sdvo_priv->cur_hpos == temp_value) | |
2060 | goto out; | |
2061 | ||
2062 | cmd = SDVO_CMD_SET_POSITION_H; | |
2063 | sdvo_priv->cur_hpos = temp_value; | |
2064 | } else if (sdvo_priv->vpos_property == property) { | |
2065 | if (sdvo_priv->cur_vpos == temp_value) | |
2066 | goto out; | |
2067 | ||
2068 | cmd = SDVO_CMD_SET_POSITION_V; | |
2069 | sdvo_priv->cur_vpos = temp_value; | |
2070 | } else if (sdvo_priv->saturation_property == property) { | |
2071 | if (sdvo_priv->cur_saturation == temp_value) | |
2072 | goto out; | |
2073 | ||
2074 | cmd = SDVO_CMD_SET_SATURATION; | |
2075 | sdvo_priv->cur_saturation = temp_value; | |
2076 | } else if (sdvo_priv->contrast_property == property) { | |
2077 | if (sdvo_priv->cur_contrast == temp_value) | |
2078 | goto out; | |
2079 | ||
2080 | cmd = SDVO_CMD_SET_CONTRAST; | |
2081 | sdvo_priv->cur_contrast = temp_value; | |
2082 | } else if (sdvo_priv->hue_property == property) { | |
2083 | if (sdvo_priv->cur_hue == temp_value) | |
2084 | goto out; | |
2085 | ||
2086 | cmd = SDVO_CMD_SET_HUE; | |
2087 | sdvo_priv->cur_hue = temp_value; | |
2088 | } else if (sdvo_priv->brightness_property == property) { | |
2089 | if (sdvo_priv->cur_brightness == temp_value) | |
2090 | goto out; | |
2091 | ||
2092 | cmd = SDVO_CMD_SET_BRIGHTNESS; | |
2093 | sdvo_priv->cur_brightness = temp_value; | |
2094 | } | |
2095 | if (cmd) { | |
2096 | intel_sdvo_write_cmd(intel_output, cmd, &temp_value, 2); | |
2097 | status = intel_sdvo_read_response(intel_output, | |
2098 | NULL, 0); | |
2099 | if (status != SDVO_CMD_STATUS_SUCCESS) { | |
2100 | DRM_DEBUG_KMS("Incorrect SDVO command \n"); | |
2101 | return -EINVAL; | |
2102 | } | |
2103 | changed = true; | |
2104 | } | |
2105 | } | |
ce6feabd ZY |
2106 | if (changed && crtc) |
2107 | drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x, | |
2108 | crtc->y, crtc->fb); | |
2109 | out: | |
2110 | return ret; | |
2111 | } | |
2112 | ||
79e53945 JB |
2113 | static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = { |
2114 | .dpms = intel_sdvo_dpms, | |
2115 | .mode_fixup = intel_sdvo_mode_fixup, | |
2116 | .prepare = intel_encoder_prepare, | |
2117 | .mode_set = intel_sdvo_mode_set, | |
2118 | .commit = intel_encoder_commit, | |
2119 | }; | |
2120 | ||
2121 | static const struct drm_connector_funcs intel_sdvo_connector_funcs = { | |
c9fb15f6 | 2122 | .dpms = drm_helper_connector_dpms, |
79e53945 JB |
2123 | .save = intel_sdvo_save, |
2124 | .restore = intel_sdvo_restore, | |
2125 | .detect = intel_sdvo_detect, | |
2126 | .fill_modes = drm_helper_probe_single_connector_modes, | |
ce6feabd | 2127 | .set_property = intel_sdvo_set_property, |
79e53945 JB |
2128 | .destroy = intel_sdvo_destroy, |
2129 | }; | |
2130 | ||
2131 | static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = { | |
2132 | .get_modes = intel_sdvo_get_modes, | |
2133 | .mode_valid = intel_sdvo_mode_valid, | |
2134 | .best_encoder = intel_best_encoder, | |
2135 | }; | |
2136 | ||
b358d0a6 | 2137 | static void intel_sdvo_enc_destroy(struct drm_encoder *encoder) |
79e53945 JB |
2138 | { |
2139 | drm_encoder_cleanup(encoder); | |
2140 | } | |
2141 | ||
2142 | static const struct drm_encoder_funcs intel_sdvo_enc_funcs = { | |
2143 | .destroy = intel_sdvo_enc_destroy, | |
2144 | }; | |
2145 | ||
2146 | ||
e2f0ba97 JB |
2147 | /** |
2148 | * Choose the appropriate DDC bus for control bus switch command for this | |
2149 | * SDVO output based on the controlled output. | |
2150 | * | |
2151 | * DDC bus number assignment is in a priority order of RGB outputs, then TMDS | |
2152 | * outputs, then LVDS outputs. | |
2153 | */ | |
2154 | static void | |
2155 | intel_sdvo_select_ddc_bus(struct intel_sdvo_priv *dev_priv) | |
2156 | { | |
2157 | uint16_t mask = 0; | |
2158 | unsigned int num_bits; | |
2159 | ||
2160 | /* Make a mask of outputs less than or equal to our own priority in the | |
2161 | * list. | |
2162 | */ | |
2163 | switch (dev_priv->controlled_output) { | |
2164 | case SDVO_OUTPUT_LVDS1: | |
2165 | mask |= SDVO_OUTPUT_LVDS1; | |
2166 | case SDVO_OUTPUT_LVDS0: | |
2167 | mask |= SDVO_OUTPUT_LVDS0; | |
2168 | case SDVO_OUTPUT_TMDS1: | |
2169 | mask |= SDVO_OUTPUT_TMDS1; | |
2170 | case SDVO_OUTPUT_TMDS0: | |
2171 | mask |= SDVO_OUTPUT_TMDS0; | |
2172 | case SDVO_OUTPUT_RGB1: | |
2173 | mask |= SDVO_OUTPUT_RGB1; | |
2174 | case SDVO_OUTPUT_RGB0: | |
2175 | mask |= SDVO_OUTPUT_RGB0; | |
2176 | break; | |
2177 | } | |
2178 | ||
2179 | /* Count bits to find what number we are in the priority list. */ | |
2180 | mask &= dev_priv->caps.output_flags; | |
2181 | num_bits = hweight16(mask); | |
2182 | if (num_bits > 3) { | |
2183 | /* if more than 3 outputs, default to DDC bus 3 for now */ | |
2184 | num_bits = 3; | |
2185 | } | |
2186 | ||
2187 | /* Corresponds to SDVO_CONTROL_BUS_DDCx */ | |
2188 | dev_priv->ddc_bus = 1 << num_bits; | |
2189 | } | |
2190 | ||
2191 | static bool | |
2192 | intel_sdvo_get_digital_encoding_mode(struct intel_output *output) | |
2193 | { | |
2194 | struct intel_sdvo_priv *sdvo_priv = output->dev_priv; | |
2195 | uint8_t status; | |
2196 | ||
2197 | intel_sdvo_set_target_output(output, sdvo_priv->controlled_output); | |
2198 | ||
2199 | intel_sdvo_write_cmd(output, SDVO_CMD_GET_ENCODE, NULL, 0); | |
2200 | status = intel_sdvo_read_response(output, &sdvo_priv->is_hdmi, 1); | |
2201 | if (status != SDVO_CMD_STATUS_SUCCESS) | |
2202 | return false; | |
2203 | return true; | |
2204 | } | |
2205 | ||
619ac3b7 ML |
2206 | static struct intel_output * |
2207 | intel_sdvo_chan_to_intel_output(struct intel_i2c_chan *chan) | |
2208 | { | |
2209 | struct drm_device *dev = chan->drm_dev; | |
2210 | struct drm_connector *connector; | |
2211 | struct intel_output *intel_output = NULL; | |
2212 | ||
2213 | list_for_each_entry(connector, | |
2214 | &dev->mode_config.connector_list, head) { | |
f9c10a9b | 2215 | if (to_intel_output(connector)->ddc_bus == &chan->adapter) { |
619ac3b7 ML |
2216 | intel_output = to_intel_output(connector); |
2217 | break; | |
2218 | } | |
2219 | } | |
2220 | return intel_output; | |
2221 | } | |
2222 | ||
2223 | static int intel_sdvo_master_xfer(struct i2c_adapter *i2c_adap, | |
2224 | struct i2c_msg msgs[], int num) | |
2225 | { | |
2226 | struct intel_output *intel_output; | |
2227 | struct intel_sdvo_priv *sdvo_priv; | |
2228 | struct i2c_algo_bit_data *algo_data; | |
f9c10a9b | 2229 | const struct i2c_algorithm *algo; |
619ac3b7 ML |
2230 | |
2231 | algo_data = (struct i2c_algo_bit_data *)i2c_adap->algo_data; | |
2232 | intel_output = | |
2233 | intel_sdvo_chan_to_intel_output( | |
2234 | (struct intel_i2c_chan *)(algo_data->data)); | |
2235 | if (intel_output == NULL) | |
2236 | return -EINVAL; | |
2237 | ||
2238 | sdvo_priv = intel_output->dev_priv; | |
f9c10a9b | 2239 | algo = intel_output->i2c_bus->algo; |
619ac3b7 ML |
2240 | |
2241 | intel_sdvo_set_control_bus_switch(intel_output, sdvo_priv->ddc_bus); | |
2242 | return algo->master_xfer(i2c_adap, msgs, num); | |
2243 | } | |
2244 | ||
2245 | static struct i2c_algorithm intel_sdvo_i2c_bit_algo = { | |
2246 | .master_xfer = intel_sdvo_master_xfer, | |
2247 | }; | |
2248 | ||
714605e4 | 2249 | static u8 |
2250 | intel_sdvo_get_slave_addr(struct drm_device *dev, int output_device) | |
2251 | { | |
2252 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2253 | struct sdvo_device_mapping *my_mapping, *other_mapping; | |
2254 | ||
2255 | if (output_device == SDVOB) { | |
2256 | my_mapping = &dev_priv->sdvo_mappings[0]; | |
2257 | other_mapping = &dev_priv->sdvo_mappings[1]; | |
2258 | } else { | |
2259 | my_mapping = &dev_priv->sdvo_mappings[1]; | |
2260 | other_mapping = &dev_priv->sdvo_mappings[0]; | |
2261 | } | |
2262 | ||
2263 | /* If the BIOS described our SDVO device, take advantage of it. */ | |
2264 | if (my_mapping->slave_addr) | |
2265 | return my_mapping->slave_addr; | |
2266 | ||
2267 | /* If the BIOS only described a different SDVO device, use the | |
2268 | * address that it isn't using. | |
2269 | */ | |
2270 | if (other_mapping->slave_addr) { | |
2271 | if (other_mapping->slave_addr == 0x70) | |
2272 | return 0x72; | |
2273 | else | |
2274 | return 0x70; | |
2275 | } | |
2276 | ||
2277 | /* No SDVO device info is found for another DVO port, | |
2278 | * so use mapping assumption we had before BIOS parsing. | |
2279 | */ | |
2280 | if (output_device == SDVOB) | |
2281 | return 0x70; | |
2282 | else | |
2283 | return 0x72; | |
2284 | } | |
2285 | ||
fb7a46f3 | 2286 | static bool |
2287 | intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags) | |
2288 | { | |
2289 | struct drm_connector *connector = &intel_output->base; | |
2290 | struct drm_encoder *encoder = &intel_output->enc; | |
2291 | struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; | |
2292 | bool ret = true, registered = false; | |
2293 | ||
2294 | sdvo_priv->is_tv = false; | |
2295 | intel_output->needs_tv_clock = false; | |
2296 | sdvo_priv->is_lvds = false; | |
2297 | ||
2298 | if (device_is_registered(&connector->kdev)) { | |
2299 | drm_sysfs_connector_remove(connector); | |
2300 | registered = true; | |
2301 | } | |
2302 | ||
2303 | if (flags & | |
2304 | (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) { | |
2305 | if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_TMDS0) | |
2306 | sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS0; | |
2307 | else | |
2308 | sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS1; | |
2309 | ||
2310 | encoder->encoder_type = DRM_MODE_ENCODER_TMDS; | |
2311 | connector->connector_type = DRM_MODE_CONNECTOR_DVID; | |
2312 | ||
2313 | if (intel_sdvo_get_supp_encode(intel_output, | |
2314 | &sdvo_priv->encode) && | |
2315 | intel_sdvo_get_digital_encoding_mode(intel_output) && | |
2316 | sdvo_priv->is_hdmi) { | |
2317 | /* enable hdmi encoding mode if supported */ | |
2318 | intel_sdvo_set_encode(intel_output, SDVO_ENCODE_HDMI); | |
2319 | intel_sdvo_set_colorimetry(intel_output, | |
2320 | SDVO_COLORIMETRY_RGB256); | |
2321 | connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; | |
f8aed700 ML |
2322 | intel_output->clone_mask = |
2323 | (1 << INTEL_SDVO_NON_TV_CLONE_BIT) | | |
2324 | (1 << INTEL_ANALOG_CLONE_BIT); | |
fb7a46f3 | 2325 | } |
2326 | } else if (flags & SDVO_OUTPUT_SVID0) { | |
2327 | ||
2328 | sdvo_priv->controlled_output = SDVO_OUTPUT_SVID0; | |
2329 | encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; | |
2330 | connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; | |
2331 | sdvo_priv->is_tv = true; | |
2332 | intel_output->needs_tv_clock = true; | |
f8aed700 | 2333 | intel_output->clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT; |
fb7a46f3 | 2334 | } else if (flags & SDVO_OUTPUT_RGB0) { |
2335 | ||
2336 | sdvo_priv->controlled_output = SDVO_OUTPUT_RGB0; | |
2337 | encoder->encoder_type = DRM_MODE_ENCODER_DAC; | |
2338 | connector->connector_type = DRM_MODE_CONNECTOR_VGA; | |
f8aed700 ML |
2339 | intel_output->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) | |
2340 | (1 << INTEL_ANALOG_CLONE_BIT); | |
fb7a46f3 | 2341 | } else if (flags & SDVO_OUTPUT_RGB1) { |
2342 | ||
2343 | sdvo_priv->controlled_output = SDVO_OUTPUT_RGB1; | |
2344 | encoder->encoder_type = DRM_MODE_ENCODER_DAC; | |
2345 | connector->connector_type = DRM_MODE_CONNECTOR_VGA; | |
e270846f ZY |
2346 | intel_output->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) | |
2347 | (1 << INTEL_ANALOG_CLONE_BIT); | |
fb7a46f3 | 2348 | } else if (flags & SDVO_OUTPUT_LVDS0) { |
2349 | ||
2350 | sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS0; | |
2351 | encoder->encoder_type = DRM_MODE_ENCODER_LVDS; | |
2352 | connector->connector_type = DRM_MODE_CONNECTOR_LVDS; | |
2353 | sdvo_priv->is_lvds = true; | |
f8aed700 ML |
2354 | intel_output->clone_mask = (1 << INTEL_ANALOG_CLONE_BIT) | |
2355 | (1 << INTEL_SDVO_LVDS_CLONE_BIT); | |
fb7a46f3 | 2356 | } else if (flags & SDVO_OUTPUT_LVDS1) { |
2357 | ||
2358 | sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS1; | |
2359 | encoder->encoder_type = DRM_MODE_ENCODER_LVDS; | |
2360 | connector->connector_type = DRM_MODE_CONNECTOR_LVDS; | |
2361 | sdvo_priv->is_lvds = true; | |
f8aed700 ML |
2362 | intel_output->clone_mask = (1 << INTEL_ANALOG_CLONE_BIT) | |
2363 | (1 << INTEL_SDVO_LVDS_CLONE_BIT); | |
fb7a46f3 | 2364 | } else { |
2365 | ||
2366 | unsigned char bytes[2]; | |
2367 | ||
2368 | sdvo_priv->controlled_output = 0; | |
2369 | memcpy(bytes, &sdvo_priv->caps.output_flags, 2); | |
51c8b407 DA |
2370 | DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n", |
2371 | SDVO_NAME(sdvo_priv), | |
2372 | bytes[0], bytes[1]); | |
fb7a46f3 | 2373 | ret = false; |
2374 | } | |
f8aed700 | 2375 | intel_output->crtc_mask = (1 << 0) | (1 << 1); |
fb7a46f3 | 2376 | |
2377 | if (ret && registered) | |
2378 | ret = drm_sysfs_connector_add(connector) == 0 ? true : false; | |
2379 | ||
2380 | ||
2381 | return ret; | |
2382 | ||
2383 | } | |
2384 | ||
ce6feabd ZY |
2385 | static void intel_sdvo_tv_create_property(struct drm_connector *connector) |
2386 | { | |
2387 | struct intel_output *intel_output = to_intel_output(connector); | |
2388 | struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; | |
2389 | struct intel_sdvo_tv_format format; | |
2390 | uint32_t format_map, i; | |
2391 | uint8_t status; | |
2392 | ||
2393 | intel_sdvo_set_target_output(intel_output, | |
2394 | sdvo_priv->controlled_output); | |
2395 | ||
2396 | intel_sdvo_write_cmd(intel_output, | |
2397 | SDVO_CMD_GET_SUPPORTED_TV_FORMATS, NULL, 0); | |
2398 | status = intel_sdvo_read_response(intel_output, | |
2399 | &format, sizeof(format)); | |
2400 | if (status != SDVO_CMD_STATUS_SUCCESS) | |
2401 | return; | |
2402 | ||
2403 | memcpy(&format_map, &format, sizeof(format) > sizeof(format_map) ? | |
2404 | sizeof(format_map) : sizeof(format)); | |
2405 | ||
2406 | if (format_map == 0) | |
2407 | return; | |
2408 | ||
2409 | sdvo_priv->format_supported_num = 0; | |
2410 | for (i = 0 ; i < TV_FORMAT_NUM; i++) | |
2411 | if (format_map & (1 << i)) { | |
2412 | sdvo_priv->tv_format_supported | |
2413 | [sdvo_priv->format_supported_num++] = | |
2414 | tv_format_names[i]; | |
2415 | } | |
2416 | ||
2417 | ||
2418 | sdvo_priv->tv_format_property = | |
2419 | drm_property_create( | |
2420 | connector->dev, DRM_MODE_PROP_ENUM, | |
2421 | "mode", sdvo_priv->format_supported_num); | |
2422 | ||
2423 | for (i = 0; i < sdvo_priv->format_supported_num; i++) | |
2424 | drm_property_add_enum( | |
2425 | sdvo_priv->tv_format_property, i, | |
2426 | i, sdvo_priv->tv_format_supported[i]); | |
2427 | ||
2428 | sdvo_priv->tv_format_name = sdvo_priv->tv_format_supported[0]; | |
2429 | drm_connector_attach_property( | |
2430 | connector, sdvo_priv->tv_format_property, 0); | |
2431 | ||
2432 | } | |
2433 | ||
b9219c5e ZY |
2434 | static void intel_sdvo_create_enhance_property(struct drm_connector *connector) |
2435 | { | |
2436 | struct intel_output *intel_output = to_intel_output(connector); | |
2437 | struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; | |
2438 | struct intel_sdvo_enhancements_reply sdvo_data; | |
2439 | struct drm_device *dev = connector->dev; | |
2440 | uint8_t status; | |
2441 | uint16_t response, data_value[2]; | |
2442 | ||
2443 | intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, | |
2444 | NULL, 0); | |
2445 | status = intel_sdvo_read_response(intel_output, &sdvo_data, | |
2446 | sizeof(sdvo_data)); | |
2447 | if (status != SDVO_CMD_STATUS_SUCCESS) { | |
2448 | DRM_DEBUG_KMS(" incorrect response is returned\n"); | |
2449 | return; | |
2450 | } | |
2451 | response = *((uint16_t *)&sdvo_data); | |
2452 | if (!response) { | |
2453 | DRM_DEBUG_KMS("No enhancement is supported\n"); | |
2454 | return; | |
2455 | } | |
2456 | if (sdvo_priv->is_tv) { | |
2457 | /* when horizontal overscan is supported, Add the left/right | |
2458 | * property | |
2459 | */ | |
2460 | if (sdvo_data.overscan_h) { | |
2461 | intel_sdvo_write_cmd(intel_output, | |
2462 | SDVO_CMD_GET_MAX_OVERSCAN_H, NULL, 0); | |
2463 | status = intel_sdvo_read_response(intel_output, | |
2464 | &data_value, 4); | |
2465 | if (status != SDVO_CMD_STATUS_SUCCESS) { | |
2466 | DRM_DEBUG_KMS("Incorrect SDVO max " | |
2467 | "h_overscan\n"); | |
2468 | return; | |
2469 | } | |
2470 | intel_sdvo_write_cmd(intel_output, | |
2471 | SDVO_CMD_GET_OVERSCAN_H, NULL, 0); | |
2472 | status = intel_sdvo_read_response(intel_output, | |
2473 | &response, 2); | |
2474 | if (status != SDVO_CMD_STATUS_SUCCESS) { | |
2475 | DRM_DEBUG_KMS("Incorrect SDVO h_overscan\n"); | |
2476 | return; | |
2477 | } | |
2478 | sdvo_priv->max_hscan = data_value[0]; | |
2479 | sdvo_priv->left_margin = data_value[0] - response; | |
2480 | sdvo_priv->right_margin = sdvo_priv->left_margin; | |
2481 | sdvo_priv->left_property = | |
2482 | drm_property_create(dev, DRM_MODE_PROP_RANGE, | |
2483 | "left_margin", 2); | |
2484 | sdvo_priv->left_property->values[0] = 0; | |
2485 | sdvo_priv->left_property->values[1] = data_value[0]; | |
2486 | drm_connector_attach_property(connector, | |
2487 | sdvo_priv->left_property, | |
2488 | sdvo_priv->left_margin); | |
2489 | sdvo_priv->right_property = | |
2490 | drm_property_create(dev, DRM_MODE_PROP_RANGE, | |
2491 | "right_margin", 2); | |
2492 | sdvo_priv->right_property->values[0] = 0; | |
2493 | sdvo_priv->right_property->values[1] = data_value[0]; | |
2494 | drm_connector_attach_property(connector, | |
2495 | sdvo_priv->right_property, | |
2496 | sdvo_priv->right_margin); | |
2497 | DRM_DEBUG_KMS("h_overscan: max %d, " | |
2498 | "default %d, current %d\n", | |
2499 | data_value[0], data_value[1], response); | |
2500 | } | |
2501 | if (sdvo_data.overscan_v) { | |
2502 | intel_sdvo_write_cmd(intel_output, | |
2503 | SDVO_CMD_GET_MAX_OVERSCAN_V, NULL, 0); | |
2504 | status = intel_sdvo_read_response(intel_output, | |
2505 | &data_value, 4); | |
2506 | if (status != SDVO_CMD_STATUS_SUCCESS) { | |
2507 | DRM_DEBUG_KMS("Incorrect SDVO max " | |
2508 | "v_overscan\n"); | |
2509 | return; | |
2510 | } | |
2511 | intel_sdvo_write_cmd(intel_output, | |
2512 | SDVO_CMD_GET_OVERSCAN_V, NULL, 0); | |
2513 | status = intel_sdvo_read_response(intel_output, | |
2514 | &response, 2); | |
2515 | if (status != SDVO_CMD_STATUS_SUCCESS) { | |
2516 | DRM_DEBUG_KMS("Incorrect SDVO v_overscan\n"); | |
2517 | return; | |
2518 | } | |
2519 | sdvo_priv->max_vscan = data_value[0]; | |
2520 | sdvo_priv->top_margin = data_value[0] - response; | |
2521 | sdvo_priv->bottom_margin = sdvo_priv->top_margin; | |
2522 | sdvo_priv->top_property = | |
2523 | drm_property_create(dev, DRM_MODE_PROP_RANGE, | |
2524 | "top_margin", 2); | |
2525 | sdvo_priv->top_property->values[0] = 0; | |
2526 | sdvo_priv->top_property->values[1] = data_value[0]; | |
2527 | drm_connector_attach_property(connector, | |
2528 | sdvo_priv->top_property, | |
2529 | sdvo_priv->top_margin); | |
2530 | sdvo_priv->bottom_property = | |
2531 | drm_property_create(dev, DRM_MODE_PROP_RANGE, | |
2532 | "bottom_margin", 2); | |
2533 | sdvo_priv->bottom_property->values[0] = 0; | |
2534 | sdvo_priv->bottom_property->values[1] = data_value[0]; | |
2535 | drm_connector_attach_property(connector, | |
2536 | sdvo_priv->bottom_property, | |
2537 | sdvo_priv->bottom_margin); | |
2538 | DRM_DEBUG_KMS("v_overscan: max %d, " | |
2539 | "default %d, current %d\n", | |
2540 | data_value[0], data_value[1], response); | |
2541 | } | |
2542 | if (sdvo_data.position_h) { | |
2543 | intel_sdvo_write_cmd(intel_output, | |
2544 | SDVO_CMD_GET_MAX_POSITION_H, NULL, 0); | |
2545 | status = intel_sdvo_read_response(intel_output, | |
2546 | &data_value, 4); | |
2547 | if (status != SDVO_CMD_STATUS_SUCCESS) { | |
2548 | DRM_DEBUG_KMS("Incorrect SDVO Max h_pos\n"); | |
2549 | return; | |
2550 | } | |
2551 | intel_sdvo_write_cmd(intel_output, | |
2552 | SDVO_CMD_GET_POSITION_H, NULL, 0); | |
2553 | status = intel_sdvo_read_response(intel_output, | |
2554 | &response, 2); | |
2555 | if (status != SDVO_CMD_STATUS_SUCCESS) { | |
2556 | DRM_DEBUG_KMS("Incorrect SDVO get h_postion\n"); | |
2557 | return; | |
2558 | } | |
2559 | sdvo_priv->max_hpos = data_value[0]; | |
2560 | sdvo_priv->cur_hpos = response; | |
2561 | sdvo_priv->hpos_property = | |
2562 | drm_property_create(dev, DRM_MODE_PROP_RANGE, | |
2563 | "hpos", 2); | |
2564 | sdvo_priv->hpos_property->values[0] = 0; | |
2565 | sdvo_priv->hpos_property->values[1] = data_value[0]; | |
2566 | drm_connector_attach_property(connector, | |
2567 | sdvo_priv->hpos_property, | |
2568 | sdvo_priv->cur_hpos); | |
2569 | DRM_DEBUG_KMS("h_position: max %d, " | |
2570 | "default %d, current %d\n", | |
2571 | data_value[0], data_value[1], response); | |
2572 | } | |
2573 | if (sdvo_data.position_v) { | |
2574 | intel_sdvo_write_cmd(intel_output, | |
2575 | SDVO_CMD_GET_MAX_POSITION_V, NULL, 0); | |
2576 | status = intel_sdvo_read_response(intel_output, | |
2577 | &data_value, 4); | |
2578 | if (status != SDVO_CMD_STATUS_SUCCESS) { | |
2579 | DRM_DEBUG_KMS("Incorrect SDVO Max v_pos\n"); | |
2580 | return; | |
2581 | } | |
2582 | intel_sdvo_write_cmd(intel_output, | |
2583 | SDVO_CMD_GET_POSITION_V, NULL, 0); | |
2584 | status = intel_sdvo_read_response(intel_output, | |
2585 | &response, 2); | |
2586 | if (status != SDVO_CMD_STATUS_SUCCESS) { | |
2587 | DRM_DEBUG_KMS("Incorrect SDVO get v_postion\n"); | |
2588 | return; | |
2589 | } | |
2590 | sdvo_priv->max_vpos = data_value[0]; | |
2591 | sdvo_priv->cur_vpos = response; | |
2592 | sdvo_priv->vpos_property = | |
2593 | drm_property_create(dev, DRM_MODE_PROP_RANGE, | |
2594 | "vpos", 2); | |
2595 | sdvo_priv->vpos_property->values[0] = 0; | |
2596 | sdvo_priv->vpos_property->values[1] = data_value[0]; | |
2597 | drm_connector_attach_property(connector, | |
2598 | sdvo_priv->vpos_property, | |
2599 | sdvo_priv->cur_vpos); | |
2600 | DRM_DEBUG_KMS("v_position: max %d, " | |
2601 | "default %d, current %d\n", | |
2602 | data_value[0], data_value[1], response); | |
2603 | } | |
2604 | } | |
2605 | if (sdvo_priv->is_tv) { | |
2606 | if (sdvo_data.saturation) { | |
2607 | intel_sdvo_write_cmd(intel_output, | |
2608 | SDVO_CMD_GET_MAX_SATURATION, NULL, 0); | |
2609 | status = intel_sdvo_read_response(intel_output, | |
2610 | &data_value, 4); | |
2611 | if (status != SDVO_CMD_STATUS_SUCCESS) { | |
2612 | DRM_DEBUG_KMS("Incorrect SDVO Max sat\n"); | |
2613 | return; | |
2614 | } | |
2615 | intel_sdvo_write_cmd(intel_output, | |
2616 | SDVO_CMD_GET_SATURATION, NULL, 0); | |
2617 | status = intel_sdvo_read_response(intel_output, | |
2618 | &response, 2); | |
2619 | if (status != SDVO_CMD_STATUS_SUCCESS) { | |
2620 | DRM_DEBUG_KMS("Incorrect SDVO get sat\n"); | |
2621 | return; | |
2622 | } | |
2623 | sdvo_priv->max_saturation = data_value[0]; | |
2624 | sdvo_priv->cur_saturation = response; | |
2625 | sdvo_priv->saturation_property = | |
2626 | drm_property_create(dev, DRM_MODE_PROP_RANGE, | |
2627 | "saturation", 2); | |
2628 | sdvo_priv->saturation_property->values[0] = 0; | |
2629 | sdvo_priv->saturation_property->values[1] = | |
2630 | data_value[0]; | |
2631 | drm_connector_attach_property(connector, | |
2632 | sdvo_priv->saturation_property, | |
2633 | sdvo_priv->cur_saturation); | |
2634 | DRM_DEBUG_KMS("saturation: max %d, " | |
2635 | "default %d, current %d\n", | |
2636 | data_value[0], data_value[1], response); | |
2637 | } | |
2638 | if (sdvo_data.contrast) { | |
2639 | intel_sdvo_write_cmd(intel_output, | |
2640 | SDVO_CMD_GET_MAX_CONTRAST, NULL, 0); | |
2641 | status = intel_sdvo_read_response(intel_output, | |
2642 | &data_value, 4); | |
2643 | if (status != SDVO_CMD_STATUS_SUCCESS) { | |
2644 | DRM_DEBUG_KMS("Incorrect SDVO Max contrast\n"); | |
2645 | return; | |
2646 | } | |
2647 | intel_sdvo_write_cmd(intel_output, | |
2648 | SDVO_CMD_GET_CONTRAST, NULL, 0); | |
2649 | status = intel_sdvo_read_response(intel_output, | |
2650 | &response, 2); | |
2651 | if (status != SDVO_CMD_STATUS_SUCCESS) { | |
2652 | DRM_DEBUG_KMS("Incorrect SDVO get contrast\n"); | |
2653 | return; | |
2654 | } | |
2655 | sdvo_priv->max_contrast = data_value[0]; | |
2656 | sdvo_priv->cur_contrast = response; | |
2657 | sdvo_priv->contrast_property = | |
2658 | drm_property_create(dev, DRM_MODE_PROP_RANGE, | |
2659 | "contrast", 2); | |
2660 | sdvo_priv->contrast_property->values[0] = 0; | |
2661 | sdvo_priv->contrast_property->values[1] = data_value[0]; | |
2662 | drm_connector_attach_property(connector, | |
2663 | sdvo_priv->contrast_property, | |
2664 | sdvo_priv->cur_contrast); | |
2665 | DRM_DEBUG_KMS("contrast: max %d, " | |
2666 | "default %d, current %d\n", | |
2667 | data_value[0], data_value[1], response); | |
2668 | } | |
2669 | if (sdvo_data.hue) { | |
2670 | intel_sdvo_write_cmd(intel_output, | |
2671 | SDVO_CMD_GET_MAX_HUE, NULL, 0); | |
2672 | status = intel_sdvo_read_response(intel_output, | |
2673 | &data_value, 4); | |
2674 | if (status != SDVO_CMD_STATUS_SUCCESS) { | |
2675 | DRM_DEBUG_KMS("Incorrect SDVO Max hue\n"); | |
2676 | return; | |
2677 | } | |
2678 | intel_sdvo_write_cmd(intel_output, | |
2679 | SDVO_CMD_GET_HUE, NULL, 0); | |
2680 | status = intel_sdvo_read_response(intel_output, | |
2681 | &response, 2); | |
2682 | if (status != SDVO_CMD_STATUS_SUCCESS) { | |
2683 | DRM_DEBUG_KMS("Incorrect SDVO get hue\n"); | |
2684 | return; | |
2685 | } | |
2686 | sdvo_priv->max_hue = data_value[0]; | |
2687 | sdvo_priv->cur_hue = response; | |
2688 | sdvo_priv->hue_property = | |
2689 | drm_property_create(dev, DRM_MODE_PROP_RANGE, | |
2690 | "hue", 2); | |
2691 | sdvo_priv->hue_property->values[0] = 0; | |
2692 | sdvo_priv->hue_property->values[1] = | |
2693 | data_value[0]; | |
2694 | drm_connector_attach_property(connector, | |
2695 | sdvo_priv->hue_property, | |
2696 | sdvo_priv->cur_hue); | |
2697 | DRM_DEBUG_KMS("hue: max %d, default %d, current %d\n", | |
2698 | data_value[0], data_value[1], response); | |
2699 | } | |
2700 | } | |
d0cbde93 | 2701 | if (sdvo_priv->is_tv || sdvo_priv->is_lvds) { |
b9219c5e ZY |
2702 | if (sdvo_data.brightness) { |
2703 | intel_sdvo_write_cmd(intel_output, | |
2704 | SDVO_CMD_GET_MAX_BRIGHTNESS, NULL, 0); | |
2705 | status = intel_sdvo_read_response(intel_output, | |
2706 | &data_value, 4); | |
2707 | if (status != SDVO_CMD_STATUS_SUCCESS) { | |
2708 | DRM_DEBUG_KMS("Incorrect SDVO Max bright\n"); | |
2709 | return; | |
2710 | } | |
2711 | intel_sdvo_write_cmd(intel_output, | |
2712 | SDVO_CMD_GET_BRIGHTNESS, NULL, 0); | |
2713 | status = intel_sdvo_read_response(intel_output, | |
2714 | &response, 2); | |
2715 | if (status != SDVO_CMD_STATUS_SUCCESS) { | |
2716 | DRM_DEBUG_KMS("Incorrect SDVO get brigh\n"); | |
2717 | return; | |
2718 | } | |
2719 | sdvo_priv->max_brightness = data_value[0]; | |
2720 | sdvo_priv->cur_brightness = response; | |
2721 | sdvo_priv->brightness_property = | |
2722 | drm_property_create(dev, DRM_MODE_PROP_RANGE, | |
2723 | "brightness", 2); | |
2724 | sdvo_priv->brightness_property->values[0] = 0; | |
2725 | sdvo_priv->brightness_property->values[1] = | |
2726 | data_value[0]; | |
2727 | drm_connector_attach_property(connector, | |
2728 | sdvo_priv->brightness_property, | |
2729 | sdvo_priv->cur_brightness); | |
2730 | DRM_DEBUG_KMS("brightness: max %d, " | |
2731 | "default %d, current %d\n", | |
2732 | data_value[0], data_value[1], response); | |
2733 | } | |
2734 | } | |
2735 | return; | |
2736 | } | |
2737 | ||
7d57382e | 2738 | bool intel_sdvo_init(struct drm_device *dev, int output_device) |
79e53945 | 2739 | { |
b01f2c3a | 2740 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 JB |
2741 | struct drm_connector *connector; |
2742 | struct intel_output *intel_output; | |
2743 | struct intel_sdvo_priv *sdvo_priv; | |
f9c10a9b | 2744 | |
79e53945 JB |
2745 | u8 ch[0x40]; |
2746 | int i; | |
79e53945 JB |
2747 | |
2748 | intel_output = kcalloc(sizeof(struct intel_output)+sizeof(struct intel_sdvo_priv), 1, GFP_KERNEL); | |
2749 | if (!intel_output) { | |
7d57382e | 2750 | return false; |
79e53945 JB |
2751 | } |
2752 | ||
79e53945 | 2753 | sdvo_priv = (struct intel_sdvo_priv *)(intel_output + 1); |
308cd3a2 KP |
2754 | sdvo_priv->output_device = output_device; |
2755 | ||
2756 | intel_output->dev_priv = sdvo_priv; | |
79e53945 JB |
2757 | intel_output->type = INTEL_OUTPUT_SDVO; |
2758 | ||
79e53945 | 2759 | /* setup the DDC bus. */ |
308cd3a2 KP |
2760 | if (output_device == SDVOB) |
2761 | intel_output->i2c_bus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOB"); | |
2762 | else | |
2763 | intel_output->i2c_bus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOC"); | |
2764 | ||
2765 | if (!intel_output->i2c_bus) | |
ad5b2a6d | 2766 | goto err_inteloutput; |
79e53945 | 2767 | |
308cd3a2 | 2768 | sdvo_priv->slave_addr = intel_sdvo_get_slave_addr(dev, output_device); |
79e53945 | 2769 | |
308cd3a2 KP |
2770 | /* Save the bit-banging i2c functionality for use by the DDC wrapper */ |
2771 | intel_sdvo_i2c_bit_algo.functionality = intel_output->i2c_bus->algo->functionality; | |
79e53945 | 2772 | |
79e53945 JB |
2773 | /* Read the regs to test if we can talk to the device */ |
2774 | for (i = 0; i < 0x40; i++) { | |
2775 | if (!intel_sdvo_read_byte(intel_output, i, &ch[i])) { | |
8a4c47f3 | 2776 | DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n", |
342dc382 | 2777 | output_device == SDVOB ? 'B' : 'C'); |
79e53945 JB |
2778 | goto err_i2c; |
2779 | } | |
2780 | } | |
2781 | ||
619ac3b7 | 2782 | /* setup the DDC bus. */ |
57cdaf90 | 2783 | if (output_device == SDVOB) { |
308cd3a2 | 2784 | intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOB DDC BUS"); |
57cdaf90 KP |
2785 | sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA, |
2786 | "SDVOB/VGA DDC BUS"); | |
b01f2c3a | 2787 | dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS; |
57cdaf90 | 2788 | } else { |
308cd3a2 | 2789 | intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOC DDC BUS"); |
57cdaf90 KP |
2790 | sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA, |
2791 | "SDVOC/VGA DDC BUS"); | |
b01f2c3a | 2792 | dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS; |
57cdaf90 | 2793 | } |
619ac3b7 | 2794 | |
308cd3a2 | 2795 | if (intel_output->ddc_bus == NULL) |
619ac3b7 ML |
2796 | goto err_i2c; |
2797 | ||
308cd3a2 KP |
2798 | /* Wrap with our custom algo which switches to DDC mode */ |
2799 | intel_output->ddc_bus->algo = &intel_sdvo_i2c_bit_algo; | |
619ac3b7 | 2800 | |
af901ca1 | 2801 | /* In default case sdvo lvds is false */ |
79e53945 JB |
2802 | intel_sdvo_get_capabilities(intel_output, &sdvo_priv->caps); |
2803 | ||
fb7a46f3 | 2804 | if (intel_sdvo_output_setup(intel_output, |
2805 | sdvo_priv->caps.output_flags) != true) { | |
51c8b407 | 2806 | DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n", |
fb7a46f3 | 2807 | output_device == SDVOB ? 'B' : 'C'); |
79e53945 JB |
2808 | goto err_i2c; |
2809 | } | |
2810 | ||
fb7a46f3 | 2811 | |
ad5b2a6d JB |
2812 | connector = &intel_output->base; |
2813 | drm_connector_init(dev, connector, &intel_sdvo_connector_funcs, | |
fb7a46f3 | 2814 | connector->connector_type); |
2815 | ||
ad5b2a6d JB |
2816 | drm_connector_helper_add(connector, &intel_sdvo_connector_helper_funcs); |
2817 | connector->interlace_allowed = 0; | |
2818 | connector->doublescan_allowed = 0; | |
2819 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; | |
2820 | ||
fb7a46f3 | 2821 | drm_encoder_init(dev, &intel_output->enc, |
2822 | &intel_sdvo_enc_funcs, intel_output->enc.encoder_type); | |
2823 | ||
79e53945 | 2824 | drm_encoder_helper_add(&intel_output->enc, &intel_sdvo_helper_funcs); |
79e53945 JB |
2825 | |
2826 | drm_mode_connector_attach_encoder(&intel_output->base, &intel_output->enc); | |
d0cbde93 | 2827 | if (sdvo_priv->is_tv) |
ce6feabd | 2828 | intel_sdvo_tv_create_property(connector); |
d0cbde93 ZY |
2829 | |
2830 | if (sdvo_priv->is_tv || sdvo_priv->is_lvds) | |
b9219c5e | 2831 | intel_sdvo_create_enhance_property(connector); |
d0cbde93 | 2832 | |
79e53945 JB |
2833 | drm_sysfs_connector_add(connector); |
2834 | ||
e2f0ba97 JB |
2835 | intel_sdvo_select_ddc_bus(sdvo_priv); |
2836 | ||
79e53945 JB |
2837 | /* Set the input timing to the screen. Assume always input 0. */ |
2838 | intel_sdvo_set_target_input(intel_output, true, false); | |
2839 | ||
2840 | intel_sdvo_get_input_pixel_clock_range(intel_output, | |
2841 | &sdvo_priv->pixel_clock_min, | |
2842 | &sdvo_priv->pixel_clock_max); | |
2843 | ||
2844 | ||
8a4c47f3 | 2845 | DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, " |
342dc382 | 2846 | "clock range %dMHz - %dMHz, " |
2847 | "input 1: %c, input 2: %c, " | |
2848 | "output 1: %c, output 2: %c\n", | |
2849 | SDVO_NAME(sdvo_priv), | |
2850 | sdvo_priv->caps.vendor_id, sdvo_priv->caps.device_id, | |
2851 | sdvo_priv->caps.device_rev_id, | |
2852 | sdvo_priv->pixel_clock_min / 1000, | |
2853 | sdvo_priv->pixel_clock_max / 1000, | |
2854 | (sdvo_priv->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N', | |
2855 | (sdvo_priv->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N', | |
2856 | /* check currently supported outputs */ | |
2857 | sdvo_priv->caps.output_flags & | |
79e53945 | 2858 | (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N', |
342dc382 | 2859 | sdvo_priv->caps.output_flags & |
79e53945 JB |
2860 | (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N'); |
2861 | ||
7d57382e | 2862 | return true; |
79e53945 JB |
2863 | |
2864 | err_i2c: | |
57cdaf90 KP |
2865 | if (sdvo_priv->analog_ddc_bus != NULL) |
2866 | intel_i2c_destroy(sdvo_priv->analog_ddc_bus); | |
308cd3a2 | 2867 | if (intel_output->ddc_bus != NULL) |
619ac3b7 | 2868 | intel_i2c_destroy(intel_output->ddc_bus); |
308cd3a2 KP |
2869 | if (intel_output->i2c_bus != NULL) |
2870 | intel_i2c_destroy(intel_output->i2c_bus); | |
ad5b2a6d | 2871 | err_inteloutput: |
79e53945 JB |
2872 | kfree(intel_output); |
2873 | ||
7d57382e | 2874 | return false; |
79e53945 | 2875 | } |