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drm/i915: add tons of modeset state checks
[linux-block.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
79e53945 30#include <linux/delay.h>
2d1a8a48 31#include <linux/export.h>
79e53945
JB		 32#include "drmP.h"
33#include "drm.h"
34#include "drm_crtc.h"
2b8d33f7 35#include "drm_edid.h"
ea5b213a 36#include "intel_drv.h"
79e53945
JB		 37#include "i915_drm.h"
38#include "i915_drv.h"
39#include "intel_sdvo_regs.h"
40
14571b4c
ZW		 41#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
42#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
43#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
a0b1c7a5 44#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
14571b4c
ZW		 45
46#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
0206e353 47 SDVO_TV_MASK)
14571b4c
ZW		 48
49#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
13946743 50#define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
14571b4c 51#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
32aad86f 52#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
52220085 53#define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
14571b4c 54
79e53945 55
2e88e40b 56static const char *tv_format_names[] = {
ce6feabd
ZY		 57 "NTSC_M" , "NTSC_J" , "NTSC_443",
58 "PAL_B" , "PAL_D" , "PAL_G" ,
59 "PAL_H" , "PAL_I" , "PAL_M" ,
60 "PAL_N" , "PAL_NC" , "PAL_60" ,
61 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
62 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
63 "SECAM_60"
64};
65
66#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
67
ea5b213a
CW		 68struct intel_sdvo {
69 struct intel_encoder base;
70
f899fc64 71 struct i2c_adapter *i2c;
f9c10a9b 72 u8 slave_addr;
e2f0ba97 73
e957d772
CW		 74 struct i2c_adapter ddc;
75
e2f0ba97 76 /* Register for the SDVO device: SDVOB or SDVOC */
eef4eacb 77 uint32_t sdvo_reg;
79e53945 78
e2f0ba97
JB		 79 /* Active outputs controlled by this SDVO output */
80 uint16_t controlled_output;
79e53945 81
e2f0ba97
JB		 82 /*
83 * Capabilities of the SDVO device returned by
84 * i830_sdvo_get_capabilities()
85 */
79e53945 86 struct intel_sdvo_caps caps;
e2f0ba97
JB		 87
88 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 89 int pixel_clock_min, pixel_clock_max;
90
fb7a46f3 91 /*
92 * For multiple function SDVO device,
93 * this is for current attached outputs.
94 */
95 uint16_t attached_output;
96
cc68c81a
SF		 97 /*
98 * Hotplug activation bits for this device
99 */
100 uint8_t hotplug_active[2];
101
e953fd7b
CW		 102 /**
103 * This is used to select the color range of RBG outputs in HDMI mode.
104 * It is only valid when using TMDS encoding and 8 bit per color mode.
105 */
106 uint32_t color_range;
107
e2f0ba97
JB		 108 /**
109 * This is set if we're going to treat the device as TV-out.
110 *
111 * While we have these nice friendly flags for output types that ought
112 * to decide this for us, the S-Video output on our HDMI+S-Video card
113 * shows up as RGB1 (VGA).
114 */
115 bool is_tv;
116
eef4eacb
DV		 117 /* On different gens SDVOB is at different places. */
118 bool is_sdvob;
119
ce6feabd 120 /* This is for current tv format name */
40039750 121 int tv_format_index;
ce6feabd 122
e2f0ba97
JB		 123 /**
124 * This is set if we treat the device as HDMI, instead of DVI.
125 */
126 bool is_hdmi;
da79de97
CW		 127 bool has_hdmi_monitor;
128 bool has_hdmi_audio;
12682a97 129
7086c87f 130 /**
6c9547ff
CW		 131 * This is set if we detect output of sdvo device as LVDS and
132 * have a valid fixed mode to use with the panel.
7086c87f
ML		 133 */
134 bool is_lvds;
e2f0ba97 135
12682a97 136 /**
137 * This is sdvo fixed pannel mode pointer
138 */
139 struct drm_display_mode *sdvo_lvds_fixed_mode;
140
c751ce4f 141 /* DDC bus used by this SDVO encoder */
e2f0ba97 142 uint8_t ddc_bus;
14571b4c
ZW		 143};
144
145struct intel_sdvo_connector {
615fb93f
CW		 146 struct intel_connector base;
147
14571b4c
ZW		 148 /* Mark the type of connector */
149 uint16_t output_flag;
150
c3e5f67b 151 enum hdmi_force_audio force_audio;
7f36e7ed 152
14571b4c 153 /* This contains all current supported TV format */
40039750 154 u8 tv_format_supported[TV_FORMAT_NUM];
14571b4c 155 int format_supported_num;
c5521706 156 struct drm_property *tv_format;
14571b4c 157
b9219c5e 158 /* add the property for the SDVO-TV */
c5521706
CW		 159 struct drm_property *left;
160 struct drm_property *right;
161 struct drm_property *top;
162 struct drm_property *bottom;
163 struct drm_property *hpos;
164 struct drm_property *vpos;
165 struct drm_property *contrast;
166 struct drm_property *saturation;
167 struct drm_property *hue;
168 struct drm_property *sharpness;
169 struct drm_property *flicker_filter;
170 struct drm_property *flicker_filter_adaptive;
171 struct drm_property *flicker_filter_2d;
172 struct drm_property *tv_chroma_filter;
173 struct drm_property *tv_luma_filter;
e044218a 174 struct drm_property *dot_crawl;
b9219c5e
ZY		 175
176 /* add the property for the SDVO-TV/LVDS */
c5521706 177 struct drm_property *brightness;
b9219c5e
ZY		 178
179 /* Add variable to record current setting for the above property */
180 u32 left_margin, right_margin, top_margin, bottom_margin;
c5521706 181
b9219c5e
ZY		 182 /* this is to get the range of margin.*/
183 u32 max_hscan, max_vscan;
184 u32 max_hpos, cur_hpos;
185 u32 max_vpos, cur_vpos;
186 u32 cur_brightness, max_brightness;
187 u32 cur_contrast, max_contrast;
188 u32 cur_saturation, max_saturation;
189 u32 cur_hue, max_hue;
c5521706
CW		 190 u32 cur_sharpness, max_sharpness;
191 u32 cur_flicker_filter, max_flicker_filter;
192 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
193 u32 cur_flicker_filter_2d, max_flicker_filter_2d;
194 u32 cur_tv_chroma_filter, max_tv_chroma_filter;
195 u32 cur_tv_luma_filter, max_tv_luma_filter;
e044218a 196 u32 cur_dot_crawl, max_dot_crawl;
79e53945
JB		 197};
198
890f3359 199static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder)
ea5b213a 200{
4ef69c7a 201 return container_of(encoder, struct intel_sdvo, base.base);
ea5b213a
CW		 202}
203
df0e9248
CW		 204static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
205{
206 return container_of(intel_attached_encoder(connector),
207 struct intel_sdvo, base);
208}
209
615fb93f
CW		 210static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
211{
212 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
213}
214
fb7a46f3 215static bool
ea5b213a 216intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
32aad86f
CW		 217static bool
218intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
219 struct intel_sdvo_connector *intel_sdvo_connector,
220 int type);
221static bool
222intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
223 struct intel_sdvo_connector *intel_sdvo_connector);
fb7a46f3 224
79e53945
JB		 225/**
226 * Writes the SDVOB or SDVOC with the given value, but always writes both
227 * SDVOB and SDVOC to work around apparent hardware issues (according to
228 * comments in the BIOS).
229 */
ea5b213a 230static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
79e53945 231{
4ef69c7a 232 struct drm_device *dev = intel_sdvo->base.base.dev;
79e53945 233 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 234 u32 bval = val, cval = val;
235 int i;
236
ea5b213a
CW		 237 if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
238 I915_WRITE(intel_sdvo->sdvo_reg, val);
239 I915_READ(intel_sdvo->sdvo_reg);
461ed3ca
ZY		 240 return;
241 }
242
ea5b213a 243 if (intel_sdvo->sdvo_reg == SDVOB) {
79e53945
JB		 244 cval = I915_READ(SDVOC);
245 } else {
246 bval = I915_READ(SDVOB);
247 }
248 /*
249 * Write the registers twice for luck. Sometimes,
250 * writing them only once doesn't appear to 'stick'.
251 * The BIOS does this too. Yay, magic
252 */
253 for (i = 0; i < 2; i++)
254 {
255 I915_WRITE(SDVOB, bval);
256 I915_READ(SDVOB);
257 I915_WRITE(SDVOC, cval);
258 I915_READ(SDVOC);
259 }
260}
261
32aad86f 262static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
79e53945 263{
79e53945
JB		 264 struct i2c_msg msgs[] = {
265 {
e957d772 266 .addr = intel_sdvo->slave_addr,
79e53945
JB		 267 .flags = 0,
268 .len = 1,
e957d772 269 .buf = &addr,
79e53945
JB		 270 },
271 {
e957d772 272 .addr = intel_sdvo->slave_addr,
79e53945
JB		 273 .flags = I2C_M_RD,
274 .len = 1,
e957d772 275 .buf = ch,
79e53945
JB		 276 }
277 };
32aad86f 278 int ret;
79e53945 279
f899fc64 280 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
79e53945 281 return true;
79e53945 282
8a4c47f3 283 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 284 return false;
285}
286
79e53945
JB		 287#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
288/** Mapping of command numbers to names, for debug output */
005568be 289static const struct _sdvo_cmd_name {
e2f0ba97 290 u8 cmd;
2e88e40b 291 const char *name;
79e53945 292} sdvo_cmd_names[] = {
0206e353
AJ		 293 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
294 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
295 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
296 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
297 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
336
337 /* Add the op code for SDVO enhancements */
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
382
383 /* HDMI op code */
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 404};
405
eef4eacb 406#define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC")
79e53945 407
ea5b213a 408static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
32aad86f 409 const void *args, int args_len)
79e53945 410{
79e53945
JB		 411 int i;
412
8a4c47f3 413 DRM_DEBUG_KMS("%s: W: %02X ",
ea5b213a 414 SDVO_NAME(intel_sdvo), cmd);
79e53945 415 for (i = 0; i < args_len; i++)
342dc382 416 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
79e53945 417 for (; i < 8; i++)
342dc382 418 DRM_LOG_KMS(" ");
04ad327f 419 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
79e53945 420 if (cmd == sdvo_cmd_names[i].cmd) {
342dc382 421 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 422 break;
423 }
424 }
04ad327f 425 if (i == ARRAY_SIZE(sdvo_cmd_names))
342dc382 426 DRM_LOG_KMS("(%02X)", cmd);
427 DRM_LOG_KMS("\n");
79e53945 428}
79e53945 429
e957d772
CW		 430static const char *cmd_status_names[] = {
431 "Power on",
432 "Success",
433 "Not supported",
434 "Invalid arg",
435 "Pending",
436 "Target not specified",
437 "Scaling not supported"
438};
439
32aad86f
CW		 440static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
441 const void *args, int args_len)
79e53945 442{
3bf3f452
BW		 443 u8 *buf, status;
444 struct i2c_msg *msgs;
445 int i, ret = true;
446
0274df3e 447 /* Would be simpler to allocate both in one go ? */
3bf3f452
BW		 448 buf = (u8 *)kzalloc(args_len * 2 + 2, GFP_KERNEL);
449 if (!buf)
450 return false;
451
452 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
0274df3e
AC		 453 if (!msgs) {
454 kfree(buf);
3bf3f452 455 return false;
0274df3e 456 }
79e53945 457
ea5b213a 458 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
79e53945
JB		 459
460 for (i = 0; i < args_len; i++) {
e957d772
CW		 461 msgs[i].addr = intel_sdvo->slave_addr;
462 msgs[i].flags = 0;
463 msgs[i].len = 2;
464 msgs[i].buf = buf + 2 *i;
465 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
466 buf[2*i + 1] = ((u8*)args)[i];
467 }
468 msgs[i].addr = intel_sdvo->slave_addr;
469 msgs[i].flags = 0;
470 msgs[i].len = 2;
471 msgs[i].buf = buf + 2*i;
472 buf[2*i + 0] = SDVO_I2C_OPCODE;
473 buf[2*i + 1] = cmd;
474
475 /* the following two are to read the response */
476 status = SDVO_I2C_CMD_STATUS;
477 msgs[i+1].addr = intel_sdvo->slave_addr;
478 msgs[i+1].flags = 0;
479 msgs[i+1].len = 1;
480 msgs[i+1].buf = &status;
481
482 msgs[i+2].addr = intel_sdvo->slave_addr;
483 msgs[i+2].flags = I2C_M_RD;
484 msgs[i+2].len = 1;
485 msgs[i+2].buf = &status;
486
487 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
488 if (ret < 0) {
489 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
3bf3f452
BW		 490 ret = false;
491 goto out;
e957d772
CW		 492 }
493 if (ret != i+3) {
494 /* failure in I2C transfer */
495 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
3bf3f452 496 ret = false;
e957d772
CW		 497 }
498
3bf3f452
BW		 499out:
500 kfree(msgs);
501 kfree(buf);
502 return ret;
79e53945
JB		 503}
504
b5c616a7
CW		 505static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
506 void *response, int response_len)
79e53945 507{
b5c616a7
CW		 508 u8 retry = 5;
509 u8 status;
33b52961 510 int i;
79e53945 511
d121a5d2
CW		 512 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
513
b5c616a7
CW		 514 /*
515 * The documentation states that all commands will be
516 * processed within 15µs, and that we need only poll
517 * the status byte a maximum of 3 times in order for the
518 * command to be complete.
519 *
520 * Check 5 times in case the hardware failed to read the docs.
521 */
d121a5d2
CW		 522 if (!intel_sdvo_read_byte(intel_sdvo,
523 SDVO_I2C_CMD_STATUS,
524 &status))
525 goto log_fail;
526
527 while (status == SDVO_CMD_STATUS_PENDING && retry--) {
528 udelay(15);
b5c616a7
CW		 529 if (!intel_sdvo_read_byte(intel_sdvo,
530 SDVO_I2C_CMD_STATUS,
531 &status))
d121a5d2
CW		 532 goto log_fail;
533 }
b5c616a7 534
79e53945 535 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
342dc382 536 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
79e53945 537 else
342dc382 538 DRM_LOG_KMS("(??? %d)", status);
79e53945 539
b5c616a7
CW		 540 if (status != SDVO_CMD_STATUS_SUCCESS)
541 goto log_fail;
79e53945 542
b5c616a7
CW		 543 /* Read the command response */
544 for (i = 0; i < response_len; i++) {
545 if (!intel_sdvo_read_byte(intel_sdvo,
546 SDVO_I2C_RETURN_0 + i,
547 &((u8 *)response)[i]))
548 goto log_fail;
e957d772 549 DRM_LOG_KMS(" %02X", ((u8 *)response)[i]);
b5c616a7 550 }
b5c616a7 551 DRM_LOG_KMS("\n");
b5c616a7 552 return true;
79e53945 553
b5c616a7 554log_fail:
d121a5d2 555 DRM_LOG_KMS("... failed\n");
b5c616a7 556 return false;
79e53945
JB		 557}
558
b358d0a6 559static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
79e53945
JB		 560{
561 if (mode->clock >= 100000)
562 return 1;
563 else if (mode->clock >= 50000)
564 return 2;
565 else
566 return 4;
567}
568
e957d772
CW		 569static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
570 u8 ddc_bus)
79e53945 571{
d121a5d2 572 /* This must be the immediately preceding write before the i2c xfer */
e957d772
CW		 573 return intel_sdvo_write_cmd(intel_sdvo,
574 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
575 &ddc_bus, 1);
79e53945
JB		 576}
577
32aad86f 578static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
79e53945 579{
d121a5d2
CW		 580 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
581 return false;
582
583 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
32aad86f 584}
79e53945 585
32aad86f
CW		 586static bool
587intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
588{
589 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
590 return false;
79e53945 591
32aad86f
CW		 592 return intel_sdvo_read_response(intel_sdvo, value, len);
593}
79e53945 594
32aad86f
CW		 595static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
596{
597 struct intel_sdvo_set_target_input_args targets = {0};
598 return intel_sdvo_set_value(intel_sdvo,
599 SDVO_CMD_SET_TARGET_INPUT,
600 &targets, sizeof(targets));
79e53945
JB		 601}
602
603/**
604 * Return whether each input is trained.
605 *
606 * This function is making an assumption about the layout of the response,
607 * which should be checked against the docs.
608 */
ea5b213a 609static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
79e53945
JB		 610{
611 struct intel_sdvo_get_trained_inputs_response response;
79e53945 612
1a3665c8 613 BUILD_BUG_ON(sizeof(response) != 1);
32aad86f
CW		 614 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
615 &response, sizeof(response)))
79e53945
JB		 616 return false;
617
618 *input_1 = response.input0_trained;
619 *input_2 = response.input1_trained;
620 return true;
621}
622
ea5b213a 623static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
79e53945
JB		 624 u16 outputs)
625{
32aad86f
CW		 626 return intel_sdvo_set_value(intel_sdvo,
627 SDVO_CMD_SET_ACTIVE_OUTPUTS,
628 &outputs, sizeof(outputs));
79e53945
JB		 629}
630
4ac41f47
DV		 631static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo,
632 u16 *outputs)
633{
634 return intel_sdvo_get_value(intel_sdvo,
635 SDVO_CMD_GET_ACTIVE_OUTPUTS,
636 outputs, sizeof(*outputs));
637}
638
ea5b213a 639static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
79e53945
JB		 640 int mode)
641{
32aad86f 642 u8 state = SDVO_ENCODER_STATE_ON;
79e53945
JB		 643
644 switch (mode) {
645 case DRM_MODE_DPMS_ON:
646 state = SDVO_ENCODER_STATE_ON;
647 break;
648 case DRM_MODE_DPMS_STANDBY:
649 state = SDVO_ENCODER_STATE_STANDBY;
650 break;
651 case DRM_MODE_DPMS_SUSPEND:
652 state = SDVO_ENCODER_STATE_SUSPEND;
653 break;
654 case DRM_MODE_DPMS_OFF:
655 state = SDVO_ENCODER_STATE_OFF;
656 break;
657 }
658
32aad86f
CW		 659 return intel_sdvo_set_value(intel_sdvo,
660 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
79e53945
JB		 661}
662
ea5b213a 663static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
79e53945
JB		 664 int *clock_min,
665 int *clock_max)
666{
667 struct intel_sdvo_pixel_clock_range clocks;
79e53945 668
1a3665c8 669 BUILD_BUG_ON(sizeof(clocks) != 4);
32aad86f
CW		 670 if (!intel_sdvo_get_value(intel_sdvo,
671 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
672 &clocks, sizeof(clocks)))
79e53945
JB		 673 return false;
674
675 /* Convert the values from units of 10 kHz to kHz. */
676 *clock_min = clocks.min * 10;
677 *clock_max = clocks.max * 10;
79e53945
JB		 678 return true;
679}
680
ea5b213a 681static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
79e53945
JB		 682 u16 outputs)
683{
32aad86f
CW		 684 return intel_sdvo_set_value(intel_sdvo,
685 SDVO_CMD_SET_TARGET_OUTPUT,
686 &outputs, sizeof(outputs));
79e53945
JB		 687}
688
ea5b213a 689static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
79e53945
JB		 690 struct intel_sdvo_dtd *dtd)
691{
32aad86f
CW		 692 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
693 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
79e53945
JB		 694}
695
ea5b213a 696static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 697 struct intel_sdvo_dtd *dtd)
698{
ea5b213a 699 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 700 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
701}
702
ea5b213a 703static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 704 struct intel_sdvo_dtd *dtd)
705{
ea5b213a 706 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 707 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
708}
709
e2f0ba97 710static bool
ea5b213a 711intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 712 uint16_t clock,
713 uint16_t width,
714 uint16_t height)
715{
716 struct intel_sdvo_preferred_input_timing_args args;
e2f0ba97 717
e642c6f1 718 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 719 args.clock = clock;
720 args.width = width;
721 args.height = height;
e642c6f1 722 args.interlace = 0;
12682a97 723
ea5b213a
CW		 724 if (intel_sdvo->is_lvds &&
725 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
726 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
12682a97 727 args.scaled = 1;
728
32aad86f
CW		 729 return intel_sdvo_set_value(intel_sdvo,
730 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
731 &args, sizeof(args));
e2f0ba97
JB		 732}
733
ea5b213a 734static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 735 struct intel_sdvo_dtd *dtd)
736{
1a3665c8
CW		 737 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
738 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
32aad86f
CW		 739 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
740 &dtd->part1, sizeof(dtd->part1)) &&
741 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
742 &dtd->part2, sizeof(dtd->part2));
e2f0ba97 743}
79e53945 744
ea5b213a 745static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
79e53945 746{
32aad86f 747 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
79e53945
JB		 748}
749
e2f0ba97 750static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
32aad86f 751 const struct drm_display_mode *mode)
79e53945 752{
e2f0ba97
JB		 753 uint16_t width, height;
754 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
755 uint16_t h_sync_offset, v_sync_offset;
6651819b 756 int mode_clock;
79e53945 757
c6ebd4c0
DV		 758 width = mode->hdisplay;
759 height = mode->vdisplay;
79e53945
JB		 760
761 /* do some mode translations */
c6ebd4c0
DV		 762 h_blank_len = mode->htotal - mode->hdisplay;
763 h_sync_len = mode->hsync_end - mode->hsync_start;
79e53945 764
c6ebd4c0
DV		 765 v_blank_len = mode->vtotal - mode->vdisplay;
766 v_sync_len = mode->vsync_end - mode->vsync_start;
79e53945 767
c6ebd4c0
DV		 768 h_sync_offset = mode->hsync_start - mode->hdisplay;
769 v_sync_offset = mode->vsync_start - mode->vdisplay;
79e53945 770
6651819b
DV		 771 mode_clock = mode->clock;
772 mode_clock /= intel_mode_get_pixel_multiplier(mode) ?: 1;
773 mode_clock /= 10;
774 dtd->part1.clock = mode_clock;
775
e2f0ba97
JB		 776 dtd->part1.h_active = width & 0xff;
777 dtd->part1.h_blank = h_blank_len & 0xff;
778 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 779 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 780 dtd->part1.v_active = height & 0xff;
781 dtd->part1.v_blank = v_blank_len & 0xff;
782 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 783 ((v_blank_len >> 8) & 0xf);
784
171a9e96 785 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 786 dtd->part2.h_sync_width = h_sync_len & 0xff;
787 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 788 (v_sync_len & 0xf);
e2f0ba97 789 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 790 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
791 ((v_sync_len & 0x30) >> 4);
792
e2f0ba97 793 dtd->part2.dtd_flags = 0x18;
59d92bfa
DV		 794 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
795 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
79e53945 796 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
59d92bfa 797 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
79e53945 798 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
59d92bfa 799 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
e2f0ba97
JB		 800
801 dtd->part2.sdvo_flags = 0;
802 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
803 dtd->part2.reserved = 0;
804}
805
806static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
32aad86f 807 const struct intel_sdvo_dtd *dtd)
e2f0ba97 808{
e2f0ba97
JB		 809 mode->hdisplay = dtd->part1.h_active;
810 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
811 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
171a9e96 812 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
e2f0ba97
JB		 813 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
814 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
815 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
816 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
817
818 mode->vdisplay = dtd->part1.v_active;
819 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
820 mode->vsync_start = mode->vdisplay;
821 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
171a9e96 822 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
e2f0ba97
JB		 823 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
824 mode->vsync_end = mode->vsync_start +
825 (dtd->part2.v_sync_off_width & 0xf);
826 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
827 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
828 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
829
830 mode->clock = dtd->part1.clock * 10;
831
171a9e96 832 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
59d92bfa
DV		 833 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
834 mode->flags |= DRM_MODE_FLAG_INTERLACE;
835 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
e2f0ba97 836 mode->flags |= DRM_MODE_FLAG_PHSYNC;
59d92bfa 837 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
e2f0ba97
JB		 838 mode->flags |= DRM_MODE_FLAG_PVSYNC;
839}
840
e27d8538 841static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
e2f0ba97 842{
e27d8538 843 struct intel_sdvo_encode encode;
e2f0ba97 844
1a3665c8 845 BUILD_BUG_ON(sizeof(encode) != 2);
e27d8538
CW		 846 return intel_sdvo_get_value(intel_sdvo,
847 SDVO_CMD_GET_SUPP_ENCODE,
848 &encode, sizeof(encode));
e2f0ba97
JB		 849}
850
ea5b213a 851static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
c751ce4f 852 uint8_t mode)
e2f0ba97 853{
32aad86f 854 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
e2f0ba97
JB		 855}
856
ea5b213a 857static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 858 uint8_t mode)
859{
32aad86f 860 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
e2f0ba97
JB		 861}
862
863#if 0
ea5b213a 864static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 865{
866 int i, j;
867 uint8_t set_buf_index[2];
868 uint8_t av_split;
869 uint8_t buf_size;
870 uint8_t buf[48];
871 uint8_t *pos;
872
32aad86f 873 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
e2f0ba97
JB		 874
875 for (i = 0; i <= av_split; i++) {
876 set_buf_index[0] = i; set_buf_index[1] = 0;
c751ce4f 877 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
e2f0ba97 878 set_buf_index, 2);
c751ce4f
EA		 879 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
880 intel_sdvo_read_response(encoder, &buf_size, 1);
e2f0ba97
JB		 881
882 pos = buf;
883 for (j = 0; j <= buf_size; j += 8) {
c751ce4f 884 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
e2f0ba97 885 NULL, 0);
c751ce4f 886 intel_sdvo_read_response(encoder, pos, 8);
e2f0ba97
JB		 887 pos += 8;
888 }
889 }
890}
891#endif
892
3c17fe4b 893static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 894{
895 struct dip_infoframe avi_if = {
896 .type = DIP_TYPE_AVI,
3c17fe4b 897 .ver = DIP_VERSION_AVI,
e2f0ba97
JB		 898 .len = DIP_LEN_AVI,
899 };
3c17fe4b
DH		 900 uint8_t tx_rate = SDVO_HBUF_TX_VSYNC;
901 uint8_t set_buf_index[2] = { 1, 0 };
81014b9d
DV		 902 uint8_t sdvo_data[4 + sizeof(avi_if.body.avi)];
903 uint64_t *data = (uint64_t *)sdvo_data;
3c17fe4b
DH		 904 unsigned i;
905
906 intel_dip_infoframe_csum(&avi_if);
907
81014b9d
DV		 908 /* sdvo spec says that the ecc is handled by the hw, and it looks like
909 * we must not send the ecc field, either. */
910 memcpy(sdvo_data, &avi_if, 3);
911 sdvo_data[3] = avi_if.checksum;
912 memcpy(&sdvo_data[4], &avi_if.body, sizeof(avi_if.body.avi));
913
d121a5d2
CW		 914 if (!intel_sdvo_set_value(intel_sdvo,
915 SDVO_CMD_SET_HBUF_INDEX,
3c17fe4b
DH		 916 set_buf_index, 2))
917 return false;
918
81014b9d 919 for (i = 0; i < sizeof(sdvo_data); i += 8) {
d121a5d2
CW		 920 if (!intel_sdvo_set_value(intel_sdvo,
921 SDVO_CMD_SET_HBUF_DATA,
3c17fe4b
DH		 922 data, 8))
923 return false;
924 data++;
925 }
e2f0ba97 926
d121a5d2
CW		 927 return intel_sdvo_set_value(intel_sdvo,
928 SDVO_CMD_SET_HBUF_TXRATE,
3c17fe4b 929 &tx_rate, 1);
e2f0ba97
JB		 930}
931
32aad86f 932static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
7026d4ac 933{
ce6feabd 934 struct intel_sdvo_tv_format format;
40039750 935 uint32_t format_map;
ce6feabd 936
40039750 937 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 938 memset(&format, 0, sizeof(format));
32aad86f 939 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
ce6feabd 940
32aad86f
CW		 941 BUILD_BUG_ON(sizeof(format) != 6);
942 return intel_sdvo_set_value(intel_sdvo,
943 SDVO_CMD_SET_TV_FORMAT,
944 &format, sizeof(format));
7026d4ac
ZW		 945}
946
32aad86f
CW		 947static bool
948intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
e811f5ae 949 const struct drm_display_mode *mode)
e2f0ba97 950{
32aad86f 951 struct intel_sdvo_dtd output_dtd;
79e53945 952
32aad86f
CW		 953 if (!intel_sdvo_set_target_output(intel_sdvo,
954 intel_sdvo->attached_output))
955 return false;
e2f0ba97 956
32aad86f
CW		 957 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
958 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
959 return false;
e2f0ba97 960
32aad86f
CW		 961 return true;
962}
963
c9a29698
DV		 964/* Asks the sdvo controller for the preferred input mode given the output mode.
965 * Unfortunately we have to set up the full output mode to do that. */
32aad86f 966static bool
c9a29698 967intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
e811f5ae 968 const struct drm_display_mode *mode,
c9a29698 969 struct drm_display_mode *adjusted_mode)
32aad86f 970{
c9a29698
DV		 971 struct intel_sdvo_dtd input_dtd;
972
32aad86f
CW		 973 /* Reset the input timing to the screen. Assume always input 0. */
974 if (!intel_sdvo_set_target_input(intel_sdvo))
975 return false;
e2f0ba97 976
32aad86f
CW		 977 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
978 mode->clock / 10,
979 mode->hdisplay,
980 mode->vdisplay))
981 return false;
e2f0ba97 982
32aad86f 983 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
c9a29698 984 &input_dtd))
32aad86f 985 return false;
e2f0ba97 986
c9a29698 987 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
79e53945 988
32aad86f
CW		 989 return true;
990}
12682a97 991
32aad86f 992static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
e811f5ae 993 const struct drm_display_mode *mode,
32aad86f
CW		 994 struct drm_display_mode *adjusted_mode)
995{
890f3359 996 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
6c9547ff 997 int multiplier;
12682a97 998
32aad86f
CW		 999 /* We need to construct preferred input timings based on our
1000 * output timings. To do that, we have to set the output
1001 * timings, even though this isn't really the right place in
1002 * the sequence to do it. Oh well.
1003 */
1004 if (intel_sdvo->is_tv) {
1005 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
1006 return false;
12682a97 1007
c9a29698
DV		 1008 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1009 mode,
1010 adjusted_mode);
ea5b213a 1011 } else if (intel_sdvo->is_lvds) {
32aad86f 1012 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
6c9547ff 1013 intel_sdvo->sdvo_lvds_fixed_mode))
e2f0ba97 1014 return false;
12682a97 1015
c9a29698
DV		 1016 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1017 mode,
1018 adjusted_mode);
e2f0ba97 1019 }
32aad86f
CW		 1020
1021 /* Make the CRTC code factor in the SDVO pixel multiplier. The
6c9547ff 1022 * SDVO device will factor out the multiplier during mode_set.
32aad86f 1023 */
6c9547ff
CW		 1024 multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode);
1025 intel_mode_set_pixel_multiplier(adjusted_mode, multiplier);
32aad86f 1026
e2f0ba97
JB		 1027 return true;
1028}
1029
1030static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1031 struct drm_display_mode *mode,
1032 struct drm_display_mode *adjusted_mode)
1033{
1034 struct drm_device *dev = encoder->dev;
1035 struct drm_i915_private *dev_priv = dev->dev_private;
1036 struct drm_crtc *crtc = encoder->crtc;
1037 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
890f3359 1038 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
6c9547ff 1039 u32 sdvox;
e2f0ba97 1040 struct intel_sdvo_in_out_map in_out;
6651819b 1041 struct intel_sdvo_dtd input_dtd, output_dtd;
6c9547ff
CW		 1042 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
1043 int rate;
e2f0ba97
JB		 1044
1045 if (!mode)
1046 return;
1047
1048 /* First, set the input mapping for the first input to our controlled
1049 * output. This is only correct if we're a single-input device, in
1050 * which case the first input is the output from the appropriate SDVO
1051 * channel on the motherboard. In a two-input device, the first input
1052 * will be SDVOB and the second SDVOC.
1053 */
ea5b213a 1054 in_out.in0 = intel_sdvo->attached_output;
e2f0ba97
JB		 1055 in_out.in1 = 0;
1056
c74696b9
PR		 1057 intel_sdvo_set_value(intel_sdvo,
1058 SDVO_CMD_SET_IN_OUT_MAP,
1059 &in_out, sizeof(in_out));
e2f0ba97 1060
6c9547ff
CW		 1061 /* Set the output timings to the screen */
1062 if (!intel_sdvo_set_target_output(intel_sdvo,
1063 intel_sdvo->attached_output))
1064 return;
e2f0ba97 1065
6651819b
DV		 1066 /* lvds has a special fixed output timing. */
1067 if (intel_sdvo->is_lvds)
1068 intel_sdvo_get_dtd_from_mode(&output_dtd,
1069 intel_sdvo->sdvo_lvds_fixed_mode);
1070 else
1071 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
c8d4bb54
DV		 1072 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1073 DRM_INFO("Setting output timings on %s failed\n",
1074 SDVO_NAME(intel_sdvo));
79e53945
JB		 1075
1076 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 1077 if (!intel_sdvo_set_target_input(intel_sdvo))
1078 return;
79e53945 1079
97aaf910
CW		 1080 if (intel_sdvo->has_hdmi_monitor) {
1081 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1082 intel_sdvo_set_colorimetry(intel_sdvo,
1083 SDVO_COLORIMETRY_RGB256);
1084 intel_sdvo_set_avi_infoframe(intel_sdvo);
1085 } else
1086 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
7026d4ac 1087
6c9547ff
CW		 1088 if (intel_sdvo->is_tv &&
1089 !intel_sdvo_set_tv_format(intel_sdvo))
1090 return;
e2f0ba97 1091
6651819b
DV		 1092 /* We have tried to get input timing in mode_fixup, and filled into
1093 * adjusted_mode.
1094 */
1095 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
c8d4bb54
DV		 1096 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
1097 DRM_INFO("Setting input timings on %s failed\n",
1098 SDVO_NAME(intel_sdvo));
79e53945 1099
6c9547ff
CW		 1100 switch (pixel_multiplier) {
1101 default:
32aad86f
CW		 1102 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1103 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1104 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
79e53945 1105 }
32aad86f
CW		 1106 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1107 return;
79e53945
JB		 1108
1109 /* Set the SDVO control regs. */
a6c45cf0 1110 if (INTEL_INFO(dev)->gen >= 4) {
ba68e086
PZ		 1111 /* The real mode polarity is set by the SDVO commands, using
1112 * struct intel_sdvo_dtd. */
1113 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
e953fd7b
CW		 1114 if (intel_sdvo->is_hdmi)
1115 sdvox |= intel_sdvo->color_range;
6714afb1
CW		 1116 if (INTEL_INFO(dev)->gen < 5)
1117 sdvox |= SDVO_BORDER_ENABLE;
e2f0ba97 1118 } else {
6c9547ff 1119 sdvox = I915_READ(intel_sdvo->sdvo_reg);
ea5b213a 1120 switch (intel_sdvo->sdvo_reg) {
e2f0ba97
JB		 1121 case SDVOB:
1122 sdvox &= SDVOB_PRESERVE_MASK;
1123 break;
1124 case SDVOC:
1125 sdvox &= SDVOC_PRESERVE_MASK;
1126 break;
1127 }
1128 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1129 }
3573c410
PZ		 1130
1131 if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
1132 sdvox |= TRANSCODER_CPT(intel_crtc->pipe);
1133 else
1134 sdvox |= TRANSCODER(intel_crtc->pipe);
1135
da79de97 1136 if (intel_sdvo->has_hdmi_audio)
6c9547ff 1137 sdvox |= SDVO_AUDIO_ENABLE;
79e53945 1138
a6c45cf0 1139 if (INTEL_INFO(dev)->gen >= 4) {
e2f0ba97
JB		 1140 /* done in crtc_mode_set as the dpll_md reg must be written early */
1141 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1142 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945 1143 } else {
6c9547ff 1144 sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT;
79e53945
JB		 1145 }
1146
6714afb1
CW		 1147 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
1148 INTEL_INFO(dev)->gen < 5)
12682a97 1149 sdvox |= SDVO_STALL_SELECT;
ea5b213a 1150 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
79e53945
JB		 1151}
1152
4ac41f47
DV		 1153static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
1154{
1155 struct intel_sdvo_connector *intel_sdvo_connector =
1156 to_intel_sdvo_connector(&connector->base);
1157 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base);
1158 u16 active_outputs;
1159
1160 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1161
1162 if (active_outputs & intel_sdvo_connector->output_flag)
1163 return true;
1164 else
1165 return false;
1166}
1167
1168static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
1169 enum pipe *pipe)
1170{
1171 struct drm_device *dev = encoder->base.dev;
1172 struct drm_i915_private *dev_priv = dev->dev_private;
1173 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
1174 u32 tmp;
1175
1176 tmp = I915_READ(intel_sdvo->sdvo_reg);
1177
1178 if (!(tmp & SDVO_ENABLE))
1179 return false;
1180
1181 if (HAS_PCH_CPT(dev))
1182 *pipe = PORT_TO_PIPE_CPT(tmp);
1183 else
1184 *pipe = PORT_TO_PIPE(tmp);
1185
1186 return true;
1187}
1188
ce22c320
DV		 1189static void intel_disable_sdvo(struct intel_encoder *encoder)
1190{
1191 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1192 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
1193 u32 temp;
1194
1195 intel_sdvo_set_active_outputs(intel_sdvo, 0);
1196 if (0)
1197 intel_sdvo_set_encoder_power_state(intel_sdvo,
1198 DRM_MODE_DPMS_OFF);
1199
1200 temp = I915_READ(intel_sdvo->sdvo_reg);
1201 if ((temp & SDVO_ENABLE) != 0) {
1202 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
1203 }
1204}
1205
1206static void intel_enable_sdvo(struct intel_encoder *encoder)
1207{
1208 struct drm_device *dev = encoder->base.dev;
1209 struct drm_i915_private *dev_priv = dev->dev_private;
1210 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
1211 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1212 u32 temp;
1213 bool input1, input2;
1214 int i;
1215 u8 status;
1216
1217 temp = I915_READ(intel_sdvo->sdvo_reg);
1218 if ((temp & SDVO_ENABLE) == 0)
1219 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
1220 for (i = 0; i < 2; i++)
1221 intel_wait_for_vblank(dev, intel_crtc->pipe);
1222
1223 status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
1224 /* Warn if the device reported failure to sync.
1225 * A lot of SDVO devices fail to notify of sync, but it's
1226 * a given it the status is a success, we succeeded.
1227 */
1228 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
1229 DRM_DEBUG_KMS("First %s output reported failure to "
1230 "sync\n", SDVO_NAME(intel_sdvo));
1231 }
1232
1233 if (0)
1234 intel_sdvo_set_encoder_power_state(intel_sdvo,
1235 DRM_MODE_DPMS_ON);
1236 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
1237}
1238
b2cabb0e 1239static void intel_sdvo_dpms(struct drm_connector *connector, int mode)
79e53945 1240{
b2cabb0e
DV		 1241 struct drm_crtc *crtc;
1242 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1243
1244 /* dvo supports only 2 dpms states. */
1245 if (mode != DRM_MODE_DPMS_ON)
1246 mode = DRM_MODE_DPMS_OFF;
1247
1248 if (mode == connector->dpms)
1249 return;
1250
1251 connector->dpms = mode;
1252
1253 /* Only need to change hw state when actually enabled */
1254 crtc = intel_sdvo->base.base.crtc;
1255 if (!crtc) {
1256 intel_sdvo->base.connectors_active = false;
1257 return;
1258 }
79e53945
JB		 1259
1260 if (mode != DRM_MODE_DPMS_ON) {
ea5b213a 1261 intel_sdvo_set_active_outputs(intel_sdvo, 0);
79e53945 1262 if (0)
ea5b213a 1263 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
79e53945 1264
b2cabb0e
DV		 1265 intel_sdvo->base.connectors_active = false;
1266
1267 intel_crtc_update_dpms(crtc);
79e53945 1268 } else {
b2cabb0e
DV		 1269 intel_sdvo->base.connectors_active = true;
1270
1271 intel_crtc_update_dpms(crtc);
79e53945
JB		 1272
1273 if (0)
ea5b213a
CW		 1274 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1275 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
79e53945 1276 }
0a91ca29
DV		 1277
1278 intel_connector_check_state(to_intel_connector(connector));
79e53945
JB		 1279}
1280
79e53945
JB		 1281static int intel_sdvo_mode_valid(struct drm_connector *connector,
1282 struct drm_display_mode *mode)
1283{
df0e9248 1284 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
79e53945
JB		 1285
1286 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1287 return MODE_NO_DBLESCAN;
1288
ea5b213a 1289 if (intel_sdvo->pixel_clock_min > mode->clock)
79e53945
JB		 1290 return MODE_CLOCK_LOW;
1291
ea5b213a 1292 if (intel_sdvo->pixel_clock_max < mode->clock)
79e53945
JB		 1293 return MODE_CLOCK_HIGH;
1294
8545423a 1295 if (intel_sdvo->is_lvds) {
ea5b213a 1296 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
12682a97 1297 return MODE_PANEL;
1298
ea5b213a 1299 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
12682a97 1300 return MODE_PANEL;
1301 }
1302
79e53945
JB		 1303 return MODE_OK;
1304}
1305
ea5b213a 1306static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
79e53945 1307{
1a3665c8 1308 BUILD_BUG_ON(sizeof(*caps) != 8);
e957d772
CW		 1309 if (!intel_sdvo_get_value(intel_sdvo,
1310 SDVO_CMD_GET_DEVICE_CAPS,
1311 caps, sizeof(*caps)))
1312 return false;
1313
1314 DRM_DEBUG_KMS("SDVO capabilities:\n"
1315 " vendor_id: %d\n"
1316 " device_id: %d\n"
1317 " device_rev_id: %d\n"
1318 " sdvo_version_major: %d\n"
1319 " sdvo_version_minor: %d\n"
1320 " sdvo_inputs_mask: %d\n"
1321 " smooth_scaling: %d\n"
1322 " sharp_scaling: %d\n"
1323 " up_scaling: %d\n"
1324 " down_scaling: %d\n"
1325 " stall_support: %d\n"
1326 " output_flags: %d\n",
1327 caps->vendor_id,
1328 caps->device_id,
1329 caps->device_rev_id,
1330 caps->sdvo_version_major,
1331 caps->sdvo_version_minor,
1332 caps->sdvo_inputs_mask,
1333 caps->smooth_scaling,
1334 caps->sharp_scaling,
1335 caps->up_scaling,
1336 caps->down_scaling,
1337 caps->stall_support,
1338 caps->output_flags);
1339
1340 return true;
79e53945
JB		 1341}
1342
cc68c81a 1343static int intel_sdvo_supports_hotplug(struct intel_sdvo *intel_sdvo)
79e53945 1344{
768b107e 1345 struct drm_device *dev = intel_sdvo->base.base.dev;
79e53945 1346 u8 response[2];
79e53945 1347
768b107e
DV		 1348 /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
1349 * on the line. */
1350 if (IS_I945G(dev) || IS_I945GM(dev))
1351 return false;
1352
32aad86f
CW		 1353 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1354 &response, 2) && response[0];
79e53945
JB		 1355}
1356
cc68c81a 1357static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
79e53945 1358{
cc68c81a 1359 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
79e53945 1360
cc68c81a 1361 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &intel_sdvo->hotplug_active, 2);
79e53945
JB		 1362}
1363
fb7a46f3 1364static bool
ea5b213a 1365intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
fb7a46f3 1366{
bc65212c 1367 /* Is there more than one type of output? */
2294488d 1368 return hweight16(intel_sdvo->caps.output_flags) > 1;
fb7a46f3 1369}
1370
f899fc64 1371static struct edid *
e957d772 1372intel_sdvo_get_edid(struct drm_connector *connector)
f899fc64 1373{
e957d772
CW		 1374 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1375 return drm_get_edid(connector, &sdvo->ddc);
f899fc64
CW		 1376}
1377
ff482d83
CW		 1378/* Mac mini hack -- use the same DDC as the analog connector */
1379static struct edid *
1380intel_sdvo_get_analog_edid(struct drm_connector *connector)
1381{
f899fc64 1382 struct drm_i915_private *dev_priv = connector->dev->dev_private;
ff482d83 1383
0c1dab89 1384 return drm_get_edid(connector,
3bd7d909
DK		 1385 intel_gmbus_get_adapter(dev_priv,
1386 dev_priv->crt_ddc_pin));
ff482d83
CW		 1387}
1388
c43b5634 1389static enum drm_connector_status
8bf38485 1390intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
9dff6af8 1391{
df0e9248 1392 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
9d1a903d
CW		 1393 enum drm_connector_status status;
1394 struct edid *edid;
9dff6af8 1395
e957d772 1396 edid = intel_sdvo_get_edid(connector);
57cdaf90 1397
ea5b213a 1398 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
e957d772 1399 u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
9d1a903d 1400
7c3f0a27
ZY		 1401 /*
1402 * Don't use the 1 as the argument of DDC bus switch to get
1403 * the EDID. It is used for SDVO SPD ROM.
1404 */
9d1a903d 1405 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
e957d772
CW		 1406 intel_sdvo->ddc_bus = ddc;
1407 edid = intel_sdvo_get_edid(connector);
1408 if (edid)
7c3f0a27 1409 break;
7c3f0a27 1410 }
e957d772
CW		 1411 /*
1412 * If we found the EDID on the other bus,
1413 * assume that is the correct DDC bus.
1414 */
1415 if (edid == NULL)
1416 intel_sdvo->ddc_bus = saved_ddc;
7c3f0a27 1417 }
9d1a903d
CW		 1418
1419 /*
1420 * When there is no edid and no monitor is connected with VGA
1421 * port, try to use the CRT ddc to read the EDID for DVI-connector.
57cdaf90 1422 */
ff482d83
CW		 1423 if (edid == NULL)
1424 edid = intel_sdvo_get_analog_edid(connector);
149c36a3 1425
2f551c84 1426 status = connector_status_unknown;
9dff6af8 1427 if (edid != NULL) {
149c36a3 1428 /* DDC bus is shared, match EDID to connector type */
9d1a903d
CW		 1429 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1430 status = connector_status_connected;
da79de97
CW		 1431 if (intel_sdvo->is_hdmi) {
1432 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
1433 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
1434 }
13946743
CW		 1435 } else
1436 status = connector_status_disconnected;
149c36a3 1437 connector->display_info.raw_edid = NULL;
9d1a903d
CW		 1438 kfree(edid);
1439 }
7f36e7ed
CW		 1440
1441 if (status == connector_status_connected) {
1442 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
c3e5f67b
DV		 1443 if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO)
1444 intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON);
7f36e7ed
CW		 1445 }
1446
2b8d33f7 1447 return status;
9dff6af8
ML		 1448}
1449
52220085
CW		 1450static bool
1451intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
1452 struct edid *edid)
1453{
1454 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1455 bool connector_is_digital = !!IS_DIGITAL(sdvo);
1456
1457 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
1458 connector_is_digital, monitor_is_digital);
1459 return connector_is_digital == monitor_is_digital;
1460}
1461
7b334fcb 1462static enum drm_connector_status
930a9e28 1463intel_sdvo_detect(struct drm_connector *connector, bool force)
79e53945 1464{
fb7a46f3 1465 uint16_t response;
df0e9248 1466 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1467 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
14571b4c 1468 enum drm_connector_status ret;
79e53945 1469
32aad86f 1470 if (!intel_sdvo_write_cmd(intel_sdvo,
e957d772 1471 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0))
32aad86f 1472 return connector_status_unknown;
ba84cd1f
CW		 1473
1474 /* add 30ms delay when the output type might be TV */
a0b1c7a5 1475 if (intel_sdvo->caps.output_flags & SDVO_TV_MASK)
6c982376 1476 msleep(30);
ba84cd1f 1477
32aad86f
CW		 1478 if (!intel_sdvo_read_response(intel_sdvo, &response, 2))
1479 return connector_status_unknown;
79e53945 1480
e957d772
CW		 1481 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
1482 response & 0xff, response >> 8,
1483 intel_sdvo_connector->output_flag);
e2f0ba97 1484
fb7a46f3 1485 if (response == 0)
79e53945 1486 return connector_status_disconnected;
fb7a46f3 1487
ea5b213a 1488 intel_sdvo->attached_output = response;
14571b4c 1489
97aaf910
CW		 1490 intel_sdvo->has_hdmi_monitor = false;
1491 intel_sdvo->has_hdmi_audio = false;
1492
615fb93f 1493 if ((intel_sdvo_connector->output_flag & response) == 0)
14571b4c 1494 ret = connector_status_disconnected;
13946743 1495 else if (IS_TMDS(intel_sdvo_connector))
8bf38485 1496 ret = intel_sdvo_tmds_sink_detect(connector);
13946743
CW		 1497 else {
1498 struct edid *edid;
1499
1500 /* if we have an edid check it matches the connection */
1501 edid = intel_sdvo_get_edid(connector);
1502 if (edid == NULL)
1503 edid = intel_sdvo_get_analog_edid(connector);
1504 if (edid != NULL) {
52220085
CW		 1505 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
1506 edid))
13946743 1507 ret = connector_status_connected;
52220085
CW		 1508 else
1509 ret = connector_status_disconnected;
1510
13946743
CW		 1511 connector->display_info.raw_edid = NULL;
1512 kfree(edid);
1513 } else
1514 ret = connector_status_connected;
1515 }
14571b4c
ZW		 1516
1517 /* May update encoder flag for like clock for SDVO TV, etc.*/
1518 if (ret == connector_status_connected) {
ea5b213a
CW		 1519 intel_sdvo->is_tv = false;
1520 intel_sdvo->is_lvds = false;
1521 intel_sdvo->base.needs_tv_clock = false;
14571b4c
ZW		 1522
1523 if (response & SDVO_TV_MASK) {
ea5b213a
CW		 1524 intel_sdvo->is_tv = true;
1525 intel_sdvo->base.needs_tv_clock = true;
14571b4c
ZW		 1526 }
1527 if (response & SDVO_LVDS_MASK)
8545423a 1528 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
fb7a46f3 1529 }
14571b4c
ZW		 1530
1531 return ret;
79e53945
JB		 1532}
1533
e2f0ba97 1534static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945 1535{
ff482d83 1536 struct edid *edid;
79e53945
JB		 1537
1538 /* set the bus switch and get the modes */
e957d772 1539 edid = intel_sdvo_get_edid(connector);
79e53945 1540
57cdaf90
KP		 1541 /*
1542 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1543 * link between analog and digital outputs. So, if the regular SDVO
1544 * DDC fails, check to see if the analog output is disconnected, in
1545 * which case we'll look there for the digital DDC data.
e2f0ba97 1546 */
f899fc64
CW		 1547 if (edid == NULL)
1548 edid = intel_sdvo_get_analog_edid(connector);
1549
ff482d83 1550 if (edid != NULL) {
52220085
CW		 1551 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
1552 edid)) {
0c1dab89
CW		 1553 drm_mode_connector_update_edid_property(connector, edid);
1554 drm_add_edid_modes(connector, edid);
1555 }
13946743 1556
ff482d83
CW		 1557 connector->display_info.raw_edid = NULL;
1558 kfree(edid);
e2f0ba97 1559 }
e2f0ba97
JB		 1560}
1561
1562/*
1563 * Set of SDVO TV modes.
1564 * Note! This is in reply order (see loop in get_tv_modes).
1565 * XXX: all 60Hz refresh?
1566 */
b1f559ec 1567static const struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1568 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1569 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1570 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1571 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1572 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1573 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1574 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1575 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1576 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1577 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1578 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1579 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1580 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1581 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1582 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1583 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1584 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1585 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1586 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1587 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1588 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1589 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1590 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1591 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1592 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1593 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1594 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1595 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1596 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1597 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1598 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1599 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1600 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1601 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1602 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1603 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1604 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1605 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1606 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1607 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1608 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1609 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1610 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1611 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1612 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1613 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1614 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1615 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1616 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1617 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1618 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1619 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1620 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1621 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1622 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1623 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1624 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1625};
1626
1627static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1628{
df0e9248 1629 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7026d4ac 1630 struct intel_sdvo_sdtv_resolution_request tv_res;
ce6feabd
ZY		 1631 uint32_t reply = 0, format_map = 0;
1632 int i;
e2f0ba97
JB		 1633
1634 /* Read the list of supported input resolutions for the selected TV
1635 * format.
1636 */
40039750 1637 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1638 memcpy(&tv_res, &format_map,
32aad86f 1639 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
ce6feabd 1640
32aad86f
CW		 1641 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1642 return;
ce6feabd 1643
32aad86f 1644 BUILD_BUG_ON(sizeof(tv_res) != 3);
e957d772
CW		 1645 if (!intel_sdvo_write_cmd(intel_sdvo,
1646 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
32aad86f
CW		 1647 &tv_res, sizeof(tv_res)))
1648 return;
1649 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
e2f0ba97
JB		 1650 return;
1651
1652 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 1653 if (reply & (1 << i)) {
1654 struct drm_display_mode *nmode;
1655 nmode = drm_mode_duplicate(connector->dev,
32aad86f 1656 &sdvo_tv_modes[i]);
7026d4ac
ZW		 1657 if (nmode)
1658 drm_mode_probed_add(connector, nmode);
1659 }
e2f0ba97
JB		 1660}
1661
7086c87f
ML		 1662static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1663{
df0e9248 1664 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7086c87f 1665 struct drm_i915_private *dev_priv = connector->dev->dev_private;
12682a97 1666 struct drm_display_mode *newmode;
7086c87f
ML		 1667
1668 /*
1669 * Attempt to get the mode list from DDC.
1670 * Assume that the preferred modes are
1671 * arranged in priority order.
1672 */
f899fc64 1673 intel_ddc_get_modes(connector, intel_sdvo->i2c);
7086c87f 1674 if (list_empty(&connector->probed_modes) == false)
12682a97 1675 goto end;
7086c87f
ML		 1676
1677 /* Fetch modes from VBT */
1678 if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
7086c87f
ML		 1679 newmode = drm_mode_duplicate(connector->dev,
1680 dev_priv->sdvo_lvds_vbt_mode);
1681 if (newmode != NULL) {
1682 /* Guarantee the mode is preferred */
1683 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1684 DRM_MODE_TYPE_DRIVER);
1685 drm_mode_probed_add(connector, newmode);
1686 }
1687 }
12682a97 1688
1689end:
1690 list_for_each_entry(newmode, &connector->probed_modes, head) {
1691 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
ea5b213a 1692 intel_sdvo->sdvo_lvds_fixed_mode =
12682a97 1693 drm_mode_duplicate(connector->dev, newmode);
6c9547ff 1694
8545423a 1695 intel_sdvo->is_lvds = true;
12682a97 1696 break;
1697 }
1698 }
1699
7086c87f
ML		 1700}
1701
e2f0ba97
JB		 1702static int intel_sdvo_get_modes(struct drm_connector *connector)
1703{
615fb93f 1704 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e2f0ba97 1705
615fb93f 1706 if (IS_TV(intel_sdvo_connector))
e2f0ba97 1707 intel_sdvo_get_tv_modes(connector);
615fb93f 1708 else if (IS_LVDS(intel_sdvo_connector))
7086c87f 1709 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 1710 else
1711 intel_sdvo_get_ddc_modes(connector);
1712
32aad86f 1713 return !list_empty(&connector->probed_modes);
79e53945
JB		 1714}
1715
fcc8d672
CW		 1716static void
1717intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
b9219c5e 1718{
615fb93f 1719 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
b9219c5e
ZY		 1720 struct drm_device *dev = connector->dev;
1721
c5521706
CW		 1722 if (intel_sdvo_connector->left)
1723 drm_property_destroy(dev, intel_sdvo_connector->left);
1724 if (intel_sdvo_connector->right)
1725 drm_property_destroy(dev, intel_sdvo_connector->right);
1726 if (intel_sdvo_connector->top)
1727 drm_property_destroy(dev, intel_sdvo_connector->top);
1728 if (intel_sdvo_connector->bottom)
1729 drm_property_destroy(dev, intel_sdvo_connector->bottom);
1730 if (intel_sdvo_connector->hpos)
1731 drm_property_destroy(dev, intel_sdvo_connector->hpos);
1732 if (intel_sdvo_connector->vpos)
1733 drm_property_destroy(dev, intel_sdvo_connector->vpos);
1734 if (intel_sdvo_connector->saturation)
1735 drm_property_destroy(dev, intel_sdvo_connector->saturation);
1736 if (intel_sdvo_connector->contrast)
1737 drm_property_destroy(dev, intel_sdvo_connector->contrast);
1738 if (intel_sdvo_connector->hue)
1739 drm_property_destroy(dev, intel_sdvo_connector->hue);
1740 if (intel_sdvo_connector->sharpness)
1741 drm_property_destroy(dev, intel_sdvo_connector->sharpness);
1742 if (intel_sdvo_connector->flicker_filter)
1743 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
1744 if (intel_sdvo_connector->flicker_filter_2d)
1745 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
1746 if (intel_sdvo_connector->flicker_filter_adaptive)
1747 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
1748 if (intel_sdvo_connector->tv_luma_filter)
1749 drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
1750 if (intel_sdvo_connector->tv_chroma_filter)
1751 drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
e044218a
CW		 1752 if (intel_sdvo_connector->dot_crawl)
1753 drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
c5521706
CW		 1754 if (intel_sdvo_connector->brightness)
1755 drm_property_destroy(dev, intel_sdvo_connector->brightness);
b9219c5e
ZY		 1756}
1757
79e53945
JB		 1758static void intel_sdvo_destroy(struct drm_connector *connector)
1759{
615fb93f 1760 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
79e53945 1761
c5521706 1762 if (intel_sdvo_connector->tv_format)
ce6feabd 1763 drm_property_destroy(connector->dev,
c5521706 1764 intel_sdvo_connector->tv_format);
b9219c5e 1765
d2a82a6f 1766 intel_sdvo_destroy_enhance_property(connector);
79e53945
JB		 1767 drm_sysfs_connector_remove(connector);
1768 drm_connector_cleanup(connector);
d2a82a6f 1769 kfree(connector);
79e53945
JB		 1770}
1771
1aad7ac0
CW		 1772static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
1773{
1774 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1775 struct edid *edid;
1776 bool has_audio = false;
1777
1778 if (!intel_sdvo->is_hdmi)
1779 return false;
1780
1781 edid = intel_sdvo_get_edid(connector);
1782 if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
1783 has_audio = drm_detect_monitor_audio(edid);
1784
1785 return has_audio;
1786}
1787
ce6feabd
ZY		 1788static int
1789intel_sdvo_set_property(struct drm_connector *connector,
1790 struct drm_property *property,
1791 uint64_t val)
1792{
df0e9248 1793 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1794 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e953fd7b 1795 struct drm_i915_private *dev_priv = connector->dev->dev_private;
b9219c5e 1796 uint16_t temp_value;
32aad86f
CW		 1797 uint8_t cmd;
1798 int ret;
ce6feabd
ZY		 1799
1800 ret = drm_connector_property_set_value(connector, property, val);
32aad86f
CW		 1801 if (ret)
1802 return ret;
ce6feabd 1803
3f43c48d 1804 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 1805 int i = val;
1806 bool has_audio;
1807
1808 if (i == intel_sdvo_connector->force_audio)
7f36e7ed
CW		 1809 return 0;
1810
1aad7ac0 1811 intel_sdvo_connector->force_audio = i;
7f36e7ed 1812
c3e5f67b 1813 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 1814 has_audio = intel_sdvo_detect_hdmi_audio(connector);
1815 else
c3e5f67b 1816 has_audio = (i == HDMI_AUDIO_ON);
7f36e7ed 1817
1aad7ac0 1818 if (has_audio == intel_sdvo->has_hdmi_audio)
7f36e7ed 1819 return 0;
7f36e7ed 1820
1aad7ac0 1821 intel_sdvo->has_hdmi_audio = has_audio;
7f36e7ed
CW		 1822 goto done;
1823 }
1824
e953fd7b
CW		 1825 if (property == dev_priv->broadcast_rgb_property) {
1826 if (val == !!intel_sdvo->color_range)
7f36e7ed
CW		 1827 return 0;
1828
e953fd7b 1829 intel_sdvo->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
7f36e7ed
CW		 1830 goto done;
1831 }
1832
c5521706
CW		 1833#define CHECK_PROPERTY(name, NAME) \
1834 if (intel_sdvo_connector->name == property) { \
1835 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
1836 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
1837 cmd = SDVO_CMD_SET_##NAME; \
1838 intel_sdvo_connector->cur_##name = temp_value; \
1839 goto set_value; \
1840 }
1841
1842 if (property == intel_sdvo_connector->tv_format) {
32aad86f
CW		 1843 if (val >= TV_FORMAT_NUM)
1844 return -EINVAL;
1845
40039750 1846 if (intel_sdvo->tv_format_index ==
615fb93f 1847 intel_sdvo_connector->tv_format_supported[val])
32aad86f 1848 return 0;
ce6feabd 1849
40039750 1850 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
c5521706 1851 goto done;
32aad86f 1852 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
b9219c5e 1853 temp_value = val;
c5521706 1854 if (intel_sdvo_connector->left == property) {
b9219c5e 1855 drm_connector_property_set_value(connector,
c5521706 1856 intel_sdvo_connector->right, val);
615fb93f 1857 if (intel_sdvo_connector->left_margin == temp_value)
32aad86f 1858 return 0;
b9219c5e 1859
615fb93f
CW		 1860 intel_sdvo_connector->left_margin = temp_value;
1861 intel_sdvo_connector->right_margin = temp_value;
1862 temp_value = intel_sdvo_connector->max_hscan -
c5521706 1863 intel_sdvo_connector->left_margin;
b9219c5e 1864 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1865 goto set_value;
1866 } else if (intel_sdvo_connector->right == property) {
b9219c5e 1867 drm_connector_property_set_value(connector,
c5521706 1868 intel_sdvo_connector->left, val);
615fb93f 1869 if (intel_sdvo_connector->right_margin == temp_value)
32aad86f 1870 return 0;
b9219c5e 1871
615fb93f
CW		 1872 intel_sdvo_connector->left_margin = temp_value;
1873 intel_sdvo_connector->right_margin = temp_value;
1874 temp_value = intel_sdvo_connector->max_hscan -
1875 intel_sdvo_connector->left_margin;
b9219c5e 1876 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1877 goto set_value;
1878 } else if (intel_sdvo_connector->top == property) {
b9219c5e 1879 drm_connector_property_set_value(connector,
c5521706 1880 intel_sdvo_connector->bottom, val);
615fb93f 1881 if (intel_sdvo_connector->top_margin == temp_value)
32aad86f 1882 return 0;
b9219c5e 1883
615fb93f
CW		 1884 intel_sdvo_connector->top_margin = temp_value;
1885 intel_sdvo_connector->bottom_margin = temp_value;
1886 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1887 intel_sdvo_connector->top_margin;
b9219c5e 1888 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1889 goto set_value;
1890 } else if (intel_sdvo_connector->bottom == property) {
b9219c5e 1891 drm_connector_property_set_value(connector,
c5521706 1892 intel_sdvo_connector->top, val);
615fb93f 1893 if (intel_sdvo_connector->bottom_margin == temp_value)
32aad86f
CW		 1894 return 0;
1895
615fb93f
CW		 1896 intel_sdvo_connector->top_margin = temp_value;
1897 intel_sdvo_connector->bottom_margin = temp_value;
1898 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1899 intel_sdvo_connector->top_margin;
b9219c5e 1900 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1901 goto set_value;
1902 }
1903 CHECK_PROPERTY(hpos, HPOS)
1904 CHECK_PROPERTY(vpos, VPOS)
1905 CHECK_PROPERTY(saturation, SATURATION)
1906 CHECK_PROPERTY(contrast, CONTRAST)
1907 CHECK_PROPERTY(hue, HUE)
1908 CHECK_PROPERTY(brightness, BRIGHTNESS)
1909 CHECK_PROPERTY(sharpness, SHARPNESS)
1910 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
1911 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
1912 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
1913 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
1914 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
e044218a 1915 CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
c5521706 1916 }
b9219c5e 1917
c5521706 1918 return -EINVAL; /* unknown property */
b9219c5e 1919
c5521706
CW		 1920set_value:
1921 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
1922 return -EIO;
b9219c5e 1923
b9219c5e 1924
c5521706 1925done:
df0e9248
CW		 1926 if (intel_sdvo->base.base.crtc) {
1927 struct drm_crtc *crtc = intel_sdvo->base.base.crtc;
a6778b3c
DV		 1928 intel_set_mode(crtc, &crtc->mode,
1929 crtc->x, crtc->y, crtc->fb);
c5521706
CW		 1930 }
1931
32aad86f 1932 return 0;
c5521706 1933#undef CHECK_PROPERTY
ce6feabd
ZY		 1934}
1935
79e53945 1936static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
79e53945 1937 .mode_fixup = intel_sdvo_mode_fixup,
79e53945 1938 .mode_set = intel_sdvo_mode_set,
1f703855 1939 .disable = intel_encoder_noop,
79e53945
JB		 1940};
1941
1942static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
b2cabb0e 1943 .dpms = intel_sdvo_dpms,
79e53945
JB		 1944 .detect = intel_sdvo_detect,
1945 .fill_modes = drm_helper_probe_single_connector_modes,
ce6feabd 1946 .set_property = intel_sdvo_set_property,
79e53945
JB		 1947 .destroy = intel_sdvo_destroy,
1948};
1949
1950static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
1951 .get_modes = intel_sdvo_get_modes,
1952 .mode_valid = intel_sdvo_mode_valid,
df0e9248 1953 .best_encoder = intel_best_encoder,
79e53945
JB		 1954};
1955
b358d0a6 1956static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945 1957{
890f3359 1958 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
d2a82a6f 1959
ea5b213a 1960 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
d2a82a6f 1961 drm_mode_destroy(encoder->dev,
ea5b213a 1962 intel_sdvo->sdvo_lvds_fixed_mode);
d2a82a6f 1963
e957d772 1964 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 1965 intel_encoder_destroy(encoder);
79e53945
JB		 1966}
1967
1968static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
1969 .destroy = intel_sdvo_enc_destroy,
1970};
1971
b66d8424
CW		 1972static void
1973intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
1974{
1975 uint16_t mask = 0;
1976 unsigned int num_bits;
1977
1978 /* Make a mask of outputs less than or equal to our own priority in the
1979 * list.
1980 */
1981 switch (sdvo->controlled_output) {
1982 case SDVO_OUTPUT_LVDS1:
1983 mask |= SDVO_OUTPUT_LVDS1;
1984 case SDVO_OUTPUT_LVDS0:
1985 mask |= SDVO_OUTPUT_LVDS0;
1986 case SDVO_OUTPUT_TMDS1:
1987 mask |= SDVO_OUTPUT_TMDS1;
1988 case SDVO_OUTPUT_TMDS0:
1989 mask |= SDVO_OUTPUT_TMDS0;
1990 case SDVO_OUTPUT_RGB1:
1991 mask |= SDVO_OUTPUT_RGB1;
1992 case SDVO_OUTPUT_RGB0:
1993 mask |= SDVO_OUTPUT_RGB0;
1994 break;
1995 }
1996
1997 /* Count bits to find what number we are in the priority list. */
1998 mask &= sdvo->caps.output_flags;
1999 num_bits = hweight16(mask);
2000 /* If more than 3 outputs, default to DDC bus 3 for now. */
2001 if (num_bits > 3)
2002 num_bits = 3;
2003
2004 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
2005 sdvo->ddc_bus = 1 << num_bits;
2006}
79e53945 2007
e2f0ba97
JB		 2008/**
2009 * Choose the appropriate DDC bus for control bus switch command for this
2010 * SDVO output based on the controlled output.
2011 *
2012 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
2013 * outputs, then LVDS outputs.
2014 */
2015static void
b1083333 2016intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
ea5b213a 2017 struct intel_sdvo *sdvo, u32 reg)
e2f0ba97 2018{
b1083333 2019 struct sdvo_device_mapping *mapping;
e2f0ba97 2020
eef4eacb 2021 if (sdvo->is_sdvob)
b1083333
AJ		 2022 mapping = &(dev_priv->sdvo_mappings[0]);
2023 else
2024 mapping = &(dev_priv->sdvo_mappings[1]);
e2f0ba97 2025
b66d8424
CW		 2026 if (mapping->initialized)
2027 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
2028 else
2029 intel_sdvo_guess_ddc_bus(sdvo);
e2f0ba97
JB		 2030}
2031
e957d772
CW		 2032static void
2033intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
2034 struct intel_sdvo *sdvo, u32 reg)
2035{
2036 struct sdvo_device_mapping *mapping;
46eb3036 2037 u8 pin;
e957d772 2038
eef4eacb 2039 if (sdvo->is_sdvob)
e957d772
CW		 2040 mapping = &dev_priv->sdvo_mappings[0];
2041 else
2042 mapping = &dev_priv->sdvo_mappings[1];
2043
2044 pin = GMBUS_PORT_DPB;
46eb3036 2045 if (mapping->initialized)
e957d772 2046 pin = mapping->i2c_pin;
e957d772 2047
3bd7d909
DK		 2048 if (intel_gmbus_is_port_valid(pin)) {
2049 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
d5090b96 2050 intel_gmbus_set_speed(sdvo->i2c, GMBUS_RATE_1MHZ);
63abf3ed 2051 intel_gmbus_force_bit(sdvo->i2c, true);
46eb3036 2052 } else {
3bd7d909 2053 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB);
46eb3036 2054 }
e957d772
CW		 2055}
2056
e2f0ba97 2057static bool
e27d8538 2058intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
e2f0ba97 2059{
97aaf910 2060 return intel_sdvo_check_supp_encode(intel_sdvo);
e2f0ba97
JB		 2061}
2062
714605e4 2063static u8
eef4eacb 2064intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo)
714605e4 2065{
2066 struct drm_i915_private *dev_priv = dev->dev_private;
2067 struct sdvo_device_mapping *my_mapping, *other_mapping;
2068
eef4eacb 2069 if (sdvo->is_sdvob) {
714605e4 2070 my_mapping = &dev_priv->sdvo_mappings[0];
2071 other_mapping = &dev_priv->sdvo_mappings[1];
2072 } else {
2073 my_mapping = &dev_priv->sdvo_mappings[1];
2074 other_mapping = &dev_priv->sdvo_mappings[0];
2075 }
2076
2077 /* If the BIOS described our SDVO device, take advantage of it. */
2078 if (my_mapping->slave_addr)
2079 return my_mapping->slave_addr;
2080
2081 /* If the BIOS only described a different SDVO device, use the
2082 * address that it isn't using.
2083 */
2084 if (other_mapping->slave_addr) {
2085 if (other_mapping->slave_addr == 0x70)
2086 return 0x72;
2087 else
2088 return 0x70;
2089 }
2090
2091 /* No SDVO device info is found for another DVO port,
2092 * so use mapping assumption we had before BIOS parsing.
2093 */
eef4eacb 2094 if (sdvo->is_sdvob)
714605e4 2095 return 0x70;
2096 else
2097 return 0x72;
2098}
2099
14571b4c 2100static void
df0e9248
CW		 2101intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
2102 struct intel_sdvo *encoder)
14571b4c 2103{
df0e9248
CW		 2104 drm_connector_init(encoder->base.base.dev,
2105 &connector->base.base,
2106 &intel_sdvo_connector_funcs,
2107 connector->base.base.connector_type);
6070a4a9 2108
df0e9248
CW		 2109 drm_connector_helper_add(&connector->base.base,
2110 &intel_sdvo_connector_helper_funcs);
14571b4c 2111
8f4839e2 2112 connector->base.base.interlace_allowed = 1;
df0e9248
CW		 2113 connector->base.base.doublescan_allowed = 0;
2114 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
4ac41f47 2115 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
14571b4c 2116
df0e9248
CW		 2117 intel_connector_attach_encoder(&connector->base, &encoder->base);
2118 drm_sysfs_connector_add(&connector->base.base);
14571b4c 2119}
6070a4a9 2120
7f36e7ed
CW		 2121static void
2122intel_sdvo_add_hdmi_properties(struct intel_sdvo_connector *connector)
2123{
2124 struct drm_device *dev = connector->base.base.dev;
2125
3f43c48d 2126 intel_attach_force_audio_property(&connector->base.base);
e953fd7b
CW		 2127 if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev))
2128 intel_attach_broadcast_rgb_property(&connector->base.base);
7f36e7ed
CW		 2129}
2130
fb7a46f3 2131static bool
ea5b213a 2132intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
fb7a46f3 2133{
4ef69c7a 2134 struct drm_encoder *encoder = &intel_sdvo->base.base;
14571b4c 2135 struct drm_connector *connector;
cc68c81a 2136 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
14571b4c 2137 struct intel_connector *intel_connector;
615fb93f 2138 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2139
615fb93f
CW		 2140 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2141 if (!intel_sdvo_connector)
14571b4c
ZW		 2142 return false;
2143
14571b4c 2144 if (device == 0) {
ea5b213a 2145 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
615fb93f 2146 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
14571b4c 2147 } else if (device == 1) {
ea5b213a 2148 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
615fb93f 2149 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
14571b4c
ZW		 2150 }
2151
615fb93f 2152 intel_connector = &intel_sdvo_connector->base;
14571b4c 2153 connector = &intel_connector->base;
cc68c81a
SF		 2154 if (intel_sdvo_supports_hotplug(intel_sdvo) & (1 << device)) {
2155 connector->polled = DRM_CONNECTOR_POLL_HPD;
2156 intel_sdvo->hotplug_active[0] |= 1 << device;
2157 /* Some SDVO devices have one-shot hotplug interrupts.
2158 * Ensure that they get re-enabled when an interrupt happens.
2159 */
2160 intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
2161 intel_sdvo_enable_hotplug(intel_encoder);
2162 }
2163 else
2164 connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
14571b4c
ZW		 2165 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2166 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2167
e27d8538 2168 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
14571b4c 2169 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
e27d8538 2170 intel_sdvo->is_hdmi = true;
14571b4c 2171 }
66a9278e 2172 intel_sdvo->base.cloneable = true;
14571b4c 2173
df0e9248 2174 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
f797d221
CW		 2175 if (intel_sdvo->is_hdmi)
2176 intel_sdvo_add_hdmi_properties(intel_sdvo_connector);
14571b4c
ZW		 2177
2178 return true;
2179}
2180
2181static bool
ea5b213a 2182intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
14571b4c 2183{
4ef69c7a
CW		 2184 struct drm_encoder *encoder = &intel_sdvo->base.base;
2185 struct drm_connector *connector;
2186 struct intel_connector *intel_connector;
2187 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2188
615fb93f
CW		 2189 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2190 if (!intel_sdvo_connector)
2191 return false;
14571b4c 2192
615fb93f 2193 intel_connector = &intel_sdvo_connector->base;
4ef69c7a
CW		 2194 connector = &intel_connector->base;
2195 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2196 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
14571b4c 2197
4ef69c7a
CW		 2198 intel_sdvo->controlled_output |= type;
2199 intel_sdvo_connector->output_flag = type;
14571b4c 2200
4ef69c7a
CW		 2201 intel_sdvo->is_tv = true;
2202 intel_sdvo->base.needs_tv_clock = true;
66a9278e 2203 intel_sdvo->base.cloneable = false;
14571b4c 2204
df0e9248 2205 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
14571b4c 2206
4ef69c7a 2207 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
32aad86f 2208 goto err;
14571b4c 2209
4ef69c7a 2210 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f 2211 goto err;
14571b4c 2212
4ef69c7a 2213 return true;
32aad86f
CW		 2214
2215err:
123d5c01 2216 intel_sdvo_destroy(connector);
32aad86f 2217 return false;
14571b4c
ZW		 2218}
2219
2220static bool
ea5b213a 2221intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2222{
4ef69c7a
CW		 2223 struct drm_encoder *encoder = &intel_sdvo->base.base;
2224 struct drm_connector *connector;
2225 struct intel_connector *intel_connector;
2226 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2227
615fb93f
CW		 2228 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2229 if (!intel_sdvo_connector)
2230 return false;
14571b4c 2231
615fb93f 2232 intel_connector = &intel_sdvo_connector->base;
4ef69c7a 2233 connector = &intel_connector->base;
eb1f8e4f 2234 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
4ef69c7a
CW		 2235 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2236 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2237
2238 if (device == 0) {
2239 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2240 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2241 } else if (device == 1) {
2242 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2243 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2244 }
2245
66a9278e 2246 intel_sdvo->base.cloneable = true;
14571b4c 2247
df0e9248
CW		 2248 intel_sdvo_connector_init(intel_sdvo_connector,
2249 intel_sdvo);
4ef69c7a 2250 return true;
14571b4c
ZW		 2251}
2252
2253static bool
ea5b213a 2254intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2255{
4ef69c7a
CW		 2256 struct drm_encoder *encoder = &intel_sdvo->base.base;
2257 struct drm_connector *connector;
2258 struct intel_connector *intel_connector;
2259 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2260
615fb93f
CW		 2261 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2262 if (!intel_sdvo_connector)
2263 return false;
14571b4c 2264
615fb93f
CW		 2265 intel_connector = &intel_sdvo_connector->base;
2266 connector = &intel_connector->base;
4ef69c7a
CW		 2267 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2268 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2269
2270 if (device == 0) {
2271 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2272 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2273 } else if (device == 1) {
2274 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2275 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2276 }
2277
66a9278e
DV		 2278 /* SDVO LVDS is cloneable because the SDVO encoder does the upscaling,
2279 * as opposed to native LVDS, where we upscale with the panel-fitter
2280 * (and hence only the native LVDS resolution could be cloned). */
2281 intel_sdvo->base.cloneable = true;
14571b4c 2282
df0e9248 2283 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
4ef69c7a 2284 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f
CW		 2285 goto err;
2286
2287 return true;
2288
2289err:
123d5c01 2290 intel_sdvo_destroy(connector);
32aad86f 2291 return false;
14571b4c
ZW		 2292}
2293
2294static bool
ea5b213a 2295intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
14571b4c 2296{
ea5b213a
CW		 2297 intel_sdvo->is_tv = false;
2298 intel_sdvo->base.needs_tv_clock = false;
2299 intel_sdvo->is_lvds = false;
fb7a46f3 2300
14571b4c 2301 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
fb7a46f3 2302
14571b4c 2303 if (flags & SDVO_OUTPUT_TMDS0)
ea5b213a 2304 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
14571b4c
ZW		 2305 return false;
2306
2307 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
ea5b213a 2308 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
14571b4c
ZW		 2309 return false;
2310
2311 /* TV has no XXX1 function block */
a1f4b7ff 2312 if (flags & SDVO_OUTPUT_SVID0)
ea5b213a 2313 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
14571b4c
ZW		 2314 return false;
2315
2316 if (flags & SDVO_OUTPUT_CVBS0)
ea5b213a 2317 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
14571b4c 2318 return false;
fb7a46f3 2319
a0b1c7a5
CW		 2320 if (flags & SDVO_OUTPUT_YPRPB0)
2321 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
2322 return false;
2323
14571b4c 2324 if (flags & SDVO_OUTPUT_RGB0)
ea5b213a 2325 if (!intel_sdvo_analog_init(intel_sdvo, 0))
14571b4c
ZW		 2326 return false;
2327
2328 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
ea5b213a 2329 if (!intel_sdvo_analog_init(intel_sdvo, 1))
14571b4c
ZW		 2330 return false;
2331
2332 if (flags & SDVO_OUTPUT_LVDS0)
ea5b213a 2333 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
14571b4c
ZW		 2334 return false;
2335
2336 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
ea5b213a 2337 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
14571b4c 2338 return false;
fb7a46f3 2339
14571b4c 2340 if ((flags & SDVO_OUTPUT_MASK) == 0) {
fb7a46f3 2341 unsigned char bytes[2];
2342
ea5b213a
CW		 2343 intel_sdvo->controlled_output = 0;
2344 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
51c8b407 2345 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
ea5b213a 2346 SDVO_NAME(intel_sdvo),
51c8b407 2347 bytes[0], bytes[1]);
14571b4c 2348 return false;
fb7a46f3 2349 }
27f8227b 2350 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
fb7a46f3 2351
14571b4c 2352 return true;
fb7a46f3 2353}
2354
32aad86f
CW		 2355static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2356 struct intel_sdvo_connector *intel_sdvo_connector,
2357 int type)
ce6feabd 2358{
4ef69c7a 2359 struct drm_device *dev = intel_sdvo->base.base.dev;
ce6feabd
ZY		 2360 struct intel_sdvo_tv_format format;
2361 uint32_t format_map, i;
ce6feabd 2362
32aad86f
CW		 2363 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2364 return false;
ce6feabd 2365
1a3665c8 2366 BUILD_BUG_ON(sizeof(format) != 6);
32aad86f
CW		 2367 if (!intel_sdvo_get_value(intel_sdvo,
2368 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2369 &format, sizeof(format)))
2370 return false;
ce6feabd 2371
32aad86f 2372 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
ce6feabd
ZY		 2373
2374 if (format_map == 0)
32aad86f 2375 return false;
ce6feabd 2376
615fb93f 2377 intel_sdvo_connector->format_supported_num = 0;
ce6feabd 2378 for (i = 0 ; i < TV_FORMAT_NUM; i++)
40039750
CW		 2379 if (format_map & (1 << i))
2380 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
ce6feabd
ZY		 2381
2382
c5521706 2383 intel_sdvo_connector->tv_format =
32aad86f
CW		 2384 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2385 "mode", intel_sdvo_connector->format_supported_num);
c5521706 2386 if (!intel_sdvo_connector->tv_format)
fcc8d672 2387 return false;
ce6feabd 2388
615fb93f 2389 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
ce6feabd 2390 drm_property_add_enum(
c5521706 2391 intel_sdvo_connector->tv_format, i,
40039750 2392 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
ce6feabd 2393
40039750 2394 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
32aad86f 2395 drm_connector_attach_property(&intel_sdvo_connector->base.base,
c5521706 2396 intel_sdvo_connector->tv_format, 0);
32aad86f 2397 return true;
ce6feabd
ZY		 2398
2399}
2400
c5521706
CW		 2401#define ENHANCEMENT(name, NAME) do { \
2402 if (enhancements.name) { \
2403 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2404 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2405 return false; \
2406 intel_sdvo_connector->max_##name = data_value[0]; \
2407 intel_sdvo_connector->cur_##name = response; \
2408 intel_sdvo_connector->name = \
d9bc3c02 2409 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
c5521706 2410 if (!intel_sdvo_connector->name) return false; \
c5521706
CW		 2411 drm_connector_attach_property(connector, \
2412 intel_sdvo_connector->name, \
2413 intel_sdvo_connector->cur_##name); \
2414 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2415 data_value[0], data_value[1], response); \
2416 } \
0206e353 2417} while (0)
c5521706
CW		 2418
2419static bool
2420intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2421 struct intel_sdvo_connector *intel_sdvo_connector,
2422 struct intel_sdvo_enhancements_reply enhancements)
b9219c5e 2423{
4ef69c7a 2424 struct drm_device *dev = intel_sdvo->base.base.dev;
32aad86f 2425 struct drm_connector *connector = &intel_sdvo_connector->base.base;
b9219c5e
ZY		 2426 uint16_t response, data_value[2];
2427
c5521706
CW		 2428 /* when horizontal overscan is supported, Add the left/right property */
2429 if (enhancements.overscan_h) {
2430 if (!intel_sdvo_get_value(intel_sdvo,
2431 SDVO_CMD_GET_MAX_OVERSCAN_H,
2432 &data_value, 4))
2433 return false;
32aad86f 2434
c5521706
CW		 2435 if (!intel_sdvo_get_value(intel_sdvo,
2436 SDVO_CMD_GET_OVERSCAN_H,
2437 &response, 2))
2438 return false;
fcc8d672 2439
c5521706
CW		 2440 intel_sdvo_connector->max_hscan = data_value[0];
2441 intel_sdvo_connector->left_margin = data_value[0] - response;
2442 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
2443 intel_sdvo_connector->left =
d9bc3c02 2444 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
c5521706
CW		 2445 if (!intel_sdvo_connector->left)
2446 return false;
fcc8d672 2447
c5521706
CW		 2448 drm_connector_attach_property(connector,
2449 intel_sdvo_connector->left,
2450 intel_sdvo_connector->left_margin);
fcc8d672 2451
c5521706 2452 intel_sdvo_connector->right =
d9bc3c02 2453 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
c5521706
CW		 2454 if (!intel_sdvo_connector->right)
2455 return false;
32aad86f 2456
c5521706
CW		 2457 drm_connector_attach_property(connector,
2458 intel_sdvo_connector->right,
2459 intel_sdvo_connector->right_margin);
2460 DRM_DEBUG_KMS("h_overscan: max %d, "
2461 "default %d, current %d\n",
2462 data_value[0], data_value[1], response);
2463 }
32aad86f 2464
c5521706
CW		 2465 if (enhancements.overscan_v) {
2466 if (!intel_sdvo_get_value(intel_sdvo,
2467 SDVO_CMD_GET_MAX_OVERSCAN_V,
2468 &data_value, 4))
2469 return false;
fcc8d672 2470
c5521706
CW		 2471 if (!intel_sdvo_get_value(intel_sdvo,
2472 SDVO_CMD_GET_OVERSCAN_V,
2473 &response, 2))
2474 return false;
32aad86f 2475
c5521706
CW		 2476 intel_sdvo_connector->max_vscan = data_value[0];
2477 intel_sdvo_connector->top_margin = data_value[0] - response;
2478 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
2479 intel_sdvo_connector->top =
d9bc3c02
SH		 2480 drm_property_create_range(dev, 0,
2481 "top_margin", 0, data_value[0]);
c5521706
CW		 2482 if (!intel_sdvo_connector->top)
2483 return false;
32aad86f 2484
c5521706
CW		 2485 drm_connector_attach_property(connector,
2486 intel_sdvo_connector->top,
2487 intel_sdvo_connector->top_margin);
fcc8d672 2488
c5521706 2489 intel_sdvo_connector->bottom =
d9bc3c02
SH		 2490 drm_property_create_range(dev, 0,
2491 "bottom_margin", 0, data_value[0]);
c5521706
CW		 2492 if (!intel_sdvo_connector->bottom)
2493 return false;
32aad86f 2494
c5521706
CW		 2495 drm_connector_attach_property(connector,
2496 intel_sdvo_connector->bottom,
2497 intel_sdvo_connector->bottom_margin);
2498 DRM_DEBUG_KMS("v_overscan: max %d, "
2499 "default %d, current %d\n",
2500 data_value[0], data_value[1], response);
2501 }
32aad86f 2502
c5521706
CW		 2503 ENHANCEMENT(hpos, HPOS);
2504 ENHANCEMENT(vpos, VPOS);
2505 ENHANCEMENT(saturation, SATURATION);
2506 ENHANCEMENT(contrast, CONTRAST);
2507 ENHANCEMENT(hue, HUE);
2508 ENHANCEMENT(sharpness, SHARPNESS);
2509 ENHANCEMENT(brightness, BRIGHTNESS);
2510 ENHANCEMENT(flicker_filter, FLICKER_FILTER);
2511 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2512 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
2513 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
2514 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
fcc8d672 2515
e044218a
CW		 2516 if (enhancements.dot_crawl) {
2517 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2518 return false;
2519
2520 intel_sdvo_connector->max_dot_crawl = 1;
2521 intel_sdvo_connector->cur_dot_crawl = response & 0x1;
2522 intel_sdvo_connector->dot_crawl =
d9bc3c02 2523 drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
e044218a
CW		 2524 if (!intel_sdvo_connector->dot_crawl)
2525 return false;
2526
e044218a
CW		 2527 drm_connector_attach_property(connector,
2528 intel_sdvo_connector->dot_crawl,
2529 intel_sdvo_connector->cur_dot_crawl);
2530 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2531 }
2532
c5521706
CW		 2533 return true;
2534}
32aad86f 2535
c5521706
CW		 2536static bool
2537intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2538 struct intel_sdvo_connector *intel_sdvo_connector,
2539 struct intel_sdvo_enhancements_reply enhancements)
2540{
4ef69c7a 2541 struct drm_device *dev = intel_sdvo->base.base.dev;
c5521706
CW		 2542 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2543 uint16_t response, data_value[2];
32aad86f 2544
c5521706 2545 ENHANCEMENT(brightness, BRIGHTNESS);
fcc8d672 2546
c5521706
CW		 2547 return true;
2548}
2549#undef ENHANCEMENT
32aad86f 2550
c5521706
CW		 2551static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2552 struct intel_sdvo_connector *intel_sdvo_connector)
2553{
2554 union {
2555 struct intel_sdvo_enhancements_reply reply;
2556 uint16_t response;
2557 } enhancements;
32aad86f 2558
1a3665c8
CW		 2559 BUILD_BUG_ON(sizeof(enhancements) != 2);
2560
cf9a2f3a
CW		 2561 enhancements.response = 0;
2562 intel_sdvo_get_value(intel_sdvo,
2563 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2564 &enhancements, sizeof(enhancements));
c5521706
CW		 2565 if (enhancements.response == 0) {
2566 DRM_DEBUG_KMS("No enhancement is supported\n");
2567 return true;
b9219c5e 2568 }
32aad86f 2569
c5521706
CW		 2570 if (IS_TV(intel_sdvo_connector))
2571 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
0206e353 2572 else if (IS_LVDS(intel_sdvo_connector))
c5521706
CW		 2573 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2574 else
2575 return true;
e957d772
CW		 2576}
2577
2578static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
2579 struct i2c_msg *msgs,
2580 int num)
2581{
2582 struct intel_sdvo *sdvo = adapter->algo_data;
fcc8d672 2583
e957d772
CW		 2584 if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
2585 return -EIO;
2586
2587 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
2588}
2589
2590static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
2591{
2592 struct intel_sdvo *sdvo = adapter->algo_data;
2593 return sdvo->i2c->algo->functionality(sdvo->i2c);
2594}
2595
2596static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
2597 .master_xfer = intel_sdvo_ddc_proxy_xfer,
2598 .functionality = intel_sdvo_ddc_proxy_func
2599};
2600
2601static bool
2602intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
2603 struct drm_device *dev)
2604{
2605 sdvo->ddc.owner = THIS_MODULE;
2606 sdvo->ddc.class = I2C_CLASS_DDC;
2607 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
2608 sdvo->ddc.dev.parent = &dev->pdev->dev;
2609 sdvo->ddc.algo_data = sdvo;
2610 sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
2611
2612 return i2c_add_adapter(&sdvo->ddc) == 0;
b9219c5e
ZY		 2613}
2614
eef4eacb 2615bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
79e53945 2616{
b01f2c3a 2617 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 2618 struct intel_encoder *intel_encoder;
ea5b213a 2619 struct intel_sdvo *intel_sdvo;
084b612e 2620 u32 hotplug_mask;
79e53945 2621 int i;
79e53945 2622
ea5b213a
CW		 2623 intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
2624 if (!intel_sdvo)
7d57382e 2625 return false;
79e53945 2626
56184e3d 2627 intel_sdvo->sdvo_reg = sdvo_reg;
eef4eacb
DV		 2628 intel_sdvo->is_sdvob = is_sdvob;
2629 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1;
56184e3d 2630 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
e957d772
CW		 2631 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev)) {
2632 kfree(intel_sdvo);
2633 return false;
2634 }
2635
56184e3d 2636 /* encoder type will be decided later */
ea5b213a 2637 intel_encoder = &intel_sdvo->base;
21d40d37 2638 intel_encoder->type = INTEL_OUTPUT_SDVO;
373a3cf7 2639 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
79e53945 2640
79e53945
JB		 2641 /* Read the regs to test if we can talk to the device */
2642 for (i = 0; i < 0x40; i++) {
f899fc64
CW		 2643 u8 byte;
2644
2645 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
eef4eacb
DV		 2646 DRM_DEBUG_KMS("No SDVO device found on %s\n",
2647 SDVO_NAME(intel_sdvo));
f899fc64 2648 goto err;
79e53945
JB		 2649 }
2650 }
2651
084b612e
CW		 2652 hotplug_mask = 0;
2653 if (IS_G4X(dev)) {
2654 hotplug_mask = intel_sdvo->is_sdvob ?
2655 SDVOB_HOTPLUG_INT_STATUS_G4X : SDVOC_HOTPLUG_INT_STATUS_G4X;
2656 } else if (IS_GEN4(dev)) {
2657 hotplug_mask = intel_sdvo->is_sdvob ?
2658 SDVOB_HOTPLUG_INT_STATUS_I965 : SDVOC_HOTPLUG_INT_STATUS_I965;
2659 } else {
2660 hotplug_mask = intel_sdvo->is_sdvob ?
2661 SDVOB_HOTPLUG_INT_STATUS_I915 : SDVOC_HOTPLUG_INT_STATUS_I915;
2662 }
2663 dev_priv->hotplug_supported_mask |= hotplug_mask;
619ac3b7 2664
4ef69c7a 2665 drm_encoder_helper_add(&intel_encoder->base, &intel_sdvo_helper_funcs);
14571b4c 2666
ce22c320
DV		 2667 intel_encoder->disable = intel_disable_sdvo;
2668 intel_encoder->enable = intel_enable_sdvo;
4ac41f47 2669 intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
ce22c320 2670
af901ca1 2671 /* In default case sdvo lvds is false */
32aad86f 2672 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
f899fc64 2673 goto err;
79e53945 2674
cc68c81a
SF		 2675 /* Set up hotplug command - note paranoia about contents of reply.
2676 * We assume that the hardware is in a sane state, and only touch
2677 * the bits we think we understand.
2678 */
2679 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG,
2680 &intel_sdvo->hotplug_active, 2);
2681 intel_sdvo->hotplug_active[0] &= ~0x3;
2682
ea5b213a
CW		 2683 if (intel_sdvo_output_setup(intel_sdvo,
2684 intel_sdvo->caps.output_flags) != true) {
eef4eacb
DV		 2685 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
2686 SDVO_NAME(intel_sdvo));
f899fc64 2687 goto err;
79e53945
JB		 2688 }
2689
ea5b213a 2690 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
e2f0ba97 2691
79e53945 2692 /* Set the input timing to the screen. Assume always input 0. */
32aad86f 2693 if (!intel_sdvo_set_target_input(intel_sdvo))
f899fc64 2694 goto err;
79e53945 2695
32aad86f
CW		 2696 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
2697 &intel_sdvo->pixel_clock_min,
2698 &intel_sdvo->pixel_clock_max))
f899fc64 2699 goto err;
79e53945 2700
8a4c47f3 2701 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
342dc382 2702 "clock range %dMHz - %dMHz, "
2703 "input 1: %c, input 2: %c, "
2704 "output 1: %c, output 2: %c\n",
ea5b213a
CW		 2705 SDVO_NAME(intel_sdvo),
2706 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
2707 intel_sdvo->caps.device_rev_id,
2708 intel_sdvo->pixel_clock_min / 1000,
2709 intel_sdvo->pixel_clock_max / 1000,
2710 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2711 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
342dc382 2712 /* check currently supported outputs */
ea5b213a 2713 intel_sdvo->caps.output_flags &
79e53945 2714 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
ea5b213a 2715 intel_sdvo->caps.output_flags &
79e53945 2716 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
7d57382e 2717 return true;
79e53945 2718
f899fc64 2719err:
373a3cf7 2720 drm_encoder_cleanup(&intel_encoder->base);
e957d772 2721 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 2722 kfree(intel_sdvo);
79e53945 2723
7d57382e 2724 return false;
79e53945 2725}
Linux 6.x block layer and io_uring tree(s)