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Merge tag 'gvt-next-2017-06-08' of https://github.com/01org/gvt-linux into drm-intel...
[linux-block.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
79e53945 30#include <linux/delay.h>
2d1a8a48 31#include <linux/export.h>
760285e7 32#include <drm/drmP.h>
c6f95f27 33#include <drm/drm_atomic_helper.h>
760285e7
DH		 34#include <drm/drm_crtc.h>
35#include <drm/drm_edid.h>
ea5b213a 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945
JB		 38#include "i915_drv.h"
39#include "intel_sdvo_regs.h"
40
14571b4c
ZW		 41#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
42#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
43#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
a0b1c7a5 44#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
14571b4c
ZW		 45
46#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
0206e353 47 SDVO_TV_MASK)
14571b4c
ZW		 48
49#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
13946743 50#define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
14571b4c 51#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
32aad86f 52#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
52220085 53#define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
14571b4c 54
79e53945 55
4d9194de 56static const char * const tv_format_names[] = {
ce6feabd
ZY		 57 "NTSC_M" , "NTSC_J" , "NTSC_443",
58 "PAL_B" , "PAL_D" , "PAL_G" ,
59 "PAL_H" , "PAL_I" , "PAL_M" ,
60 "PAL_N" , "PAL_NC" , "PAL_60" ,
61 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
62 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
63 "SECAM_60"
64};
65
53abb679 66#define TV_FORMAT_NUM ARRAY_SIZE(tv_format_names)
ce6feabd 67
ea5b213a
CW		 68struct intel_sdvo {
69 struct intel_encoder base;
70
f899fc64 71 struct i2c_adapter *i2c;
f9c10a9b 72 u8 slave_addr;
e2f0ba97 73
e957d772
CW		 74 struct i2c_adapter ddc;
75
e2f0ba97 76 /* Register for the SDVO device: SDVOB or SDVOC */
f0f59a00 77 i915_reg_t sdvo_reg;
79e53945 78
e2f0ba97
JB		 79 /* Active outputs controlled by this SDVO output */
80 uint16_t controlled_output;
79e53945 81
e2f0ba97
JB		 82 /*
83 * Capabilities of the SDVO device returned by
19d415a2 84 * intel_sdvo_get_capabilities()
e2f0ba97 85 */
79e53945 86 struct intel_sdvo_caps caps;
e2f0ba97
JB		 87
88 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 89 int pixel_clock_min, pixel_clock_max;
90
fb7a46f3 91 /*
92 * For multiple function SDVO device,
93 * this is for current attached outputs.
94 */
95 uint16_t attached_output;
96
cc68c81a
SF		 97 /*
98 * Hotplug activation bits for this device
99 */
5fa7ac9c 100 uint16_t hotplug_active;
cc68c81a 101
e2f0ba97
JB		 102 /**
103 * This is set if we're going to treat the device as TV-out.
104 *
105 * While we have these nice friendly flags for output types that ought
106 * to decide this for us, the S-Video output on our HDMI+S-Video card
107 * shows up as RGB1 (VGA).
108 */
109 bool is_tv;
110
2a5c0832 111 enum port port;
eef4eacb 112
e2f0ba97
JB		 113 /**
114 * This is set if we treat the device as HDMI, instead of DVI.
115 */
116 bool is_hdmi;
da79de97
CW		 117 bool has_hdmi_monitor;
118 bool has_hdmi_audio;
abedc077 119 bool rgb_quant_range_selectable;
12682a97 120
7086c87f 121 /**
6c9547ff
CW		 122 * This is set if we detect output of sdvo device as LVDS and
123 * have a valid fixed mode to use with the panel.
7086c87f
ML		 124 */
125 bool is_lvds;
e2f0ba97 126
12682a97 127 /**
128 * This is sdvo fixed pannel mode pointer
129 */
130 struct drm_display_mode *sdvo_lvds_fixed_mode;
131
c751ce4f 132 /* DDC bus used by this SDVO encoder */
e2f0ba97 133 uint8_t ddc_bus;
e751823d
EE		 134
135 /*
136 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd
137 */
138 uint8_t dtd_sdvo_flags;
14571b4c
ZW		 139};
140
141struct intel_sdvo_connector {
615fb93f
CW		 142 struct intel_connector base;
143
14571b4c
ZW		 144 /* Mark the type of connector */
145 uint16_t output_flag;
146
147 /* This contains all current supported TV format */
40039750 148 u8 tv_format_supported[TV_FORMAT_NUM];
14571b4c 149 int format_supported_num;
c5521706 150 struct drm_property *tv_format;
14571b4c 151
b9219c5e 152 /* add the property for the SDVO-TV */
c5521706
CW		 153 struct drm_property *left;
154 struct drm_property *right;
155 struct drm_property *top;
156 struct drm_property *bottom;
157 struct drm_property *hpos;
158 struct drm_property *vpos;
159 struct drm_property *contrast;
160 struct drm_property *saturation;
161 struct drm_property *hue;
162 struct drm_property *sharpness;
163 struct drm_property *flicker_filter;
164 struct drm_property *flicker_filter_adaptive;
165 struct drm_property *flicker_filter_2d;
166 struct drm_property *tv_chroma_filter;
167 struct drm_property *tv_luma_filter;
e044218a 168 struct drm_property *dot_crawl;
b9219c5e
ZY		 169
170 /* add the property for the SDVO-TV/LVDS */
c5521706 171 struct drm_property *brightness;
b9219c5e 172
b9219c5e 173 /* this is to get the range of margin.*/
630d30a4
ML		 174 u32 max_hscan, max_vscan;
175};
176
177struct intel_sdvo_connector_state {
178 /* base.base: tv.saturation/contrast/hue/brightness */
179 struct intel_digital_connector_state base;
180
181 struct {
182 unsigned overscan_h, overscan_v, hpos, vpos, sharpness;
183 unsigned flicker_filter, flicker_filter_2d, flicker_filter_adaptive;
184 unsigned chroma_filter, luma_filter, dot_crawl;
185 } tv;
79e53945
JB		 186};
187
8aca63aa 188static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder)
ea5b213a 189{
8aca63aa 190 return container_of(encoder, struct intel_sdvo, base);
ea5b213a
CW		 191}
192
df0e9248
CW		 193static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
194{
8aca63aa 195 return to_sdvo(intel_attached_encoder(connector));
df0e9248
CW		 196}
197
630d30a4
ML		 198static struct intel_sdvo_connector *
199to_intel_sdvo_connector(struct drm_connector *connector)
200{
201 return container_of(connector, struct intel_sdvo_connector, base.base);
202}
203
204static struct intel_sdvo_connector_state *
205to_intel_sdvo_connector_state(struct drm_connector_state *conn_state)
615fb93f 206{
630d30a4 207 return container_of(conn_state, struct intel_sdvo_connector_state, base.base);
615fb93f
CW		 208}
209
fb7a46f3 210static bool
ea5b213a 211intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
32aad86f
CW		 212static bool
213intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
214 struct intel_sdvo_connector *intel_sdvo_connector,
215 int type);
216static bool
217intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
218 struct intel_sdvo_connector *intel_sdvo_connector);
fb7a46f3 219
79e53945
JB		 220/**
221 * Writes the SDVOB or SDVOC with the given value, but always writes both
222 * SDVOB and SDVOC to work around apparent hardware issues (according to
223 * comments in the BIOS).
224 */
ea5b213a 225static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
79e53945 226{
4ef69c7a 227 struct drm_device *dev = intel_sdvo->base.base.dev;
fac5e23e 228 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945
JB		 229 u32 bval = val, cval = val;
230 int i;
231
2a5c0832 232 if (HAS_PCH_SPLIT(dev_priv)) {
ea5b213a 233 I915_WRITE(intel_sdvo->sdvo_reg, val);
abab6311 234 POSTING_READ(intel_sdvo->sdvo_reg);
e8504ee2
VS		 235 /*
236 * HW workaround, need to write this twice for issue
237 * that may result in first write getting masked.
238 */
6e266956 239 if (HAS_PCH_IBX(dev_priv)) {
e8504ee2
VS		 240 I915_WRITE(intel_sdvo->sdvo_reg, val);
241 POSTING_READ(intel_sdvo->sdvo_reg);
242 }
461ed3ca
ZY		 243 return;
244 }
245
2a5c0832 246 if (intel_sdvo->port == PORT_B)
e2debe91
PZ		 247 cval = I915_READ(GEN3_SDVOC);
248 else
249 bval = I915_READ(GEN3_SDVOB);
250
79e53945
JB		 251 /*
252 * Write the registers twice for luck. Sometimes,
253 * writing them only once doesn't appear to 'stick'.
254 * The BIOS does this too. Yay, magic
255 */
256 for (i = 0; i < 2; i++)
257 {
e2debe91 258 I915_WRITE(GEN3_SDVOB, bval);
abab6311 259 POSTING_READ(GEN3_SDVOB);
e2debe91 260 I915_WRITE(GEN3_SDVOC, cval);
abab6311 261 POSTING_READ(GEN3_SDVOC);
79e53945
JB		 262 }
263}
264
32aad86f 265static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
79e53945 266{
79e53945
JB		 267 struct i2c_msg msgs[] = {
268 {
e957d772 269 .addr = intel_sdvo->slave_addr,
79e53945
JB		 270 .flags = 0,
271 .len = 1,
e957d772 272 .buf = &addr,
79e53945
JB		 273 },
274 {
e957d772 275 .addr = intel_sdvo->slave_addr,
79e53945
JB		 276 .flags = I2C_M_RD,
277 .len = 1,
e957d772 278 .buf = ch,
79e53945
JB		 279 }
280 };
32aad86f 281 int ret;
79e53945 282
f899fc64 283 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
79e53945 284 return true;
79e53945 285
8a4c47f3 286 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 287 return false;
288}
289
79e53945
JB		 290#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
291/** Mapping of command numbers to names, for debug output */
005568be 292static const struct _sdvo_cmd_name {
e2f0ba97 293 u8 cmd;
2e88e40b 294 const char *name;
579627ea 295} __attribute__ ((packed)) sdvo_cmd_names[] = {
0206e353
AJ		 296 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
297 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
339
340 /* Add the op code for SDVO enhancements */
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
385
386 /* HDMI op code */
387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
404 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
405 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
406 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 407};
408
2a5c0832 409#define SDVO_NAME(svdo) ((svdo)->port == PORT_B ? "SDVOB" : "SDVOC")
79e53945 410
ea5b213a 411static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
32aad86f 412 const void *args, int args_len)
79e53945 413{
84fcb469
DV		 414 int i, pos = 0;
415#define BUF_LEN 256
416 char buffer[BUF_LEN];
417
418#define BUF_PRINT(args...) \
419 pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args)
420
79e53945 421
84fcb469
DV		 422 for (i = 0; i < args_len; i++) {
423 BUF_PRINT("%02X ", ((u8 *)args)[i]);
424 }
425 for (; i < 8; i++) {
426 BUF_PRINT(" ");
427 }
04ad327f 428 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
79e53945 429 if (cmd == sdvo_cmd_names[i].cmd) {
84fcb469 430 BUF_PRINT("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 431 break;
432 }
433 }
84fcb469
DV		 434 if (i == ARRAY_SIZE(sdvo_cmd_names)) {
435 BUF_PRINT("(%02X)", cmd);
436 }
437 BUG_ON(pos >= BUF_LEN - 1);
438#undef BUF_PRINT
439#undef BUF_LEN
440
441 DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer);
79e53945 442}
79e53945 443
4d9194de 444static const char * const cmd_status_names[] = {
e957d772
CW		 445 "Power on",
446 "Success",
447 "Not supported",
448 "Invalid arg",
449 "Pending",
450 "Target not specified",
451 "Scaling not supported"
452};
453
32aad86f
CW		 454static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
455 const void *args, int args_len)
79e53945 456{
3bf3f452
BW		 457 u8 *buf, status;
458 struct i2c_msg *msgs;
459 int i, ret = true;
460
0274df3e 461 /* Would be simpler to allocate both in one go ? */
5c67eeb6 462 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL);
3bf3f452
BW		 463 if (!buf)
464 return false;
465
466 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
0274df3e
AC		 467 if (!msgs) {
468 kfree(buf);
3bf3f452 469 return false;
0274df3e 470 }
79e53945 471
ea5b213a 472 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
79e53945
JB		 473
474 for (i = 0; i < args_len; i++) {
e957d772
CW		 475 msgs[i].addr = intel_sdvo->slave_addr;
476 msgs[i].flags = 0;
477 msgs[i].len = 2;
478 msgs[i].buf = buf + 2 *i;
479 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
480 buf[2*i + 1] = ((u8*)args)[i];
481 }
482 msgs[i].addr = intel_sdvo->slave_addr;
483 msgs[i].flags = 0;
484 msgs[i].len = 2;
485 msgs[i].buf = buf + 2*i;
486 buf[2*i + 0] = SDVO_I2C_OPCODE;
487 buf[2*i + 1] = cmd;
488
489 /* the following two are to read the response */
490 status = SDVO_I2C_CMD_STATUS;
491 msgs[i+1].addr = intel_sdvo->slave_addr;
492 msgs[i+1].flags = 0;
493 msgs[i+1].len = 1;
494 msgs[i+1].buf = &status;
495
496 msgs[i+2].addr = intel_sdvo->slave_addr;
497 msgs[i+2].flags = I2C_M_RD;
498 msgs[i+2].len = 1;
499 msgs[i+2].buf = &status;
500
501 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
502 if (ret < 0) {
503 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
3bf3f452
BW		 504 ret = false;
505 goto out;
e957d772
CW		 506 }
507 if (ret != i+3) {
508 /* failure in I2C transfer */
509 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
3bf3f452 510 ret = false;
e957d772
CW		 511 }
512
3bf3f452
BW		 513out:
514 kfree(msgs);
515 kfree(buf);
516 return ret;
79e53945
JB		 517}
518
b5c616a7
CW		 519static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
520 void *response, int response_len)
79e53945 521{
fc37381c 522 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
b5c616a7 523 u8 status;
84fcb469
DV		 524 int i, pos = 0;
525#define BUF_LEN 256
526 char buffer[BUF_LEN];
79e53945 527
d121a5d2 528
b5c616a7
CW		 529 /*
530 * The documentation states that all commands will be
531 * processed within 15µs, and that we need only poll
532 * the status byte a maximum of 3 times in order for the
533 * command to be complete.
534 *
535 * Check 5 times in case the hardware failed to read the docs.
fc37381c
CW		 536 *
537 * Also beware that the first response by many devices is to
538 * reply PENDING and stall for time. TVs are notorious for
539 * requiring longer than specified to complete their replies.
540 * Originally (in the DDX long ago), the delay was only ever 15ms
541 * with an additional delay of 30ms applied for TVs added later after
542 * many experiments. To accommodate both sets of delays, we do a
543 * sequence of slow checks if the device is falling behind and fails
544 * to reply within 5*15µs.
b5c616a7 545 */
d121a5d2
CW		 546 if (!intel_sdvo_read_byte(intel_sdvo,
547 SDVO_I2C_CMD_STATUS,
548 &status))
549 goto log_fail;
550
1ad87e72 551 while ((status == SDVO_CMD_STATUS_PENDING ||
46a3f4a3 552 status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) {
fc37381c
CW		 553 if (retry < 10)
554 msleep(15);
555 else
556 udelay(15);
557
b5c616a7
CW		 558 if (!intel_sdvo_read_byte(intel_sdvo,
559 SDVO_I2C_CMD_STATUS,
560 &status))
d121a5d2
CW		 561 goto log_fail;
562 }
b5c616a7 563
84fcb469
DV		 564#define BUF_PRINT(args...) \
565 pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args)
566
79e53945 567 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
84fcb469 568 BUF_PRINT("(%s)", cmd_status_names[status]);
79e53945 569 else
84fcb469 570 BUF_PRINT("(??? %d)", status);
79e53945 571
b5c616a7
CW		 572 if (status != SDVO_CMD_STATUS_SUCCESS)
573 goto log_fail;
79e53945 574
b5c616a7
CW		 575 /* Read the command response */
576 for (i = 0; i < response_len; i++) {
577 if (!intel_sdvo_read_byte(intel_sdvo,
578 SDVO_I2C_RETURN_0 + i,
579 &((u8 *)response)[i]))
580 goto log_fail;
84fcb469 581 BUF_PRINT(" %02X", ((u8 *)response)[i]);
b5c616a7 582 }
84fcb469
DV		 583 BUG_ON(pos >= BUF_LEN - 1);
584#undef BUF_PRINT
585#undef BUF_LEN
586
587 DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer);
b5c616a7 588 return true;
79e53945 589
b5c616a7 590log_fail:
84fcb469 591 DRM_DEBUG_KMS("%s: R: ... failed\n", SDVO_NAME(intel_sdvo));
b5c616a7 592 return false;
79e53945
JB		 593}
594
5e7234c9 595static int intel_sdvo_get_pixel_multiplier(const struct drm_display_mode *adjusted_mode)
79e53945 596{
aad941d5 597 if (adjusted_mode->crtc_clock >= 100000)
79e53945 598 return 1;
aad941d5 599 else if (adjusted_mode->crtc_clock >= 50000)
79e53945
JB		 600 return 2;
601 else
602 return 4;
603}
604
e957d772
CW		 605static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
606 u8 ddc_bus)
79e53945 607{
d121a5d2 608 /* This must be the immediately preceding write before the i2c xfer */
e957d772
CW		 609 return intel_sdvo_write_cmd(intel_sdvo,
610 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
611 &ddc_bus, 1);
79e53945
JB		 612}
613
32aad86f 614static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
79e53945 615{
d121a5d2
CW		 616 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
617 return false;
618
619 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
32aad86f 620}
79e53945 621
32aad86f
CW		 622static bool
623intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
624{
625 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
626 return false;
79e53945 627
32aad86f
CW		 628 return intel_sdvo_read_response(intel_sdvo, value, len);
629}
79e53945 630
32aad86f
CW		 631static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
632{
633 struct intel_sdvo_set_target_input_args targets = {0};
634 return intel_sdvo_set_value(intel_sdvo,
635 SDVO_CMD_SET_TARGET_INPUT,
636 &targets, sizeof(targets));
79e53945
JB		 637}
638
639/**
640 * Return whether each input is trained.
641 *
642 * This function is making an assumption about the layout of the response,
643 * which should be checked against the docs.
644 */
ea5b213a 645static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
79e53945
JB		 646{
647 struct intel_sdvo_get_trained_inputs_response response;
79e53945 648
1a3665c8 649 BUILD_BUG_ON(sizeof(response) != 1);
32aad86f
CW		 650 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
651 &response, sizeof(response)))
79e53945
JB		 652 return false;
653
654 *input_1 = response.input0_trained;
655 *input_2 = response.input1_trained;
656 return true;
657}
658
ea5b213a 659static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
79e53945
JB		 660 u16 outputs)
661{
32aad86f
CW		 662 return intel_sdvo_set_value(intel_sdvo,
663 SDVO_CMD_SET_ACTIVE_OUTPUTS,
664 &outputs, sizeof(outputs));
79e53945
JB		 665}
666
4ac41f47
DV		 667static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo,
668 u16 *outputs)
669{
670 return intel_sdvo_get_value(intel_sdvo,
671 SDVO_CMD_GET_ACTIVE_OUTPUTS,
672 outputs, sizeof(*outputs));
673}
674
ea5b213a 675static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
79e53945
JB		 676 int mode)
677{
32aad86f 678 u8 state = SDVO_ENCODER_STATE_ON;
79e53945
JB		 679
680 switch (mode) {
681 case DRM_MODE_DPMS_ON:
682 state = SDVO_ENCODER_STATE_ON;
683 break;
684 case DRM_MODE_DPMS_STANDBY:
685 state = SDVO_ENCODER_STATE_STANDBY;
686 break;
687 case DRM_MODE_DPMS_SUSPEND:
688 state = SDVO_ENCODER_STATE_SUSPEND;
689 break;
690 case DRM_MODE_DPMS_OFF:
691 state = SDVO_ENCODER_STATE_OFF;
692 break;
693 }
694
32aad86f
CW		 695 return intel_sdvo_set_value(intel_sdvo,
696 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
79e53945
JB		 697}
698
ea5b213a 699static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
79e53945
JB		 700 int *clock_min,
701 int *clock_max)
702{
703 struct intel_sdvo_pixel_clock_range clocks;
79e53945 704
1a3665c8 705 BUILD_BUG_ON(sizeof(clocks) != 4);
32aad86f
CW		 706 if (!intel_sdvo_get_value(intel_sdvo,
707 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
708 &clocks, sizeof(clocks)))
79e53945
JB		 709 return false;
710
711 /* Convert the values from units of 10 kHz to kHz. */
712 *clock_min = clocks.min * 10;
713 *clock_max = clocks.max * 10;
79e53945
JB		 714 return true;
715}
716
ea5b213a 717static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
79e53945
JB		 718 u16 outputs)
719{
32aad86f
CW		 720 return intel_sdvo_set_value(intel_sdvo,
721 SDVO_CMD_SET_TARGET_OUTPUT,
722 &outputs, sizeof(outputs));
79e53945
JB		 723}
724
ea5b213a 725static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
79e53945
JB		 726 struct intel_sdvo_dtd *dtd)
727{
32aad86f
CW		 728 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
729 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
79e53945
JB		 730}
731
045ac3b5
JB		 732static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
733 struct intel_sdvo_dtd *dtd)
734{
735 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
736 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
737}
738
ea5b213a 739static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 740 struct intel_sdvo_dtd *dtd)
741{
ea5b213a 742 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 743 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
744}
745
ea5b213a 746static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 747 struct intel_sdvo_dtd *dtd)
748{
ea5b213a 749 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 750 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
751}
752
045ac3b5
JB		 753static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo,
754 struct intel_sdvo_dtd *dtd)
755{
756 return intel_sdvo_get_timing(intel_sdvo,
757 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
758}
759
e2f0ba97 760static bool
ea5b213a 761intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 762 uint16_t clock,
763 uint16_t width,
764 uint16_t height)
765{
766 struct intel_sdvo_preferred_input_timing_args args;
e2f0ba97 767
e642c6f1 768 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 769 args.clock = clock;
770 args.width = width;
771 args.height = height;
e642c6f1 772 args.interlace = 0;
12682a97 773
ea5b213a
CW		 774 if (intel_sdvo->is_lvds &&
775 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
776 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
12682a97 777 args.scaled = 1;
778
32aad86f
CW		 779 return intel_sdvo_set_value(intel_sdvo,
780 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
781 &args, sizeof(args));
e2f0ba97
JB		 782}
783
ea5b213a 784static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 785 struct intel_sdvo_dtd *dtd)
786{
1a3665c8
CW		 787 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
788 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
32aad86f
CW		 789 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
790 &dtd->part1, sizeof(dtd->part1)) &&
791 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
792 &dtd->part2, sizeof(dtd->part2));
e2f0ba97 793}
79e53945 794
ea5b213a 795static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
79e53945 796{
32aad86f 797 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
79e53945
JB		 798}
799
e2f0ba97 800static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
32aad86f 801 const struct drm_display_mode *mode)
79e53945 802{
e2f0ba97
JB		 803 uint16_t width, height;
804 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
805 uint16_t h_sync_offset, v_sync_offset;
6651819b 806 int mode_clock;
79e53945 807
1c4a814e
DV		 808 memset(dtd, 0, sizeof(*dtd));
809
c6ebd4c0
DV		 810 width = mode->hdisplay;
811 height = mode->vdisplay;
79e53945
JB		 812
813 /* do some mode translations */
c6ebd4c0
DV		 814 h_blank_len = mode->htotal - mode->hdisplay;
815 h_sync_len = mode->hsync_end - mode->hsync_start;
79e53945 816
c6ebd4c0
DV		 817 v_blank_len = mode->vtotal - mode->vdisplay;
818 v_sync_len = mode->vsync_end - mode->vsync_start;
79e53945 819
c6ebd4c0
DV		 820 h_sync_offset = mode->hsync_start - mode->hdisplay;
821 v_sync_offset = mode->vsync_start - mode->vdisplay;
79e53945 822
6651819b 823 mode_clock = mode->clock;
6651819b
DV		 824 mode_clock /= 10;
825 dtd->part1.clock = mode_clock;
826
e2f0ba97
JB		 827 dtd->part1.h_active = width & 0xff;
828 dtd->part1.h_blank = h_blank_len & 0xff;
829 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 830 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 831 dtd->part1.v_active = height & 0xff;
832 dtd->part1.v_blank = v_blank_len & 0xff;
833 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 834 ((v_blank_len >> 8) & 0xf);
835
171a9e96 836 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 837 dtd->part2.h_sync_width = h_sync_len & 0xff;
838 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 839 (v_sync_len & 0xf);
e2f0ba97 840 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 841 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
842 ((v_sync_len & 0x30) >> 4);
843
e2f0ba97 844 dtd->part2.dtd_flags = 0x18;
59d92bfa
DV		 845 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
846 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
79e53945 847 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
59d92bfa 848 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
79e53945 849 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
59d92bfa 850 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
e2f0ba97 851
e2f0ba97 852 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
e2f0ba97
JB		 853}
854
1c4a814e 855static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode,
32aad86f 856 const struct intel_sdvo_dtd *dtd)
e2f0ba97 857{
1c4a814e
DV		 858 struct drm_display_mode mode = {};
859
860 mode.hdisplay = dtd->part1.h_active;
861 mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
862 mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off;
863 mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
864 mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width;
865 mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
866 mode.htotal = mode.hdisplay + dtd->part1.h_blank;
867 mode.htotal += (dtd->part1.h_high & 0xf) << 8;
868
869 mode.vdisplay = dtd->part1.v_active;
870 mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
871 mode.vsync_start = mode.vdisplay;
872 mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
873 mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
874 mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0;
875 mode.vsync_end = mode.vsync_start +
e2f0ba97 876 (dtd->part2.v_sync_off_width & 0xf);
1c4a814e
DV		 877 mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
878 mode.vtotal = mode.vdisplay + dtd->part1.v_blank;
879 mode.vtotal += (dtd->part1.v_high & 0xf) << 8;
e2f0ba97 880
1c4a814e 881 mode.clock = dtd->part1.clock * 10;
e2f0ba97 882
59d92bfa 883 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
1c4a814e 884 mode.flags |= DRM_MODE_FLAG_INTERLACE;
59d92bfa 885 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
1c4a814e 886 mode.flags |= DRM_MODE_FLAG_PHSYNC;
3cea210f 887 else
1c4a814e 888 mode.flags |= DRM_MODE_FLAG_NHSYNC;
59d92bfa 889 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
1c4a814e 890 mode.flags |= DRM_MODE_FLAG_PVSYNC;
3cea210f 891 else
1c4a814e
DV		 892 mode.flags |= DRM_MODE_FLAG_NVSYNC;
893
894 drm_mode_set_crtcinfo(&mode, 0);
895
896 drm_mode_copy(pmode, &mode);
e2f0ba97
JB		 897}
898
e27d8538 899static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
e2f0ba97 900{
e27d8538 901 struct intel_sdvo_encode encode;
e2f0ba97 902
1a3665c8 903 BUILD_BUG_ON(sizeof(encode) != 2);
e27d8538
CW		 904 return intel_sdvo_get_value(intel_sdvo,
905 SDVO_CMD_GET_SUPP_ENCODE,
906 &encode, sizeof(encode));
e2f0ba97
JB		 907}
908
ea5b213a 909static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
c751ce4f 910 uint8_t mode)
e2f0ba97 911{
32aad86f 912 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
e2f0ba97
JB		 913}
914
ea5b213a 915static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 916 uint8_t mode)
917{
32aad86f 918 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
e2f0ba97
JB		 919}
920
921#if 0
ea5b213a 922static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 923{
924 int i, j;
925 uint8_t set_buf_index[2];
926 uint8_t av_split;
927 uint8_t buf_size;
928 uint8_t buf[48];
929 uint8_t *pos;
930
32aad86f 931 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
e2f0ba97
JB		 932
933 for (i = 0; i <= av_split; i++) {
934 set_buf_index[0] = i; set_buf_index[1] = 0;
c751ce4f 935 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
e2f0ba97 936 set_buf_index, 2);
c751ce4f
EA		 937 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
938 intel_sdvo_read_response(encoder, &buf_size, 1);
e2f0ba97
JB		 939
940 pos = buf;
941 for (j = 0; j <= buf_size; j += 8) {
c751ce4f 942 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
e2f0ba97 943 NULL, 0);
c751ce4f 944 intel_sdvo_read_response(encoder, pos, 8);
e2f0ba97
JB		 945 pos += 8;
946 }
947 }
948}
949#endif
950
b6e0e543
DV		 951static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
952 unsigned if_index, uint8_t tx_rate,
fff63867 953 const uint8_t *data, unsigned length)
b6e0e543
DV		 954{
955 uint8_t set_buf_index[2] = { if_index, 0 };
956 uint8_t hbuf_size, tmp[8];
957 int i;
958
959 if (!intel_sdvo_set_value(intel_sdvo,
960 SDVO_CMD_SET_HBUF_INDEX,
961 set_buf_index, 2))
962 return false;
963
964 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
965 &hbuf_size, 1))
966 return false;
967
968 /* Buffer size is 0 based, hooray! */
969 hbuf_size++;
970
971 DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
972 if_index, length, hbuf_size);
973
974 for (i = 0; i < hbuf_size; i += 8) {
975 memset(tmp, 0, 8);
976 if (i < length)
977 memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
978
979 if (!intel_sdvo_set_value(intel_sdvo,
980 SDVO_CMD_SET_HBUF_DATA,
981 tmp, 8))
982 return false;
983 }
984
985 return intel_sdvo_set_value(intel_sdvo,
986 SDVO_CMD_SET_HBUF_TXRATE,
987 &tx_rate, 1);
988}
989
abedc077 990static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
f9fe0530 991 struct intel_crtc_state *pipe_config)
e2f0ba97 992{
15dcd350 993 uint8_t sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
15dcd350
DL		 994 union hdmi_infoframe frame;
995 int ret;
996 ssize_t len;
997
998 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
f9fe0530 999 &pipe_config->base.adjusted_mode);
15dcd350
DL		 1000 if (ret < 0) {
1001 DRM_ERROR("couldn't fill AVI infoframe\n");
1002 return false;
1003 }
3c17fe4b 1004
abedc077 1005 if (intel_sdvo->rgb_quant_range_selectable) {
f9fe0530 1006 if (pipe_config->limited_color_range)
15dcd350
DL		 1007 frame.avi.quantization_range =
1008 HDMI_QUANTIZATION_RANGE_LIMITED;
abedc077 1009 else
15dcd350
DL		 1010 frame.avi.quantization_range =
1011 HDMI_QUANTIZATION_RANGE_FULL;
abedc077
VS		 1012 }
1013
15dcd350
DL		 1014 len = hdmi_infoframe_pack(&frame, sdvo_data, sizeof(sdvo_data));
1015 if (len < 0)
1016 return false;
81014b9d 1017
b6e0e543
DV		 1018 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
1019 SDVO_HBUF_TX_VSYNC,
1020 sdvo_data, sizeof(sdvo_data));
e2f0ba97
JB		 1021}
1022
630d30a4
ML		 1023static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo,
1024 struct drm_connector_state *conn_state)
7026d4ac 1025{
ce6feabd 1026 struct intel_sdvo_tv_format format;
40039750 1027 uint32_t format_map;
ce6feabd 1028
630d30a4 1029 format_map = 1 << conn_state->tv.mode;
ce6feabd 1030 memset(&format, 0, sizeof(format));
32aad86f 1031 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
ce6feabd 1032
32aad86f
CW		 1033 BUILD_BUG_ON(sizeof(format) != 6);
1034 return intel_sdvo_set_value(intel_sdvo,
1035 SDVO_CMD_SET_TV_FORMAT,
1036 &format, sizeof(format));
7026d4ac
ZW		 1037}
1038
32aad86f
CW		 1039static bool
1040intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
e811f5ae 1041 const struct drm_display_mode *mode)
e2f0ba97 1042{
32aad86f 1043 struct intel_sdvo_dtd output_dtd;
79e53945 1044
32aad86f
CW		 1045 if (!intel_sdvo_set_target_output(intel_sdvo,
1046 intel_sdvo->attached_output))
1047 return false;
e2f0ba97 1048
32aad86f
CW		 1049 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1050 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1051 return false;
e2f0ba97 1052
32aad86f
CW		 1053 return true;
1054}
1055
c9a29698
DV		 1056/* Asks the sdvo controller for the preferred input mode given the output mode.
1057 * Unfortunately we have to set up the full output mode to do that. */
32aad86f 1058static bool
c9a29698 1059intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
e811f5ae 1060 const struct drm_display_mode *mode,
c9a29698 1061 struct drm_display_mode *adjusted_mode)
32aad86f 1062{
c9a29698
DV		 1063 struct intel_sdvo_dtd input_dtd;
1064
32aad86f
CW		 1065 /* Reset the input timing to the screen. Assume always input 0. */
1066 if (!intel_sdvo_set_target_input(intel_sdvo))
1067 return false;
e2f0ba97 1068
32aad86f
CW		 1069 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
1070 mode->clock / 10,
1071 mode->hdisplay,
1072 mode->vdisplay))
1073 return false;
e2f0ba97 1074
32aad86f 1075 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
c9a29698 1076 &input_dtd))
32aad86f 1077 return false;
e2f0ba97 1078
c9a29698 1079 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
e751823d 1080 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags;
79e53945 1081
32aad86f
CW		 1082 return true;
1083}
12682a97 1084
5cec258b 1085static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config)
70484559 1086{
3c52f4eb 1087 unsigned dotclock = pipe_config->port_clock;
70484559
DV		 1088 struct dpll *clock = &pipe_config->dpll;
1089
1090 /* SDVO TV has fixed PLL values depend on its clock range,
1091 this mirrors vbios setting. */
1092 if (dotclock >= 100000 && dotclock < 140500) {
1093 clock->p1 = 2;
1094 clock->p2 = 10;
1095 clock->n = 3;
1096 clock->m1 = 16;
1097 clock->m2 = 8;
1098 } else if (dotclock >= 140500 && dotclock <= 200000) {
1099 clock->p1 = 1;
1100 clock->p2 = 10;
1101 clock->n = 6;
1102 clock->m1 = 12;
1103 clock->m2 = 8;
1104 } else {
1105 WARN(1, "SDVO TV clock out of range: %i\n", dotclock);
1106 }
1107
1108 pipe_config->clock_set = true;
1109}
1110
6cc5f341 1111static bool intel_sdvo_compute_config(struct intel_encoder *encoder,
0a478c27
ML		 1112 struct intel_crtc_state *pipe_config,
1113 struct drm_connector_state *conn_state)
32aad86f 1114{
8aca63aa 1115 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
630d30a4
ML		 1116 struct intel_sdvo_connector_state *intel_sdvo_state =
1117 to_intel_sdvo_connector_state(conn_state);
2d112de7
ACO		 1118 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1119 struct drm_display_mode *mode = &pipe_config->base.mode;
12682a97 1120
5d2d38dd
DV		 1121 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
1122 pipe_config->pipe_bpp = 8*3;
1123
6e266956 1124 if (HAS_PCH_SPLIT(to_i915(encoder->base.dev)))
5bfe2ac0
DV		 1125 pipe_config->has_pch_encoder = true;
1126
32aad86f
CW		 1127 /* We need to construct preferred input timings based on our
1128 * output timings. To do that, we have to set the output
1129 * timings, even though this isn't really the right place in
1130 * the sequence to do it. Oh well.
1131 */
1132 if (intel_sdvo->is_tv) {
1133 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
1134 return false;
12682a97 1135
c9a29698
DV		 1136 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1137 mode,
1138 adjusted_mode);
09ede541 1139 pipe_config->sdvo_tv_clock = true;
ea5b213a 1140 } else if (intel_sdvo->is_lvds) {
32aad86f 1141 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
6c9547ff 1142 intel_sdvo->sdvo_lvds_fixed_mode))
e2f0ba97 1143 return false;
12682a97 1144
c9a29698
DV		 1145 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1146 mode,
1147 adjusted_mode);
e2f0ba97 1148 }
32aad86f
CW		 1149
1150 /* Make the CRTC code factor in the SDVO pixel multiplier. The
6c9547ff 1151 * SDVO device will factor out the multiplier during mode_set.
32aad86f 1152 */
6cc5f341
DV		 1153 pipe_config->pixel_multiplier =
1154 intel_sdvo_get_pixel_multiplier(adjusted_mode);
32aad86f 1155
630d30a4 1156 if (intel_sdvo_state->base.force_audio != HDMI_AUDIO_OFF_DVI)
b32962f8
ML		 1157 pipe_config->has_hdmi_sink = intel_sdvo->has_hdmi_monitor;
1158
630d30a4
ML		 1159 if (intel_sdvo_state->base.force_audio == HDMI_AUDIO_ON ||
1160 (intel_sdvo_state->base.force_audio == HDMI_AUDIO_AUTO && intel_sdvo->has_hdmi_audio))
b32962f8 1161 pipe_config->has_audio = true;
9f04003e 1162
630d30a4 1163 if (intel_sdvo_state->base.broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
55bc60db 1164 /* See CEA-861-E - 5.1 Default Encoding Parameters */
4f3a8bc7
PZ		 1165 /* FIXME: This bit is only valid when using TMDS encoding and 8
1166 * bit per color mode. */
9f04003e 1167 if (pipe_config->has_hdmi_sink &&
18316c8c 1168 drm_match_cea_mode(adjusted_mode) > 1)
69f5acc8
DV		 1169 pipe_config->limited_color_range = true;
1170 } else {
9f04003e 1171 if (pipe_config->has_hdmi_sink &&
630d30a4 1172 intel_sdvo_state->base.broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED)
69f5acc8 1173 pipe_config->limited_color_range = true;
55bc60db
VS		 1174 }
1175
70484559
DV		 1176 /* Clock computation needs to happen after pixel multiplier. */
1177 if (intel_sdvo->is_tv)
1178 i9xx_adjust_sdvo_tv_clock(pipe_config);
1179
7949dd47
VS		 1180 /* Set user selected PAR to incoming mode's member */
1181 if (intel_sdvo->is_hdmi)
0e9f25d0 1182 adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio;
7949dd47 1183
e2f0ba97
JB		 1184 return true;
1185}
1186
630d30a4
ML		 1187#define UPDATE_PROPERTY(input, NAME) \
1188 do { \
1189 val = input; \
1190 intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_##NAME, &val, sizeof(val)); \
1191 } while (0)
1192
1193static void intel_sdvo_update_props(struct intel_sdvo *intel_sdvo,
1194 struct intel_sdvo_connector_state *sdvo_state)
1195{
1196 struct drm_connector_state *conn_state = &sdvo_state->base.base;
1197 struct intel_sdvo_connector *intel_sdvo_conn =
1198 to_intel_sdvo_connector(conn_state->connector);
1199 uint16_t val;
1200
1201 if (intel_sdvo_conn->left)
1202 UPDATE_PROPERTY(sdvo_state->tv.overscan_h, OVERSCAN_H);
1203
1204 if (intel_sdvo_conn->top)
1205 UPDATE_PROPERTY(sdvo_state->tv.overscan_v, OVERSCAN_V);
1206
1207 if (intel_sdvo_conn->hpos)
1208 UPDATE_PROPERTY(sdvo_state->tv.hpos, HPOS);
1209
1210 if (intel_sdvo_conn->vpos)
1211 UPDATE_PROPERTY(sdvo_state->tv.vpos, VPOS);
1212
1213 if (intel_sdvo_conn->saturation)
1214 UPDATE_PROPERTY(conn_state->tv.saturation, SATURATION);
1215
1216 if (intel_sdvo_conn->contrast)
1217 UPDATE_PROPERTY(conn_state->tv.contrast, CONTRAST);
1218
1219 if (intel_sdvo_conn->hue)
1220 UPDATE_PROPERTY(conn_state->tv.hue, HUE);
1221
1222 if (intel_sdvo_conn->brightness)
1223 UPDATE_PROPERTY(conn_state->tv.brightness, BRIGHTNESS);
1224
1225 if (intel_sdvo_conn->sharpness)
1226 UPDATE_PROPERTY(sdvo_state->tv.sharpness, SHARPNESS);
1227
1228 if (intel_sdvo_conn->flicker_filter)
1229 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter, FLICKER_FILTER);
1230
1231 if (intel_sdvo_conn->flicker_filter_2d)
1232 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_2d, FLICKER_FILTER_2D);
1233
1234 if (intel_sdvo_conn->flicker_filter_adaptive)
1235 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
1236
1237 if (intel_sdvo_conn->tv_chroma_filter)
1238 UPDATE_PROPERTY(sdvo_state->tv.chroma_filter, TV_CHROMA_FILTER);
1239
1240 if (intel_sdvo_conn->tv_luma_filter)
1241 UPDATE_PROPERTY(sdvo_state->tv.luma_filter, TV_LUMA_FILTER);
1242
1243 if (intel_sdvo_conn->dot_crawl)
1244 UPDATE_PROPERTY(sdvo_state->tv.dot_crawl, DOT_CRAWL);
1245
1246#undef UPDATE_PROPERTY
1247}
1248
fd6bbda9
ML		 1249static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
1250 struct intel_crtc_state *crtc_state,
1251 struct drm_connector_state *conn_state)
e2f0ba97 1252{
66478475 1253 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
f9fe0530
ML		 1254 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1255 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
630d30a4 1256 struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state(conn_state);
f9fe0530 1257 struct drm_display_mode *mode = &crtc_state->base.mode;
8aca63aa 1258 struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder);
6c9547ff 1259 u32 sdvox;
e2f0ba97 1260 struct intel_sdvo_in_out_map in_out;
6651819b 1261 struct intel_sdvo_dtd input_dtd, output_dtd;
6c9547ff 1262 int rate;
e2f0ba97 1263
630d30a4
ML		 1264 intel_sdvo_update_props(intel_sdvo, sdvo_state);
1265
e2f0ba97
JB		 1266 /* First, set the input mapping for the first input to our controlled
1267 * output. This is only correct if we're a single-input device, in
1268 * which case the first input is the output from the appropriate SDVO
1269 * channel on the motherboard. In a two-input device, the first input
1270 * will be SDVOB and the second SDVOC.
1271 */
ea5b213a 1272 in_out.in0 = intel_sdvo->attached_output;
e2f0ba97
JB		 1273 in_out.in1 = 0;
1274
c74696b9
PR		 1275 intel_sdvo_set_value(intel_sdvo,
1276 SDVO_CMD_SET_IN_OUT_MAP,
1277 &in_out, sizeof(in_out));
e2f0ba97 1278
6c9547ff
CW		 1279 /* Set the output timings to the screen */
1280 if (!intel_sdvo_set_target_output(intel_sdvo,
1281 intel_sdvo->attached_output))
1282 return;
e2f0ba97 1283
6651819b
DV		 1284 /* lvds has a special fixed output timing. */
1285 if (intel_sdvo->is_lvds)
1286 intel_sdvo_get_dtd_from_mode(&output_dtd,
1287 intel_sdvo->sdvo_lvds_fixed_mode);
1288 else
1289 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
c8d4bb54
DV		 1290 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1291 DRM_INFO("Setting output timings on %s failed\n",
1292 SDVO_NAME(intel_sdvo));
79e53945
JB		 1293
1294 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 1295 if (!intel_sdvo_set_target_input(intel_sdvo))
1296 return;
79e53945 1297
f9fe0530 1298 if (crtc_state->has_hdmi_sink) {
97aaf910
CW		 1299 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1300 intel_sdvo_set_colorimetry(intel_sdvo,
1301 SDVO_COLORIMETRY_RGB256);
f9fe0530 1302 intel_sdvo_set_avi_infoframe(intel_sdvo, crtc_state);
97aaf910
CW		 1303 } else
1304 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
7026d4ac 1305
6c9547ff 1306 if (intel_sdvo->is_tv &&
630d30a4 1307 !intel_sdvo_set_tv_format(intel_sdvo, conn_state))
6c9547ff 1308 return;
e2f0ba97 1309
6651819b 1310 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
eeb47937 1311
e751823d
EE		 1312 if (intel_sdvo->is_tv || intel_sdvo->is_lvds)
1313 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
c8d4bb54
DV		 1314 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
1315 DRM_INFO("Setting input timings on %s failed\n",
1316 SDVO_NAME(intel_sdvo));
79e53945 1317
f9fe0530 1318 switch (crtc_state->pixel_multiplier) {
6c9547ff 1319 default:
fd0753cf 1320 WARN(1, "unknown pixel multiplier specified\n");
32aad86f
CW		 1321 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1322 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1323 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
79e53945 1324 }
32aad86f
CW		 1325 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1326 return;
79e53945
JB		 1327
1328 /* Set the SDVO control regs. */
66478475 1329 if (INTEL_GEN(dev_priv) >= 4) {
ba68e086
PZ		 1330 /* The real mode polarity is set by the SDVO commands, using
1331 * struct intel_sdvo_dtd. */
1332 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
6e266956 1333 if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
69f5acc8 1334 sdvox |= HDMI_COLOR_RANGE_16_235;
66478475 1335 if (INTEL_GEN(dev_priv) < 5)
6714afb1 1336 sdvox |= SDVO_BORDER_ENABLE;
e2f0ba97 1337 } else {
6c9547ff 1338 sdvox = I915_READ(intel_sdvo->sdvo_reg);
2a5c0832 1339 if (intel_sdvo->port == PORT_B)
e2f0ba97 1340 sdvox &= SDVOB_PRESERVE_MASK;
2a5c0832 1341 else
e2f0ba97 1342 sdvox &= SDVOC_PRESERVE_MASK;
e2f0ba97
JB		 1343 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1344 }
3573c410 1345
6e266956 1346 if (INTEL_PCH_TYPE(dev_priv) >= PCH_CPT)
eeb47937 1347 sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe);
3573c410 1348 else
eeb47937 1349 sdvox |= SDVO_PIPE_SEL(crtc->pipe);
3573c410 1350
b32962f8 1351 if (crtc_state->has_audio)
6c9547ff 1352 sdvox |= SDVO_AUDIO_ENABLE;
79e53945 1353
66478475 1354 if (INTEL_GEN(dev_priv) >= 4) {
e2f0ba97 1355 /* done in crtc_mode_set as the dpll_md reg must be written early */
50a0bc90 1356 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
73f67aa8 1357 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
e2f0ba97 1358 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945 1359 } else {
f9fe0530 1360 sdvox |= (crtc_state->pixel_multiplier - 1)
6cc5f341 1361 << SDVO_PORT_MULTIPLY_SHIFT;
79e53945
JB		 1362 }
1363
6714afb1 1364 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
66478475 1365 INTEL_GEN(dev_priv) < 5)
12682a97 1366 sdvox |= SDVO_STALL_SELECT;
ea5b213a 1367 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
79e53945
JB		 1368}
1369
4ac41f47 1370static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
79e53945 1371{
4ac41f47
DV		 1372 struct intel_sdvo_connector *intel_sdvo_connector =
1373 to_intel_sdvo_connector(&connector->base);
1374 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base);
2f28c50b 1375 u16 active_outputs = 0;
4ac41f47
DV		 1376
1377 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1378
1379 if (active_outputs & intel_sdvo_connector->output_flag)
1380 return true;
1381 else
1382 return false;
1383}
1384
1385static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
1386 enum pipe *pipe)
1387{
1388 struct drm_device *dev = encoder->base.dev;
fac5e23e 1389 struct drm_i915_private *dev_priv = to_i915(dev);
8aca63aa 1390 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
2f28c50b 1391 u16 active_outputs = 0;
4ac41f47
DV		 1392 u32 tmp;
1393
1394 tmp = I915_READ(intel_sdvo->sdvo_reg);
7a7d1fb7 1395 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
4ac41f47 1396
7a7d1fb7 1397 if (!(tmp & SDVO_ENABLE) && (active_outputs == 0))
4ac41f47
DV		 1398 return false;
1399
6e266956 1400 if (HAS_PCH_CPT(dev_priv))
4ac41f47
DV		 1401 *pipe = PORT_TO_PIPE_CPT(tmp);
1402 else
1403 *pipe = PORT_TO_PIPE(tmp);
1404
1405 return true;
1406}
1407
045ac3b5 1408static void intel_sdvo_get_config(struct intel_encoder *encoder,
5cec258b 1409 struct intel_crtc_state *pipe_config)
045ac3b5 1410{
6c49f241 1411 struct drm_device *dev = encoder->base.dev;
fac5e23e 1412 struct drm_i915_private *dev_priv = to_i915(dev);
8aca63aa 1413 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
045ac3b5 1414 struct intel_sdvo_dtd dtd;
6c49f241 1415 int encoder_pixel_multiplier = 0;
18442d08 1416 int dotclock;
6c49f241
DV		 1417 u32 flags = 0, sdvox;
1418 u8 val;
045ac3b5
JB		 1419 bool ret;
1420
b5a9fa09
DV		 1421 sdvox = I915_READ(intel_sdvo->sdvo_reg);
1422
045ac3b5
JB		 1423 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd);
1424 if (!ret) {
bb760063
DV		 1425 /* Some sdvo encoders are not spec compliant and don't
1426 * implement the mandatory get_timings function. */
045ac3b5 1427 DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n");
bb760063
DV		 1428 pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS;
1429 } else {
1430 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
1431 flags |= DRM_MODE_FLAG_PHSYNC;
1432 else
1433 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1434
bb760063
DV		 1435 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
1436 flags |= DRM_MODE_FLAG_PVSYNC;
1437 else
1438 flags |= DRM_MODE_FLAG_NVSYNC;
045ac3b5
JB		 1439 }
1440
2d112de7 1441 pipe_config->base.adjusted_mode.flags |= flags;
045ac3b5 1442
fdafa9e2
DV		 1443 /*
1444 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in
1445 * the sdvo port register, on all other platforms it is part of the dpll
1446 * state. Since the general pipe state readout happens before the
1447 * encoder->get_config we so already have a valid pixel multplier on all
1448 * other platfroms.
1449 */
50a0bc90 1450 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
6c49f241
DV		 1451 pipe_config->pixel_multiplier =
1452 ((sdvox & SDVO_PORT_MULTIPLY_MASK)
1453 >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
1454 }
045ac3b5 1455
2b85886a 1456 dotclock = pipe_config->port_clock;
e3b247da 1457
2b85886a
VS		 1458 if (pipe_config->pixel_multiplier)
1459 dotclock /= pipe_config->pixel_multiplier;
18442d08 1460
2d112de7 1461 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
18442d08 1462
6c49f241 1463 /* Cross check the port pixel multiplier with the sdvo encoder state. */
53b91408
DL		 1464 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT,
1465 &val, 1)) {
1466 switch (val) {
1467 case SDVO_CLOCK_RATE_MULT_1X:
1468 encoder_pixel_multiplier = 1;
1469 break;
1470 case SDVO_CLOCK_RATE_MULT_2X:
1471 encoder_pixel_multiplier = 2;
1472 break;
1473 case SDVO_CLOCK_RATE_MULT_4X:
1474 encoder_pixel_multiplier = 4;
1475 break;
1476 }
6c49f241 1477 }
fdafa9e2 1478
b5a9fa09
DV		 1479 if (sdvox & HDMI_COLOR_RANGE_16_235)
1480 pipe_config->limited_color_range = true;
1481
9f04003e
DV		 1482 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE,
1483 &val, 1)) {
1484 if (val == SDVO_ENCODE_HDMI)
1485 pipe_config->has_hdmi_sink = true;
1486 }
1487
6c49f241
DV		 1488 WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier,
1489 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
1490 pipe_config->pixel_multiplier, encoder_pixel_multiplier);
045ac3b5
JB		 1491}
1492
fd6bbda9
ML		 1493static void intel_disable_sdvo(struct intel_encoder *encoder,
1494 struct intel_crtc_state *old_crtc_state,
1495 struct drm_connector_state *conn_state)
ce22c320 1496{
fac5e23e 1497 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
8aca63aa 1498 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1612c8bd 1499 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
ce22c320
DV		 1500 u32 temp;
1501
1502 intel_sdvo_set_active_outputs(intel_sdvo, 0);
1503 if (0)
1504 intel_sdvo_set_encoder_power_state(intel_sdvo,
1505 DRM_MODE_DPMS_OFF);
1506
1507 temp = I915_READ(intel_sdvo->sdvo_reg);
776ca7cf 1508
1612c8bd
VS		 1509 temp &= ~SDVO_ENABLE;
1510 intel_sdvo_write_sdvox(intel_sdvo, temp);
1511
1512 /*
1513 * HW workaround for IBX, we need to move the port
1514 * to transcoder A after disabling it to allow the
1515 * matching DP port to be enabled on transcoder A.
1516 */
1517 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
0c241d5b
VS		 1518 /*
1519 * We get CPU/PCH FIFO underruns on the other pipe when
1520 * doing the workaround. Sweep them under the rug.
1521 */
1522 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1523 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1524
1612c8bd
VS		 1525 temp &= ~SDVO_PIPE_B_SELECT;
1526 temp |= SDVO_ENABLE;
1527 intel_sdvo_write_sdvox(intel_sdvo, temp);
1528
1529 temp &= ~SDVO_ENABLE;
1530 intel_sdvo_write_sdvox(intel_sdvo, temp);
0c241d5b 1531
0f0f74bc 1532 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
0c241d5b
VS		 1533 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1534 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
ce22c320
DV		 1535 }
1536}
1537
fd6bbda9
ML		 1538static void pch_disable_sdvo(struct intel_encoder *encoder,
1539 struct intel_crtc_state *old_crtc_state,
1540 struct drm_connector_state *old_conn_state)
3c65d1d1
VS		 1541{
1542}
1543
fd6bbda9
ML		 1544static void pch_post_disable_sdvo(struct intel_encoder *encoder,
1545 struct intel_crtc_state *old_crtc_state,
1546 struct drm_connector_state *old_conn_state)
3c65d1d1 1547{
fd6bbda9 1548 intel_disable_sdvo(encoder, old_crtc_state, old_conn_state);
3c65d1d1
VS		 1549}
1550
fd6bbda9
ML		 1551static void intel_enable_sdvo(struct intel_encoder *encoder,
1552 struct intel_crtc_state *pipe_config,
1553 struct drm_connector_state *conn_state)
ce22c320
DV		 1554{
1555 struct drm_device *dev = encoder->base.dev;
fac5e23e 1556 struct drm_i915_private *dev_priv = to_i915(dev);
8aca63aa 1557 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
ce22c320 1558 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
79e53945 1559 u32 temp;
ce22c320
DV		 1560 bool input1, input2;
1561 int i;
d0a7b6de 1562 bool success;
ce22c320
DV		 1563
1564 temp = I915_READ(intel_sdvo->sdvo_reg);
3c65d1d1
VS		 1565 temp |= SDVO_ENABLE;
1566 intel_sdvo_write_sdvox(intel_sdvo, temp);
776ca7cf 1567
ce22c320 1568 for (i = 0; i < 2; i++)
0f0f74bc 1569 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
ce22c320 1570
d0a7b6de 1571 success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
ce22c320
DV		 1572 /* Warn if the device reported failure to sync.
1573 * A lot of SDVO devices fail to notify of sync, but it's
1574 * a given it the status is a success, we succeeded.
1575 */
d0a7b6de 1576 if (success && !input1) {
ce22c320
DV		 1577 DRM_DEBUG_KMS("First %s output reported failure to "
1578 "sync\n", SDVO_NAME(intel_sdvo));
1579 }
1580
1581 if (0)
1582 intel_sdvo_set_encoder_power_state(intel_sdvo,
1583 DRM_MODE_DPMS_ON);
1584 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
1585}
1586
c19de8eb
DL		 1587static enum drm_mode_status
1588intel_sdvo_mode_valid(struct drm_connector *connector,
1589 struct drm_display_mode *mode)
79e53945 1590{
df0e9248 1591 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
24b23882 1592 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
79e53945
JB		 1593
1594 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1595 return MODE_NO_DBLESCAN;
1596
ea5b213a 1597 if (intel_sdvo->pixel_clock_min > mode->clock)
79e53945
JB		 1598 return MODE_CLOCK_LOW;
1599
ea5b213a 1600 if (intel_sdvo->pixel_clock_max < mode->clock)
79e53945
JB		 1601 return MODE_CLOCK_HIGH;
1602
24b23882
MK		 1603 if (mode->clock > max_dotclk)
1604 return MODE_CLOCK_HIGH;
1605
8545423a 1606 if (intel_sdvo->is_lvds) {
ea5b213a 1607 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
12682a97 1608 return MODE_PANEL;
1609
ea5b213a 1610 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
12682a97 1611 return MODE_PANEL;
1612 }
1613
79e53945
JB		 1614 return MODE_OK;
1615}
1616
ea5b213a 1617static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
79e53945 1618{
1a3665c8 1619 BUILD_BUG_ON(sizeof(*caps) != 8);
e957d772
CW		 1620 if (!intel_sdvo_get_value(intel_sdvo,
1621 SDVO_CMD_GET_DEVICE_CAPS,
1622 caps, sizeof(*caps)))
1623 return false;
1624
1625 DRM_DEBUG_KMS("SDVO capabilities:\n"
1626 " vendor_id: %d\n"
1627 " device_id: %d\n"
1628 " device_rev_id: %d\n"
1629 " sdvo_version_major: %d\n"
1630 " sdvo_version_minor: %d\n"
1631 " sdvo_inputs_mask: %d\n"
1632 " smooth_scaling: %d\n"
1633 " sharp_scaling: %d\n"
1634 " up_scaling: %d\n"
1635 " down_scaling: %d\n"
1636 " stall_support: %d\n"
1637 " output_flags: %d\n",
1638 caps->vendor_id,
1639 caps->device_id,
1640 caps->device_rev_id,
1641 caps->sdvo_version_major,
1642 caps->sdvo_version_minor,
1643 caps->sdvo_inputs_mask,
1644 caps->smooth_scaling,
1645 caps->sharp_scaling,
1646 caps->up_scaling,
1647 caps->down_scaling,
1648 caps->stall_support,
1649 caps->output_flags);
1650
1651 return true;
79e53945
JB		 1652}
1653
5fa7ac9c 1654static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
79e53945 1655{
50a0bc90 1656 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
5fa7ac9c 1657 uint16_t hotplug;
79e53945 1658
50a0bc90 1659 if (!I915_HAS_HOTPLUG(dev_priv))
1d83d957
VS		 1660 return 0;
1661
768b107e
DV		 1662 /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
1663 * on the line. */
50a0bc90 1664 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
5fa7ac9c 1665 return 0;
768b107e 1666
5fa7ac9c
JN		 1667 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1668 &hotplug, sizeof(hotplug)))
1669 return 0;
768b107e 1670
5fa7ac9c 1671 return hotplug;
79e53945
JB		 1672}
1673
cc68c81a 1674static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
79e53945 1675{
8aca63aa 1676 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
79e53945 1677
5fa7ac9c
JN		 1678 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG,
1679 &intel_sdvo->hotplug_active, 2);
79e53945
JB		 1680}
1681
fb7a46f3 1682static bool
ea5b213a 1683intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
fb7a46f3 1684{
bc65212c 1685 /* Is there more than one type of output? */
2294488d 1686 return hweight16(intel_sdvo->caps.output_flags) > 1;
fb7a46f3 1687}
1688
f899fc64 1689static struct edid *
e957d772 1690intel_sdvo_get_edid(struct drm_connector *connector)
f899fc64 1691{
e957d772
CW		 1692 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1693 return drm_get_edid(connector, &sdvo->ddc);
f899fc64
CW		 1694}
1695
ff482d83
CW		 1696/* Mac mini hack -- use the same DDC as the analog connector */
1697static struct edid *
1698intel_sdvo_get_analog_edid(struct drm_connector *connector)
1699{
fac5e23e 1700 struct drm_i915_private *dev_priv = to_i915(connector->dev);
ff482d83 1701
0c1dab89 1702 return drm_get_edid(connector,
3bd7d909 1703 intel_gmbus_get_adapter(dev_priv,
41aa3448 1704 dev_priv->vbt.crt_ddc_pin));
ff482d83
CW		 1705}
1706
c43b5634 1707static enum drm_connector_status
8bf38485 1708intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
9dff6af8 1709{
df0e9248 1710 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
9d1a903d
CW		 1711 enum drm_connector_status status;
1712 struct edid *edid;
9dff6af8 1713
e957d772 1714 edid = intel_sdvo_get_edid(connector);
57cdaf90 1715
ea5b213a 1716 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
e957d772 1717 u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
9d1a903d 1718
7c3f0a27
ZY		 1719 /*
1720 * Don't use the 1 as the argument of DDC bus switch to get
1721 * the EDID. It is used for SDVO SPD ROM.
1722 */
9d1a903d 1723 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
e957d772
CW		 1724 intel_sdvo->ddc_bus = ddc;
1725 edid = intel_sdvo_get_edid(connector);
1726 if (edid)
7c3f0a27 1727 break;
7c3f0a27 1728 }
e957d772
CW		 1729 /*
1730 * If we found the EDID on the other bus,
1731 * assume that is the correct DDC bus.
1732 */
1733 if (edid == NULL)
1734 intel_sdvo->ddc_bus = saved_ddc;
7c3f0a27 1735 }
9d1a903d
CW		 1736
1737 /*
1738 * When there is no edid and no monitor is connected with VGA
1739 * port, try to use the CRT ddc to read the EDID for DVI-connector.
57cdaf90 1740 */
ff482d83
CW		 1741 if (edid == NULL)
1742 edid = intel_sdvo_get_analog_edid(connector);
149c36a3 1743
2f551c84 1744 status = connector_status_unknown;
9dff6af8 1745 if (edid != NULL) {
149c36a3 1746 /* DDC bus is shared, match EDID to connector type */
9d1a903d
CW		 1747 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1748 status = connector_status_connected;
da79de97
CW		 1749 if (intel_sdvo->is_hdmi) {
1750 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
1751 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
abedc077
VS		 1752 intel_sdvo->rgb_quant_range_selectable =
1753 drm_rgb_quant_range_selectable(edid);
da79de97 1754 }
13946743
CW		 1755 } else
1756 status = connector_status_disconnected;
9d1a903d
CW		 1757 kfree(edid);
1758 }
7f36e7ed 1759
2b8d33f7 1760 return status;
9dff6af8
ML		 1761}
1762
52220085
CW		 1763static bool
1764intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
1765 struct edid *edid)
1766{
1767 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1768 bool connector_is_digital = !!IS_DIGITAL(sdvo);
1769
1770 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
1771 connector_is_digital, monitor_is_digital);
1772 return connector_is_digital == monitor_is_digital;
1773}
1774
7b334fcb 1775static enum drm_connector_status
930a9e28 1776intel_sdvo_detect(struct drm_connector *connector, bool force)
79e53945 1777{
fb7a46f3 1778 uint16_t response;
df0e9248 1779 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1780 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
14571b4c 1781 enum drm_connector_status ret;
79e53945 1782
164c8598 1783 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 1784 connector->base.id, connector->name);
164c8598 1785
fc37381c
CW		 1786 if (!intel_sdvo_get_value(intel_sdvo,
1787 SDVO_CMD_GET_ATTACHED_DISPLAYS,
1788 &response, 2))
32aad86f 1789 return connector_status_unknown;
79e53945 1790
e957d772
CW		 1791 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
1792 response & 0xff, response >> 8,
1793 intel_sdvo_connector->output_flag);
e2f0ba97 1794
fb7a46f3 1795 if (response == 0)
79e53945 1796 return connector_status_disconnected;
fb7a46f3 1797
ea5b213a 1798 intel_sdvo->attached_output = response;
14571b4c 1799
97aaf910
CW		 1800 intel_sdvo->has_hdmi_monitor = false;
1801 intel_sdvo->has_hdmi_audio = false;
abedc077 1802 intel_sdvo->rgb_quant_range_selectable = false;
97aaf910 1803
615fb93f 1804 if ((intel_sdvo_connector->output_flag & response) == 0)
14571b4c 1805 ret = connector_status_disconnected;
13946743 1806 else if (IS_TMDS(intel_sdvo_connector))
8bf38485 1807 ret = intel_sdvo_tmds_sink_detect(connector);
13946743
CW		 1808 else {
1809 struct edid *edid;
1810
1811 /* if we have an edid check it matches the connection */
1812 edid = intel_sdvo_get_edid(connector);
1813 if (edid == NULL)
1814 edid = intel_sdvo_get_analog_edid(connector);
1815 if (edid != NULL) {
52220085
CW		 1816 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
1817 edid))
13946743 1818 ret = connector_status_connected;
52220085
CW		 1819 else
1820 ret = connector_status_disconnected;
1821
13946743
CW		 1822 kfree(edid);
1823 } else
1824 ret = connector_status_connected;
1825 }
14571b4c
ZW		 1826
1827 /* May update encoder flag for like clock for SDVO TV, etc.*/
1828 if (ret == connector_status_connected) {
ea5b213a
CW		 1829 intel_sdvo->is_tv = false;
1830 intel_sdvo->is_lvds = false;
14571b4c 1831
09ede541 1832 if (response & SDVO_TV_MASK)
ea5b213a 1833 intel_sdvo->is_tv = true;
14571b4c 1834 if (response & SDVO_LVDS_MASK)
8545423a 1835 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
fb7a46f3 1836 }
14571b4c
ZW		 1837
1838 return ret;
79e53945
JB		 1839}
1840
e2f0ba97 1841static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945 1842{
ff482d83 1843 struct edid *edid;
79e53945 1844
46a3f4a3 1845 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 1846 connector->base.id, connector->name);
46a3f4a3 1847
79e53945 1848 /* set the bus switch and get the modes */
e957d772 1849 edid = intel_sdvo_get_edid(connector);
79e53945 1850
57cdaf90
KP		 1851 /*
1852 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1853 * link between analog and digital outputs. So, if the regular SDVO
1854 * DDC fails, check to see if the analog output is disconnected, in
1855 * which case we'll look there for the digital DDC data.
e2f0ba97 1856 */
f899fc64
CW		 1857 if (edid == NULL)
1858 edid = intel_sdvo_get_analog_edid(connector);
1859
ff482d83 1860 if (edid != NULL) {
52220085
CW		 1861 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
1862 edid)) {
0c1dab89
CW		 1863 drm_mode_connector_update_edid_property(connector, edid);
1864 drm_add_edid_modes(connector, edid);
1865 }
13946743 1866
ff482d83 1867 kfree(edid);
e2f0ba97 1868 }
e2f0ba97
JB		 1869}
1870
1871/*
1872 * Set of SDVO TV modes.
1873 * Note! This is in reply order (see loop in get_tv_modes).
1874 * XXX: all 60Hz refresh?
1875 */
b1f559ec 1876static const struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1877 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1878 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1879 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1880 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1881 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1882 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1883 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1884 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1885 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1886 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1887 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1888 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1889 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1890 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1891 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1892 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1893 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1894 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1895 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1896 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1897 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1898 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1899 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1900 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1901 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1902 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1903 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1904 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1905 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1906 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1907 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1908 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1909 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1910 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1911 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1912 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1913 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1914 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1915 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1916 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1917 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1918 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1919 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1920 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1921 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1922 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1923 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1924 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1925 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1926 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1927 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1928 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1929 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1930 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1931 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1932 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1933 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1934};
1935
1936static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1937{
df0e9248 1938 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
630d30a4 1939 const struct drm_connector_state *conn_state = connector->state;
7026d4ac 1940 struct intel_sdvo_sdtv_resolution_request tv_res;
ce6feabd
ZY		 1941 uint32_t reply = 0, format_map = 0;
1942 int i;
e2f0ba97 1943
46a3f4a3 1944 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 1945 connector->base.id, connector->name);
46a3f4a3 1946
e2f0ba97
JB		 1947 /* Read the list of supported input resolutions for the selected TV
1948 * format.
1949 */
630d30a4 1950 format_map = 1 << conn_state->tv.mode;
ce6feabd 1951 memcpy(&tv_res, &format_map,
32aad86f 1952 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
ce6feabd 1953
32aad86f
CW		 1954 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1955 return;
ce6feabd 1956
32aad86f 1957 BUILD_BUG_ON(sizeof(tv_res) != 3);
e957d772
CW		 1958 if (!intel_sdvo_write_cmd(intel_sdvo,
1959 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
32aad86f
CW		 1960 &tv_res, sizeof(tv_res)))
1961 return;
1962 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
e2f0ba97
JB		 1963 return;
1964
1965 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 1966 if (reply & (1 << i)) {
1967 struct drm_display_mode *nmode;
1968 nmode = drm_mode_duplicate(connector->dev,
32aad86f 1969 &sdvo_tv_modes[i]);
7026d4ac
ZW		 1970 if (nmode)
1971 drm_mode_probed_add(connector, nmode);
1972 }
e2f0ba97
JB		 1973}
1974
7086c87f
ML		 1975static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1976{
df0e9248 1977 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
fac5e23e 1978 struct drm_i915_private *dev_priv = to_i915(connector->dev);
12682a97 1979 struct drm_display_mode *newmode;
7086c87f 1980
46a3f4a3 1981 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 1982 connector->base.id, connector->name);
46a3f4a3 1983
7086c87f 1984 /*
c3456fb3 1985 * Fetch modes from VBT. For SDVO prefer the VBT mode since some
4300a0f8 1986 * SDVO->LVDS transcoders can't cope with the EDID mode.
7086c87f 1987 */
41aa3448 1988 if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) {
7086c87f 1989 newmode = drm_mode_duplicate(connector->dev,
41aa3448 1990 dev_priv->vbt.sdvo_lvds_vbt_mode);
7086c87f
ML		 1991 if (newmode != NULL) {
1992 /* Guarantee the mode is preferred */
1993 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1994 DRM_MODE_TYPE_DRIVER);
1995 drm_mode_probed_add(connector, newmode);
1996 }
1997 }
12682a97 1998
4300a0f8
DA		 1999 /*
2000 * Attempt to get the mode list from DDC.
2001 * Assume that the preferred modes are
2002 * arranged in priority order.
2003 */
2004 intel_ddc_get_modes(connector, &intel_sdvo->ddc);
2005
12682a97 2006 list_for_each_entry(newmode, &connector->probed_modes, head) {
2007 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
ea5b213a 2008 intel_sdvo->sdvo_lvds_fixed_mode =
12682a97 2009 drm_mode_duplicate(connector->dev, newmode);
6c9547ff 2010
8545423a 2011 intel_sdvo->is_lvds = true;
12682a97 2012 break;
2013 }
2014 }
7086c87f
ML		 2015}
2016
e2f0ba97
JB		 2017static int intel_sdvo_get_modes(struct drm_connector *connector)
2018{
615fb93f 2019 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e2f0ba97 2020
615fb93f 2021 if (IS_TV(intel_sdvo_connector))
e2f0ba97 2022 intel_sdvo_get_tv_modes(connector);
615fb93f 2023 else if (IS_LVDS(intel_sdvo_connector))
7086c87f 2024 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 2025 else
2026 intel_sdvo_get_ddc_modes(connector);
2027
32aad86f 2028 return !list_empty(&connector->probed_modes);
79e53945
JB		 2029}
2030
2031static void intel_sdvo_destroy(struct drm_connector *connector)
2032{
615fb93f 2033 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
79e53945 2034
79e53945 2035 drm_connector_cleanup(connector);
4b745b1e 2036 kfree(intel_sdvo_connector);
79e53945
JB		 2037}
2038
ce6feabd 2039static int
630d30a4
ML		 2040intel_sdvo_connector_atomic_get_property(struct drm_connector *connector,
2041 const struct drm_connector_state *state,
2042 struct drm_property *property,
2043 uint64_t *val)
ce6feabd 2044{
615fb93f 2045 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
630d30a4 2046 const struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state((void *)state);
c5521706
CW		 2047
2048 if (property == intel_sdvo_connector->tv_format) {
630d30a4 2049 int i;
b9219c5e 2050
630d30a4
ML		 2051 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
2052 if (state->tv.mode == intel_sdvo_connector->tv_format_supported[i]) {
2053 *val = i;
b9219c5e 2054
32aad86f 2055 return 0;
630d30a4 2056 }
b9219c5e 2057
630d30a4
ML		 2058 WARN_ON(1);
2059 *val = 0;
2060 } else if (property == intel_sdvo_connector->top ||
2061 property == intel_sdvo_connector->bottom)
2062 *val = intel_sdvo_connector->max_vscan - sdvo_state->tv.overscan_v;
2063 else if (property == intel_sdvo_connector->left ||
2064 property == intel_sdvo_connector->right)
2065 *val = intel_sdvo_connector->max_hscan - sdvo_state->tv.overscan_h;
2066 else if (property == intel_sdvo_connector->hpos)
2067 *val = sdvo_state->tv.hpos;
2068 else if (property == intel_sdvo_connector->vpos)
2069 *val = sdvo_state->tv.vpos;
2070 else if (property == intel_sdvo_connector->saturation)
2071 *val = state->tv.saturation;
2072 else if (property == intel_sdvo_connector->contrast)
2073 *val = state->tv.contrast;
2074 else if (property == intel_sdvo_connector->hue)
2075 *val = state->tv.hue;
2076 else if (property == intel_sdvo_connector->brightness)
2077 *val = state->tv.brightness;
2078 else if (property == intel_sdvo_connector->sharpness)
2079 *val = sdvo_state->tv.sharpness;
2080 else if (property == intel_sdvo_connector->flicker_filter)
2081 *val = sdvo_state->tv.flicker_filter;
2082 else if (property == intel_sdvo_connector->flicker_filter_2d)
2083 *val = sdvo_state->tv.flicker_filter_2d;
2084 else if (property == intel_sdvo_connector->flicker_filter_adaptive)
2085 *val = sdvo_state->tv.flicker_filter_adaptive;
2086 else if (property == intel_sdvo_connector->tv_chroma_filter)
2087 *val = sdvo_state->tv.chroma_filter;
2088 else if (property == intel_sdvo_connector->tv_luma_filter)
2089 *val = sdvo_state->tv.luma_filter;
2090 else if (property == intel_sdvo_connector->dot_crawl)
2091 *val = sdvo_state->tv.dot_crawl;
2092 else
2093 return intel_digital_connector_atomic_get_property(connector, state, property, val);
32aad86f 2094
630d30a4
ML		 2095 return 0;
2096}
b9219c5e 2097
630d30a4
ML		 2098static int
2099intel_sdvo_connector_atomic_set_property(struct drm_connector *connector,
2100 struct drm_connector_state *state,
2101 struct drm_property *property,
2102 uint64_t val)
2103{
2104 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2105 struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state(state);
b9219c5e 2106
630d30a4
ML		 2107 if (property == intel_sdvo_connector->tv_format) {
2108 state->tv.mode = intel_sdvo_connector->tv_format_supported[val];
b9219c5e 2109
630d30a4
ML		 2110 if (state->crtc) {
2111 struct drm_crtc_state *crtc_state =
2112 drm_atomic_get_new_crtc_state(state->state, state->crtc);
b9219c5e 2113
630d30a4
ML		 2114 crtc_state->connectors_changed = true;
2115 }
2116 } else if (property == intel_sdvo_connector->top ||
2117 property == intel_sdvo_connector->bottom)
2118 /* Cannot set these independent from each other */
2119 sdvo_state->tv.overscan_v = intel_sdvo_connector->max_vscan - val;
2120 else if (property == intel_sdvo_connector->left ||
2121 property == intel_sdvo_connector->right)
2122 /* Cannot set these independent from each other */
2123 sdvo_state->tv.overscan_h = intel_sdvo_connector->max_hscan - val;
2124 else if (property == intel_sdvo_connector->hpos)
2125 sdvo_state->tv.hpos = val;
2126 else if (property == intel_sdvo_connector->vpos)
2127 sdvo_state->tv.vpos = val;
2128 else if (property == intel_sdvo_connector->saturation)
2129 state->tv.saturation = val;
2130 else if (property == intel_sdvo_connector->contrast)
2131 state->tv.contrast = val;
2132 else if (property == intel_sdvo_connector->hue)
2133 state->tv.hue = val;
2134 else if (property == intel_sdvo_connector->brightness)
2135 state->tv.brightness = val;
2136 else if (property == intel_sdvo_connector->sharpness)
2137 sdvo_state->tv.sharpness = val;
2138 else if (property == intel_sdvo_connector->flicker_filter)
2139 sdvo_state->tv.flicker_filter = val;
2140 else if (property == intel_sdvo_connector->flicker_filter_2d)
2141 sdvo_state->tv.flicker_filter_2d = val;
2142 else if (property == intel_sdvo_connector->flicker_filter_adaptive)
2143 sdvo_state->tv.flicker_filter_adaptive = val;
2144 else if (property == intel_sdvo_connector->tv_chroma_filter)
2145 sdvo_state->tv.chroma_filter = val;
2146 else if (property == intel_sdvo_connector->tv_luma_filter)
2147 sdvo_state->tv.luma_filter = val;
2148 else if (property == intel_sdvo_connector->dot_crawl)
2149 sdvo_state->tv.dot_crawl = val;
2150 else
2151 return intel_digital_connector_atomic_set_property(connector, state, property, val);
c5521706 2152
32aad86f 2153 return 0;
ce6feabd
ZY		 2154}
2155
7a418e34
CW		 2156static int
2157intel_sdvo_connector_register(struct drm_connector *connector)
2158{
2159 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1ebaa0b9
CW		 2160 int ret;
2161
2162 ret = intel_connector_register(connector);
2163 if (ret)
2164 return ret;
7a418e34
CW		 2165
2166 return sysfs_create_link(&connector->kdev->kobj,
2167 &sdvo->ddc.dev.kobj,
2168 sdvo->ddc.dev.kobj.name);
2169}
2170
c191eca1
CW		 2171static void
2172intel_sdvo_connector_unregister(struct drm_connector *connector)
2173{
2174 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
2175
2176 sysfs_remove_link(&connector->kdev->kobj,
2177 sdvo->ddc.dev.kobj.name);
2178 intel_connector_unregister(connector);
2179}
2180
630d30a4
ML		 2181static struct drm_connector_state *
2182intel_sdvo_connector_duplicate_state(struct drm_connector *connector)
2183{
2184 struct intel_sdvo_connector_state *state;
2185
2186 state = kmemdup(connector->state, sizeof(*state), GFP_KERNEL);
2187 if (!state)
2188 return NULL;
2189
2190 __drm_atomic_helper_connector_duplicate_state(connector, &state->base.base);
2191 return &state->base.base;
2192}
2193
79e53945 2194static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
4d688a2a 2195 .dpms = drm_atomic_helper_connector_dpms,
79e53945
JB		 2196 .detect = intel_sdvo_detect,
2197 .fill_modes = drm_helper_probe_single_connector_modes,
630d30a4
ML		 2198 .set_property = drm_atomic_helper_connector_set_property,
2199 .atomic_get_property = intel_sdvo_connector_atomic_get_property,
2200 .atomic_set_property = intel_sdvo_connector_atomic_set_property,
7a418e34 2201 .late_register = intel_sdvo_connector_register,
c191eca1 2202 .early_unregister = intel_sdvo_connector_unregister,
79e53945 2203 .destroy = intel_sdvo_destroy,
c6f95f27 2204 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
630d30a4 2205 .atomic_duplicate_state = intel_sdvo_connector_duplicate_state,
79e53945
JB		 2206};
2207
630d30a4
ML		 2208static int intel_sdvo_atomic_check(struct drm_connector *conn,
2209 struct drm_connector_state *new_conn_state)
2210{
2211 struct drm_atomic_state *state = new_conn_state->state;
2212 struct drm_connector_state *old_conn_state =
2213 drm_atomic_get_old_connector_state(state, conn);
2214 struct intel_sdvo_connector_state *old_state =
2215 to_intel_sdvo_connector_state(old_conn_state);
2216 struct intel_sdvo_connector_state *new_state =
2217 to_intel_sdvo_connector_state(new_conn_state);
2218
2219 if (new_conn_state->crtc &&
2220 (memcmp(&old_state->tv, &new_state->tv, sizeof(old_state->tv)) ||
2221 memcmp(&old_conn_state->tv, &new_conn_state->tv, sizeof(old_conn_state->tv)))) {
2222 struct drm_crtc_state *crtc_state =
2223 drm_atomic_get_new_crtc_state(new_conn_state->state,
2224 new_conn_state->crtc);
2225
2226 crtc_state->connectors_changed = true;
2227 }
2228
2229 return intel_digital_connector_atomic_check(conn, new_conn_state);
2230}
2231
79e53945
JB		 2232static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
2233 .get_modes = intel_sdvo_get_modes,
2234 .mode_valid = intel_sdvo_mode_valid,
630d30a4 2235 .atomic_check = intel_sdvo_atomic_check,
79e53945
JB		 2236};
2237
b358d0a6 2238static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945 2239{
8aca63aa 2240 struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder));
d2a82a6f 2241
ea5b213a 2242 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
d2a82a6f 2243 drm_mode_destroy(encoder->dev,
ea5b213a 2244 intel_sdvo->sdvo_lvds_fixed_mode);
d2a82a6f 2245
e957d772 2246 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 2247 intel_encoder_destroy(encoder);
79e53945
JB		 2248}
2249
2250static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
2251 .destroy = intel_sdvo_enc_destroy,
2252};
2253
b66d8424
CW		 2254static void
2255intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
2256{
2257 uint16_t mask = 0;
2258 unsigned int num_bits;
2259
2260 /* Make a mask of outputs less than or equal to our own priority in the
2261 * list.
2262 */
2263 switch (sdvo->controlled_output) {
2264 case SDVO_OUTPUT_LVDS1:
2265 mask |= SDVO_OUTPUT_LVDS1;
2266 case SDVO_OUTPUT_LVDS0:
2267 mask |= SDVO_OUTPUT_LVDS0;
2268 case SDVO_OUTPUT_TMDS1:
2269 mask |= SDVO_OUTPUT_TMDS1;
2270 case SDVO_OUTPUT_TMDS0:
2271 mask |= SDVO_OUTPUT_TMDS0;
2272 case SDVO_OUTPUT_RGB1:
2273 mask |= SDVO_OUTPUT_RGB1;
2274 case SDVO_OUTPUT_RGB0:
2275 mask |= SDVO_OUTPUT_RGB0;
2276 break;
2277 }
2278
2279 /* Count bits to find what number we are in the priority list. */
2280 mask &= sdvo->caps.output_flags;
2281 num_bits = hweight16(mask);
2282 /* If more than 3 outputs, default to DDC bus 3 for now. */
2283 if (num_bits > 3)
2284 num_bits = 3;
2285
2286 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
2287 sdvo->ddc_bus = 1 << num_bits;
2288}
79e53945 2289
e2f0ba97
JB		 2290/**
2291 * Choose the appropriate DDC bus for control bus switch command for this
2292 * SDVO output based on the controlled output.
2293 *
2294 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
2295 * outputs, then LVDS outputs.
2296 */
2297static void
b1083333 2298intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
8bd864b8 2299 struct intel_sdvo *sdvo)
e2f0ba97 2300{
b1083333 2301 struct sdvo_device_mapping *mapping;
e2f0ba97 2302
2a5c0832 2303 if (sdvo->port == PORT_B)
9d6c875d 2304 mapping = &dev_priv->vbt.sdvo_mappings[0];
b1083333 2305 else
9d6c875d 2306 mapping = &dev_priv->vbt.sdvo_mappings[1];
e2f0ba97 2307
b66d8424
CW		 2308 if (mapping->initialized)
2309 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
2310 else
2311 intel_sdvo_guess_ddc_bus(sdvo);
e2f0ba97
JB		 2312}
2313
e957d772
CW		 2314static void
2315intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
8bd864b8 2316 struct intel_sdvo *sdvo)
e957d772
CW		 2317{
2318 struct sdvo_device_mapping *mapping;
46eb3036 2319 u8 pin;
e957d772 2320
2a5c0832 2321 if (sdvo->port == PORT_B)
9d6c875d 2322 mapping = &dev_priv->vbt.sdvo_mappings[0];
e957d772 2323 else
9d6c875d 2324 mapping = &dev_priv->vbt.sdvo_mappings[1];
e957d772 2325
88ac7939
JN		 2326 if (mapping->initialized &&
2327 intel_gmbus_is_valid_pin(dev_priv, mapping->i2c_pin))
e957d772 2328 pin = mapping->i2c_pin;
6cb1612a 2329 else
988c7015 2330 pin = GMBUS_PIN_DPB;
e957d772 2331
6cb1612a
JN		 2332 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
2333
2334 /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow
2335 * our code totally fails once we start using gmbus. Hence fall back to
2336 * bit banging for now. */
2337 intel_gmbus_force_bit(sdvo->i2c, true);
e957d772
CW		 2338}
2339
fbfcc4f3
JN		 2340/* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */
2341static void
2342intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo)
2343{
2344 intel_gmbus_force_bit(sdvo->i2c, false);
e957d772
CW		 2345}
2346
e2f0ba97 2347static bool
e27d8538 2348intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
e2f0ba97 2349{
97aaf910 2350 return intel_sdvo_check_supp_encode(intel_sdvo);
e2f0ba97
JB		 2351}
2352
714605e4 2353static u8
c39055b0
ACO		 2354intel_sdvo_get_slave_addr(struct drm_i915_private *dev_priv,
2355 struct intel_sdvo *sdvo)
714605e4 2356{
714605e4 2357 struct sdvo_device_mapping *my_mapping, *other_mapping;
2358
2a5c0832 2359 if (sdvo->port == PORT_B) {
9d6c875d
JN		 2360 my_mapping = &dev_priv->vbt.sdvo_mappings[0];
2361 other_mapping = &dev_priv->vbt.sdvo_mappings[1];
714605e4 2362 } else {
9d6c875d
JN		 2363 my_mapping = &dev_priv->vbt.sdvo_mappings[1];
2364 other_mapping = &dev_priv->vbt.sdvo_mappings[0];
714605e4 2365 }
2366
2367 /* If the BIOS described our SDVO device, take advantage of it. */
2368 if (my_mapping->slave_addr)
2369 return my_mapping->slave_addr;
2370
2371 /* If the BIOS only described a different SDVO device, use the
2372 * address that it isn't using.
2373 */
2374 if (other_mapping->slave_addr) {
2375 if (other_mapping->slave_addr == 0x70)
2376 return 0x72;
2377 else
2378 return 0x70;
2379 }
2380
2381 /* No SDVO device info is found for another DVO port,
2382 * so use mapping assumption we had before BIOS parsing.
2383 */
2a5c0832 2384 if (sdvo->port == PORT_B)
714605e4 2385 return 0x70;
2386 else
2387 return 0x72;
2388}
2389
c393454d 2390static int
df0e9248
CW		 2391intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
2392 struct intel_sdvo *encoder)
14571b4c 2393{
c393454d
ID		 2394 struct drm_connector *drm_connector;
2395 int ret;
2396
2397 drm_connector = &connector->base.base;
2398 ret = drm_connector_init(encoder->base.base.dev,
2399 drm_connector,
df0e9248
CW		 2400 &intel_sdvo_connector_funcs,
2401 connector->base.base.connector_type);
c393454d
ID		 2402 if (ret < 0)
2403 return ret;
6070a4a9 2404
c393454d 2405 drm_connector_helper_add(drm_connector,
df0e9248 2406 &intel_sdvo_connector_helper_funcs);
14571b4c 2407
8f4839e2 2408 connector->base.base.interlace_allowed = 1;
df0e9248
CW		 2409 connector->base.base.doublescan_allowed = 0;
2410 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
4ac41f47 2411 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
14571b4c 2412
df0e9248 2413 intel_connector_attach_encoder(&connector->base, &encoder->base);
c393454d
ID		 2414
2415 return 0;
14571b4c 2416}
6070a4a9 2417
7f36e7ed 2418static void
55bc60db
VS		 2419intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
2420 struct intel_sdvo_connector *connector)
7f36e7ed 2421{
646d5772 2422 struct drm_i915_private *dev_priv = to_i915(connector->base.base.dev);
7f36e7ed 2423
3f43c48d 2424 intel_attach_force_audio_property(&connector->base.base);
646d5772 2425 if (INTEL_GEN(dev_priv) >= 4 && IS_MOBILE(dev_priv)) {
e953fd7b 2426 intel_attach_broadcast_rgb_property(&connector->base.base);
55bc60db 2427 }
7949dd47 2428 intel_attach_aspect_ratio_property(&connector->base.base);
0e9f25d0 2429 connector->base.base.state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
7f36e7ed
CW		 2430}
2431
08d9bc92
ACO		 2432static struct intel_sdvo_connector *intel_sdvo_connector_alloc(void)
2433{
2434 struct intel_sdvo_connector *sdvo_connector;
630d30a4 2435 struct intel_sdvo_connector_state *conn_state;
08d9bc92
ACO		 2436
2437 sdvo_connector = kzalloc(sizeof(*sdvo_connector), GFP_KERNEL);
2438 if (!sdvo_connector)
2439 return NULL;
2440
630d30a4
ML		 2441 conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL);
2442 if (!conn_state) {
08d9bc92
ACO		 2443 kfree(sdvo_connector);
2444 return NULL;
2445 }
2446
630d30a4
ML		 2447 __drm_atomic_helper_connector_reset(&sdvo_connector->base.base,
2448 &conn_state->base.base);
2449
08d9bc92
ACO		 2450 return sdvo_connector;
2451}
2452
fb7a46f3 2453static bool
ea5b213a 2454intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
fb7a46f3 2455{
4ef69c7a 2456 struct drm_encoder *encoder = &intel_sdvo->base.base;
14571b4c 2457 struct drm_connector *connector;
cc68c81a 2458 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
14571b4c 2459 struct intel_connector *intel_connector;
615fb93f 2460 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2461
46a3f4a3
CW		 2462 DRM_DEBUG_KMS("initialising DVI device %d\n", device);
2463
08d9bc92 2464 intel_sdvo_connector = intel_sdvo_connector_alloc();
615fb93f 2465 if (!intel_sdvo_connector)
14571b4c
ZW		 2466 return false;
2467
14571b4c 2468 if (device == 0) {
ea5b213a 2469 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
615fb93f 2470 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
14571b4c 2471 } else if (device == 1) {
ea5b213a 2472 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
615fb93f 2473 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
14571b4c
ZW		 2474 }
2475
615fb93f 2476 intel_connector = &intel_sdvo_connector->base;
14571b4c 2477 connector = &intel_connector->base;
5fa7ac9c
JN		 2478 if (intel_sdvo_get_hotplug_support(intel_sdvo) &
2479 intel_sdvo_connector->output_flag) {
5fa7ac9c 2480 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag;
cc68c81a
SF		 2481 /* Some SDVO devices have one-shot hotplug interrupts.
2482 * Ensure that they get re-enabled when an interrupt happens.
2483 */
2484 intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
3a2fb2c3 2485 intel_sdvo_enable_hotplug(intel_encoder);
5fa7ac9c 2486 } else {
821450c6 2487 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
5fa7ac9c 2488 }
14571b4c
ZW		 2489 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2490 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2491
e27d8538 2492 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
14571b4c 2493 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
e27d8538 2494 intel_sdvo->is_hdmi = true;
14571b4c 2495 }
14571b4c 2496
c393454d
ID		 2497 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2498 kfree(intel_sdvo_connector);
2499 return false;
2500 }
2501
f797d221 2502 if (intel_sdvo->is_hdmi)
55bc60db 2503 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector);
14571b4c
ZW		 2504
2505 return true;
2506}
2507
2508static bool
ea5b213a 2509intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
14571b4c 2510{
4ef69c7a
CW		 2511 struct drm_encoder *encoder = &intel_sdvo->base.base;
2512 struct drm_connector *connector;
2513 struct intel_connector *intel_connector;
2514 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2515
46a3f4a3
CW		 2516 DRM_DEBUG_KMS("initialising TV type %d\n", type);
2517
08d9bc92 2518 intel_sdvo_connector = intel_sdvo_connector_alloc();
615fb93f
CW		 2519 if (!intel_sdvo_connector)
2520 return false;
14571b4c 2521
615fb93f 2522 intel_connector = &intel_sdvo_connector->base;
4ef69c7a
CW		 2523 connector = &intel_connector->base;
2524 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2525 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
14571b4c 2526
4ef69c7a
CW		 2527 intel_sdvo->controlled_output |= type;
2528 intel_sdvo_connector->output_flag = type;
14571b4c 2529
4ef69c7a 2530 intel_sdvo->is_tv = true;
14571b4c 2531
c393454d
ID		 2532 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2533 kfree(intel_sdvo_connector);
2534 return false;
2535 }
14571b4c 2536
4ef69c7a 2537 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
32aad86f 2538 goto err;
14571b4c 2539
4ef69c7a 2540 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f 2541 goto err;
14571b4c 2542
4ef69c7a 2543 return true;
32aad86f
CW		 2544
2545err:
123d5c01 2546 intel_sdvo_destroy(connector);
32aad86f 2547 return false;
14571b4c
ZW		 2548}
2549
2550static bool
ea5b213a 2551intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2552{
4ef69c7a
CW		 2553 struct drm_encoder *encoder = &intel_sdvo->base.base;
2554 struct drm_connector *connector;
2555 struct intel_connector *intel_connector;
2556 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2557
46a3f4a3
CW		 2558 DRM_DEBUG_KMS("initialising analog device %d\n", device);
2559
8ce7da47 2560 intel_sdvo_connector = intel_sdvo_connector_alloc();
615fb93f
CW		 2561 if (!intel_sdvo_connector)
2562 return false;
14571b4c 2563
615fb93f 2564 intel_connector = &intel_sdvo_connector->base;
4ef69c7a 2565 connector = &intel_connector->base;
821450c6 2566 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
4ef69c7a
CW		 2567 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2568 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2569
2570 if (device == 0) {
2571 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2572 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2573 } else if (device == 1) {
2574 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2575 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2576 }
2577
c393454d
ID		 2578 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2579 kfree(intel_sdvo_connector);
2580 return false;
2581 }
2582
4ef69c7a 2583 return true;
14571b4c
ZW		 2584}
2585
2586static bool
ea5b213a 2587intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2588{
4ef69c7a
CW		 2589 struct drm_encoder *encoder = &intel_sdvo->base.base;
2590 struct drm_connector *connector;
2591 struct intel_connector *intel_connector;
2592 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2593
46a3f4a3
CW		 2594 DRM_DEBUG_KMS("initialising LVDS device %d\n", device);
2595
08d9bc92 2596 intel_sdvo_connector = intel_sdvo_connector_alloc();
615fb93f
CW		 2597 if (!intel_sdvo_connector)
2598 return false;
14571b4c 2599
615fb93f
CW		 2600 intel_connector = &intel_sdvo_connector->base;
2601 connector = &intel_connector->base;
4ef69c7a
CW		 2602 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2603 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2604
2605 if (device == 0) {
2606 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2607 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2608 } else if (device == 1) {
2609 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2610 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2611 }
2612
c393454d
ID		 2613 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2614 kfree(intel_sdvo_connector);
2615 return false;
2616 }
2617
4ef69c7a 2618 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f
CW		 2619 goto err;
2620
2621 return true;
2622
2623err:
123d5c01 2624 intel_sdvo_destroy(connector);
32aad86f 2625 return false;
14571b4c
ZW		 2626}
2627
2628static bool
ea5b213a 2629intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
14571b4c 2630{
ea5b213a 2631 intel_sdvo->is_tv = false;
ea5b213a 2632 intel_sdvo->is_lvds = false;
fb7a46f3 2633
14571b4c 2634 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
fb7a46f3 2635
14571b4c 2636 if (flags & SDVO_OUTPUT_TMDS0)
ea5b213a 2637 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
14571b4c
ZW		 2638 return false;
2639
2640 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
ea5b213a 2641 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
14571b4c
ZW		 2642 return false;
2643
2644 /* TV has no XXX1 function block */
a1f4b7ff 2645 if (flags & SDVO_OUTPUT_SVID0)
ea5b213a 2646 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
14571b4c
ZW		 2647 return false;
2648
2649 if (flags & SDVO_OUTPUT_CVBS0)
ea5b213a 2650 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
14571b4c 2651 return false;
fb7a46f3 2652
a0b1c7a5
CW		 2653 if (flags & SDVO_OUTPUT_YPRPB0)
2654 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
2655 return false;
2656
14571b4c 2657 if (flags & SDVO_OUTPUT_RGB0)
ea5b213a 2658 if (!intel_sdvo_analog_init(intel_sdvo, 0))
14571b4c
ZW		 2659 return false;
2660
2661 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
ea5b213a 2662 if (!intel_sdvo_analog_init(intel_sdvo, 1))
14571b4c
ZW		 2663 return false;
2664
2665 if (flags & SDVO_OUTPUT_LVDS0)
ea5b213a 2666 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
14571b4c
ZW		 2667 return false;
2668
2669 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
ea5b213a 2670 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
14571b4c 2671 return false;
fb7a46f3 2672
14571b4c 2673 if ((flags & SDVO_OUTPUT_MASK) == 0) {
fb7a46f3 2674 unsigned char bytes[2];
2675
ea5b213a
CW		 2676 intel_sdvo->controlled_output = 0;
2677 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
51c8b407 2678 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
ea5b213a 2679 SDVO_NAME(intel_sdvo),
51c8b407 2680 bytes[0], bytes[1]);
14571b4c 2681 return false;
fb7a46f3 2682 }
27f8227b 2683 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
fb7a46f3 2684
14571b4c 2685 return true;
fb7a46f3 2686}
2687
d0ddfbd3
JN		 2688static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)
2689{
2690 struct drm_device *dev = intel_sdvo->base.base.dev;
2691 struct drm_connector *connector, *tmp;
2692
2693 list_for_each_entry_safe(connector, tmp,
2694 &dev->mode_config.connector_list, head) {
d9255d57 2695 if (intel_attached_encoder(connector) == &intel_sdvo->base) {
34ea3d38 2696 drm_connector_unregister(connector);
d0ddfbd3 2697 intel_sdvo_destroy(connector);
d9255d57 2698 }
d0ddfbd3
JN		 2699 }
2700}
2701
32aad86f
CW		 2702static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2703 struct intel_sdvo_connector *intel_sdvo_connector,
2704 int type)
ce6feabd 2705{
4ef69c7a 2706 struct drm_device *dev = intel_sdvo->base.base.dev;
ce6feabd
ZY		 2707 struct intel_sdvo_tv_format format;
2708 uint32_t format_map, i;
ce6feabd 2709
32aad86f
CW		 2710 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2711 return false;
ce6feabd 2712
1a3665c8 2713 BUILD_BUG_ON(sizeof(format) != 6);
32aad86f
CW		 2714 if (!intel_sdvo_get_value(intel_sdvo,
2715 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2716 &format, sizeof(format)))
2717 return false;
ce6feabd 2718
32aad86f 2719 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
ce6feabd
ZY		 2720
2721 if (format_map == 0)
32aad86f 2722 return false;
ce6feabd 2723
615fb93f 2724 intel_sdvo_connector->format_supported_num = 0;
ce6feabd 2725 for (i = 0 ; i < TV_FORMAT_NUM; i++)
40039750
CW		 2726 if (format_map & (1 << i))
2727 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
ce6feabd
ZY		 2728
2729
c5521706 2730 intel_sdvo_connector->tv_format =
32aad86f
CW		 2731 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2732 "mode", intel_sdvo_connector->format_supported_num);
c5521706 2733 if (!intel_sdvo_connector->tv_format)
fcc8d672 2734 return false;
ce6feabd 2735
615fb93f 2736 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
ce6feabd 2737 drm_property_add_enum(
c5521706 2738 intel_sdvo_connector->tv_format, i,
40039750 2739 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
ce6feabd 2740
630d30a4
ML		 2741 intel_sdvo_connector->base.base.state->tv.mode = intel_sdvo_connector->tv_format_supported[0];
2742 drm_object_attach_property(&intel_sdvo_connector->base.base.base, 0, 0);
32aad86f 2743 return true;
ce6feabd
ZY		 2744
2745}
2746
630d30a4 2747#define _ENHANCEMENT(state_assignment, name, NAME) do { \
c5521706
CW		 2748 if (enhancements.name) { \
2749 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2750 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2751 return false; \
c5521706 2752 intel_sdvo_connector->name = \
d9bc3c02 2753 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
c5521706 2754 if (!intel_sdvo_connector->name) return false; \
630d30a4 2755 state_assignment = response; \
662595df 2756 drm_object_attach_property(&connector->base, \
630d30a4 2757 intel_sdvo_connector->name, 0); \
c5521706
CW		 2758 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2759 data_value[0], data_value[1], response); \
2760 } \
0206e353 2761} while (0)
c5521706 2762
630d30a4
ML		 2763#define ENHANCEMENT(state, name, NAME) _ENHANCEMENT((state)->name, name, NAME)
2764
c5521706
CW		 2765static bool
2766intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2767 struct intel_sdvo_connector *intel_sdvo_connector,
2768 struct intel_sdvo_enhancements_reply enhancements)
b9219c5e 2769{
4ef69c7a 2770 struct drm_device *dev = intel_sdvo->base.base.dev;
32aad86f 2771 struct drm_connector *connector = &intel_sdvo_connector->base.base;
630d30a4
ML		 2772 struct drm_connector_state *conn_state = connector->state;
2773 struct intel_sdvo_connector_state *sdvo_state =
2774 to_intel_sdvo_connector_state(conn_state);
b9219c5e
ZY		 2775 uint16_t response, data_value[2];
2776
c5521706
CW		 2777 /* when horizontal overscan is supported, Add the left/right property */
2778 if (enhancements.overscan_h) {
2779 if (!intel_sdvo_get_value(intel_sdvo,
2780 SDVO_CMD_GET_MAX_OVERSCAN_H,
2781 &data_value, 4))
2782 return false;
32aad86f 2783
c5521706
CW		 2784 if (!intel_sdvo_get_value(intel_sdvo,
2785 SDVO_CMD_GET_OVERSCAN_H,
2786 &response, 2))
2787 return false;
fcc8d672 2788
630d30a4
ML		 2789 sdvo_state->tv.overscan_h = response;
2790
c5521706 2791 intel_sdvo_connector->max_hscan = data_value[0];
c5521706 2792 intel_sdvo_connector->left =
d9bc3c02 2793 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
c5521706
CW		 2794 if (!intel_sdvo_connector->left)
2795 return false;
fcc8d672 2796
662595df 2797 drm_object_attach_property(&connector->base,
630d30a4 2798 intel_sdvo_connector->left, 0);
fcc8d672 2799
c5521706 2800 intel_sdvo_connector->right =
d9bc3c02 2801 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
c5521706
CW		 2802 if (!intel_sdvo_connector->right)
2803 return false;
32aad86f 2804
662595df 2805 drm_object_attach_property(&connector->base,
630d30a4 2806 intel_sdvo_connector->right, 0);
c5521706
CW		 2807 DRM_DEBUG_KMS("h_overscan: max %d, "
2808 "default %d, current %d\n",
2809 data_value[0], data_value[1], response);
2810 }
32aad86f 2811
c5521706
CW		 2812 if (enhancements.overscan_v) {
2813 if (!intel_sdvo_get_value(intel_sdvo,
2814 SDVO_CMD_GET_MAX_OVERSCAN_V,
2815 &data_value, 4))
2816 return false;
fcc8d672 2817
c5521706
CW		 2818 if (!intel_sdvo_get_value(intel_sdvo,
2819 SDVO_CMD_GET_OVERSCAN_V,
2820 &response, 2))
2821 return false;
32aad86f 2822
630d30a4
ML		 2823 sdvo_state->tv.overscan_v = response;
2824
c5521706 2825 intel_sdvo_connector->max_vscan = data_value[0];
c5521706 2826 intel_sdvo_connector->top =
d9bc3c02
SH		 2827 drm_property_create_range(dev, 0,
2828 "top_margin", 0, data_value[0]);
c5521706
CW		 2829 if (!intel_sdvo_connector->top)
2830 return false;
32aad86f 2831
662595df 2832 drm_object_attach_property(&connector->base,
630d30a4 2833 intel_sdvo_connector->top, 0);
fcc8d672 2834
c5521706 2835 intel_sdvo_connector->bottom =
d9bc3c02
SH		 2836 drm_property_create_range(dev, 0,
2837 "bottom_margin", 0, data_value[0]);
c5521706
CW		 2838 if (!intel_sdvo_connector->bottom)
2839 return false;
32aad86f 2840
662595df 2841 drm_object_attach_property(&connector->base,
630d30a4 2842 intel_sdvo_connector->bottom, 0);
c5521706
CW		 2843 DRM_DEBUG_KMS("v_overscan: max %d, "
2844 "default %d, current %d\n",
2845 data_value[0], data_value[1], response);
2846 }
32aad86f 2847
630d30a4
ML		 2848 ENHANCEMENT(&sdvo_state->tv, hpos, HPOS);
2849 ENHANCEMENT(&sdvo_state->tv, vpos, VPOS);
2850 ENHANCEMENT(&conn_state->tv, saturation, SATURATION);
2851 ENHANCEMENT(&conn_state->tv, contrast, CONTRAST);
2852 ENHANCEMENT(&conn_state->tv, hue, HUE);
2853 ENHANCEMENT(&conn_state->tv, brightness, BRIGHTNESS);
2854 ENHANCEMENT(&sdvo_state->tv, sharpness, SHARPNESS);
2855 ENHANCEMENT(&sdvo_state->tv, flicker_filter, FLICKER_FILTER);
2856 ENHANCEMENT(&sdvo_state->tv, flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2857 ENHANCEMENT(&sdvo_state->tv, flicker_filter_2d, FLICKER_FILTER_2D);
2858 _ENHANCEMENT(sdvo_state->tv.chroma_filter, tv_chroma_filter, TV_CHROMA_FILTER);
2859 _ENHANCEMENT(sdvo_state->tv.luma_filter, tv_luma_filter, TV_LUMA_FILTER);
fcc8d672 2860
e044218a
CW		 2861 if (enhancements.dot_crawl) {
2862 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2863 return false;
2864
630d30a4 2865 sdvo_state->tv.dot_crawl = response & 0x1;
e044218a 2866 intel_sdvo_connector->dot_crawl =
d9bc3c02 2867 drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
e044218a
CW		 2868 if (!intel_sdvo_connector->dot_crawl)
2869 return false;
2870
662595df 2871 drm_object_attach_property(&connector->base,
630d30a4 2872 intel_sdvo_connector->dot_crawl, 0);
e044218a
CW		 2873 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2874 }
2875
c5521706
CW		 2876 return true;
2877}
32aad86f 2878
c5521706
CW		 2879static bool
2880intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2881 struct intel_sdvo_connector *intel_sdvo_connector,
2882 struct intel_sdvo_enhancements_reply enhancements)
2883{
4ef69c7a 2884 struct drm_device *dev = intel_sdvo->base.base.dev;
c5521706
CW		 2885 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2886 uint16_t response, data_value[2];
32aad86f 2887
630d30a4 2888 ENHANCEMENT(&connector->state->tv, brightness, BRIGHTNESS);
fcc8d672 2889
c5521706
CW		 2890 return true;
2891}
2892#undef ENHANCEMENT
630d30a4 2893#undef _ENHANCEMENT
32aad86f 2894
c5521706
CW		 2895static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2896 struct intel_sdvo_connector *intel_sdvo_connector)
2897{
2898 union {
2899 struct intel_sdvo_enhancements_reply reply;
2900 uint16_t response;
2901 } enhancements;
32aad86f 2902
1a3665c8
CW		 2903 BUILD_BUG_ON(sizeof(enhancements) != 2);
2904
99016646
ID		 2905 if (!intel_sdvo_get_value(intel_sdvo,
2906 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2907 &enhancements, sizeof(enhancements)) ||
2908 enhancements.response == 0) {
c5521706
CW		 2909 DRM_DEBUG_KMS("No enhancement is supported\n");
2910 return true;
b9219c5e 2911 }
32aad86f 2912
c5521706
CW		 2913 if (IS_TV(intel_sdvo_connector))
2914 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
0206e353 2915 else if (IS_LVDS(intel_sdvo_connector))
c5521706
CW		 2916 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2917 else
2918 return true;
e957d772
CW		 2919}
2920
2921static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
2922 struct i2c_msg *msgs,
2923 int num)
2924{
2925 struct intel_sdvo *sdvo = adapter->algo_data;
fcc8d672 2926
e957d772
CW		 2927 if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
2928 return -EIO;
2929
2930 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
2931}
2932
2933static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
2934{
2935 struct intel_sdvo *sdvo = adapter->algo_data;
2936 return sdvo->i2c->algo->functionality(sdvo->i2c);
2937}
2938
2939static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
2940 .master_xfer = intel_sdvo_ddc_proxy_xfer,
2941 .functionality = intel_sdvo_ddc_proxy_func
2942};
2943
2944static bool
2945intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
c39055b0 2946 struct drm_i915_private *dev_priv)
e957d772 2947{
c39055b0 2948 struct pci_dev *pdev = dev_priv->drm.pdev;
52a05c30 2949
e957d772
CW		 2950 sdvo->ddc.owner = THIS_MODULE;
2951 sdvo->ddc.class = I2C_CLASS_DDC;
2952 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
52a05c30 2953 sdvo->ddc.dev.parent = &pdev->dev;
e957d772
CW		 2954 sdvo->ddc.algo_data = sdvo;
2955 sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
2956
2957 return i2c_add_adapter(&sdvo->ddc) == 0;
b9219c5e
ZY		 2958}
2959
2a5c0832
VS		 2960static void assert_sdvo_port_valid(const struct drm_i915_private *dev_priv,
2961 enum port port)
2962{
2963 if (HAS_PCH_SPLIT(dev_priv))
2964 WARN_ON(port != PORT_B);
2965 else
2966 WARN_ON(port != PORT_B && port != PORT_C);
2967}
2968
c39055b0 2969bool intel_sdvo_init(struct drm_i915_private *dev_priv,
f0f59a00 2970 i915_reg_t sdvo_reg, enum port port)
79e53945 2971{
21d40d37 2972 struct intel_encoder *intel_encoder;
ea5b213a 2973 struct intel_sdvo *intel_sdvo;
79e53945 2974 int i;
2a5c0832
VS		 2975
2976 assert_sdvo_port_valid(dev_priv, port);
2977
b14c5679 2978 intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL);
ea5b213a 2979 if (!intel_sdvo)
7d57382e 2980 return false;
79e53945 2981
56184e3d 2982 intel_sdvo->sdvo_reg = sdvo_reg;
2a5c0832 2983 intel_sdvo->port = port;
c39055b0
ACO		 2984 intel_sdvo->slave_addr =
2985 intel_sdvo_get_slave_addr(dev_priv, intel_sdvo) >> 1;
8bd864b8 2986 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo);
c39055b0 2987 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev_priv))
fbfcc4f3 2988 goto err_i2c_bus;
e957d772 2989
56184e3d 2990 /* encoder type will be decided later */
ea5b213a 2991 intel_encoder = &intel_sdvo->base;
21d40d37 2992 intel_encoder->type = INTEL_OUTPUT_SDVO;
79f255a0 2993 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
03cdc1d4 2994 intel_encoder->port = port;
c39055b0
ACO		 2995 drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
2996 &intel_sdvo_enc_funcs, 0,
580d8ed5 2997 "SDVO %c", port_name(port));
79e53945 2998
79e53945
JB		 2999 /* Read the regs to test if we can talk to the device */
3000 for (i = 0; i < 0x40; i++) {
f899fc64
CW		 3001 u8 byte;
3002
3003 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
eef4eacb
DV		 3004 DRM_DEBUG_KMS("No SDVO device found on %s\n",
3005 SDVO_NAME(intel_sdvo));
f899fc64 3006 goto err;
79e53945
JB		 3007 }
3008 }
3009
6cc5f341 3010 intel_encoder->compute_config = intel_sdvo_compute_config;
6e266956 3011 if (HAS_PCH_SPLIT(dev_priv)) {
3c65d1d1
VS		 3012 intel_encoder->disable = pch_disable_sdvo;
3013 intel_encoder->post_disable = pch_post_disable_sdvo;
3014 } else {
3015 intel_encoder->disable = intel_disable_sdvo;
3016 }
192d47a6 3017 intel_encoder->pre_enable = intel_sdvo_pre_enable;
ce22c320 3018 intel_encoder->enable = intel_enable_sdvo;
4ac41f47 3019 intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
045ac3b5 3020 intel_encoder->get_config = intel_sdvo_get_config;
ce22c320 3021
af901ca1 3022 /* In default case sdvo lvds is false */
32aad86f 3023 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
f899fc64 3024 goto err;
79e53945 3025
ea5b213a
CW		 3026 if (intel_sdvo_output_setup(intel_sdvo,
3027 intel_sdvo->caps.output_flags) != true) {
eef4eacb
DV		 3028 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
3029 SDVO_NAME(intel_sdvo));
d0ddfbd3
JN		 3030 /* Output_setup can leave behind connectors! */
3031 goto err_output;
79e53945
JB		 3032 }
3033
7ba220ce
CW		 3034 /* Only enable the hotplug irq if we need it, to work around noisy
3035 * hotplug lines.
3036 */
3037 if (intel_sdvo->hotplug_active) {
2a5c0832
VS		 3038 if (intel_sdvo->port == PORT_B)
3039 intel_encoder->hpd_pin = HPD_SDVO_B;
3040 else
3041 intel_encoder->hpd_pin = HPD_SDVO_C;
7ba220ce
CW		 3042 }
3043
e506d6fd
DV		 3044 /*
3045 * Cloning SDVO with anything is often impossible, since the SDVO
3046 * encoder can request a special input timing mode. And even if that's
3047 * not the case we have evidence that cloning a plain unscaled mode with
3048 * VGA doesn't really work. Furthermore the cloning flags are way too
3049 * simplistic anyway to express such constraints, so just give up on
3050 * cloning for SDVO encoders.
3051 */
bc079e8b 3052 intel_sdvo->base.cloneable = 0;
e506d6fd 3053
8bd864b8 3054 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo);
e2f0ba97 3055
79e53945 3056 /* Set the input timing to the screen. Assume always input 0. */
32aad86f 3057 if (!intel_sdvo_set_target_input(intel_sdvo))
d0ddfbd3 3058 goto err_output;
79e53945 3059
32aad86f
CW		 3060 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
3061 &intel_sdvo->pixel_clock_min,
3062 &intel_sdvo->pixel_clock_max))
d0ddfbd3 3063 goto err_output;
79e53945 3064
8a4c47f3 3065 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
342dc382 3066 "clock range %dMHz - %dMHz, "
3067 "input 1: %c, input 2: %c, "
3068 "output 1: %c, output 2: %c\n",
ea5b213a
CW		 3069 SDVO_NAME(intel_sdvo),
3070 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
3071 intel_sdvo->caps.device_rev_id,
3072 intel_sdvo->pixel_clock_min / 1000,
3073 intel_sdvo->pixel_clock_max / 1000,
3074 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
3075 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
342dc382 3076 /* check currently supported outputs */
ea5b213a 3077 intel_sdvo->caps.output_flags &
79e53945 3078 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
ea5b213a 3079 intel_sdvo->caps.output_flags &
79e53945 3080 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
7d57382e 3081 return true;
79e53945 3082
d0ddfbd3
JN		 3083err_output:
3084 intel_sdvo_output_cleanup(intel_sdvo);
3085
f899fc64 3086err:
373a3cf7 3087 drm_encoder_cleanup(&intel_encoder->base);
e957d772 3088 i2c_del_adapter(&intel_sdvo->ddc);
fbfcc4f3
JN		 3089err_i2c_bus:
3090 intel_sdvo_unselect_i2c_bus(intel_sdvo);
ea5b213a 3091 kfree(intel_sdvo);
79e53945 3092
7d57382e 3093 return false;
79e53945 3094}
Linux 6.x block layer and io_uring tree(s)