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79e53945 JB |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2007 Intel Corporation | |
4 | * Jesse Barnes <jesse.barnes@intel.com> | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
23 | * DEALINGS IN THE SOFTWARE. | |
24 | * | |
25 | * Authors: | |
26 | * Eric Anholt <eric@anholt.net> | |
27 | */ | |
28 | #include <linux/i2c.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
79e53945 | 30 | #include <linux/delay.h> |
2d1a8a48 | 31 | #include <linux/export.h> |
79e53945 JB |
32 | #include "drmP.h" |
33 | #include "drm.h" | |
34 | #include "drm_crtc.h" | |
2b8d33f7 | 35 | #include "drm_edid.h" |
ea5b213a | 36 | #include "intel_drv.h" |
79e53945 JB |
37 | #include "i915_drm.h" |
38 | #include "i915_drv.h" | |
39 | #include "intel_sdvo_regs.h" | |
40 | ||
14571b4c ZW |
41 | #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1) |
42 | #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1) | |
43 | #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1) | |
44 | #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0) | |
45 | ||
46 | #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\ | |
0206e353 | 47 | SDVO_TV_MASK) |
14571b4c ZW |
48 | |
49 | #define IS_TV(c) (c->output_flag & SDVO_TV_MASK) | |
13946743 | 50 | #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK) |
14571b4c | 51 | #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK) |
32aad86f | 52 | #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK)) |
52220085 | 53 | #define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK)) |
14571b4c | 54 | |
79e53945 | 55 | |
2e88e40b | 56 | static const char *tv_format_names[] = { |
ce6feabd ZY |
57 | "NTSC_M" , "NTSC_J" , "NTSC_443", |
58 | "PAL_B" , "PAL_D" , "PAL_G" , | |
59 | "PAL_H" , "PAL_I" , "PAL_M" , | |
60 | "PAL_N" , "PAL_NC" , "PAL_60" , | |
61 | "SECAM_B" , "SECAM_D" , "SECAM_G" , | |
62 | "SECAM_K" , "SECAM_K1", "SECAM_L" , | |
63 | "SECAM_60" | |
64 | }; | |
65 | ||
66 | #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names)) | |
67 | ||
ea5b213a CW |
68 | struct intel_sdvo { |
69 | struct intel_encoder base; | |
70 | ||
f899fc64 | 71 | struct i2c_adapter *i2c; |
f9c10a9b | 72 | u8 slave_addr; |
e2f0ba97 | 73 | |
e957d772 CW |
74 | struct i2c_adapter ddc; |
75 | ||
e2f0ba97 | 76 | /* Register for the SDVO device: SDVOB or SDVOC */ |
c751ce4f | 77 | int sdvo_reg; |
79e53945 | 78 | |
e2f0ba97 JB |
79 | /* Active outputs controlled by this SDVO output */ |
80 | uint16_t controlled_output; | |
79e53945 | 81 | |
e2f0ba97 JB |
82 | /* |
83 | * Capabilities of the SDVO device returned by | |
84 | * i830_sdvo_get_capabilities() | |
85 | */ | |
79e53945 | 86 | struct intel_sdvo_caps caps; |
e2f0ba97 JB |
87 | |
88 | /* Pixel clock limitations reported by the SDVO device, in kHz */ | |
79e53945 JB |
89 | int pixel_clock_min, pixel_clock_max; |
90 | ||
fb7a46f3 | 91 | /* |
92 | * For multiple function SDVO device, | |
93 | * this is for current attached outputs. | |
94 | */ | |
95 | uint16_t attached_output; | |
96 | ||
cc68c81a SF |
97 | /* |
98 | * Hotplug activation bits for this device | |
99 | */ | |
100 | uint8_t hotplug_active[2]; | |
101 | ||
e953fd7b CW |
102 | /** |
103 | * This is used to select the color range of RBG outputs in HDMI mode. | |
104 | * It is only valid when using TMDS encoding and 8 bit per color mode. | |
105 | */ | |
106 | uint32_t color_range; | |
107 | ||
e2f0ba97 JB |
108 | /** |
109 | * This is set if we're going to treat the device as TV-out. | |
110 | * | |
111 | * While we have these nice friendly flags for output types that ought | |
112 | * to decide this for us, the S-Video output on our HDMI+S-Video card | |
113 | * shows up as RGB1 (VGA). | |
114 | */ | |
115 | bool is_tv; | |
116 | ||
ce6feabd | 117 | /* This is for current tv format name */ |
40039750 | 118 | int tv_format_index; |
ce6feabd | 119 | |
e2f0ba97 JB |
120 | /** |
121 | * This is set if we treat the device as HDMI, instead of DVI. | |
122 | */ | |
123 | bool is_hdmi; | |
da79de97 CW |
124 | bool has_hdmi_monitor; |
125 | bool has_hdmi_audio; | |
12682a97 | 126 | |
7086c87f | 127 | /** |
6c9547ff CW |
128 | * This is set if we detect output of sdvo device as LVDS and |
129 | * have a valid fixed mode to use with the panel. | |
7086c87f ML |
130 | */ |
131 | bool is_lvds; | |
e2f0ba97 | 132 | |
12682a97 | 133 | /** |
134 | * This is sdvo fixed pannel mode pointer | |
135 | */ | |
136 | struct drm_display_mode *sdvo_lvds_fixed_mode; | |
137 | ||
c751ce4f | 138 | /* DDC bus used by this SDVO encoder */ |
e2f0ba97 JB |
139 | uint8_t ddc_bus; |
140 | ||
6c9547ff CW |
141 | /* Input timings for adjusted_mode */ |
142 | struct intel_sdvo_dtd input_dtd; | |
14571b4c ZW |
143 | }; |
144 | ||
145 | struct intel_sdvo_connector { | |
615fb93f CW |
146 | struct intel_connector base; |
147 | ||
14571b4c ZW |
148 | /* Mark the type of connector */ |
149 | uint16_t output_flag; | |
150 | ||
7f36e7ed CW |
151 | int force_audio; |
152 | ||
14571b4c | 153 | /* This contains all current supported TV format */ |
40039750 | 154 | u8 tv_format_supported[TV_FORMAT_NUM]; |
14571b4c | 155 | int format_supported_num; |
c5521706 | 156 | struct drm_property *tv_format; |
14571b4c | 157 | |
b9219c5e | 158 | /* add the property for the SDVO-TV */ |
c5521706 CW |
159 | struct drm_property *left; |
160 | struct drm_property *right; | |
161 | struct drm_property *top; | |
162 | struct drm_property *bottom; | |
163 | struct drm_property *hpos; | |
164 | struct drm_property *vpos; | |
165 | struct drm_property *contrast; | |
166 | struct drm_property *saturation; | |
167 | struct drm_property *hue; | |
168 | struct drm_property *sharpness; | |
169 | struct drm_property *flicker_filter; | |
170 | struct drm_property *flicker_filter_adaptive; | |
171 | struct drm_property *flicker_filter_2d; | |
172 | struct drm_property *tv_chroma_filter; | |
173 | struct drm_property *tv_luma_filter; | |
e044218a | 174 | struct drm_property *dot_crawl; |
b9219c5e ZY |
175 | |
176 | /* add the property for the SDVO-TV/LVDS */ | |
c5521706 | 177 | struct drm_property *brightness; |
b9219c5e ZY |
178 | |
179 | /* Add variable to record current setting for the above property */ | |
180 | u32 left_margin, right_margin, top_margin, bottom_margin; | |
c5521706 | 181 | |
b9219c5e ZY |
182 | /* this is to get the range of margin.*/ |
183 | u32 max_hscan, max_vscan; | |
184 | u32 max_hpos, cur_hpos; | |
185 | u32 max_vpos, cur_vpos; | |
186 | u32 cur_brightness, max_brightness; | |
187 | u32 cur_contrast, max_contrast; | |
188 | u32 cur_saturation, max_saturation; | |
189 | u32 cur_hue, max_hue; | |
c5521706 CW |
190 | u32 cur_sharpness, max_sharpness; |
191 | u32 cur_flicker_filter, max_flicker_filter; | |
192 | u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive; | |
193 | u32 cur_flicker_filter_2d, max_flicker_filter_2d; | |
194 | u32 cur_tv_chroma_filter, max_tv_chroma_filter; | |
195 | u32 cur_tv_luma_filter, max_tv_luma_filter; | |
e044218a | 196 | u32 cur_dot_crawl, max_dot_crawl; |
79e53945 JB |
197 | }; |
198 | ||
890f3359 | 199 | static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder) |
ea5b213a | 200 | { |
4ef69c7a | 201 | return container_of(encoder, struct intel_sdvo, base.base); |
ea5b213a CW |
202 | } |
203 | ||
df0e9248 CW |
204 | static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector) |
205 | { | |
206 | return container_of(intel_attached_encoder(connector), | |
207 | struct intel_sdvo, base); | |
208 | } | |
209 | ||
615fb93f CW |
210 | static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector) |
211 | { | |
212 | return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base); | |
213 | } | |
214 | ||
fb7a46f3 | 215 | static bool |
ea5b213a | 216 | intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags); |
32aad86f CW |
217 | static bool |
218 | intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, | |
219 | struct intel_sdvo_connector *intel_sdvo_connector, | |
220 | int type); | |
221 | static bool | |
222 | intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, | |
223 | struct intel_sdvo_connector *intel_sdvo_connector); | |
fb7a46f3 | 224 | |
79e53945 JB |
225 | /** |
226 | * Writes the SDVOB or SDVOC with the given value, but always writes both | |
227 | * SDVOB and SDVOC to work around apparent hardware issues (according to | |
228 | * comments in the BIOS). | |
229 | */ | |
ea5b213a | 230 | static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) |
79e53945 | 231 | { |
4ef69c7a | 232 | struct drm_device *dev = intel_sdvo->base.base.dev; |
79e53945 | 233 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 JB |
234 | u32 bval = val, cval = val; |
235 | int i; | |
236 | ||
ea5b213a CW |
237 | if (intel_sdvo->sdvo_reg == PCH_SDVOB) { |
238 | I915_WRITE(intel_sdvo->sdvo_reg, val); | |
239 | I915_READ(intel_sdvo->sdvo_reg); | |
461ed3ca ZY |
240 | return; |
241 | } | |
242 | ||
ea5b213a | 243 | if (intel_sdvo->sdvo_reg == SDVOB) { |
79e53945 JB |
244 | cval = I915_READ(SDVOC); |
245 | } else { | |
246 | bval = I915_READ(SDVOB); | |
247 | } | |
248 | /* | |
249 | * Write the registers twice for luck. Sometimes, | |
250 | * writing them only once doesn't appear to 'stick'. | |
251 | * The BIOS does this too. Yay, magic | |
252 | */ | |
253 | for (i = 0; i < 2; i++) | |
254 | { | |
255 | I915_WRITE(SDVOB, bval); | |
256 | I915_READ(SDVOB); | |
257 | I915_WRITE(SDVOC, cval); | |
258 | I915_READ(SDVOC); | |
259 | } | |
260 | } | |
261 | ||
32aad86f | 262 | static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch) |
79e53945 | 263 | { |
79e53945 JB |
264 | struct i2c_msg msgs[] = { |
265 | { | |
e957d772 | 266 | .addr = intel_sdvo->slave_addr, |
79e53945 JB |
267 | .flags = 0, |
268 | .len = 1, | |
e957d772 | 269 | .buf = &addr, |
79e53945 JB |
270 | }, |
271 | { | |
e957d772 | 272 | .addr = intel_sdvo->slave_addr, |
79e53945 JB |
273 | .flags = I2C_M_RD, |
274 | .len = 1, | |
e957d772 | 275 | .buf = ch, |
79e53945 JB |
276 | } |
277 | }; | |
32aad86f | 278 | int ret; |
79e53945 | 279 | |
f899fc64 | 280 | if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2) |
79e53945 | 281 | return true; |
79e53945 | 282 | |
8a4c47f3 | 283 | DRM_DEBUG_KMS("i2c transfer returned %d\n", ret); |
79e53945 JB |
284 | return false; |
285 | } | |
286 | ||
79e53945 JB |
287 | #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd} |
288 | /** Mapping of command numbers to names, for debug output */ | |
005568be | 289 | static const struct _sdvo_cmd_name { |
e2f0ba97 | 290 | u8 cmd; |
2e88e40b | 291 | const char *name; |
79e53945 | 292 | } sdvo_cmd_names[] = { |
0206e353 AJ |
293 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET), |
294 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS), | |
295 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV), | |
296 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS), | |
297 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS), | |
298 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS), | |
299 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP), | |
300 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP), | |
301 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS), | |
302 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT), | |
303 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG), | |
304 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG), | |
305 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE), | |
306 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT), | |
307 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT), | |
308 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1), | |
309 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2), | |
310 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), | |
311 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2), | |
312 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), | |
313 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1), | |
314 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2), | |
315 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1), | |
316 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2), | |
317 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING), | |
318 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1), | |
319 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2), | |
320 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE), | |
321 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE), | |
322 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS), | |
323 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT), | |
324 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT), | |
325 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS), | |
326 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT), | |
327 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT), | |
328 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES), | |
329 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE), | |
330 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE), | |
331 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE), | |
332 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH), | |
333 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT), | |
334 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT), | |
335 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS), | |
336 | ||
337 | /* Add the op code for SDVO enhancements */ | |
338 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS), | |
339 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS), | |
340 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS), | |
341 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS), | |
342 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS), | |
343 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS), | |
344 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION), | |
345 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION), | |
346 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION), | |
347 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE), | |
348 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE), | |
349 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE), | |
350 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST), | |
351 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST), | |
352 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST), | |
353 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS), | |
354 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS), | |
355 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS), | |
356 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H), | |
357 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H), | |
358 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H), | |
359 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V), | |
360 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V), | |
361 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V), | |
362 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER), | |
363 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER), | |
364 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER), | |
365 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE), | |
366 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE), | |
367 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE), | |
368 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D), | |
369 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D), | |
370 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D), | |
371 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS), | |
372 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS), | |
373 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS), | |
374 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL), | |
375 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL), | |
376 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER), | |
377 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER), | |
378 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER), | |
379 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER), | |
380 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER), | |
381 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER), | |
382 | ||
383 | /* HDMI op code */ | |
384 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE), | |
385 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE), | |
386 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE), | |
387 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI), | |
388 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI), | |
389 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP), | |
390 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY), | |
391 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY), | |
392 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER), | |
393 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT), | |
394 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT), | |
395 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX), | |
396 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX), | |
397 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO), | |
398 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT), | |
399 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT), | |
400 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE), | |
401 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE), | |
402 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA), | |
403 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA), | |
79e53945 JB |
404 | }; |
405 | ||
461ed3ca | 406 | #define IS_SDVOB(reg) (reg == SDVOB || reg == PCH_SDVOB) |
ea5b213a | 407 | #define SDVO_NAME(svdo) (IS_SDVOB((svdo)->sdvo_reg) ? "SDVOB" : "SDVOC") |
79e53945 | 408 | |
ea5b213a | 409 | static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd, |
32aad86f | 410 | const void *args, int args_len) |
79e53945 | 411 | { |
79e53945 JB |
412 | int i; |
413 | ||
8a4c47f3 | 414 | DRM_DEBUG_KMS("%s: W: %02X ", |
ea5b213a | 415 | SDVO_NAME(intel_sdvo), cmd); |
79e53945 | 416 | for (i = 0; i < args_len; i++) |
342dc382 | 417 | DRM_LOG_KMS("%02X ", ((u8 *)args)[i]); |
79e53945 | 418 | for (; i < 8; i++) |
342dc382 | 419 | DRM_LOG_KMS(" "); |
04ad327f | 420 | for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) { |
79e53945 | 421 | if (cmd == sdvo_cmd_names[i].cmd) { |
342dc382 | 422 | DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name); |
79e53945 JB |
423 | break; |
424 | } | |
425 | } | |
04ad327f | 426 | if (i == ARRAY_SIZE(sdvo_cmd_names)) |
342dc382 | 427 | DRM_LOG_KMS("(%02X)", cmd); |
428 | DRM_LOG_KMS("\n"); | |
79e53945 | 429 | } |
79e53945 | 430 | |
e957d772 CW |
431 | static const char *cmd_status_names[] = { |
432 | "Power on", | |
433 | "Success", | |
434 | "Not supported", | |
435 | "Invalid arg", | |
436 | "Pending", | |
437 | "Target not specified", | |
438 | "Scaling not supported" | |
439 | }; | |
440 | ||
32aad86f CW |
441 | static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, |
442 | const void *args, int args_len) | |
79e53945 | 443 | { |
e957d772 CW |
444 | u8 buf[args_len*2 + 2], status; |
445 | struct i2c_msg msgs[args_len + 3]; | |
446 | int i, ret; | |
79e53945 | 447 | |
ea5b213a | 448 | intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len); |
79e53945 JB |
449 | |
450 | for (i = 0; i < args_len; i++) { | |
e957d772 CW |
451 | msgs[i].addr = intel_sdvo->slave_addr; |
452 | msgs[i].flags = 0; | |
453 | msgs[i].len = 2; | |
454 | msgs[i].buf = buf + 2 *i; | |
455 | buf[2*i + 0] = SDVO_I2C_ARG_0 - i; | |
456 | buf[2*i + 1] = ((u8*)args)[i]; | |
457 | } | |
458 | msgs[i].addr = intel_sdvo->slave_addr; | |
459 | msgs[i].flags = 0; | |
460 | msgs[i].len = 2; | |
461 | msgs[i].buf = buf + 2*i; | |
462 | buf[2*i + 0] = SDVO_I2C_OPCODE; | |
463 | buf[2*i + 1] = cmd; | |
464 | ||
465 | /* the following two are to read the response */ | |
466 | status = SDVO_I2C_CMD_STATUS; | |
467 | msgs[i+1].addr = intel_sdvo->slave_addr; | |
468 | msgs[i+1].flags = 0; | |
469 | msgs[i+1].len = 1; | |
470 | msgs[i+1].buf = &status; | |
471 | ||
472 | msgs[i+2].addr = intel_sdvo->slave_addr; | |
473 | msgs[i+2].flags = I2C_M_RD; | |
474 | msgs[i+2].len = 1; | |
475 | msgs[i+2].buf = &status; | |
476 | ||
477 | ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3); | |
478 | if (ret < 0) { | |
479 | DRM_DEBUG_KMS("I2c transfer returned %d\n", ret); | |
480 | return false; | |
481 | } | |
482 | if (ret != i+3) { | |
483 | /* failure in I2C transfer */ | |
484 | DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3); | |
485 | return false; | |
486 | } | |
487 | ||
e957d772 | 488 | return true; |
79e53945 JB |
489 | } |
490 | ||
b5c616a7 CW |
491 | static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, |
492 | void *response, int response_len) | |
79e53945 | 493 | { |
b5c616a7 CW |
494 | u8 retry = 5; |
495 | u8 status; | |
33b52961 | 496 | int i; |
79e53945 | 497 | |
d121a5d2 CW |
498 | DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo)); |
499 | ||
b5c616a7 CW |
500 | /* |
501 | * The documentation states that all commands will be | |
502 | * processed within 15µs, and that we need only poll | |
503 | * the status byte a maximum of 3 times in order for the | |
504 | * command to be complete. | |
505 | * | |
506 | * Check 5 times in case the hardware failed to read the docs. | |
507 | */ | |
d121a5d2 CW |
508 | if (!intel_sdvo_read_byte(intel_sdvo, |
509 | SDVO_I2C_CMD_STATUS, | |
510 | &status)) | |
511 | goto log_fail; | |
512 | ||
513 | while (status == SDVO_CMD_STATUS_PENDING && retry--) { | |
514 | udelay(15); | |
b5c616a7 CW |
515 | if (!intel_sdvo_read_byte(intel_sdvo, |
516 | SDVO_I2C_CMD_STATUS, | |
517 | &status)) | |
d121a5d2 CW |
518 | goto log_fail; |
519 | } | |
b5c616a7 | 520 | |
79e53945 | 521 | if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP) |
342dc382 | 522 | DRM_LOG_KMS("(%s)", cmd_status_names[status]); |
79e53945 | 523 | else |
342dc382 | 524 | DRM_LOG_KMS("(??? %d)", status); |
79e53945 | 525 | |
b5c616a7 CW |
526 | if (status != SDVO_CMD_STATUS_SUCCESS) |
527 | goto log_fail; | |
79e53945 | 528 | |
b5c616a7 CW |
529 | /* Read the command response */ |
530 | for (i = 0; i < response_len; i++) { | |
531 | if (!intel_sdvo_read_byte(intel_sdvo, | |
532 | SDVO_I2C_RETURN_0 + i, | |
533 | &((u8 *)response)[i])) | |
534 | goto log_fail; | |
e957d772 | 535 | DRM_LOG_KMS(" %02X", ((u8 *)response)[i]); |
b5c616a7 | 536 | } |
b5c616a7 | 537 | DRM_LOG_KMS("\n"); |
b5c616a7 | 538 | return true; |
79e53945 | 539 | |
b5c616a7 | 540 | log_fail: |
d121a5d2 | 541 | DRM_LOG_KMS("... failed\n"); |
b5c616a7 | 542 | return false; |
79e53945 JB |
543 | } |
544 | ||
b358d0a6 | 545 | static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode) |
79e53945 JB |
546 | { |
547 | if (mode->clock >= 100000) | |
548 | return 1; | |
549 | else if (mode->clock >= 50000) | |
550 | return 2; | |
551 | else | |
552 | return 4; | |
553 | } | |
554 | ||
e957d772 CW |
555 | static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo, |
556 | u8 ddc_bus) | |
79e53945 | 557 | { |
d121a5d2 | 558 | /* This must be the immediately preceding write before the i2c xfer */ |
e957d772 CW |
559 | return intel_sdvo_write_cmd(intel_sdvo, |
560 | SDVO_CMD_SET_CONTROL_BUS_SWITCH, | |
561 | &ddc_bus, 1); | |
79e53945 JB |
562 | } |
563 | ||
32aad86f | 564 | static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len) |
79e53945 | 565 | { |
d121a5d2 CW |
566 | if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len)) |
567 | return false; | |
568 | ||
569 | return intel_sdvo_read_response(intel_sdvo, NULL, 0); | |
32aad86f | 570 | } |
79e53945 | 571 | |
32aad86f CW |
572 | static bool |
573 | intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len) | |
574 | { | |
575 | if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0)) | |
576 | return false; | |
79e53945 | 577 | |
32aad86f CW |
578 | return intel_sdvo_read_response(intel_sdvo, value, len); |
579 | } | |
79e53945 | 580 | |
32aad86f CW |
581 | static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo) |
582 | { | |
583 | struct intel_sdvo_set_target_input_args targets = {0}; | |
584 | return intel_sdvo_set_value(intel_sdvo, | |
585 | SDVO_CMD_SET_TARGET_INPUT, | |
586 | &targets, sizeof(targets)); | |
79e53945 JB |
587 | } |
588 | ||
589 | /** | |
590 | * Return whether each input is trained. | |
591 | * | |
592 | * This function is making an assumption about the layout of the response, | |
593 | * which should be checked against the docs. | |
594 | */ | |
ea5b213a | 595 | static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2) |
79e53945 JB |
596 | { |
597 | struct intel_sdvo_get_trained_inputs_response response; | |
79e53945 | 598 | |
1a3665c8 | 599 | BUILD_BUG_ON(sizeof(response) != 1); |
32aad86f CW |
600 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS, |
601 | &response, sizeof(response))) | |
79e53945 JB |
602 | return false; |
603 | ||
604 | *input_1 = response.input0_trained; | |
605 | *input_2 = response.input1_trained; | |
606 | return true; | |
607 | } | |
608 | ||
ea5b213a | 609 | static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo, |
79e53945 JB |
610 | u16 outputs) |
611 | { | |
32aad86f CW |
612 | return intel_sdvo_set_value(intel_sdvo, |
613 | SDVO_CMD_SET_ACTIVE_OUTPUTS, | |
614 | &outputs, sizeof(outputs)); | |
79e53945 JB |
615 | } |
616 | ||
ea5b213a | 617 | static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo, |
79e53945 JB |
618 | int mode) |
619 | { | |
32aad86f | 620 | u8 state = SDVO_ENCODER_STATE_ON; |
79e53945 JB |
621 | |
622 | switch (mode) { | |
623 | case DRM_MODE_DPMS_ON: | |
624 | state = SDVO_ENCODER_STATE_ON; | |
625 | break; | |
626 | case DRM_MODE_DPMS_STANDBY: | |
627 | state = SDVO_ENCODER_STATE_STANDBY; | |
628 | break; | |
629 | case DRM_MODE_DPMS_SUSPEND: | |
630 | state = SDVO_ENCODER_STATE_SUSPEND; | |
631 | break; | |
632 | case DRM_MODE_DPMS_OFF: | |
633 | state = SDVO_ENCODER_STATE_OFF; | |
634 | break; | |
635 | } | |
636 | ||
32aad86f CW |
637 | return intel_sdvo_set_value(intel_sdvo, |
638 | SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state)); | |
79e53945 JB |
639 | } |
640 | ||
ea5b213a | 641 | static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo, |
79e53945 JB |
642 | int *clock_min, |
643 | int *clock_max) | |
644 | { | |
645 | struct intel_sdvo_pixel_clock_range clocks; | |
79e53945 | 646 | |
1a3665c8 | 647 | BUILD_BUG_ON(sizeof(clocks) != 4); |
32aad86f CW |
648 | if (!intel_sdvo_get_value(intel_sdvo, |
649 | SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, | |
650 | &clocks, sizeof(clocks))) | |
79e53945 JB |
651 | return false; |
652 | ||
653 | /* Convert the values from units of 10 kHz to kHz. */ | |
654 | *clock_min = clocks.min * 10; | |
655 | *clock_max = clocks.max * 10; | |
79e53945 JB |
656 | return true; |
657 | } | |
658 | ||
ea5b213a | 659 | static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo, |
79e53945 JB |
660 | u16 outputs) |
661 | { | |
32aad86f CW |
662 | return intel_sdvo_set_value(intel_sdvo, |
663 | SDVO_CMD_SET_TARGET_OUTPUT, | |
664 | &outputs, sizeof(outputs)); | |
79e53945 JB |
665 | } |
666 | ||
ea5b213a | 667 | static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd, |
79e53945 JB |
668 | struct intel_sdvo_dtd *dtd) |
669 | { | |
32aad86f CW |
670 | return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && |
671 | intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); | |
79e53945 JB |
672 | } |
673 | ||
ea5b213a | 674 | static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo, |
79e53945 JB |
675 | struct intel_sdvo_dtd *dtd) |
676 | { | |
ea5b213a | 677 | return intel_sdvo_set_timing(intel_sdvo, |
79e53945 JB |
678 | SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); |
679 | } | |
680 | ||
ea5b213a | 681 | static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo, |
79e53945 JB |
682 | struct intel_sdvo_dtd *dtd) |
683 | { | |
ea5b213a | 684 | return intel_sdvo_set_timing(intel_sdvo, |
79e53945 JB |
685 | SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); |
686 | } | |
687 | ||
e2f0ba97 | 688 | static bool |
ea5b213a | 689 | intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo, |
e2f0ba97 JB |
690 | uint16_t clock, |
691 | uint16_t width, | |
692 | uint16_t height) | |
693 | { | |
694 | struct intel_sdvo_preferred_input_timing_args args; | |
e2f0ba97 | 695 | |
e642c6f1 | 696 | memset(&args, 0, sizeof(args)); |
e2f0ba97 JB |
697 | args.clock = clock; |
698 | args.width = width; | |
699 | args.height = height; | |
e642c6f1 | 700 | args.interlace = 0; |
12682a97 | 701 | |
ea5b213a CW |
702 | if (intel_sdvo->is_lvds && |
703 | (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width || | |
704 | intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height)) | |
12682a97 | 705 | args.scaled = 1; |
706 | ||
32aad86f CW |
707 | return intel_sdvo_set_value(intel_sdvo, |
708 | SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, | |
709 | &args, sizeof(args)); | |
e2f0ba97 JB |
710 | } |
711 | ||
ea5b213a | 712 | static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo, |
e2f0ba97 JB |
713 | struct intel_sdvo_dtd *dtd) |
714 | { | |
1a3665c8 CW |
715 | BUILD_BUG_ON(sizeof(dtd->part1) != 8); |
716 | BUILD_BUG_ON(sizeof(dtd->part2) != 8); | |
32aad86f CW |
717 | return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, |
718 | &dtd->part1, sizeof(dtd->part1)) && | |
719 | intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, | |
720 | &dtd->part2, sizeof(dtd->part2)); | |
e2f0ba97 | 721 | } |
79e53945 | 722 | |
ea5b213a | 723 | static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val) |
79e53945 | 724 | { |
32aad86f | 725 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); |
79e53945 JB |
726 | } |
727 | ||
e2f0ba97 | 728 | static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, |
32aad86f | 729 | const struct drm_display_mode *mode) |
79e53945 | 730 | { |
e2f0ba97 JB |
731 | uint16_t width, height; |
732 | uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len; | |
733 | uint16_t h_sync_offset, v_sync_offset; | |
79e53945 JB |
734 | |
735 | width = mode->crtc_hdisplay; | |
736 | height = mode->crtc_vdisplay; | |
737 | ||
738 | /* do some mode translations */ | |
739 | h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start; | |
740 | h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; | |
741 | ||
742 | v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start; | |
743 | v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; | |
744 | ||
745 | h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start; | |
746 | v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start; | |
747 | ||
e2f0ba97 JB |
748 | dtd->part1.clock = mode->clock / 10; |
749 | dtd->part1.h_active = width & 0xff; | |
750 | dtd->part1.h_blank = h_blank_len & 0xff; | |
751 | dtd->part1.h_high = (((width >> 8) & 0xf) << 4) | | |
79e53945 | 752 | ((h_blank_len >> 8) & 0xf); |
e2f0ba97 JB |
753 | dtd->part1.v_active = height & 0xff; |
754 | dtd->part1.v_blank = v_blank_len & 0xff; | |
755 | dtd->part1.v_high = (((height >> 8) & 0xf) << 4) | | |
79e53945 JB |
756 | ((v_blank_len >> 8) & 0xf); |
757 | ||
171a9e96 | 758 | dtd->part2.h_sync_off = h_sync_offset & 0xff; |
e2f0ba97 JB |
759 | dtd->part2.h_sync_width = h_sync_len & 0xff; |
760 | dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 | | |
79e53945 | 761 | (v_sync_len & 0xf); |
e2f0ba97 | 762 | dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) | |
79e53945 JB |
763 | ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) | |
764 | ((v_sync_len & 0x30) >> 4); | |
765 | ||
e2f0ba97 | 766 | dtd->part2.dtd_flags = 0x18; |
79e53945 | 767 | if (mode->flags & DRM_MODE_FLAG_PHSYNC) |
e2f0ba97 | 768 | dtd->part2.dtd_flags |= 0x2; |
79e53945 | 769 | if (mode->flags & DRM_MODE_FLAG_PVSYNC) |
e2f0ba97 JB |
770 | dtd->part2.dtd_flags |= 0x4; |
771 | ||
772 | dtd->part2.sdvo_flags = 0; | |
773 | dtd->part2.v_sync_off_high = v_sync_offset & 0xc0; | |
774 | dtd->part2.reserved = 0; | |
775 | } | |
776 | ||
777 | static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode, | |
32aad86f | 778 | const struct intel_sdvo_dtd *dtd) |
e2f0ba97 | 779 | { |
e2f0ba97 JB |
780 | mode->hdisplay = dtd->part1.h_active; |
781 | mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; | |
782 | mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off; | |
171a9e96 | 783 | mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2; |
e2f0ba97 JB |
784 | mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width; |
785 | mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4; | |
786 | mode->htotal = mode->hdisplay + dtd->part1.h_blank; | |
787 | mode->htotal += (dtd->part1.h_high & 0xf) << 8; | |
788 | ||
789 | mode->vdisplay = dtd->part1.v_active; | |
790 | mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8; | |
791 | mode->vsync_start = mode->vdisplay; | |
792 | mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf; | |
171a9e96 | 793 | mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2; |
e2f0ba97 JB |
794 | mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0; |
795 | mode->vsync_end = mode->vsync_start + | |
796 | (dtd->part2.v_sync_off_width & 0xf); | |
797 | mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4; | |
798 | mode->vtotal = mode->vdisplay + dtd->part1.v_blank; | |
799 | mode->vtotal += (dtd->part1.v_high & 0xf) << 8; | |
800 | ||
801 | mode->clock = dtd->part1.clock * 10; | |
802 | ||
171a9e96 | 803 | mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); |
e2f0ba97 JB |
804 | if (dtd->part2.dtd_flags & 0x2) |
805 | mode->flags |= DRM_MODE_FLAG_PHSYNC; | |
806 | if (dtd->part2.dtd_flags & 0x4) | |
807 | mode->flags |= DRM_MODE_FLAG_PVSYNC; | |
808 | } | |
809 | ||
e27d8538 | 810 | static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo) |
e2f0ba97 | 811 | { |
e27d8538 | 812 | struct intel_sdvo_encode encode; |
e2f0ba97 | 813 | |
1a3665c8 | 814 | BUILD_BUG_ON(sizeof(encode) != 2); |
e27d8538 CW |
815 | return intel_sdvo_get_value(intel_sdvo, |
816 | SDVO_CMD_GET_SUPP_ENCODE, | |
817 | &encode, sizeof(encode)); | |
e2f0ba97 JB |
818 | } |
819 | ||
ea5b213a | 820 | static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo, |
c751ce4f | 821 | uint8_t mode) |
e2f0ba97 | 822 | { |
32aad86f | 823 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1); |
e2f0ba97 JB |
824 | } |
825 | ||
ea5b213a | 826 | static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo, |
e2f0ba97 JB |
827 | uint8_t mode) |
828 | { | |
32aad86f | 829 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1); |
e2f0ba97 JB |
830 | } |
831 | ||
832 | #if 0 | |
ea5b213a | 833 | static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo) |
e2f0ba97 JB |
834 | { |
835 | int i, j; | |
836 | uint8_t set_buf_index[2]; | |
837 | uint8_t av_split; | |
838 | uint8_t buf_size; | |
839 | uint8_t buf[48]; | |
840 | uint8_t *pos; | |
841 | ||
32aad86f | 842 | intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1); |
e2f0ba97 JB |
843 | |
844 | for (i = 0; i <= av_split; i++) { | |
845 | set_buf_index[0] = i; set_buf_index[1] = 0; | |
c751ce4f | 846 | intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX, |
e2f0ba97 | 847 | set_buf_index, 2); |
c751ce4f EA |
848 | intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0); |
849 | intel_sdvo_read_response(encoder, &buf_size, 1); | |
e2f0ba97 JB |
850 | |
851 | pos = buf; | |
852 | for (j = 0; j <= buf_size; j += 8) { | |
c751ce4f | 853 | intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA, |
e2f0ba97 | 854 | NULL, 0); |
c751ce4f | 855 | intel_sdvo_read_response(encoder, pos, 8); |
e2f0ba97 JB |
856 | pos += 8; |
857 | } | |
858 | } | |
859 | } | |
860 | #endif | |
861 | ||
3c17fe4b | 862 | static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo) |
e2f0ba97 JB |
863 | { |
864 | struct dip_infoframe avi_if = { | |
865 | .type = DIP_TYPE_AVI, | |
3c17fe4b | 866 | .ver = DIP_VERSION_AVI, |
e2f0ba97 JB |
867 | .len = DIP_LEN_AVI, |
868 | }; | |
3c17fe4b DH |
869 | uint8_t tx_rate = SDVO_HBUF_TX_VSYNC; |
870 | uint8_t set_buf_index[2] = { 1, 0 }; | |
871 | uint64_t *data = (uint64_t *)&avi_if; | |
872 | unsigned i; | |
873 | ||
874 | intel_dip_infoframe_csum(&avi_if); | |
875 | ||
d121a5d2 CW |
876 | if (!intel_sdvo_set_value(intel_sdvo, |
877 | SDVO_CMD_SET_HBUF_INDEX, | |
3c17fe4b DH |
878 | set_buf_index, 2)) |
879 | return false; | |
880 | ||
881 | for (i = 0; i < sizeof(avi_if); i += 8) { | |
d121a5d2 CW |
882 | if (!intel_sdvo_set_value(intel_sdvo, |
883 | SDVO_CMD_SET_HBUF_DATA, | |
3c17fe4b DH |
884 | data, 8)) |
885 | return false; | |
886 | data++; | |
887 | } | |
e2f0ba97 | 888 | |
d121a5d2 CW |
889 | return intel_sdvo_set_value(intel_sdvo, |
890 | SDVO_CMD_SET_HBUF_TXRATE, | |
3c17fe4b | 891 | &tx_rate, 1); |
e2f0ba97 JB |
892 | } |
893 | ||
32aad86f | 894 | static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo) |
7026d4ac | 895 | { |
ce6feabd | 896 | struct intel_sdvo_tv_format format; |
40039750 | 897 | uint32_t format_map; |
ce6feabd | 898 | |
40039750 | 899 | format_map = 1 << intel_sdvo->tv_format_index; |
ce6feabd | 900 | memset(&format, 0, sizeof(format)); |
32aad86f | 901 | memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map))); |
ce6feabd | 902 | |
32aad86f CW |
903 | BUILD_BUG_ON(sizeof(format) != 6); |
904 | return intel_sdvo_set_value(intel_sdvo, | |
905 | SDVO_CMD_SET_TV_FORMAT, | |
906 | &format, sizeof(format)); | |
7026d4ac ZW |
907 | } |
908 | ||
32aad86f CW |
909 | static bool |
910 | intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo, | |
911 | struct drm_display_mode *mode) | |
e2f0ba97 | 912 | { |
32aad86f | 913 | struct intel_sdvo_dtd output_dtd; |
79e53945 | 914 | |
32aad86f CW |
915 | if (!intel_sdvo_set_target_output(intel_sdvo, |
916 | intel_sdvo->attached_output)) | |
917 | return false; | |
e2f0ba97 | 918 | |
32aad86f CW |
919 | intel_sdvo_get_dtd_from_mode(&output_dtd, mode); |
920 | if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) | |
921 | return false; | |
e2f0ba97 | 922 | |
32aad86f CW |
923 | return true; |
924 | } | |
925 | ||
926 | static bool | |
927 | intel_sdvo_set_input_timings_for_mode(struct intel_sdvo *intel_sdvo, | |
928 | struct drm_display_mode *mode, | |
929 | struct drm_display_mode *adjusted_mode) | |
930 | { | |
32aad86f CW |
931 | /* Reset the input timing to the screen. Assume always input 0. */ |
932 | if (!intel_sdvo_set_target_input(intel_sdvo)) | |
933 | return false; | |
e2f0ba97 | 934 | |
32aad86f CW |
935 | if (!intel_sdvo_create_preferred_input_timing(intel_sdvo, |
936 | mode->clock / 10, | |
937 | mode->hdisplay, | |
938 | mode->vdisplay)) | |
939 | return false; | |
e2f0ba97 | 940 | |
32aad86f | 941 | if (!intel_sdvo_get_preferred_input_timing(intel_sdvo, |
6c9547ff | 942 | &intel_sdvo->input_dtd)) |
32aad86f | 943 | return false; |
e2f0ba97 | 944 | |
6c9547ff | 945 | intel_sdvo_get_mode_from_dtd(adjusted_mode, &intel_sdvo->input_dtd); |
79e53945 | 946 | |
32aad86f | 947 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
32aad86f CW |
948 | return true; |
949 | } | |
12682a97 | 950 | |
32aad86f CW |
951 | static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder, |
952 | struct drm_display_mode *mode, | |
953 | struct drm_display_mode *adjusted_mode) | |
954 | { | |
890f3359 | 955 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder); |
6c9547ff | 956 | int multiplier; |
12682a97 | 957 | |
32aad86f CW |
958 | /* We need to construct preferred input timings based on our |
959 | * output timings. To do that, we have to set the output | |
960 | * timings, even though this isn't really the right place in | |
961 | * the sequence to do it. Oh well. | |
962 | */ | |
963 | if (intel_sdvo->is_tv) { | |
964 | if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode)) | |
965 | return false; | |
12682a97 | 966 | |
c74696b9 PR |
967 | (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo, |
968 | mode, | |
969 | adjusted_mode); | |
ea5b213a | 970 | } else if (intel_sdvo->is_lvds) { |
32aad86f | 971 | if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, |
6c9547ff | 972 | intel_sdvo->sdvo_lvds_fixed_mode)) |
e2f0ba97 | 973 | return false; |
12682a97 | 974 | |
c74696b9 PR |
975 | (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo, |
976 | mode, | |
977 | adjusted_mode); | |
e2f0ba97 | 978 | } |
32aad86f CW |
979 | |
980 | /* Make the CRTC code factor in the SDVO pixel multiplier. The | |
6c9547ff | 981 | * SDVO device will factor out the multiplier during mode_set. |
32aad86f | 982 | */ |
6c9547ff CW |
983 | multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode); |
984 | intel_mode_set_pixel_multiplier(adjusted_mode, multiplier); | |
32aad86f | 985 | |
e2f0ba97 JB |
986 | return true; |
987 | } | |
988 | ||
989 | static void intel_sdvo_mode_set(struct drm_encoder *encoder, | |
990 | struct drm_display_mode *mode, | |
991 | struct drm_display_mode *adjusted_mode) | |
992 | { | |
993 | struct drm_device *dev = encoder->dev; | |
994 | struct drm_i915_private *dev_priv = dev->dev_private; | |
995 | struct drm_crtc *crtc = encoder->crtc; | |
996 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
890f3359 | 997 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder); |
6c9547ff | 998 | u32 sdvox; |
e2f0ba97 JB |
999 | struct intel_sdvo_in_out_map in_out; |
1000 | struct intel_sdvo_dtd input_dtd; | |
6c9547ff CW |
1001 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
1002 | int rate; | |
e2f0ba97 JB |
1003 | |
1004 | if (!mode) | |
1005 | return; | |
1006 | ||
1007 | /* First, set the input mapping for the first input to our controlled | |
1008 | * output. This is only correct if we're a single-input device, in | |
1009 | * which case the first input is the output from the appropriate SDVO | |
1010 | * channel on the motherboard. In a two-input device, the first input | |
1011 | * will be SDVOB and the second SDVOC. | |
1012 | */ | |
ea5b213a | 1013 | in_out.in0 = intel_sdvo->attached_output; |
e2f0ba97 JB |
1014 | in_out.in1 = 0; |
1015 | ||
c74696b9 PR |
1016 | intel_sdvo_set_value(intel_sdvo, |
1017 | SDVO_CMD_SET_IN_OUT_MAP, | |
1018 | &in_out, sizeof(in_out)); | |
e2f0ba97 | 1019 | |
6c9547ff CW |
1020 | /* Set the output timings to the screen */ |
1021 | if (!intel_sdvo_set_target_output(intel_sdvo, | |
1022 | intel_sdvo->attached_output)) | |
1023 | return; | |
e2f0ba97 | 1024 | |
7026d4ac | 1025 | /* We have tried to get input timing in mode_fixup, and filled into |
6c9547ff | 1026 | * adjusted_mode. |
e2f0ba97 | 1027 | */ |
6c9547ff CW |
1028 | if (intel_sdvo->is_tv || intel_sdvo->is_lvds) { |
1029 | input_dtd = intel_sdvo->input_dtd; | |
1030 | } else { | |
e2f0ba97 | 1031 | /* Set the output timing to the screen */ |
32aad86f CW |
1032 | if (!intel_sdvo_set_target_output(intel_sdvo, |
1033 | intel_sdvo->attached_output)) | |
1034 | return; | |
1035 | ||
6c9547ff | 1036 | intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode); |
c74696b9 | 1037 | (void) intel_sdvo_set_output_timing(intel_sdvo, &input_dtd); |
e2f0ba97 | 1038 | } |
79e53945 JB |
1039 | |
1040 | /* Set the input timing to the screen. Assume always input 0. */ | |
32aad86f CW |
1041 | if (!intel_sdvo_set_target_input(intel_sdvo)) |
1042 | return; | |
79e53945 | 1043 | |
97aaf910 CW |
1044 | if (intel_sdvo->has_hdmi_monitor) { |
1045 | intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI); | |
1046 | intel_sdvo_set_colorimetry(intel_sdvo, | |
1047 | SDVO_COLORIMETRY_RGB256); | |
1048 | intel_sdvo_set_avi_infoframe(intel_sdvo); | |
1049 | } else | |
1050 | intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI); | |
7026d4ac | 1051 | |
6c9547ff CW |
1052 | if (intel_sdvo->is_tv && |
1053 | !intel_sdvo_set_tv_format(intel_sdvo)) | |
1054 | return; | |
e2f0ba97 | 1055 | |
c74696b9 | 1056 | (void) intel_sdvo_set_input_timing(intel_sdvo, &input_dtd); |
79e53945 | 1057 | |
6c9547ff CW |
1058 | switch (pixel_multiplier) { |
1059 | default: | |
32aad86f CW |
1060 | case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; |
1061 | case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break; | |
1062 | case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break; | |
79e53945 | 1063 | } |
32aad86f CW |
1064 | if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate)) |
1065 | return; | |
79e53945 JB |
1066 | |
1067 | /* Set the SDVO control regs. */ | |
a6c45cf0 | 1068 | if (INTEL_INFO(dev)->gen >= 4) { |
6714afb1 | 1069 | sdvox = 0; |
e953fd7b CW |
1070 | if (intel_sdvo->is_hdmi) |
1071 | sdvox |= intel_sdvo->color_range; | |
6714afb1 CW |
1072 | if (INTEL_INFO(dev)->gen < 5) |
1073 | sdvox |= SDVO_BORDER_ENABLE; | |
81a14b46 AJ |
1074 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
1075 | sdvox |= SDVO_VSYNC_ACTIVE_HIGH; | |
1076 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
1077 | sdvox |= SDVO_HSYNC_ACTIVE_HIGH; | |
e2f0ba97 | 1078 | } else { |
6c9547ff | 1079 | sdvox = I915_READ(intel_sdvo->sdvo_reg); |
ea5b213a | 1080 | switch (intel_sdvo->sdvo_reg) { |
e2f0ba97 JB |
1081 | case SDVOB: |
1082 | sdvox &= SDVOB_PRESERVE_MASK; | |
1083 | break; | |
1084 | case SDVOC: | |
1085 | sdvox &= SDVOC_PRESERVE_MASK; | |
1086 | break; | |
1087 | } | |
1088 | sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; | |
1089 | } | |
3573c410 PZ |
1090 | |
1091 | if (INTEL_PCH_TYPE(dev) >= PCH_CPT) | |
1092 | sdvox |= TRANSCODER_CPT(intel_crtc->pipe); | |
1093 | else | |
1094 | sdvox |= TRANSCODER(intel_crtc->pipe); | |
1095 | ||
da79de97 | 1096 | if (intel_sdvo->has_hdmi_audio) |
6c9547ff | 1097 | sdvox |= SDVO_AUDIO_ENABLE; |
79e53945 | 1098 | |
a6c45cf0 | 1099 | if (INTEL_INFO(dev)->gen >= 4) { |
e2f0ba97 JB |
1100 | /* done in crtc_mode_set as the dpll_md reg must be written early */ |
1101 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { | |
1102 | /* done in crtc_mode_set as it lives inside the dpll register */ | |
79e53945 | 1103 | } else { |
6c9547ff | 1104 | sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT; |
79e53945 JB |
1105 | } |
1106 | ||
6714afb1 CW |
1107 | if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL && |
1108 | INTEL_INFO(dev)->gen < 5) | |
12682a97 | 1109 | sdvox |= SDVO_STALL_SELECT; |
ea5b213a | 1110 | intel_sdvo_write_sdvox(intel_sdvo, sdvox); |
79e53945 JB |
1111 | } |
1112 | ||
1113 | static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode) | |
1114 | { | |
1115 | struct drm_device *dev = encoder->dev; | |
1116 | struct drm_i915_private *dev_priv = dev->dev_private; | |
890f3359 | 1117 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder); |
9d0498a2 | 1118 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
79e53945 JB |
1119 | u32 temp; |
1120 | ||
1121 | if (mode != DRM_MODE_DPMS_ON) { | |
ea5b213a | 1122 | intel_sdvo_set_active_outputs(intel_sdvo, 0); |
79e53945 | 1123 | if (0) |
ea5b213a | 1124 | intel_sdvo_set_encoder_power_state(intel_sdvo, mode); |
79e53945 JB |
1125 | |
1126 | if (mode == DRM_MODE_DPMS_OFF) { | |
ea5b213a | 1127 | temp = I915_READ(intel_sdvo->sdvo_reg); |
79e53945 | 1128 | if ((temp & SDVO_ENABLE) != 0) { |
ea5b213a | 1129 | intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE); |
79e53945 JB |
1130 | } |
1131 | } | |
1132 | } else { | |
1133 | bool input1, input2; | |
1134 | int i; | |
1135 | u8 status; | |
1136 | ||
ea5b213a | 1137 | temp = I915_READ(intel_sdvo->sdvo_reg); |
79e53945 | 1138 | if ((temp & SDVO_ENABLE) == 0) |
ea5b213a | 1139 | intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE); |
79e53945 | 1140 | for (i = 0; i < 2; i++) |
9d0498a2 | 1141 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
79e53945 | 1142 | |
32aad86f | 1143 | status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2); |
79e53945 JB |
1144 | /* Warn if the device reported failure to sync. |
1145 | * A lot of SDVO devices fail to notify of sync, but it's | |
1146 | * a given it the status is a success, we succeeded. | |
1147 | */ | |
1148 | if (status == SDVO_CMD_STATUS_SUCCESS && !input1) { | |
8a4c47f3 | 1149 | DRM_DEBUG_KMS("First %s output reported failure to " |
ea5b213a | 1150 | "sync\n", SDVO_NAME(intel_sdvo)); |
79e53945 JB |
1151 | } |
1152 | ||
1153 | if (0) | |
ea5b213a CW |
1154 | intel_sdvo_set_encoder_power_state(intel_sdvo, mode); |
1155 | intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output); | |
79e53945 JB |
1156 | } |
1157 | return; | |
1158 | } | |
1159 | ||
79e53945 JB |
1160 | static int intel_sdvo_mode_valid(struct drm_connector *connector, |
1161 | struct drm_display_mode *mode) | |
1162 | { | |
df0e9248 | 1163 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
79e53945 JB |
1164 | |
1165 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
1166 | return MODE_NO_DBLESCAN; | |
1167 | ||
ea5b213a | 1168 | if (intel_sdvo->pixel_clock_min > mode->clock) |
79e53945 JB |
1169 | return MODE_CLOCK_LOW; |
1170 | ||
ea5b213a | 1171 | if (intel_sdvo->pixel_clock_max < mode->clock) |
79e53945 JB |
1172 | return MODE_CLOCK_HIGH; |
1173 | ||
8545423a | 1174 | if (intel_sdvo->is_lvds) { |
ea5b213a | 1175 | if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay) |
12682a97 | 1176 | return MODE_PANEL; |
1177 | ||
ea5b213a | 1178 | if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay) |
12682a97 | 1179 | return MODE_PANEL; |
1180 | } | |
1181 | ||
79e53945 JB |
1182 | return MODE_OK; |
1183 | } | |
1184 | ||
ea5b213a | 1185 | static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps) |
79e53945 | 1186 | { |
1a3665c8 | 1187 | BUILD_BUG_ON(sizeof(*caps) != 8); |
e957d772 CW |
1188 | if (!intel_sdvo_get_value(intel_sdvo, |
1189 | SDVO_CMD_GET_DEVICE_CAPS, | |
1190 | caps, sizeof(*caps))) | |
1191 | return false; | |
1192 | ||
1193 | DRM_DEBUG_KMS("SDVO capabilities:\n" | |
1194 | " vendor_id: %d\n" | |
1195 | " device_id: %d\n" | |
1196 | " device_rev_id: %d\n" | |
1197 | " sdvo_version_major: %d\n" | |
1198 | " sdvo_version_minor: %d\n" | |
1199 | " sdvo_inputs_mask: %d\n" | |
1200 | " smooth_scaling: %d\n" | |
1201 | " sharp_scaling: %d\n" | |
1202 | " up_scaling: %d\n" | |
1203 | " down_scaling: %d\n" | |
1204 | " stall_support: %d\n" | |
1205 | " output_flags: %d\n", | |
1206 | caps->vendor_id, | |
1207 | caps->device_id, | |
1208 | caps->device_rev_id, | |
1209 | caps->sdvo_version_major, | |
1210 | caps->sdvo_version_minor, | |
1211 | caps->sdvo_inputs_mask, | |
1212 | caps->smooth_scaling, | |
1213 | caps->sharp_scaling, | |
1214 | caps->up_scaling, | |
1215 | caps->down_scaling, | |
1216 | caps->stall_support, | |
1217 | caps->output_flags); | |
1218 | ||
1219 | return true; | |
79e53945 JB |
1220 | } |
1221 | ||
cc68c81a | 1222 | static int intel_sdvo_supports_hotplug(struct intel_sdvo *intel_sdvo) |
79e53945 JB |
1223 | { |
1224 | u8 response[2]; | |
79e53945 | 1225 | |
32aad86f CW |
1226 | return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, |
1227 | &response, 2) && response[0]; | |
79e53945 JB |
1228 | } |
1229 | ||
cc68c81a | 1230 | static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder) |
79e53945 | 1231 | { |
cc68c81a | 1232 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base); |
79e53945 | 1233 | |
cc68c81a | 1234 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &intel_sdvo->hotplug_active, 2); |
79e53945 JB |
1235 | } |
1236 | ||
fb7a46f3 | 1237 | static bool |
ea5b213a | 1238 | intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo) |
fb7a46f3 | 1239 | { |
bc65212c | 1240 | /* Is there more than one type of output? */ |
2294488d | 1241 | return hweight16(intel_sdvo->caps.output_flags) > 1; |
fb7a46f3 | 1242 | } |
1243 | ||
f899fc64 | 1244 | static struct edid * |
e957d772 | 1245 | intel_sdvo_get_edid(struct drm_connector *connector) |
f899fc64 | 1246 | { |
e957d772 CW |
1247 | struct intel_sdvo *sdvo = intel_attached_sdvo(connector); |
1248 | return drm_get_edid(connector, &sdvo->ddc); | |
f899fc64 CW |
1249 | } |
1250 | ||
ff482d83 CW |
1251 | /* Mac mini hack -- use the same DDC as the analog connector */ |
1252 | static struct edid * | |
1253 | intel_sdvo_get_analog_edid(struct drm_connector *connector) | |
1254 | { | |
f899fc64 | 1255 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
ff482d83 | 1256 | |
0c1dab89 CW |
1257 | return drm_get_edid(connector, |
1258 | &dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter); | |
ff482d83 CW |
1259 | } |
1260 | ||
2b8d33f7 | 1261 | enum drm_connector_status |
8bf38485 | 1262 | intel_sdvo_tmds_sink_detect(struct drm_connector *connector) |
9dff6af8 | 1263 | { |
df0e9248 | 1264 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
9d1a903d CW |
1265 | enum drm_connector_status status; |
1266 | struct edid *edid; | |
9dff6af8 | 1267 | |
e957d772 | 1268 | edid = intel_sdvo_get_edid(connector); |
57cdaf90 | 1269 | |
ea5b213a | 1270 | if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) { |
e957d772 | 1271 | u8 ddc, saved_ddc = intel_sdvo->ddc_bus; |
9d1a903d | 1272 | |
7c3f0a27 ZY |
1273 | /* |
1274 | * Don't use the 1 as the argument of DDC bus switch to get | |
1275 | * the EDID. It is used for SDVO SPD ROM. | |
1276 | */ | |
9d1a903d | 1277 | for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) { |
e957d772 CW |
1278 | intel_sdvo->ddc_bus = ddc; |
1279 | edid = intel_sdvo_get_edid(connector); | |
1280 | if (edid) | |
7c3f0a27 | 1281 | break; |
7c3f0a27 | 1282 | } |
e957d772 CW |
1283 | /* |
1284 | * If we found the EDID on the other bus, | |
1285 | * assume that is the correct DDC bus. | |
1286 | */ | |
1287 | if (edid == NULL) | |
1288 | intel_sdvo->ddc_bus = saved_ddc; | |
7c3f0a27 | 1289 | } |
9d1a903d CW |
1290 | |
1291 | /* | |
1292 | * When there is no edid and no monitor is connected with VGA | |
1293 | * port, try to use the CRT ddc to read the EDID for DVI-connector. | |
57cdaf90 | 1294 | */ |
ff482d83 CW |
1295 | if (edid == NULL) |
1296 | edid = intel_sdvo_get_analog_edid(connector); | |
149c36a3 | 1297 | |
2f551c84 | 1298 | status = connector_status_unknown; |
9dff6af8 | 1299 | if (edid != NULL) { |
149c36a3 | 1300 | /* DDC bus is shared, match EDID to connector type */ |
9d1a903d CW |
1301 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
1302 | status = connector_status_connected; | |
da79de97 CW |
1303 | if (intel_sdvo->is_hdmi) { |
1304 | intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid); | |
1305 | intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid); | |
1306 | } | |
13946743 CW |
1307 | } else |
1308 | status = connector_status_disconnected; | |
149c36a3 | 1309 | connector->display_info.raw_edid = NULL; |
9d1a903d CW |
1310 | kfree(edid); |
1311 | } | |
7f36e7ed CW |
1312 | |
1313 | if (status == connector_status_connected) { | |
1314 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); | |
1315 | if (intel_sdvo_connector->force_audio) | |
da79de97 | 1316 | intel_sdvo->has_hdmi_audio = intel_sdvo_connector->force_audio > 0; |
7f36e7ed CW |
1317 | } |
1318 | ||
2b8d33f7 | 1319 | return status; |
9dff6af8 ML |
1320 | } |
1321 | ||
52220085 CW |
1322 | static bool |
1323 | intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo, | |
1324 | struct edid *edid) | |
1325 | { | |
1326 | bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL); | |
1327 | bool connector_is_digital = !!IS_DIGITAL(sdvo); | |
1328 | ||
1329 | DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n", | |
1330 | connector_is_digital, monitor_is_digital); | |
1331 | return connector_is_digital == monitor_is_digital; | |
1332 | } | |
1333 | ||
7b334fcb | 1334 | static enum drm_connector_status |
930a9e28 | 1335 | intel_sdvo_detect(struct drm_connector *connector, bool force) |
79e53945 | 1336 | { |
fb7a46f3 | 1337 | uint16_t response; |
df0e9248 | 1338 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
615fb93f | 1339 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
14571b4c | 1340 | enum drm_connector_status ret; |
79e53945 | 1341 | |
32aad86f | 1342 | if (!intel_sdvo_write_cmd(intel_sdvo, |
e957d772 | 1343 | SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0)) |
32aad86f | 1344 | return connector_status_unknown; |
ba84cd1f CW |
1345 | |
1346 | /* add 30ms delay when the output type might be TV */ | |
1347 | if (intel_sdvo->caps.output_flags & | |
1348 | (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_CVBS0)) | |
d09c23de | 1349 | mdelay(30); |
ba84cd1f | 1350 | |
32aad86f CW |
1351 | if (!intel_sdvo_read_response(intel_sdvo, &response, 2)) |
1352 | return connector_status_unknown; | |
79e53945 | 1353 | |
e957d772 CW |
1354 | DRM_DEBUG_KMS("SDVO response %d %d [%x]\n", |
1355 | response & 0xff, response >> 8, | |
1356 | intel_sdvo_connector->output_flag); | |
e2f0ba97 | 1357 | |
fb7a46f3 | 1358 | if (response == 0) |
79e53945 | 1359 | return connector_status_disconnected; |
fb7a46f3 | 1360 | |
ea5b213a | 1361 | intel_sdvo->attached_output = response; |
14571b4c | 1362 | |
97aaf910 CW |
1363 | intel_sdvo->has_hdmi_monitor = false; |
1364 | intel_sdvo->has_hdmi_audio = false; | |
1365 | ||
615fb93f | 1366 | if ((intel_sdvo_connector->output_flag & response) == 0) |
14571b4c | 1367 | ret = connector_status_disconnected; |
13946743 | 1368 | else if (IS_TMDS(intel_sdvo_connector)) |
8bf38485 | 1369 | ret = intel_sdvo_tmds_sink_detect(connector); |
13946743 CW |
1370 | else { |
1371 | struct edid *edid; | |
1372 | ||
1373 | /* if we have an edid check it matches the connection */ | |
1374 | edid = intel_sdvo_get_edid(connector); | |
1375 | if (edid == NULL) | |
1376 | edid = intel_sdvo_get_analog_edid(connector); | |
1377 | if (edid != NULL) { | |
52220085 CW |
1378 | if (intel_sdvo_connector_matches_edid(intel_sdvo_connector, |
1379 | edid)) | |
13946743 | 1380 | ret = connector_status_connected; |
52220085 CW |
1381 | else |
1382 | ret = connector_status_disconnected; | |
1383 | ||
13946743 CW |
1384 | connector->display_info.raw_edid = NULL; |
1385 | kfree(edid); | |
1386 | } else | |
1387 | ret = connector_status_connected; | |
1388 | } | |
14571b4c ZW |
1389 | |
1390 | /* May update encoder flag for like clock for SDVO TV, etc.*/ | |
1391 | if (ret == connector_status_connected) { | |
ea5b213a CW |
1392 | intel_sdvo->is_tv = false; |
1393 | intel_sdvo->is_lvds = false; | |
1394 | intel_sdvo->base.needs_tv_clock = false; | |
14571b4c ZW |
1395 | |
1396 | if (response & SDVO_TV_MASK) { | |
ea5b213a CW |
1397 | intel_sdvo->is_tv = true; |
1398 | intel_sdvo->base.needs_tv_clock = true; | |
14571b4c ZW |
1399 | } |
1400 | if (response & SDVO_LVDS_MASK) | |
8545423a | 1401 | intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL; |
fb7a46f3 | 1402 | } |
14571b4c ZW |
1403 | |
1404 | return ret; | |
79e53945 JB |
1405 | } |
1406 | ||
e2f0ba97 | 1407 | static void intel_sdvo_get_ddc_modes(struct drm_connector *connector) |
79e53945 | 1408 | { |
ff482d83 | 1409 | struct edid *edid; |
79e53945 JB |
1410 | |
1411 | /* set the bus switch and get the modes */ | |
e957d772 | 1412 | edid = intel_sdvo_get_edid(connector); |
79e53945 | 1413 | |
57cdaf90 KP |
1414 | /* |
1415 | * Mac mini hack. On this device, the DVI-I connector shares one DDC | |
1416 | * link between analog and digital outputs. So, if the regular SDVO | |
1417 | * DDC fails, check to see if the analog output is disconnected, in | |
1418 | * which case we'll look there for the digital DDC data. | |
e2f0ba97 | 1419 | */ |
f899fc64 CW |
1420 | if (edid == NULL) |
1421 | edid = intel_sdvo_get_analog_edid(connector); | |
1422 | ||
ff482d83 | 1423 | if (edid != NULL) { |
52220085 CW |
1424 | if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector), |
1425 | edid)) { | |
0c1dab89 CW |
1426 | drm_mode_connector_update_edid_property(connector, edid); |
1427 | drm_add_edid_modes(connector, edid); | |
1428 | } | |
13946743 | 1429 | |
ff482d83 CW |
1430 | connector->display_info.raw_edid = NULL; |
1431 | kfree(edid); | |
e2f0ba97 | 1432 | } |
e2f0ba97 JB |
1433 | } |
1434 | ||
1435 | /* | |
1436 | * Set of SDVO TV modes. | |
1437 | * Note! This is in reply order (see loop in get_tv_modes). | |
1438 | * XXX: all 60Hz refresh? | |
1439 | */ | |
b1f559ec | 1440 | static const struct drm_display_mode sdvo_tv_modes[] = { |
7026d4ac ZW |
1441 | { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384, |
1442 | 416, 0, 200, 201, 232, 233, 0, | |
e2f0ba97 | 1443 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1444 | { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384, |
1445 | 416, 0, 240, 241, 272, 273, 0, | |
e2f0ba97 | 1446 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1447 | { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464, |
1448 | 496, 0, 300, 301, 332, 333, 0, | |
e2f0ba97 | 1449 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1450 | { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704, |
1451 | 736, 0, 350, 351, 382, 383, 0, | |
e2f0ba97 | 1452 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1453 | { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704, |
1454 | 736, 0, 400, 401, 432, 433, 0, | |
e2f0ba97 | 1455 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1456 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704, |
1457 | 736, 0, 480, 481, 512, 513, 0, | |
e2f0ba97 | 1458 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1459 | { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768, |
1460 | 800, 0, 480, 481, 512, 513, 0, | |
e2f0ba97 | 1461 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1462 | { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768, |
1463 | 800, 0, 576, 577, 608, 609, 0, | |
e2f0ba97 | 1464 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1465 | { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784, |
1466 | 816, 0, 350, 351, 382, 383, 0, | |
e2f0ba97 | 1467 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1468 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784, |
1469 | 816, 0, 400, 401, 432, 433, 0, | |
e2f0ba97 | 1470 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1471 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784, |
1472 | 816, 0, 480, 481, 512, 513, 0, | |
e2f0ba97 | 1473 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1474 | { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784, |
1475 | 816, 0, 540, 541, 572, 573, 0, | |
e2f0ba97 | 1476 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1477 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784, |
1478 | 816, 0, 576, 577, 608, 609, 0, | |
e2f0ba97 | 1479 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1480 | { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832, |
1481 | 864, 0, 576, 577, 608, 609, 0, | |
e2f0ba97 | 1482 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1483 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864, |
1484 | 896, 0, 600, 601, 632, 633, 0, | |
e2f0ba97 | 1485 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1486 | { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896, |
1487 | 928, 0, 624, 625, 656, 657, 0, | |
e2f0ba97 | 1488 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1489 | { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984, |
1490 | 1016, 0, 766, 767, 798, 799, 0, | |
e2f0ba97 | 1491 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1492 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088, |
1493 | 1120, 0, 768, 769, 800, 801, 0, | |
e2f0ba97 | 1494 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1495 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344, |
1496 | 1376, 0, 1024, 1025, 1056, 1057, 0, | |
e2f0ba97 JB |
1497 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
1498 | }; | |
1499 | ||
1500 | static void intel_sdvo_get_tv_modes(struct drm_connector *connector) | |
1501 | { | |
df0e9248 | 1502 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
7026d4ac | 1503 | struct intel_sdvo_sdtv_resolution_request tv_res; |
ce6feabd ZY |
1504 | uint32_t reply = 0, format_map = 0; |
1505 | int i; | |
e2f0ba97 JB |
1506 | |
1507 | /* Read the list of supported input resolutions for the selected TV | |
1508 | * format. | |
1509 | */ | |
40039750 | 1510 | format_map = 1 << intel_sdvo->tv_format_index; |
ce6feabd | 1511 | memcpy(&tv_res, &format_map, |
32aad86f | 1512 | min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request))); |
ce6feabd | 1513 | |
32aad86f CW |
1514 | if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output)) |
1515 | return; | |
ce6feabd | 1516 | |
32aad86f | 1517 | BUILD_BUG_ON(sizeof(tv_res) != 3); |
e957d772 CW |
1518 | if (!intel_sdvo_write_cmd(intel_sdvo, |
1519 | SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, | |
32aad86f CW |
1520 | &tv_res, sizeof(tv_res))) |
1521 | return; | |
1522 | if (!intel_sdvo_read_response(intel_sdvo, &reply, 3)) | |
e2f0ba97 JB |
1523 | return; |
1524 | ||
1525 | for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) | |
7026d4ac ZW |
1526 | if (reply & (1 << i)) { |
1527 | struct drm_display_mode *nmode; | |
1528 | nmode = drm_mode_duplicate(connector->dev, | |
32aad86f | 1529 | &sdvo_tv_modes[i]); |
7026d4ac ZW |
1530 | if (nmode) |
1531 | drm_mode_probed_add(connector, nmode); | |
1532 | } | |
e2f0ba97 JB |
1533 | } |
1534 | ||
7086c87f ML |
1535 | static void intel_sdvo_get_lvds_modes(struct drm_connector *connector) |
1536 | { | |
df0e9248 | 1537 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
7086c87f | 1538 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
12682a97 | 1539 | struct drm_display_mode *newmode; |
7086c87f ML |
1540 | |
1541 | /* | |
1542 | * Attempt to get the mode list from DDC. | |
1543 | * Assume that the preferred modes are | |
1544 | * arranged in priority order. | |
1545 | */ | |
f899fc64 | 1546 | intel_ddc_get_modes(connector, intel_sdvo->i2c); |
7086c87f | 1547 | if (list_empty(&connector->probed_modes) == false) |
12682a97 | 1548 | goto end; |
7086c87f ML |
1549 | |
1550 | /* Fetch modes from VBT */ | |
1551 | if (dev_priv->sdvo_lvds_vbt_mode != NULL) { | |
7086c87f ML |
1552 | newmode = drm_mode_duplicate(connector->dev, |
1553 | dev_priv->sdvo_lvds_vbt_mode); | |
1554 | if (newmode != NULL) { | |
1555 | /* Guarantee the mode is preferred */ | |
1556 | newmode->type = (DRM_MODE_TYPE_PREFERRED | | |
1557 | DRM_MODE_TYPE_DRIVER); | |
1558 | drm_mode_probed_add(connector, newmode); | |
1559 | } | |
1560 | } | |
12682a97 | 1561 | |
1562 | end: | |
1563 | list_for_each_entry(newmode, &connector->probed_modes, head) { | |
1564 | if (newmode->type & DRM_MODE_TYPE_PREFERRED) { | |
ea5b213a | 1565 | intel_sdvo->sdvo_lvds_fixed_mode = |
12682a97 | 1566 | drm_mode_duplicate(connector->dev, newmode); |
6c9547ff CW |
1567 | |
1568 | drm_mode_set_crtcinfo(intel_sdvo->sdvo_lvds_fixed_mode, | |
1569 | 0); | |
1570 | ||
8545423a | 1571 | intel_sdvo->is_lvds = true; |
12682a97 | 1572 | break; |
1573 | } | |
1574 | } | |
1575 | ||
7086c87f ML |
1576 | } |
1577 | ||
e2f0ba97 JB |
1578 | static int intel_sdvo_get_modes(struct drm_connector *connector) |
1579 | { | |
615fb93f | 1580 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
e2f0ba97 | 1581 | |
615fb93f | 1582 | if (IS_TV(intel_sdvo_connector)) |
e2f0ba97 | 1583 | intel_sdvo_get_tv_modes(connector); |
615fb93f | 1584 | else if (IS_LVDS(intel_sdvo_connector)) |
7086c87f | 1585 | intel_sdvo_get_lvds_modes(connector); |
e2f0ba97 JB |
1586 | else |
1587 | intel_sdvo_get_ddc_modes(connector); | |
1588 | ||
32aad86f | 1589 | return !list_empty(&connector->probed_modes); |
79e53945 JB |
1590 | } |
1591 | ||
fcc8d672 CW |
1592 | static void |
1593 | intel_sdvo_destroy_enhance_property(struct drm_connector *connector) | |
b9219c5e | 1594 | { |
615fb93f | 1595 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
b9219c5e ZY |
1596 | struct drm_device *dev = connector->dev; |
1597 | ||
c5521706 CW |
1598 | if (intel_sdvo_connector->left) |
1599 | drm_property_destroy(dev, intel_sdvo_connector->left); | |
1600 | if (intel_sdvo_connector->right) | |
1601 | drm_property_destroy(dev, intel_sdvo_connector->right); | |
1602 | if (intel_sdvo_connector->top) | |
1603 | drm_property_destroy(dev, intel_sdvo_connector->top); | |
1604 | if (intel_sdvo_connector->bottom) | |
1605 | drm_property_destroy(dev, intel_sdvo_connector->bottom); | |
1606 | if (intel_sdvo_connector->hpos) | |
1607 | drm_property_destroy(dev, intel_sdvo_connector->hpos); | |
1608 | if (intel_sdvo_connector->vpos) | |
1609 | drm_property_destroy(dev, intel_sdvo_connector->vpos); | |
1610 | if (intel_sdvo_connector->saturation) | |
1611 | drm_property_destroy(dev, intel_sdvo_connector->saturation); | |
1612 | if (intel_sdvo_connector->contrast) | |
1613 | drm_property_destroy(dev, intel_sdvo_connector->contrast); | |
1614 | if (intel_sdvo_connector->hue) | |
1615 | drm_property_destroy(dev, intel_sdvo_connector->hue); | |
1616 | if (intel_sdvo_connector->sharpness) | |
1617 | drm_property_destroy(dev, intel_sdvo_connector->sharpness); | |
1618 | if (intel_sdvo_connector->flicker_filter) | |
1619 | drm_property_destroy(dev, intel_sdvo_connector->flicker_filter); | |
1620 | if (intel_sdvo_connector->flicker_filter_2d) | |
1621 | drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d); | |
1622 | if (intel_sdvo_connector->flicker_filter_adaptive) | |
1623 | drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive); | |
1624 | if (intel_sdvo_connector->tv_luma_filter) | |
1625 | drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter); | |
1626 | if (intel_sdvo_connector->tv_chroma_filter) | |
1627 | drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter); | |
e044218a CW |
1628 | if (intel_sdvo_connector->dot_crawl) |
1629 | drm_property_destroy(dev, intel_sdvo_connector->dot_crawl); | |
c5521706 CW |
1630 | if (intel_sdvo_connector->brightness) |
1631 | drm_property_destroy(dev, intel_sdvo_connector->brightness); | |
b9219c5e ZY |
1632 | } |
1633 | ||
79e53945 JB |
1634 | static void intel_sdvo_destroy(struct drm_connector *connector) |
1635 | { | |
615fb93f | 1636 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
79e53945 | 1637 | |
c5521706 | 1638 | if (intel_sdvo_connector->tv_format) |
ce6feabd | 1639 | drm_property_destroy(connector->dev, |
c5521706 | 1640 | intel_sdvo_connector->tv_format); |
b9219c5e | 1641 | |
d2a82a6f | 1642 | intel_sdvo_destroy_enhance_property(connector); |
79e53945 JB |
1643 | drm_sysfs_connector_remove(connector); |
1644 | drm_connector_cleanup(connector); | |
d2a82a6f | 1645 | kfree(connector); |
79e53945 JB |
1646 | } |
1647 | ||
1aad7ac0 CW |
1648 | static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector) |
1649 | { | |
1650 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); | |
1651 | struct edid *edid; | |
1652 | bool has_audio = false; | |
1653 | ||
1654 | if (!intel_sdvo->is_hdmi) | |
1655 | return false; | |
1656 | ||
1657 | edid = intel_sdvo_get_edid(connector); | |
1658 | if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL) | |
1659 | has_audio = drm_detect_monitor_audio(edid); | |
1660 | ||
1661 | return has_audio; | |
1662 | } | |
1663 | ||
ce6feabd ZY |
1664 | static int |
1665 | intel_sdvo_set_property(struct drm_connector *connector, | |
1666 | struct drm_property *property, | |
1667 | uint64_t val) | |
1668 | { | |
df0e9248 | 1669 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
615fb93f | 1670 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
e953fd7b | 1671 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
b9219c5e | 1672 | uint16_t temp_value; |
32aad86f CW |
1673 | uint8_t cmd; |
1674 | int ret; | |
ce6feabd ZY |
1675 | |
1676 | ret = drm_connector_property_set_value(connector, property, val); | |
32aad86f CW |
1677 | if (ret) |
1678 | return ret; | |
ce6feabd | 1679 | |
3f43c48d | 1680 | if (property == dev_priv->force_audio_property) { |
1aad7ac0 CW |
1681 | int i = val; |
1682 | bool has_audio; | |
1683 | ||
1684 | if (i == intel_sdvo_connector->force_audio) | |
7f36e7ed CW |
1685 | return 0; |
1686 | ||
1aad7ac0 | 1687 | intel_sdvo_connector->force_audio = i; |
7f36e7ed | 1688 | |
1aad7ac0 CW |
1689 | if (i == 0) |
1690 | has_audio = intel_sdvo_detect_hdmi_audio(connector); | |
1691 | else | |
1692 | has_audio = i > 0; | |
7f36e7ed | 1693 | |
1aad7ac0 | 1694 | if (has_audio == intel_sdvo->has_hdmi_audio) |
7f36e7ed | 1695 | return 0; |
7f36e7ed | 1696 | |
1aad7ac0 | 1697 | intel_sdvo->has_hdmi_audio = has_audio; |
7f36e7ed CW |
1698 | goto done; |
1699 | } | |
1700 | ||
e953fd7b CW |
1701 | if (property == dev_priv->broadcast_rgb_property) { |
1702 | if (val == !!intel_sdvo->color_range) | |
7f36e7ed CW |
1703 | return 0; |
1704 | ||
e953fd7b | 1705 | intel_sdvo->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0; |
7f36e7ed CW |
1706 | goto done; |
1707 | } | |
1708 | ||
c5521706 CW |
1709 | #define CHECK_PROPERTY(name, NAME) \ |
1710 | if (intel_sdvo_connector->name == property) { \ | |
1711 | if (intel_sdvo_connector->cur_##name == temp_value) return 0; \ | |
1712 | if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \ | |
1713 | cmd = SDVO_CMD_SET_##NAME; \ | |
1714 | intel_sdvo_connector->cur_##name = temp_value; \ | |
1715 | goto set_value; \ | |
1716 | } | |
1717 | ||
1718 | if (property == intel_sdvo_connector->tv_format) { | |
32aad86f CW |
1719 | if (val >= TV_FORMAT_NUM) |
1720 | return -EINVAL; | |
1721 | ||
40039750 | 1722 | if (intel_sdvo->tv_format_index == |
615fb93f | 1723 | intel_sdvo_connector->tv_format_supported[val]) |
32aad86f | 1724 | return 0; |
ce6feabd | 1725 | |
40039750 | 1726 | intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val]; |
c5521706 | 1727 | goto done; |
32aad86f | 1728 | } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) { |
b9219c5e | 1729 | temp_value = val; |
c5521706 | 1730 | if (intel_sdvo_connector->left == property) { |
b9219c5e | 1731 | drm_connector_property_set_value(connector, |
c5521706 | 1732 | intel_sdvo_connector->right, val); |
615fb93f | 1733 | if (intel_sdvo_connector->left_margin == temp_value) |
32aad86f | 1734 | return 0; |
b9219c5e | 1735 | |
615fb93f CW |
1736 | intel_sdvo_connector->left_margin = temp_value; |
1737 | intel_sdvo_connector->right_margin = temp_value; | |
1738 | temp_value = intel_sdvo_connector->max_hscan - | |
c5521706 | 1739 | intel_sdvo_connector->left_margin; |
b9219c5e | 1740 | cmd = SDVO_CMD_SET_OVERSCAN_H; |
c5521706 CW |
1741 | goto set_value; |
1742 | } else if (intel_sdvo_connector->right == property) { | |
b9219c5e | 1743 | drm_connector_property_set_value(connector, |
c5521706 | 1744 | intel_sdvo_connector->left, val); |
615fb93f | 1745 | if (intel_sdvo_connector->right_margin == temp_value) |
32aad86f | 1746 | return 0; |
b9219c5e | 1747 | |
615fb93f CW |
1748 | intel_sdvo_connector->left_margin = temp_value; |
1749 | intel_sdvo_connector->right_margin = temp_value; | |
1750 | temp_value = intel_sdvo_connector->max_hscan - | |
1751 | intel_sdvo_connector->left_margin; | |
b9219c5e | 1752 | cmd = SDVO_CMD_SET_OVERSCAN_H; |
c5521706 CW |
1753 | goto set_value; |
1754 | } else if (intel_sdvo_connector->top == property) { | |
b9219c5e | 1755 | drm_connector_property_set_value(connector, |
c5521706 | 1756 | intel_sdvo_connector->bottom, val); |
615fb93f | 1757 | if (intel_sdvo_connector->top_margin == temp_value) |
32aad86f | 1758 | return 0; |
b9219c5e | 1759 | |
615fb93f CW |
1760 | intel_sdvo_connector->top_margin = temp_value; |
1761 | intel_sdvo_connector->bottom_margin = temp_value; | |
1762 | temp_value = intel_sdvo_connector->max_vscan - | |
c5521706 | 1763 | intel_sdvo_connector->top_margin; |
b9219c5e | 1764 | cmd = SDVO_CMD_SET_OVERSCAN_V; |
c5521706 CW |
1765 | goto set_value; |
1766 | } else if (intel_sdvo_connector->bottom == property) { | |
b9219c5e | 1767 | drm_connector_property_set_value(connector, |
c5521706 | 1768 | intel_sdvo_connector->top, val); |
615fb93f | 1769 | if (intel_sdvo_connector->bottom_margin == temp_value) |
32aad86f CW |
1770 | return 0; |
1771 | ||
615fb93f CW |
1772 | intel_sdvo_connector->top_margin = temp_value; |
1773 | intel_sdvo_connector->bottom_margin = temp_value; | |
1774 | temp_value = intel_sdvo_connector->max_vscan - | |
c5521706 | 1775 | intel_sdvo_connector->top_margin; |
b9219c5e | 1776 | cmd = SDVO_CMD_SET_OVERSCAN_V; |
c5521706 CW |
1777 | goto set_value; |
1778 | } | |
1779 | CHECK_PROPERTY(hpos, HPOS) | |
1780 | CHECK_PROPERTY(vpos, VPOS) | |
1781 | CHECK_PROPERTY(saturation, SATURATION) | |
1782 | CHECK_PROPERTY(contrast, CONTRAST) | |
1783 | CHECK_PROPERTY(hue, HUE) | |
1784 | CHECK_PROPERTY(brightness, BRIGHTNESS) | |
1785 | CHECK_PROPERTY(sharpness, SHARPNESS) | |
1786 | CHECK_PROPERTY(flicker_filter, FLICKER_FILTER) | |
1787 | CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D) | |
1788 | CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE) | |
1789 | CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER) | |
1790 | CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER) | |
e044218a | 1791 | CHECK_PROPERTY(dot_crawl, DOT_CRAWL) |
c5521706 | 1792 | } |
b9219c5e | 1793 | |
c5521706 | 1794 | return -EINVAL; /* unknown property */ |
b9219c5e | 1795 | |
c5521706 CW |
1796 | set_value: |
1797 | if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2)) | |
1798 | return -EIO; | |
b9219c5e | 1799 | |
b9219c5e | 1800 | |
c5521706 | 1801 | done: |
df0e9248 CW |
1802 | if (intel_sdvo->base.base.crtc) { |
1803 | struct drm_crtc *crtc = intel_sdvo->base.base.crtc; | |
ce6feabd | 1804 | drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x, |
c5521706 CW |
1805 | crtc->y, crtc->fb); |
1806 | } | |
1807 | ||
32aad86f | 1808 | return 0; |
c5521706 | 1809 | #undef CHECK_PROPERTY |
ce6feabd ZY |
1810 | } |
1811 | ||
79e53945 JB |
1812 | static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = { |
1813 | .dpms = intel_sdvo_dpms, | |
1814 | .mode_fixup = intel_sdvo_mode_fixup, | |
1815 | .prepare = intel_encoder_prepare, | |
1816 | .mode_set = intel_sdvo_mode_set, | |
1817 | .commit = intel_encoder_commit, | |
1818 | }; | |
1819 | ||
1820 | static const struct drm_connector_funcs intel_sdvo_connector_funcs = { | |
c9fb15f6 | 1821 | .dpms = drm_helper_connector_dpms, |
79e53945 JB |
1822 | .detect = intel_sdvo_detect, |
1823 | .fill_modes = drm_helper_probe_single_connector_modes, | |
ce6feabd | 1824 | .set_property = intel_sdvo_set_property, |
79e53945 JB |
1825 | .destroy = intel_sdvo_destroy, |
1826 | }; | |
1827 | ||
1828 | static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = { | |
1829 | .get_modes = intel_sdvo_get_modes, | |
1830 | .mode_valid = intel_sdvo_mode_valid, | |
df0e9248 | 1831 | .best_encoder = intel_best_encoder, |
79e53945 JB |
1832 | }; |
1833 | ||
b358d0a6 | 1834 | static void intel_sdvo_enc_destroy(struct drm_encoder *encoder) |
79e53945 | 1835 | { |
890f3359 | 1836 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder); |
d2a82a6f | 1837 | |
ea5b213a | 1838 | if (intel_sdvo->sdvo_lvds_fixed_mode != NULL) |
d2a82a6f | 1839 | drm_mode_destroy(encoder->dev, |
ea5b213a | 1840 | intel_sdvo->sdvo_lvds_fixed_mode); |
d2a82a6f | 1841 | |
e957d772 | 1842 | i2c_del_adapter(&intel_sdvo->ddc); |
ea5b213a | 1843 | intel_encoder_destroy(encoder); |
79e53945 JB |
1844 | } |
1845 | ||
1846 | static const struct drm_encoder_funcs intel_sdvo_enc_funcs = { | |
1847 | .destroy = intel_sdvo_enc_destroy, | |
1848 | }; | |
1849 | ||
b66d8424 CW |
1850 | static void |
1851 | intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo) | |
1852 | { | |
1853 | uint16_t mask = 0; | |
1854 | unsigned int num_bits; | |
1855 | ||
1856 | /* Make a mask of outputs less than or equal to our own priority in the | |
1857 | * list. | |
1858 | */ | |
1859 | switch (sdvo->controlled_output) { | |
1860 | case SDVO_OUTPUT_LVDS1: | |
1861 | mask |= SDVO_OUTPUT_LVDS1; | |
1862 | case SDVO_OUTPUT_LVDS0: | |
1863 | mask |= SDVO_OUTPUT_LVDS0; | |
1864 | case SDVO_OUTPUT_TMDS1: | |
1865 | mask |= SDVO_OUTPUT_TMDS1; | |
1866 | case SDVO_OUTPUT_TMDS0: | |
1867 | mask |= SDVO_OUTPUT_TMDS0; | |
1868 | case SDVO_OUTPUT_RGB1: | |
1869 | mask |= SDVO_OUTPUT_RGB1; | |
1870 | case SDVO_OUTPUT_RGB0: | |
1871 | mask |= SDVO_OUTPUT_RGB0; | |
1872 | break; | |
1873 | } | |
1874 | ||
1875 | /* Count bits to find what number we are in the priority list. */ | |
1876 | mask &= sdvo->caps.output_flags; | |
1877 | num_bits = hweight16(mask); | |
1878 | /* If more than 3 outputs, default to DDC bus 3 for now. */ | |
1879 | if (num_bits > 3) | |
1880 | num_bits = 3; | |
1881 | ||
1882 | /* Corresponds to SDVO_CONTROL_BUS_DDCx */ | |
1883 | sdvo->ddc_bus = 1 << num_bits; | |
1884 | } | |
79e53945 | 1885 | |
e2f0ba97 JB |
1886 | /** |
1887 | * Choose the appropriate DDC bus for control bus switch command for this | |
1888 | * SDVO output based on the controlled output. | |
1889 | * | |
1890 | * DDC bus number assignment is in a priority order of RGB outputs, then TMDS | |
1891 | * outputs, then LVDS outputs. | |
1892 | */ | |
1893 | static void | |
b1083333 | 1894 | intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv, |
ea5b213a | 1895 | struct intel_sdvo *sdvo, u32 reg) |
e2f0ba97 | 1896 | { |
b1083333 | 1897 | struct sdvo_device_mapping *mapping; |
e2f0ba97 | 1898 | |
b1083333 AJ |
1899 | if (IS_SDVOB(reg)) |
1900 | mapping = &(dev_priv->sdvo_mappings[0]); | |
1901 | else | |
1902 | mapping = &(dev_priv->sdvo_mappings[1]); | |
e2f0ba97 | 1903 | |
b66d8424 CW |
1904 | if (mapping->initialized) |
1905 | sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4); | |
1906 | else | |
1907 | intel_sdvo_guess_ddc_bus(sdvo); | |
e2f0ba97 JB |
1908 | } |
1909 | ||
e957d772 CW |
1910 | static void |
1911 | intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv, | |
1912 | struct intel_sdvo *sdvo, u32 reg) | |
1913 | { | |
1914 | struct sdvo_device_mapping *mapping; | |
46eb3036 | 1915 | u8 pin; |
e957d772 CW |
1916 | |
1917 | if (IS_SDVOB(reg)) | |
1918 | mapping = &dev_priv->sdvo_mappings[0]; | |
1919 | else | |
1920 | mapping = &dev_priv->sdvo_mappings[1]; | |
1921 | ||
1922 | pin = GMBUS_PORT_DPB; | |
46eb3036 | 1923 | if (mapping->initialized) |
e957d772 | 1924 | pin = mapping->i2c_pin; |
e957d772 | 1925 | |
63abf3ed CW |
1926 | if (pin < GMBUS_NUM_PORTS) { |
1927 | sdvo->i2c = &dev_priv->gmbus[pin].adapter; | |
d5090b96 | 1928 | intel_gmbus_set_speed(sdvo->i2c, GMBUS_RATE_1MHZ); |
63abf3ed | 1929 | intel_gmbus_force_bit(sdvo->i2c, true); |
46eb3036 | 1930 | } else { |
63abf3ed | 1931 | sdvo->i2c = &dev_priv->gmbus[GMBUS_PORT_DPB].adapter; |
46eb3036 | 1932 | } |
e957d772 CW |
1933 | } |
1934 | ||
e2f0ba97 | 1935 | static bool |
e27d8538 | 1936 | intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device) |
e2f0ba97 | 1937 | { |
97aaf910 | 1938 | return intel_sdvo_check_supp_encode(intel_sdvo); |
e2f0ba97 JB |
1939 | } |
1940 | ||
714605e4 | 1941 | static u8 |
c751ce4f | 1942 | intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg) |
714605e4 | 1943 | { |
1944 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1945 | struct sdvo_device_mapping *my_mapping, *other_mapping; | |
1946 | ||
461ed3ca | 1947 | if (IS_SDVOB(sdvo_reg)) { |
714605e4 | 1948 | my_mapping = &dev_priv->sdvo_mappings[0]; |
1949 | other_mapping = &dev_priv->sdvo_mappings[1]; | |
1950 | } else { | |
1951 | my_mapping = &dev_priv->sdvo_mappings[1]; | |
1952 | other_mapping = &dev_priv->sdvo_mappings[0]; | |
1953 | } | |
1954 | ||
1955 | /* If the BIOS described our SDVO device, take advantage of it. */ | |
1956 | if (my_mapping->slave_addr) | |
1957 | return my_mapping->slave_addr; | |
1958 | ||
1959 | /* If the BIOS only described a different SDVO device, use the | |
1960 | * address that it isn't using. | |
1961 | */ | |
1962 | if (other_mapping->slave_addr) { | |
1963 | if (other_mapping->slave_addr == 0x70) | |
1964 | return 0x72; | |
1965 | else | |
1966 | return 0x70; | |
1967 | } | |
1968 | ||
1969 | /* No SDVO device info is found for another DVO port, | |
1970 | * so use mapping assumption we had before BIOS parsing. | |
1971 | */ | |
461ed3ca | 1972 | if (IS_SDVOB(sdvo_reg)) |
714605e4 | 1973 | return 0x70; |
1974 | else | |
1975 | return 0x72; | |
1976 | } | |
1977 | ||
14571b4c | 1978 | static void |
df0e9248 CW |
1979 | intel_sdvo_connector_init(struct intel_sdvo_connector *connector, |
1980 | struct intel_sdvo *encoder) | |
14571b4c | 1981 | { |
df0e9248 CW |
1982 | drm_connector_init(encoder->base.base.dev, |
1983 | &connector->base.base, | |
1984 | &intel_sdvo_connector_funcs, | |
1985 | connector->base.base.connector_type); | |
6070a4a9 | 1986 | |
df0e9248 CW |
1987 | drm_connector_helper_add(&connector->base.base, |
1988 | &intel_sdvo_connector_helper_funcs); | |
14571b4c | 1989 | |
df0e9248 CW |
1990 | connector->base.base.interlace_allowed = 0; |
1991 | connector->base.base.doublescan_allowed = 0; | |
1992 | connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB; | |
14571b4c | 1993 | |
df0e9248 CW |
1994 | intel_connector_attach_encoder(&connector->base, &encoder->base); |
1995 | drm_sysfs_connector_add(&connector->base.base); | |
14571b4c | 1996 | } |
6070a4a9 | 1997 | |
7f36e7ed CW |
1998 | static void |
1999 | intel_sdvo_add_hdmi_properties(struct intel_sdvo_connector *connector) | |
2000 | { | |
2001 | struct drm_device *dev = connector->base.base.dev; | |
2002 | ||
3f43c48d | 2003 | intel_attach_force_audio_property(&connector->base.base); |
e953fd7b CW |
2004 | if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) |
2005 | intel_attach_broadcast_rgb_property(&connector->base.base); | |
7f36e7ed CW |
2006 | } |
2007 | ||
fb7a46f3 | 2008 | static bool |
ea5b213a | 2009 | intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device) |
fb7a46f3 | 2010 | { |
4ef69c7a | 2011 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
14571b4c | 2012 | struct drm_connector *connector; |
cc68c81a | 2013 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
14571b4c | 2014 | struct intel_connector *intel_connector; |
615fb93f | 2015 | struct intel_sdvo_connector *intel_sdvo_connector; |
14571b4c | 2016 | |
615fb93f CW |
2017 | intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); |
2018 | if (!intel_sdvo_connector) | |
14571b4c ZW |
2019 | return false; |
2020 | ||
14571b4c | 2021 | if (device == 0) { |
ea5b213a | 2022 | intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0; |
615fb93f | 2023 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0; |
14571b4c | 2024 | } else if (device == 1) { |
ea5b213a | 2025 | intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1; |
615fb93f | 2026 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1; |
14571b4c ZW |
2027 | } |
2028 | ||
615fb93f | 2029 | intel_connector = &intel_sdvo_connector->base; |
14571b4c | 2030 | connector = &intel_connector->base; |
cc68c81a SF |
2031 | if (intel_sdvo_supports_hotplug(intel_sdvo) & (1 << device)) { |
2032 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
2033 | intel_sdvo->hotplug_active[0] |= 1 << device; | |
2034 | /* Some SDVO devices have one-shot hotplug interrupts. | |
2035 | * Ensure that they get re-enabled when an interrupt happens. | |
2036 | */ | |
2037 | intel_encoder->hot_plug = intel_sdvo_enable_hotplug; | |
2038 | intel_sdvo_enable_hotplug(intel_encoder); | |
2039 | } | |
2040 | else | |
2041 | connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; | |
14571b4c ZW |
2042 | encoder->encoder_type = DRM_MODE_ENCODER_TMDS; |
2043 | connector->connector_type = DRM_MODE_CONNECTOR_DVID; | |
2044 | ||
e27d8538 | 2045 | if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) { |
14571b4c | 2046 | connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; |
e27d8538 | 2047 | intel_sdvo->is_hdmi = true; |
14571b4c | 2048 | } |
ea5b213a CW |
2049 | intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) | |
2050 | (1 << INTEL_ANALOG_CLONE_BIT)); | |
14571b4c | 2051 | |
df0e9248 | 2052 | intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo); |
f797d221 CW |
2053 | if (intel_sdvo->is_hdmi) |
2054 | intel_sdvo_add_hdmi_properties(intel_sdvo_connector); | |
14571b4c ZW |
2055 | |
2056 | return true; | |
2057 | } | |
2058 | ||
2059 | static bool | |
ea5b213a | 2060 | intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type) |
14571b4c | 2061 | { |
4ef69c7a CW |
2062 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
2063 | struct drm_connector *connector; | |
2064 | struct intel_connector *intel_connector; | |
2065 | struct intel_sdvo_connector *intel_sdvo_connector; | |
14571b4c | 2066 | |
615fb93f CW |
2067 | intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); |
2068 | if (!intel_sdvo_connector) | |
2069 | return false; | |
14571b4c | 2070 | |
615fb93f | 2071 | intel_connector = &intel_sdvo_connector->base; |
4ef69c7a CW |
2072 | connector = &intel_connector->base; |
2073 | encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; | |
2074 | connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; | |
14571b4c | 2075 | |
4ef69c7a CW |
2076 | intel_sdvo->controlled_output |= type; |
2077 | intel_sdvo_connector->output_flag = type; | |
14571b4c | 2078 | |
4ef69c7a CW |
2079 | intel_sdvo->is_tv = true; |
2080 | intel_sdvo->base.needs_tv_clock = true; | |
2081 | intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT; | |
14571b4c | 2082 | |
df0e9248 | 2083 | intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo); |
14571b4c | 2084 | |
4ef69c7a | 2085 | if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type)) |
32aad86f | 2086 | goto err; |
14571b4c | 2087 | |
4ef69c7a | 2088 | if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) |
32aad86f | 2089 | goto err; |
14571b4c | 2090 | |
4ef69c7a | 2091 | return true; |
32aad86f CW |
2092 | |
2093 | err: | |
123d5c01 | 2094 | intel_sdvo_destroy(connector); |
32aad86f | 2095 | return false; |
14571b4c ZW |
2096 | } |
2097 | ||
2098 | static bool | |
ea5b213a | 2099 | intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device) |
14571b4c | 2100 | { |
4ef69c7a CW |
2101 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
2102 | struct drm_connector *connector; | |
2103 | struct intel_connector *intel_connector; | |
2104 | struct intel_sdvo_connector *intel_sdvo_connector; | |
14571b4c | 2105 | |
615fb93f CW |
2106 | intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); |
2107 | if (!intel_sdvo_connector) | |
2108 | return false; | |
14571b4c | 2109 | |
615fb93f | 2110 | intel_connector = &intel_sdvo_connector->base; |
4ef69c7a | 2111 | connector = &intel_connector->base; |
eb1f8e4f | 2112 | connector->polled = DRM_CONNECTOR_POLL_CONNECT; |
4ef69c7a CW |
2113 | encoder->encoder_type = DRM_MODE_ENCODER_DAC; |
2114 | connector->connector_type = DRM_MODE_CONNECTOR_VGA; | |
2115 | ||
2116 | if (device == 0) { | |
2117 | intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0; | |
2118 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0; | |
2119 | } else if (device == 1) { | |
2120 | intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1; | |
2121 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1; | |
2122 | } | |
2123 | ||
2124 | intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) | | |
ea5b213a | 2125 | (1 << INTEL_ANALOG_CLONE_BIT)); |
14571b4c | 2126 | |
df0e9248 CW |
2127 | intel_sdvo_connector_init(intel_sdvo_connector, |
2128 | intel_sdvo); | |
4ef69c7a | 2129 | return true; |
14571b4c ZW |
2130 | } |
2131 | ||
2132 | static bool | |
ea5b213a | 2133 | intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device) |
14571b4c | 2134 | { |
4ef69c7a CW |
2135 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
2136 | struct drm_connector *connector; | |
2137 | struct intel_connector *intel_connector; | |
2138 | struct intel_sdvo_connector *intel_sdvo_connector; | |
14571b4c | 2139 | |
615fb93f CW |
2140 | intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); |
2141 | if (!intel_sdvo_connector) | |
2142 | return false; | |
14571b4c | 2143 | |
615fb93f CW |
2144 | intel_connector = &intel_sdvo_connector->base; |
2145 | connector = &intel_connector->base; | |
4ef69c7a CW |
2146 | encoder->encoder_type = DRM_MODE_ENCODER_LVDS; |
2147 | connector->connector_type = DRM_MODE_CONNECTOR_LVDS; | |
2148 | ||
2149 | if (device == 0) { | |
2150 | intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0; | |
2151 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0; | |
2152 | } else if (device == 1) { | |
2153 | intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1; | |
2154 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1; | |
2155 | } | |
2156 | ||
2157 | intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) | | |
ea5b213a | 2158 | (1 << INTEL_SDVO_LVDS_CLONE_BIT)); |
14571b4c | 2159 | |
df0e9248 | 2160 | intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo); |
4ef69c7a | 2161 | if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) |
32aad86f CW |
2162 | goto err; |
2163 | ||
2164 | return true; | |
2165 | ||
2166 | err: | |
123d5c01 | 2167 | intel_sdvo_destroy(connector); |
32aad86f | 2168 | return false; |
14571b4c ZW |
2169 | } |
2170 | ||
2171 | static bool | |
ea5b213a | 2172 | intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags) |
14571b4c | 2173 | { |
ea5b213a CW |
2174 | intel_sdvo->is_tv = false; |
2175 | intel_sdvo->base.needs_tv_clock = false; | |
2176 | intel_sdvo->is_lvds = false; | |
fb7a46f3 | 2177 | |
14571b4c | 2178 | /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/ |
fb7a46f3 | 2179 | |
14571b4c | 2180 | if (flags & SDVO_OUTPUT_TMDS0) |
ea5b213a | 2181 | if (!intel_sdvo_dvi_init(intel_sdvo, 0)) |
14571b4c ZW |
2182 | return false; |
2183 | ||
2184 | if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK) | |
ea5b213a | 2185 | if (!intel_sdvo_dvi_init(intel_sdvo, 1)) |
14571b4c ZW |
2186 | return false; |
2187 | ||
2188 | /* TV has no XXX1 function block */ | |
a1f4b7ff | 2189 | if (flags & SDVO_OUTPUT_SVID0) |
ea5b213a | 2190 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0)) |
14571b4c ZW |
2191 | return false; |
2192 | ||
2193 | if (flags & SDVO_OUTPUT_CVBS0) | |
ea5b213a | 2194 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0)) |
14571b4c | 2195 | return false; |
fb7a46f3 | 2196 | |
14571b4c | 2197 | if (flags & SDVO_OUTPUT_RGB0) |
ea5b213a | 2198 | if (!intel_sdvo_analog_init(intel_sdvo, 0)) |
14571b4c ZW |
2199 | return false; |
2200 | ||
2201 | if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK) | |
ea5b213a | 2202 | if (!intel_sdvo_analog_init(intel_sdvo, 1)) |
14571b4c ZW |
2203 | return false; |
2204 | ||
2205 | if (flags & SDVO_OUTPUT_LVDS0) | |
ea5b213a | 2206 | if (!intel_sdvo_lvds_init(intel_sdvo, 0)) |
14571b4c ZW |
2207 | return false; |
2208 | ||
2209 | if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK) | |
ea5b213a | 2210 | if (!intel_sdvo_lvds_init(intel_sdvo, 1)) |
14571b4c | 2211 | return false; |
fb7a46f3 | 2212 | |
14571b4c | 2213 | if ((flags & SDVO_OUTPUT_MASK) == 0) { |
fb7a46f3 | 2214 | unsigned char bytes[2]; |
2215 | ||
ea5b213a CW |
2216 | intel_sdvo->controlled_output = 0; |
2217 | memcpy(bytes, &intel_sdvo->caps.output_flags, 2); | |
51c8b407 | 2218 | DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n", |
ea5b213a | 2219 | SDVO_NAME(intel_sdvo), |
51c8b407 | 2220 | bytes[0], bytes[1]); |
14571b4c | 2221 | return false; |
fb7a46f3 | 2222 | } |
27f8227b | 2223 | intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
fb7a46f3 | 2224 | |
14571b4c | 2225 | return true; |
fb7a46f3 | 2226 | } |
2227 | ||
32aad86f CW |
2228 | static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, |
2229 | struct intel_sdvo_connector *intel_sdvo_connector, | |
2230 | int type) | |
ce6feabd | 2231 | { |
4ef69c7a | 2232 | struct drm_device *dev = intel_sdvo->base.base.dev; |
ce6feabd ZY |
2233 | struct intel_sdvo_tv_format format; |
2234 | uint32_t format_map, i; | |
ce6feabd | 2235 | |
32aad86f CW |
2236 | if (!intel_sdvo_set_target_output(intel_sdvo, type)) |
2237 | return false; | |
ce6feabd | 2238 | |
1a3665c8 | 2239 | BUILD_BUG_ON(sizeof(format) != 6); |
32aad86f CW |
2240 | if (!intel_sdvo_get_value(intel_sdvo, |
2241 | SDVO_CMD_GET_SUPPORTED_TV_FORMATS, | |
2242 | &format, sizeof(format))) | |
2243 | return false; | |
ce6feabd | 2244 | |
32aad86f | 2245 | memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format))); |
ce6feabd ZY |
2246 | |
2247 | if (format_map == 0) | |
32aad86f | 2248 | return false; |
ce6feabd | 2249 | |
615fb93f | 2250 | intel_sdvo_connector->format_supported_num = 0; |
ce6feabd | 2251 | for (i = 0 ; i < TV_FORMAT_NUM; i++) |
40039750 CW |
2252 | if (format_map & (1 << i)) |
2253 | intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i; | |
ce6feabd ZY |
2254 | |
2255 | ||
c5521706 | 2256 | intel_sdvo_connector->tv_format = |
32aad86f CW |
2257 | drm_property_create(dev, DRM_MODE_PROP_ENUM, |
2258 | "mode", intel_sdvo_connector->format_supported_num); | |
c5521706 | 2259 | if (!intel_sdvo_connector->tv_format) |
fcc8d672 | 2260 | return false; |
ce6feabd | 2261 | |
615fb93f | 2262 | for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) |
ce6feabd | 2263 | drm_property_add_enum( |
c5521706 | 2264 | intel_sdvo_connector->tv_format, i, |
40039750 | 2265 | i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]); |
ce6feabd | 2266 | |
40039750 | 2267 | intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0]; |
32aad86f | 2268 | drm_connector_attach_property(&intel_sdvo_connector->base.base, |
c5521706 | 2269 | intel_sdvo_connector->tv_format, 0); |
32aad86f | 2270 | return true; |
ce6feabd ZY |
2271 | |
2272 | } | |
2273 | ||
c5521706 CW |
2274 | #define ENHANCEMENT(name, NAME) do { \ |
2275 | if (enhancements.name) { \ | |
2276 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \ | |
2277 | !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \ | |
2278 | return false; \ | |
2279 | intel_sdvo_connector->max_##name = data_value[0]; \ | |
2280 | intel_sdvo_connector->cur_##name = response; \ | |
2281 | intel_sdvo_connector->name = \ | |
2282 | drm_property_create(dev, DRM_MODE_PROP_RANGE, #name, 2); \ | |
2283 | if (!intel_sdvo_connector->name) return false; \ | |
2284 | intel_sdvo_connector->name->values[0] = 0; \ | |
2285 | intel_sdvo_connector->name->values[1] = data_value[0]; \ | |
2286 | drm_connector_attach_property(connector, \ | |
2287 | intel_sdvo_connector->name, \ | |
2288 | intel_sdvo_connector->cur_##name); \ | |
2289 | DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \ | |
2290 | data_value[0], data_value[1], response); \ | |
2291 | } \ | |
0206e353 | 2292 | } while (0) |
c5521706 CW |
2293 | |
2294 | static bool | |
2295 | intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, | |
2296 | struct intel_sdvo_connector *intel_sdvo_connector, | |
2297 | struct intel_sdvo_enhancements_reply enhancements) | |
b9219c5e | 2298 | { |
4ef69c7a | 2299 | struct drm_device *dev = intel_sdvo->base.base.dev; |
32aad86f | 2300 | struct drm_connector *connector = &intel_sdvo_connector->base.base; |
b9219c5e ZY |
2301 | uint16_t response, data_value[2]; |
2302 | ||
c5521706 CW |
2303 | /* when horizontal overscan is supported, Add the left/right property */ |
2304 | if (enhancements.overscan_h) { | |
2305 | if (!intel_sdvo_get_value(intel_sdvo, | |
2306 | SDVO_CMD_GET_MAX_OVERSCAN_H, | |
2307 | &data_value, 4)) | |
2308 | return false; | |
32aad86f | 2309 | |
c5521706 CW |
2310 | if (!intel_sdvo_get_value(intel_sdvo, |
2311 | SDVO_CMD_GET_OVERSCAN_H, | |
2312 | &response, 2)) | |
2313 | return false; | |
fcc8d672 | 2314 | |
c5521706 CW |
2315 | intel_sdvo_connector->max_hscan = data_value[0]; |
2316 | intel_sdvo_connector->left_margin = data_value[0] - response; | |
2317 | intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin; | |
2318 | intel_sdvo_connector->left = | |
2319 | drm_property_create(dev, DRM_MODE_PROP_RANGE, | |
2320 | "left_margin", 2); | |
2321 | if (!intel_sdvo_connector->left) | |
2322 | return false; | |
fcc8d672 | 2323 | |
c5521706 CW |
2324 | intel_sdvo_connector->left->values[0] = 0; |
2325 | intel_sdvo_connector->left->values[1] = data_value[0]; | |
2326 | drm_connector_attach_property(connector, | |
2327 | intel_sdvo_connector->left, | |
2328 | intel_sdvo_connector->left_margin); | |
fcc8d672 | 2329 | |
c5521706 CW |
2330 | intel_sdvo_connector->right = |
2331 | drm_property_create(dev, DRM_MODE_PROP_RANGE, | |
2332 | "right_margin", 2); | |
2333 | if (!intel_sdvo_connector->right) | |
2334 | return false; | |
32aad86f | 2335 | |
c5521706 CW |
2336 | intel_sdvo_connector->right->values[0] = 0; |
2337 | intel_sdvo_connector->right->values[1] = data_value[0]; | |
2338 | drm_connector_attach_property(connector, | |
2339 | intel_sdvo_connector->right, | |
2340 | intel_sdvo_connector->right_margin); | |
2341 | DRM_DEBUG_KMS("h_overscan: max %d, " | |
2342 | "default %d, current %d\n", | |
2343 | data_value[0], data_value[1], response); | |
2344 | } | |
32aad86f | 2345 | |
c5521706 CW |
2346 | if (enhancements.overscan_v) { |
2347 | if (!intel_sdvo_get_value(intel_sdvo, | |
2348 | SDVO_CMD_GET_MAX_OVERSCAN_V, | |
2349 | &data_value, 4)) | |
2350 | return false; | |
fcc8d672 | 2351 | |
c5521706 CW |
2352 | if (!intel_sdvo_get_value(intel_sdvo, |
2353 | SDVO_CMD_GET_OVERSCAN_V, | |
2354 | &response, 2)) | |
2355 | return false; | |
32aad86f | 2356 | |
c5521706 CW |
2357 | intel_sdvo_connector->max_vscan = data_value[0]; |
2358 | intel_sdvo_connector->top_margin = data_value[0] - response; | |
2359 | intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin; | |
2360 | intel_sdvo_connector->top = | |
2361 | drm_property_create(dev, DRM_MODE_PROP_RANGE, | |
2362 | "top_margin", 2); | |
2363 | if (!intel_sdvo_connector->top) | |
2364 | return false; | |
32aad86f | 2365 | |
c5521706 CW |
2366 | intel_sdvo_connector->top->values[0] = 0; |
2367 | intel_sdvo_connector->top->values[1] = data_value[0]; | |
2368 | drm_connector_attach_property(connector, | |
2369 | intel_sdvo_connector->top, | |
2370 | intel_sdvo_connector->top_margin); | |
fcc8d672 | 2371 | |
c5521706 CW |
2372 | intel_sdvo_connector->bottom = |
2373 | drm_property_create(dev, DRM_MODE_PROP_RANGE, | |
2374 | "bottom_margin", 2); | |
2375 | if (!intel_sdvo_connector->bottom) | |
2376 | return false; | |
32aad86f | 2377 | |
c5521706 CW |
2378 | intel_sdvo_connector->bottom->values[0] = 0; |
2379 | intel_sdvo_connector->bottom->values[1] = data_value[0]; | |
2380 | drm_connector_attach_property(connector, | |
2381 | intel_sdvo_connector->bottom, | |
2382 | intel_sdvo_connector->bottom_margin); | |
2383 | DRM_DEBUG_KMS("v_overscan: max %d, " | |
2384 | "default %d, current %d\n", | |
2385 | data_value[0], data_value[1], response); | |
2386 | } | |
32aad86f | 2387 | |
c5521706 CW |
2388 | ENHANCEMENT(hpos, HPOS); |
2389 | ENHANCEMENT(vpos, VPOS); | |
2390 | ENHANCEMENT(saturation, SATURATION); | |
2391 | ENHANCEMENT(contrast, CONTRAST); | |
2392 | ENHANCEMENT(hue, HUE); | |
2393 | ENHANCEMENT(sharpness, SHARPNESS); | |
2394 | ENHANCEMENT(brightness, BRIGHTNESS); | |
2395 | ENHANCEMENT(flicker_filter, FLICKER_FILTER); | |
2396 | ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); | |
2397 | ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D); | |
2398 | ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER); | |
2399 | ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER); | |
fcc8d672 | 2400 | |
e044218a CW |
2401 | if (enhancements.dot_crawl) { |
2402 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2)) | |
2403 | return false; | |
2404 | ||
2405 | intel_sdvo_connector->max_dot_crawl = 1; | |
2406 | intel_sdvo_connector->cur_dot_crawl = response & 0x1; | |
2407 | intel_sdvo_connector->dot_crawl = | |
2408 | drm_property_create(dev, DRM_MODE_PROP_RANGE, "dot_crawl", 2); | |
2409 | if (!intel_sdvo_connector->dot_crawl) | |
2410 | return false; | |
2411 | ||
2412 | intel_sdvo_connector->dot_crawl->values[0] = 0; | |
2413 | intel_sdvo_connector->dot_crawl->values[1] = 1; | |
2414 | drm_connector_attach_property(connector, | |
2415 | intel_sdvo_connector->dot_crawl, | |
2416 | intel_sdvo_connector->cur_dot_crawl); | |
2417 | DRM_DEBUG_KMS("dot crawl: current %d\n", response); | |
2418 | } | |
2419 | ||
c5521706 CW |
2420 | return true; |
2421 | } | |
32aad86f | 2422 | |
c5521706 CW |
2423 | static bool |
2424 | intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo, | |
2425 | struct intel_sdvo_connector *intel_sdvo_connector, | |
2426 | struct intel_sdvo_enhancements_reply enhancements) | |
2427 | { | |
4ef69c7a | 2428 | struct drm_device *dev = intel_sdvo->base.base.dev; |
c5521706 CW |
2429 | struct drm_connector *connector = &intel_sdvo_connector->base.base; |
2430 | uint16_t response, data_value[2]; | |
32aad86f | 2431 | |
c5521706 | 2432 | ENHANCEMENT(brightness, BRIGHTNESS); |
fcc8d672 | 2433 | |
c5521706 CW |
2434 | return true; |
2435 | } | |
2436 | #undef ENHANCEMENT | |
32aad86f | 2437 | |
c5521706 CW |
2438 | static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, |
2439 | struct intel_sdvo_connector *intel_sdvo_connector) | |
2440 | { | |
2441 | union { | |
2442 | struct intel_sdvo_enhancements_reply reply; | |
2443 | uint16_t response; | |
2444 | } enhancements; | |
32aad86f | 2445 | |
1a3665c8 CW |
2446 | BUILD_BUG_ON(sizeof(enhancements) != 2); |
2447 | ||
cf9a2f3a CW |
2448 | enhancements.response = 0; |
2449 | intel_sdvo_get_value(intel_sdvo, | |
2450 | SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, | |
2451 | &enhancements, sizeof(enhancements)); | |
c5521706 CW |
2452 | if (enhancements.response == 0) { |
2453 | DRM_DEBUG_KMS("No enhancement is supported\n"); | |
2454 | return true; | |
b9219c5e | 2455 | } |
32aad86f | 2456 | |
c5521706 CW |
2457 | if (IS_TV(intel_sdvo_connector)) |
2458 | return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply); | |
0206e353 | 2459 | else if (IS_LVDS(intel_sdvo_connector)) |
c5521706 CW |
2460 | return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply); |
2461 | else | |
2462 | return true; | |
e957d772 CW |
2463 | } |
2464 | ||
2465 | static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter, | |
2466 | struct i2c_msg *msgs, | |
2467 | int num) | |
2468 | { | |
2469 | struct intel_sdvo *sdvo = adapter->algo_data; | |
fcc8d672 | 2470 | |
e957d772 CW |
2471 | if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus)) |
2472 | return -EIO; | |
2473 | ||
2474 | return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num); | |
2475 | } | |
2476 | ||
2477 | static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter) | |
2478 | { | |
2479 | struct intel_sdvo *sdvo = adapter->algo_data; | |
2480 | return sdvo->i2c->algo->functionality(sdvo->i2c); | |
2481 | } | |
2482 | ||
2483 | static const struct i2c_algorithm intel_sdvo_ddc_proxy = { | |
2484 | .master_xfer = intel_sdvo_ddc_proxy_xfer, | |
2485 | .functionality = intel_sdvo_ddc_proxy_func | |
2486 | }; | |
2487 | ||
2488 | static bool | |
2489 | intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo, | |
2490 | struct drm_device *dev) | |
2491 | { | |
2492 | sdvo->ddc.owner = THIS_MODULE; | |
2493 | sdvo->ddc.class = I2C_CLASS_DDC; | |
2494 | snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy"); | |
2495 | sdvo->ddc.dev.parent = &dev->pdev->dev; | |
2496 | sdvo->ddc.algo_data = sdvo; | |
2497 | sdvo->ddc.algo = &intel_sdvo_ddc_proxy; | |
2498 | ||
2499 | return i2c_add_adapter(&sdvo->ddc) == 0; | |
b9219c5e ZY |
2500 | } |
2501 | ||
c751ce4f | 2502 | bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg) |
79e53945 | 2503 | { |
b01f2c3a | 2504 | struct drm_i915_private *dev_priv = dev->dev_private; |
21d40d37 | 2505 | struct intel_encoder *intel_encoder; |
ea5b213a | 2506 | struct intel_sdvo *intel_sdvo; |
79e53945 | 2507 | int i; |
79e53945 | 2508 | |
ea5b213a CW |
2509 | intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL); |
2510 | if (!intel_sdvo) | |
7d57382e | 2511 | return false; |
79e53945 | 2512 | |
56184e3d CW |
2513 | intel_sdvo->sdvo_reg = sdvo_reg; |
2514 | intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg) >> 1; | |
2515 | intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg); | |
e957d772 CW |
2516 | if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev)) { |
2517 | kfree(intel_sdvo); | |
2518 | return false; | |
2519 | } | |
2520 | ||
56184e3d | 2521 | /* encoder type will be decided later */ |
ea5b213a | 2522 | intel_encoder = &intel_sdvo->base; |
21d40d37 | 2523 | intel_encoder->type = INTEL_OUTPUT_SDVO; |
373a3cf7 | 2524 | drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0); |
79e53945 | 2525 | |
79e53945 JB |
2526 | /* Read the regs to test if we can talk to the device */ |
2527 | for (i = 0; i < 0x40; i++) { | |
f899fc64 CW |
2528 | u8 byte; |
2529 | ||
2530 | if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) { | |
8a4c47f3 | 2531 | DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n", |
461ed3ca | 2532 | IS_SDVOB(sdvo_reg) ? 'B' : 'C'); |
f899fc64 | 2533 | goto err; |
79e53945 JB |
2534 | } |
2535 | } | |
2536 | ||
f899fc64 | 2537 | if (IS_SDVOB(sdvo_reg)) |
b01f2c3a | 2538 | dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS; |
f899fc64 | 2539 | else |
b01f2c3a | 2540 | dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS; |
619ac3b7 | 2541 | |
4ef69c7a | 2542 | drm_encoder_helper_add(&intel_encoder->base, &intel_sdvo_helper_funcs); |
14571b4c | 2543 | |
af901ca1 | 2544 | /* In default case sdvo lvds is false */ |
32aad86f | 2545 | if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps)) |
f899fc64 | 2546 | goto err; |
79e53945 | 2547 | |
cc68c81a SF |
2548 | /* Set up hotplug command - note paranoia about contents of reply. |
2549 | * We assume that the hardware is in a sane state, and only touch | |
2550 | * the bits we think we understand. | |
2551 | */ | |
2552 | intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, | |
2553 | &intel_sdvo->hotplug_active, 2); | |
2554 | intel_sdvo->hotplug_active[0] &= ~0x3; | |
2555 | ||
ea5b213a CW |
2556 | if (intel_sdvo_output_setup(intel_sdvo, |
2557 | intel_sdvo->caps.output_flags) != true) { | |
51c8b407 | 2558 | DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n", |
461ed3ca | 2559 | IS_SDVOB(sdvo_reg) ? 'B' : 'C'); |
f899fc64 | 2560 | goto err; |
79e53945 JB |
2561 | } |
2562 | ||
ea5b213a | 2563 | intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg); |
e2f0ba97 | 2564 | |
79e53945 | 2565 | /* Set the input timing to the screen. Assume always input 0. */ |
32aad86f | 2566 | if (!intel_sdvo_set_target_input(intel_sdvo)) |
f899fc64 | 2567 | goto err; |
79e53945 | 2568 | |
32aad86f CW |
2569 | if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo, |
2570 | &intel_sdvo->pixel_clock_min, | |
2571 | &intel_sdvo->pixel_clock_max)) | |
f899fc64 | 2572 | goto err; |
79e53945 | 2573 | |
8a4c47f3 | 2574 | DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, " |
342dc382 | 2575 | "clock range %dMHz - %dMHz, " |
2576 | "input 1: %c, input 2: %c, " | |
2577 | "output 1: %c, output 2: %c\n", | |
ea5b213a CW |
2578 | SDVO_NAME(intel_sdvo), |
2579 | intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id, | |
2580 | intel_sdvo->caps.device_rev_id, | |
2581 | intel_sdvo->pixel_clock_min / 1000, | |
2582 | intel_sdvo->pixel_clock_max / 1000, | |
2583 | (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N', | |
2584 | (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N', | |
342dc382 | 2585 | /* check currently supported outputs */ |
ea5b213a | 2586 | intel_sdvo->caps.output_flags & |
79e53945 | 2587 | (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N', |
ea5b213a | 2588 | intel_sdvo->caps.output_flags & |
79e53945 | 2589 | (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N'); |
7d57382e | 2590 | return true; |
79e53945 | 2591 | |
f899fc64 | 2592 | err: |
373a3cf7 | 2593 | drm_encoder_cleanup(&intel_encoder->base); |
e957d772 | 2594 | i2c_del_adapter(&intel_sdvo->ddc); |
ea5b213a | 2595 | kfree(intel_sdvo); |
79e53945 | 2596 | |
7d57382e | 2597 | return false; |
79e53945 | 2598 | } |