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drm/i915/sdvo: Use an integer mapping for supported tv format modes
[linux-block.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
79e53945
JB		 30#include <linux/delay.h>
31#include "drmP.h"
32#include "drm.h"
33#include "drm_crtc.h"
2b8d33f7 34#include "drm_edid.h"
ea5b213a 35#include "intel_drv.h"
79e53945
JB		 36#include "i915_drm.h"
37#include "i915_drv.h"
38#include "intel_sdvo_regs.h"
39
14571b4c
ZW		 40#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
41#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
42#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
43#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0)
44
45#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
46 SDVO_TV_MASK)
47
48#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
49#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
32aad86f 50#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
14571b4c 51
79e53945 52
ce6feabd
ZY		 53static char *tv_format_names[] = {
54 "NTSC_M" , "NTSC_J" , "NTSC_443",
55 "PAL_B" , "PAL_D" , "PAL_G" ,
56 "PAL_H" , "PAL_I" , "PAL_M" ,
57 "PAL_N" , "PAL_NC" , "PAL_60" ,
58 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
59 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
60 "SECAM_60"
61};
62
63#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
64
ea5b213a
CW		 65struct intel_sdvo {
66 struct intel_encoder base;
67
f9c10a9b 68 u8 slave_addr;
e2f0ba97
JB		 69
70 /* Register for the SDVO device: SDVOB or SDVOC */
c751ce4f 71 int sdvo_reg;
79e53945 72
e2f0ba97
JB		 73 /* Active outputs controlled by this SDVO output */
74 uint16_t controlled_output;
79e53945 75
e2f0ba97
JB		 76 /*
77 * Capabilities of the SDVO device returned by
78 * i830_sdvo_get_capabilities()
79 */
79e53945 80 struct intel_sdvo_caps caps;
e2f0ba97
JB		 81
82 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 83 int pixel_clock_min, pixel_clock_max;
84
fb7a46f3 85 /*
86 * For multiple function SDVO device,
87 * this is for current attached outputs.
88 */
89 uint16_t attached_output;
90
e2f0ba97
JB		 91 /**
92 * This is set if we're going to treat the device as TV-out.
93 *
94 * While we have these nice friendly flags for output types that ought
95 * to decide this for us, the S-Video output on our HDMI+S-Video card
96 * shows up as RGB1 (VGA).
97 */
98 bool is_tv;
99
ce6feabd 100 /* This is for current tv format name */
40039750 101 int tv_format_index;
ce6feabd 102
e2f0ba97
JB		 103 /**
104 * This is set if we treat the device as HDMI, instead of DVI.
105 */
106 bool is_hdmi;
12682a97 107
7086c87f
ML		 108 /**
109 * This is set if we detect output of sdvo device as LVDS.
110 */
111 bool is_lvds;
e2f0ba97 112
12682a97 113 /**
114 * This is sdvo flags for input timing.
115 */
116 uint8_t sdvo_flags;
117
118 /**
119 * This is sdvo fixed pannel mode pointer
120 */
121 struct drm_display_mode *sdvo_lvds_fixed_mode;
122
e2f0ba97
JB		 123 /*
124 * supported encoding mode, used to determine whether HDMI is
125 * supported
126 */
127 struct intel_sdvo_encode encode;
128
c751ce4f 129 /* DDC bus used by this SDVO encoder */
e2f0ba97
JB		 130 uint8_t ddc_bus;
131
57cdaf90
KP		 132 /* Mac mini hack -- use the same DDC as the analog connector */
133 struct i2c_adapter *analog_ddc_bus;
134
14571b4c
ZW		 135};
136
137struct intel_sdvo_connector {
615fb93f
CW		 138 struct intel_connector base;
139
14571b4c
ZW		 140 /* Mark the type of connector */
141 uint16_t output_flag;
142
143 /* This contains all current supported TV format */
40039750 144 u8 tv_format_supported[TV_FORMAT_NUM];
14571b4c
ZW		 145 int format_supported_num;
146 struct drm_property *tv_format_property;
147 struct drm_property *tv_format_name_property[TV_FORMAT_NUM];
148
149 /**
150 * Returned SDTV resolutions allowed for the current format, if the
151 * device reported it.
152 */
153 struct intel_sdvo_sdtv_resolution_reply sdtv_resolutions;
154
b9219c5e
ZY		 155 /* add the property for the SDVO-TV */
156 struct drm_property *left_property;
157 struct drm_property *right_property;
158 struct drm_property *top_property;
159 struct drm_property *bottom_property;
160 struct drm_property *hpos_property;
161 struct drm_property *vpos_property;
162
163 /* add the property for the SDVO-TV/LVDS */
164 struct drm_property *brightness_property;
165 struct drm_property *contrast_property;
166 struct drm_property *saturation_property;
167 struct drm_property *hue_property;
168
169 /* Add variable to record current setting for the above property */
170 u32 left_margin, right_margin, top_margin, bottom_margin;
171 /* this is to get the range of margin.*/
172 u32 max_hscan, max_vscan;
173 u32 max_hpos, cur_hpos;
174 u32 max_vpos, cur_vpos;
175 u32 cur_brightness, max_brightness;
176 u32 cur_contrast, max_contrast;
177 u32 cur_saturation, max_saturation;
178 u32 cur_hue, max_hue;
79e53945
JB		 179};
180
ea5b213a
CW		 181static struct intel_sdvo *enc_to_intel_sdvo(struct drm_encoder *encoder)
182{
183 return container_of(enc_to_intel_encoder(encoder), struct intel_sdvo, base);
184}
185
615fb93f
CW		 186static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
187{
188 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
189}
190
fb7a46f3 191static bool
ea5b213a 192intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
32aad86f
CW		 193static bool
194intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
195 struct intel_sdvo_connector *intel_sdvo_connector,
196 int type);
197static bool
198intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
199 struct intel_sdvo_connector *intel_sdvo_connector);
fb7a46f3 200
79e53945
JB		 201/**
202 * Writes the SDVOB or SDVOC with the given value, but always writes both
203 * SDVOB and SDVOC to work around apparent hardware issues (according to
204 * comments in the BIOS).
205 */
ea5b213a 206static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
79e53945 207{
ea5b213a 208 struct drm_device *dev = intel_sdvo->base.enc.dev;
79e53945 209 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 210 u32 bval = val, cval = val;
211 int i;
212
ea5b213a
CW		 213 if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
214 I915_WRITE(intel_sdvo->sdvo_reg, val);
215 I915_READ(intel_sdvo->sdvo_reg);
461ed3ca
ZY		 216 return;
217 }
218
ea5b213a 219 if (intel_sdvo->sdvo_reg == SDVOB) {
79e53945
JB		 220 cval = I915_READ(SDVOC);
221 } else {
222 bval = I915_READ(SDVOB);
223 }
224 /*
225 * Write the registers twice for luck. Sometimes,
226 * writing them only once doesn't appear to 'stick'.
227 * The BIOS does this too. Yay, magic
228 */
229 for (i = 0; i < 2; i++)
230 {
231 I915_WRITE(SDVOB, bval);
232 I915_READ(SDVOB);
233 I915_WRITE(SDVOC, cval);
234 I915_READ(SDVOC);
235 }
236}
237
32aad86f 238static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
79e53945 239{
32aad86f 240 u8 out_buf[2] = { addr, 0 };
79e53945 241 u8 buf[2];
79e53945
JB		 242 struct i2c_msg msgs[] = {
243 {
ea5b213a 244 .addr = intel_sdvo->slave_addr >> 1,
79e53945
JB		 245 .flags = 0,
246 .len = 1,
247 .buf = out_buf,
248 },
249 {
ea5b213a 250 .addr = intel_sdvo->slave_addr >> 1,
79e53945
JB		 251 .flags = I2C_M_RD,
252 .len = 1,
253 .buf = buf,
254 }
255 };
32aad86f 256 int ret;
79e53945 257
ea5b213a 258 if ((ret = i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 2)) == 2)
79e53945
JB		 259 {
260 *ch = buf[0];
261 return true;
262 }
263
8a4c47f3 264 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 265 return false;
266}
267
32aad86f 268static bool intel_sdvo_write_byte(struct intel_sdvo *intel_sdvo, int addr, u8 ch)
79e53945 269{
32aad86f 270 u8 out_buf[2] = { addr, ch };
79e53945
JB		 271 struct i2c_msg msgs[] = {
272 {
ea5b213a 273 .addr = intel_sdvo->slave_addr >> 1,
79e53945
JB		 274 .flags = 0,
275 .len = 2,
276 .buf = out_buf,
277 }
278 };
279
32aad86f 280 return i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 1) == 1;
79e53945
JB		 281}
282
283#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
284/** Mapping of command numbers to names, for debug output */
005568be 285static const struct _sdvo_cmd_name {
e2f0ba97
JB		 286 u8 cmd;
287 char *name;
79e53945
JB		 288} sdvo_cmd_names[] = {
289 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
290 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
291 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
292 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
293 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
294 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
295 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
296 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
297 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
e2f0ba97
JB		 324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
79e53945 328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
e2f0ba97
JB		 329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
b9219c5e
ZY		 332 /* Add the op code for SDVO enhancements */
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_POSITION_H),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POSITION_H),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_POSITION_H),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_POSITION_V),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POSITION_V),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_POSITION_V),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
e2f0ba97
JB		 357 /* HDMI op code */
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 378};
379
461ed3ca 380#define IS_SDVOB(reg) (reg == SDVOB || reg == PCH_SDVOB)
ea5b213a 381#define SDVO_NAME(svdo) (IS_SDVOB((svdo)->sdvo_reg) ? "SDVOB" : "SDVOC")
79e53945 382
ea5b213a 383static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
32aad86f 384 const void *args, int args_len)
79e53945 385{
79e53945
JB		 386 int i;
387
8a4c47f3 388 DRM_DEBUG_KMS("%s: W: %02X ",
ea5b213a 389 SDVO_NAME(intel_sdvo), cmd);
79e53945 390 for (i = 0; i < args_len; i++)
342dc382 391 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
79e53945 392 for (; i < 8; i++)
342dc382 393 DRM_LOG_KMS(" ");
04ad327f 394 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
79e53945 395 if (cmd == sdvo_cmd_names[i].cmd) {
342dc382 396 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 397 break;
398 }
399 }
04ad327f 400 if (i == ARRAY_SIZE(sdvo_cmd_names))
342dc382 401 DRM_LOG_KMS("(%02X)", cmd);
402 DRM_LOG_KMS("\n");
79e53945 403}
79e53945 404
32aad86f
CW		 405static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
406 const void *args, int args_len)
79e53945
JB		 407{
408 int i;
409
ea5b213a 410 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
79e53945
JB		 411
412 for (i = 0; i < args_len; i++) {
32aad86f
CW		 413 if (!intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_ARG_0 - i,
414 ((u8*)args)[i]))
415 return false;
79e53945
JB		 416 }
417
32aad86f 418 return intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_OPCODE, cmd);
79e53945
JB		 419}
420
79e53945
JB		 421static const char *cmd_status_names[] = {
422 "Power on",
423 "Success",
424 "Not supported",
425 "Invalid arg",
426 "Pending",
427 "Target not specified",
428 "Scaling not supported"
429};
430
ea5b213a 431static void intel_sdvo_debug_response(struct intel_sdvo *intel_sdvo,
79e53945
JB		 432 void *response, int response_len,
433 u8 status)
434{
33b52961 435 int i;
79e53945 436
ea5b213a 437 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
79e53945 438 for (i = 0; i < response_len; i++)
342dc382 439 DRM_LOG_KMS("%02X ", ((u8 *)response)[i]);
79e53945 440 for (; i < 8; i++)
342dc382 441 DRM_LOG_KMS(" ");
79e53945 442 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
342dc382 443 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
79e53945 444 else
342dc382 445 DRM_LOG_KMS("(??? %d)", status);
446 DRM_LOG_KMS("\n");
79e53945 447}
79e53945 448
32aad86f
CW		 449static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
450 void *response, int response_len)
79e53945
JB		 451{
452 int i;
453 u8 status;
454 u8 retry = 50;
455
456 while (retry--) {
457 /* Read the command response */
458 for (i = 0; i < response_len; i++) {
32aad86f
CW		 459 if (!intel_sdvo_read_byte(intel_sdvo,
460 SDVO_I2C_RETURN_0 + i,
461 &((u8 *)response)[i]))
462 return false;
79e53945
JB		 463 }
464
465 /* read the return status */
32aad86f
CW		 466 if (!intel_sdvo_read_byte(intel_sdvo, SDVO_I2C_CMD_STATUS,
467 &status))
468 return false;
79e53945 469
ea5b213a 470 intel_sdvo_debug_response(intel_sdvo, response, response_len,
79e53945
JB		 471 status);
472 if (status != SDVO_CMD_STATUS_PENDING)
32aad86f 473 break;
79e53945
JB		 474
475 mdelay(50);
476 }
477
32aad86f 478 return status == SDVO_CMD_STATUS_SUCCESS;
79e53945
JB		 479}
480
b358d0a6 481static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
79e53945
JB		 482{
483 if (mode->clock >= 100000)
484 return 1;
485 else if (mode->clock >= 50000)
486 return 2;
487 else
488 return 4;
489}
490
491/**
6a304caf
ZY		 492 * Try to read the response after issuie the DDC switch command. But it
493 * is noted that we must do the action of reading response and issuing DDC
494 * switch command in one I2C transaction. Otherwise when we try to start
495 * another I2C transaction after issuing the DDC bus switch, it will be
496 * switched to the internal SDVO register.
79e53945 497 */
ea5b213a 498static void intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
b358d0a6 499 u8 target)
79e53945 500{
6a304caf
ZY		 501 u8 out_buf[2], cmd_buf[2], ret_value[2], ret;
502 struct i2c_msg msgs[] = {
503 {
ea5b213a 504 .addr = intel_sdvo->slave_addr >> 1,
6a304caf
ZY		 505 .flags = 0,
506 .len = 2,
507 .buf = out_buf,
508 },
509 /* the following two are to read the response */
510 {
ea5b213a 511 .addr = intel_sdvo->slave_addr >> 1,
6a304caf
ZY		 512 .flags = 0,
513 .len = 1,
514 .buf = cmd_buf,
515 },
516 {
ea5b213a 517 .addr = intel_sdvo->slave_addr >> 1,
6a304caf
ZY		 518 .flags = I2C_M_RD,
519 .len = 1,
520 .buf = ret_value,
521 },
522 };
523
ea5b213a 524 intel_sdvo_debug_write(intel_sdvo, SDVO_CMD_SET_CONTROL_BUS_SWITCH,
6a304caf
ZY		 525 &target, 1);
526 /* write the DDC switch command argument */
ea5b213a 527 intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_ARG_0, target);
6a304caf
ZY		 528
529 out_buf[0] = SDVO_I2C_OPCODE;
530 out_buf[1] = SDVO_CMD_SET_CONTROL_BUS_SWITCH;
531 cmd_buf[0] = SDVO_I2C_CMD_STATUS;
532 cmd_buf[1] = 0;
533 ret_value[0] = 0;
534 ret_value[1] = 0;
535
ea5b213a 536 ret = i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 3);
6a304caf
ZY		 537 if (ret != 3) {
538 /* failure in I2C transfer */
539 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
540 return;
541 }
542 if (ret_value[0] != SDVO_CMD_STATUS_SUCCESS) {
543 DRM_DEBUG_KMS("DDC switch command returns response %d\n",
544 ret_value[0]);
545 return;
546 }
547 return;
79e53945
JB		 548}
549
32aad86f 550static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
79e53945 551{
32aad86f
CW		 552 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
553 return false;
79e53945 554
32aad86f
CW		 555 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
556}
79e53945 557
32aad86f
CW		 558static bool
559intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
560{
561 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
562 return false;
79e53945 563
32aad86f
CW		 564 return intel_sdvo_read_response(intel_sdvo, value, len);
565}
79e53945 566
32aad86f
CW		 567static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
568{
569 struct intel_sdvo_set_target_input_args targets = {0};
570 return intel_sdvo_set_value(intel_sdvo,
571 SDVO_CMD_SET_TARGET_INPUT,
572 &targets, sizeof(targets));
79e53945
JB		 573}
574
575/**
576 * Return whether each input is trained.
577 *
578 * This function is making an assumption about the layout of the response,
579 * which should be checked against the docs.
580 */
ea5b213a 581static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
79e53945
JB		 582{
583 struct intel_sdvo_get_trained_inputs_response response;
79e53945 584
32aad86f
CW		 585 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
586 &response, sizeof(response)))
79e53945
JB		 587 return false;
588
589 *input_1 = response.input0_trained;
590 *input_2 = response.input1_trained;
591 return true;
592}
593
ea5b213a 594static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
79e53945
JB		 595 u16 outputs)
596{
32aad86f
CW		 597 return intel_sdvo_set_value(intel_sdvo,
598 SDVO_CMD_SET_ACTIVE_OUTPUTS,
599 &outputs, sizeof(outputs));
79e53945
JB		 600}
601
ea5b213a 602static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
79e53945
JB		 603 int mode)
604{
32aad86f 605 u8 state = SDVO_ENCODER_STATE_ON;
79e53945
JB		 606
607 switch (mode) {
608 case DRM_MODE_DPMS_ON:
609 state = SDVO_ENCODER_STATE_ON;
610 break;
611 case DRM_MODE_DPMS_STANDBY:
612 state = SDVO_ENCODER_STATE_STANDBY;
613 break;
614 case DRM_MODE_DPMS_SUSPEND:
615 state = SDVO_ENCODER_STATE_SUSPEND;
616 break;
617 case DRM_MODE_DPMS_OFF:
618 state = SDVO_ENCODER_STATE_OFF;
619 break;
620 }
621
32aad86f
CW		 622 return intel_sdvo_set_value(intel_sdvo,
623 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
79e53945
JB		 624}
625
ea5b213a 626static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
79e53945
JB		 627 int *clock_min,
628 int *clock_max)
629{
630 struct intel_sdvo_pixel_clock_range clocks;
79e53945 631
32aad86f
CW		 632 if (!intel_sdvo_get_value(intel_sdvo,
633 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
634 &clocks, sizeof(clocks)))
79e53945
JB		 635 return false;
636
637 /* Convert the values from units of 10 kHz to kHz. */
638 *clock_min = clocks.min * 10;
639 *clock_max = clocks.max * 10;
79e53945
JB		 640 return true;
641}
642
ea5b213a 643static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
79e53945
JB		 644 u16 outputs)
645{
32aad86f
CW		 646 return intel_sdvo_set_value(intel_sdvo,
647 SDVO_CMD_SET_TARGET_OUTPUT,
648 &outputs, sizeof(outputs));
79e53945
JB		 649}
650
ea5b213a 651static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
79e53945
JB		 652 struct intel_sdvo_dtd *dtd)
653{
32aad86f
CW		 654 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
655 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
79e53945
JB		 656}
657
ea5b213a 658static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 659 struct intel_sdvo_dtd *dtd)
660{
ea5b213a 661 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 662 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
663}
664
ea5b213a 665static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 666 struct intel_sdvo_dtd *dtd)
667{
ea5b213a 668 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 669 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
670}
671
e2f0ba97 672static bool
ea5b213a 673intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 674 uint16_t clock,
675 uint16_t width,
676 uint16_t height)
677{
678 struct intel_sdvo_preferred_input_timing_args args;
e2f0ba97 679
e642c6f1 680 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 681 args.clock = clock;
682 args.width = width;
683 args.height = height;
e642c6f1 684 args.interlace = 0;
12682a97 685
ea5b213a
CW		 686 if (intel_sdvo->is_lvds &&
687 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
688 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
12682a97 689 args.scaled = 1;
690
32aad86f
CW		 691 return intel_sdvo_set_value(intel_sdvo,
692 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
693 &args, sizeof(args));
e2f0ba97
JB		 694}
695
ea5b213a 696static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 697 struct intel_sdvo_dtd *dtd)
698{
32aad86f
CW		 699 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
700 &dtd->part1, sizeof(dtd->part1)) &&
701 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
702 &dtd->part2, sizeof(dtd->part2));
e2f0ba97 703}
79e53945 704
ea5b213a 705static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
79e53945 706{
32aad86f 707 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
79e53945
JB		 708}
709
e2f0ba97 710static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
32aad86f 711 const struct drm_display_mode *mode)
79e53945 712{
e2f0ba97
JB		 713 uint16_t width, height;
714 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
715 uint16_t h_sync_offset, v_sync_offset;
79e53945
JB		 716
717 width = mode->crtc_hdisplay;
718 height = mode->crtc_vdisplay;
719
720 /* do some mode translations */
721 h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
722 h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
723
724 v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
725 v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
726
727 h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
728 v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
729
e2f0ba97
JB		 730 dtd->part1.clock = mode->clock / 10;
731 dtd->part1.h_active = width & 0xff;
732 dtd->part1.h_blank = h_blank_len & 0xff;
733 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 734 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 735 dtd->part1.v_active = height & 0xff;
736 dtd->part1.v_blank = v_blank_len & 0xff;
737 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 738 ((v_blank_len >> 8) & 0xf);
739
171a9e96 740 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 741 dtd->part2.h_sync_width = h_sync_len & 0xff;
742 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 743 (v_sync_len & 0xf);
e2f0ba97 744 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 745 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
746 ((v_sync_len & 0x30) >> 4);
747
e2f0ba97 748 dtd->part2.dtd_flags = 0x18;
79e53945 749 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
e2f0ba97 750 dtd->part2.dtd_flags |= 0x2;
79e53945 751 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
e2f0ba97
JB		 752 dtd->part2.dtd_flags |= 0x4;
753
754 dtd->part2.sdvo_flags = 0;
755 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
756 dtd->part2.reserved = 0;
757}
758
759static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
32aad86f 760 const struct intel_sdvo_dtd *dtd)
e2f0ba97 761{
e2f0ba97
JB		 762 mode->hdisplay = dtd->part1.h_active;
763 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
764 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
171a9e96 765 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
e2f0ba97
JB		 766 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
767 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
768 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
769 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
770
771 mode->vdisplay = dtd->part1.v_active;
772 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
773 mode->vsync_start = mode->vdisplay;
774 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
171a9e96 775 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
e2f0ba97
JB		 776 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
777 mode->vsync_end = mode->vsync_start +
778 (dtd->part2.v_sync_off_width & 0xf);
779 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
780 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
781 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
782
783 mode->clock = dtd->part1.clock * 10;
784
171a9e96 785 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
e2f0ba97
JB		 786 if (dtd->part2.dtd_flags & 0x2)
787 mode->flags |= DRM_MODE_FLAG_PHSYNC;
788 if (dtd->part2.dtd_flags & 0x4)
789 mode->flags |= DRM_MODE_FLAG_PVSYNC;
790}
791
ea5b213a 792static bool intel_sdvo_get_supp_encode(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 793 struct intel_sdvo_encode *encode)
794{
32aad86f
CW		 795 if (intel_sdvo_get_value(intel_sdvo,
796 SDVO_CMD_GET_SUPP_ENCODE,
797 encode, sizeof(*encode)))
798 return true;
e2f0ba97 799
32aad86f
CW		 800 /* non-support means DVI */
801 memset(encode, 0, sizeof(*encode));
802 return false;
e2f0ba97
JB		 803}
804
ea5b213a 805static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
c751ce4f 806 uint8_t mode)
e2f0ba97 807{
32aad86f 808 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
e2f0ba97
JB		 809}
810
ea5b213a 811static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 812 uint8_t mode)
813{
32aad86f 814 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
e2f0ba97
JB		 815}
816
817#if 0
ea5b213a 818static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 819{
820 int i, j;
821 uint8_t set_buf_index[2];
822 uint8_t av_split;
823 uint8_t buf_size;
824 uint8_t buf[48];
825 uint8_t *pos;
826
32aad86f 827 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
e2f0ba97
JB		 828
829 for (i = 0; i <= av_split; i++) {
830 set_buf_index[0] = i; set_buf_index[1] = 0;
c751ce4f 831 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
e2f0ba97 832 set_buf_index, 2);
c751ce4f
EA		 833 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
834 intel_sdvo_read_response(encoder, &buf_size, 1);
e2f0ba97
JB		 835
836 pos = buf;
837 for (j = 0; j <= buf_size; j += 8) {
c751ce4f 838 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
e2f0ba97 839 NULL, 0);
c751ce4f 840 intel_sdvo_read_response(encoder, pos, 8);
e2f0ba97
JB		 841 pos += 8;
842 }
843 }
844}
845#endif
846
32aad86f 847static bool intel_sdvo_set_hdmi_buf(struct intel_sdvo *intel_sdvo,
c751ce4f
EA		 848 int index,
849 uint8_t *data, int8_t size, uint8_t tx_rate)
e2f0ba97
JB		 850{
851 uint8_t set_buf_index[2];
852
853 set_buf_index[0] = index;
854 set_buf_index[1] = 0;
855
32aad86f
CW		 856 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_INDEX,
857 set_buf_index, 2))
858 return false;
e2f0ba97
JB		 859
860 for (; size > 0; size -= 8) {
32aad86f
CW		 861 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_DATA, data, 8))
862 return false;
863
e2f0ba97
JB		 864 data += 8;
865 }
866
32aad86f 867 return intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1);
e2f0ba97
JB		 868}
869
870static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size)
871{
872 uint8_t csum = 0;
873 int i;
874
875 for (i = 0; i < size; i++)
876 csum += data[i];
877
878 return 0x100 - csum;
879}
880
881#define DIP_TYPE_AVI 0x82
882#define DIP_VERSION_AVI 0x2
883#define DIP_LEN_AVI 13
884
885struct dip_infoframe {
886 uint8_t type;
887 uint8_t version;
888 uint8_t len;
889 uint8_t checksum;
890 union {
891 struct {
892 /* Packet Byte #1 */
893 uint8_t S:2;
894 uint8_t B:2;
895 uint8_t A:1;
896 uint8_t Y:2;
897 uint8_t rsvd1:1;
898 /* Packet Byte #2 */
899 uint8_t R:4;
900 uint8_t M:2;
901 uint8_t C:2;
902 /* Packet Byte #3 */
903 uint8_t SC:2;
904 uint8_t Q:2;
905 uint8_t EC:3;
906 uint8_t ITC:1;
907 /* Packet Byte #4 */
908 uint8_t VIC:7;
909 uint8_t rsvd2:1;
910 /* Packet Byte #5 */
911 uint8_t PR:4;
912 uint8_t rsvd3:4;
913 /* Packet Byte #6~13 */
914 uint16_t top_bar_end;
915 uint16_t bottom_bar_start;
916 uint16_t left_bar_end;
917 uint16_t right_bar_start;
918 } avi;
919 struct {
920 /* Packet Byte #1 */
921 uint8_t channel_count:3;
922 uint8_t rsvd1:1;
923 uint8_t coding_type:4;
924 /* Packet Byte #2 */
925 uint8_t sample_size:2; /* SS0, SS1 */
926 uint8_t sample_frequency:3;
927 uint8_t rsvd2:3;
928 /* Packet Byte #3 */
929 uint8_t coding_type_private:5;
930 uint8_t rsvd3:3;
931 /* Packet Byte #4 */
932 uint8_t channel_allocation;
933 /* Packet Byte #5 */
934 uint8_t rsvd4:3;
935 uint8_t level_shift:4;
936 uint8_t downmix_inhibit:1;
937 } audio;
938 uint8_t payload[28];
939 } __attribute__ ((packed)) u;
940} __attribute__((packed));
941
32aad86f 942static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 943 struct drm_display_mode * mode)
944{
945 struct dip_infoframe avi_if = {
946 .type = DIP_TYPE_AVI,
947 .version = DIP_VERSION_AVI,
948 .len = DIP_LEN_AVI,
949 };
950
951 avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if,
952 4 + avi_if.len);
32aad86f
CW		 953 return intel_sdvo_set_hdmi_buf(intel_sdvo, 1, (uint8_t *)&avi_if,
954 4 + avi_if.len,
955 SDVO_HBUF_TX_VSYNC);
e2f0ba97
JB		 956}
957
32aad86f 958static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
7026d4ac 959{
ce6feabd 960 struct intel_sdvo_tv_format format;
40039750 961 uint32_t format_map;
ce6feabd 962
40039750 963 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 964 memset(&format, 0, sizeof(format));
32aad86f 965 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
ce6feabd 966
32aad86f
CW		 967 BUILD_BUG_ON(sizeof(format) != 6);
968 return intel_sdvo_set_value(intel_sdvo,
969 SDVO_CMD_SET_TV_FORMAT,
970 &format, sizeof(format));
7026d4ac
ZW		 971}
972
32aad86f
CW		 973static bool
974intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
975 struct drm_display_mode *mode)
e2f0ba97 976{
32aad86f 977 struct intel_sdvo_dtd output_dtd;
79e53945 978
32aad86f
CW		 979 if (!intel_sdvo_set_target_output(intel_sdvo,
980 intel_sdvo->attached_output))
981 return false;
e2f0ba97 982
32aad86f
CW		 983 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
984 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
985 return false;
e2f0ba97 986
32aad86f
CW		 987 return true;
988}
989
990static bool
991intel_sdvo_set_input_timings_for_mode(struct intel_sdvo *intel_sdvo,
992 struct drm_display_mode *mode,
993 struct drm_display_mode *adjusted_mode)
994{
995 struct intel_sdvo_dtd input_dtd;
e2f0ba97 996
32aad86f
CW		 997 /* Reset the input timing to the screen. Assume always input 0. */
998 if (!intel_sdvo_set_target_input(intel_sdvo))
999 return false;
e2f0ba97 1000
32aad86f
CW		 1001 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
1002 mode->clock / 10,
1003 mode->hdisplay,
1004 mode->vdisplay))
1005 return false;
e2f0ba97 1006
32aad86f
CW		 1007 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
1008 &input_dtd))
1009 return false;
e2f0ba97 1010
32aad86f
CW		 1011 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1012 intel_sdvo->sdvo_flags = input_dtd.part2.sdvo_flags;
79e53945 1013
32aad86f
CW		 1014 drm_mode_set_crtcinfo(adjusted_mode, 0);
1015 mode->clock = adjusted_mode->clock;
1016 return true;
1017}
12682a97 1018
32aad86f
CW		 1019static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
1020 struct drm_display_mode *mode,
1021 struct drm_display_mode *adjusted_mode)
1022{
1023 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
12682a97 1024
32aad86f
CW		 1025 /* We need to construct preferred input timings based on our
1026 * output timings. To do that, we have to set the output
1027 * timings, even though this isn't really the right place in
1028 * the sequence to do it. Oh well.
1029 */
1030 if (intel_sdvo->is_tv) {
1031 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
1032 return false;
12682a97 1033
32aad86f 1034 if (!intel_sdvo_set_input_timings_for_mode(intel_sdvo, mode, adjusted_mode))
12682a97 1035 return false;
ea5b213a 1036 } else if (intel_sdvo->is_lvds) {
ea5b213a 1037 drm_mode_set_crtcinfo(intel_sdvo->sdvo_lvds_fixed_mode, 0);
e2f0ba97 1038
32aad86f
CW		 1039 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
1040 intel_sdvo->sdvo_lvds_fixed_mode))
e2f0ba97 1041 return false;
12682a97 1042
32aad86f
CW		 1043 if (!intel_sdvo_set_input_timings_for_mode(intel_sdvo, mode, adjusted_mode))
1044 return false;
e2f0ba97 1045 }
32aad86f
CW		 1046
1047 /* Make the CRTC code factor in the SDVO pixel multiplier. The
1048 * SDVO device will be told of the multiplier during mode_set.
1049 */
1050 adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode);
1051
e2f0ba97
JB		 1052 return true;
1053}
1054
1055static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1056 struct drm_display_mode *mode,
1057 struct drm_display_mode *adjusted_mode)
1058{
1059 struct drm_device *dev = encoder->dev;
1060 struct drm_i915_private *dev_priv = dev->dev_private;
1061 struct drm_crtc *crtc = encoder->crtc;
1062 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ea5b213a 1063 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
e2f0ba97 1064 u32 sdvox = 0;
32aad86f 1065 int sdvo_pixel_multiply, rate;
e2f0ba97
JB		 1066 struct intel_sdvo_in_out_map in_out;
1067 struct intel_sdvo_dtd input_dtd;
e2f0ba97
JB		 1068
1069 if (!mode)
1070 return;
1071
1072 /* First, set the input mapping for the first input to our controlled
1073 * output. This is only correct if we're a single-input device, in
1074 * which case the first input is the output from the appropriate SDVO
1075 * channel on the motherboard. In a two-input device, the first input
1076 * will be SDVOB and the second SDVOC.
1077 */
ea5b213a 1078 in_out.in0 = intel_sdvo->attached_output;
e2f0ba97
JB		 1079 in_out.in1 = 0;
1080
32aad86f
CW		 1081 if (!intel_sdvo_set_value(intel_sdvo,
1082 SDVO_CMD_SET_IN_OUT_MAP,
1083 &in_out, sizeof(in_out)))
1084 return;
e2f0ba97 1085
ea5b213a 1086 if (intel_sdvo->is_hdmi) {
32aad86f
CW		 1087 if (!intel_sdvo_set_avi_infoframe(intel_sdvo, mode))
1088 return;
1089
e2f0ba97
JB		 1090 sdvox |= SDVO_AUDIO_ENABLE;
1091 }
1092
7026d4ac
ZW		 1093 /* We have tried to get input timing in mode_fixup, and filled into
1094 adjusted_mode */
ea5b213a 1095 if (intel_sdvo->is_tv || intel_sdvo->is_lvds) {
7026d4ac 1096 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
ea5b213a 1097 input_dtd.part2.sdvo_flags = intel_sdvo->sdvo_flags;
12682a97 1098 } else
7026d4ac 1099 intel_sdvo_get_dtd_from_mode(&input_dtd, mode);
e2f0ba97
JB		 1100
1101 /* If it's a TV, we already set the output timing in mode_fixup.
1102 * Otherwise, the output timing is equal to the input timing.
1103 */
ea5b213a 1104 if (!intel_sdvo->is_tv && !intel_sdvo->is_lvds) {
e2f0ba97 1105 /* Set the output timing to the screen */
32aad86f
CW		 1106 if (!intel_sdvo_set_target_output(intel_sdvo,
1107 intel_sdvo->attached_output))
1108 return;
1109
1110 if (!intel_sdvo_set_output_timing(intel_sdvo, &input_dtd))
1111 return;
e2f0ba97 1112 }
79e53945
JB		 1113
1114 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 1115 if (!intel_sdvo_set_target_input(intel_sdvo))
1116 return;
79e53945 1117
32aad86f
CW		 1118 if (intel_sdvo->is_tv) {
1119 if (!intel_sdvo_set_tv_format(intel_sdvo))
1120 return;
1121 }
7026d4ac 1122
e2f0ba97 1123 /* We would like to use intel_sdvo_create_preferred_input_timing() to
79e53945
JB		 1124 * provide the device with a timing it can support, if it supports that
1125 * feature. However, presumably we would need to adjust the CRTC to
1126 * output the preferred timing, and we don't support that currently.
1127 */
e2f0ba97 1128#if 0
c751ce4f 1129 success = intel_sdvo_create_preferred_input_timing(encoder, clock,
e2f0ba97
JB		 1130 width, height);
1131 if (success) {
1132 struct intel_sdvo_dtd *input_dtd;
1133
c751ce4f
EA		 1134 intel_sdvo_get_preferred_input_timing(encoder, &input_dtd);
1135 intel_sdvo_set_input_timing(encoder, &input_dtd);
e2f0ba97
JB		 1136 }
1137#else
32aad86f
CW		 1138 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
1139 return;
e2f0ba97 1140#endif
79e53945 1141
32aad86f
CW		 1142 sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode);
1143 switch (sdvo_pixel_multiply) {
1144 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1145 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1146 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
79e53945 1147 }
32aad86f
CW		 1148 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1149 return;
79e53945
JB		 1150
1151 /* Set the SDVO control regs. */
e2f0ba97 1152 if (IS_I965G(dev)) {
81a14b46
AJ		 1153 sdvox |= SDVO_BORDER_ENABLE;
1154 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1155 sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
1156 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1157 sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
e2f0ba97 1158 } else {
ea5b213a
CW		 1159 sdvox |= I915_READ(intel_sdvo->sdvo_reg);
1160 switch (intel_sdvo->sdvo_reg) {
e2f0ba97
JB		 1161 case SDVOB:
1162 sdvox &= SDVOB_PRESERVE_MASK;
1163 break;
1164 case SDVOC:
1165 sdvox &= SDVOC_PRESERVE_MASK;
1166 break;
1167 }
1168 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1169 }
79e53945
JB		 1170 if (intel_crtc->pipe == 1)
1171 sdvox |= SDVO_PIPE_B_SELECT;
1172
79e53945 1173 if (IS_I965G(dev)) {
e2f0ba97
JB		 1174 /* done in crtc_mode_set as the dpll_md reg must be written early */
1175 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1176 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945
JB		 1177 } else {
1178 sdvox |= (sdvo_pixel_multiply - 1) << SDVO_PORT_MULTIPLY_SHIFT;
1179 }
1180
ea5b213a 1181 if (intel_sdvo->sdvo_flags & SDVO_NEED_TO_STALL)
12682a97 1182 sdvox |= SDVO_STALL_SELECT;
ea5b213a 1183 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
79e53945
JB		 1184}
1185
1186static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1187{
1188 struct drm_device *dev = encoder->dev;
1189 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 1190 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
79e53945
JB		 1191 u32 temp;
1192
1193 if (mode != DRM_MODE_DPMS_ON) {
ea5b213a 1194 intel_sdvo_set_active_outputs(intel_sdvo, 0);
79e53945 1195 if (0)
ea5b213a 1196 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
79e53945
JB		 1197
1198 if (mode == DRM_MODE_DPMS_OFF) {
ea5b213a 1199 temp = I915_READ(intel_sdvo->sdvo_reg);
79e53945 1200 if ((temp & SDVO_ENABLE) != 0) {
ea5b213a 1201 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
79e53945
JB		 1202 }
1203 }
1204 } else {
1205 bool input1, input2;
1206 int i;
1207 u8 status;
1208
ea5b213a 1209 temp = I915_READ(intel_sdvo->sdvo_reg);
79e53945 1210 if ((temp & SDVO_ENABLE) == 0)
ea5b213a 1211 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
79e53945
JB		 1212 for (i = 0; i < 2; i++)
1213 intel_wait_for_vblank(dev);
1214
32aad86f 1215 status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
79e53945
JB		 1216 /* Warn if the device reported failure to sync.
1217 * A lot of SDVO devices fail to notify of sync, but it's
1218 * a given it the status is a success, we succeeded.
1219 */
1220 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
8a4c47f3 1221 DRM_DEBUG_KMS("First %s output reported failure to "
ea5b213a 1222 "sync\n", SDVO_NAME(intel_sdvo));
79e53945
JB		 1223 }
1224
1225 if (0)
ea5b213a
CW		 1226 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1227 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
79e53945
JB		 1228 }
1229 return;
1230}
1231
79e53945
JB		 1232static int intel_sdvo_mode_valid(struct drm_connector *connector,
1233 struct drm_display_mode *mode)
1234{
d2a82a6f 1235 struct drm_encoder *encoder = intel_attached_encoder(connector);
ea5b213a 1236 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
79e53945
JB		 1237
1238 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1239 return MODE_NO_DBLESCAN;
1240
ea5b213a 1241 if (intel_sdvo->pixel_clock_min > mode->clock)
79e53945
JB		 1242 return MODE_CLOCK_LOW;
1243
ea5b213a 1244 if (intel_sdvo->pixel_clock_max < mode->clock)
79e53945
JB		 1245 return MODE_CLOCK_HIGH;
1246
ea5b213a
CW		 1247 if (intel_sdvo->is_lvds == true) {
1248 if (intel_sdvo->sdvo_lvds_fixed_mode == NULL)
12682a97 1249 return MODE_PANEL;
1250
ea5b213a 1251 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
12682a97 1252 return MODE_PANEL;
1253
ea5b213a 1254 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
12682a97 1255 return MODE_PANEL;
1256 }
1257
79e53945
JB		 1258 return MODE_OK;
1259}
1260
ea5b213a 1261static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
79e53945 1262{
32aad86f 1263 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DEVICE_CAPS, caps, sizeof(*caps));
79e53945
JB		 1264}
1265
d2a82a6f
ZW		 1266/* No use! */
1267#if 0
79e53945
JB		 1268struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB)
1269{
1270 struct drm_connector *connector = NULL;
ea5b213a
CW		 1271 struct intel_sdvo *iout = NULL;
1272 struct intel_sdvo *sdvo;
79e53945
JB		 1273
1274 /* find the sdvo connector */
1275 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
ea5b213a 1276 iout = to_intel_sdvo(connector);
79e53945
JB		 1277
1278 if (iout->type != INTEL_OUTPUT_SDVO)
1279 continue;
1280
1281 sdvo = iout->dev_priv;
1282
c751ce4f 1283 if (sdvo->sdvo_reg == SDVOB && sdvoB)
79e53945
JB		 1284 return connector;
1285
c751ce4f 1286 if (sdvo->sdvo_reg == SDVOC && !sdvoB)
79e53945
JB		 1287 return connector;
1288
1289 }
1290
1291 return NULL;
1292}
1293
1294int intel_sdvo_supports_hotplug(struct drm_connector *connector)
1295{
1296 u8 response[2];
1297 u8 status;
ea5b213a 1298 struct intel_sdvo *intel_sdvo;
8a4c47f3 1299 DRM_DEBUG_KMS("\n");
79e53945
JB		 1300
1301 if (!connector)
1302 return 0;
1303
ea5b213a 1304 intel_sdvo = to_intel_sdvo(connector);
79e53945 1305
32aad86f
CW		 1306 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1307 &response, 2) && response[0];
79e53945
JB		 1308}
1309
1310void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
1311{
1312 u8 response[2];
1313 u8 status;
ea5b213a 1314 struct intel_sdvo *intel_sdvo = to_intel_sdvo(connector);
79e53945 1315
ea5b213a
CW		 1316 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1317 intel_sdvo_read_response(intel_sdvo, &response, 2);
79e53945
JB		 1318
1319 if (on) {
ea5b213a
CW		 1320 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1321 status = intel_sdvo_read_response(intel_sdvo, &response, 2);
79e53945 1322
ea5b213a 1323 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
79e53945
JB		 1324 } else {
1325 response[0] = 0;
1326 response[1] = 0;
ea5b213a 1327 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
79e53945
JB		 1328 }
1329
ea5b213a
CW		 1330 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1331 intel_sdvo_read_response(intel_sdvo, &response, 2);
79e53945 1332}
d2a82a6f 1333#endif
79e53945 1334
fb7a46f3 1335static bool
ea5b213a 1336intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
fb7a46f3 1337{
fb7a46f3 1338 int caps = 0;
1339
ea5b213a 1340 if (intel_sdvo->caps.output_flags &
fb7a46f3 1341 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1))
1342 caps++;
ea5b213a 1343 if (intel_sdvo->caps.output_flags &
fb7a46f3 1344 (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1))
1345 caps++;
ea5b213a 1346 if (intel_sdvo->caps.output_flags &
19e1f888 1347 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_SVID1))
fb7a46f3 1348 caps++;
ea5b213a 1349 if (intel_sdvo->caps.output_flags &
fb7a46f3 1350 (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_CVBS1))
1351 caps++;
ea5b213a 1352 if (intel_sdvo->caps.output_flags &
fb7a46f3 1353 (SDVO_OUTPUT_YPRPB0 | SDVO_OUTPUT_YPRPB1))
1354 caps++;
1355
ea5b213a 1356 if (intel_sdvo->caps.output_flags &
fb7a46f3 1357 (SDVO_OUTPUT_SCART0 | SDVO_OUTPUT_SCART1))
1358 caps++;
1359
ea5b213a 1360 if (intel_sdvo->caps.output_flags &
fb7a46f3 1361 (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1))
1362 caps++;
1363
1364 return (caps > 1);
1365}
1366
57cdaf90
KP		 1367static struct drm_connector *
1368intel_find_analog_connector(struct drm_device *dev)
1369{
1370 struct drm_connector *connector;
d2a82a6f 1371 struct drm_encoder *encoder;
ea5b213a 1372 struct intel_sdvo *intel_sdvo;
57cdaf90 1373
d2a82a6f 1374 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
ea5b213a
CW		 1375 intel_sdvo = enc_to_intel_sdvo(encoder);
1376 if (intel_sdvo->base.type == INTEL_OUTPUT_ANALOG) {
d2a82a6f 1377 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
90a78e8f 1378 if (encoder == intel_attached_encoder(connector))
d2a82a6f
ZW		 1379 return connector;
1380 }
1381 }
57cdaf90
KP		 1382 }
1383 return NULL;
1384}
1385
1386static int
1387intel_analog_is_connected(struct drm_device *dev)
1388{
1389 struct drm_connector *analog_connector;
57cdaf90 1390
32aad86f 1391 analog_connector = intel_find_analog_connector(dev);
57cdaf90
KP		 1392 if (!analog_connector)
1393 return false;
1394
1395 if (analog_connector->funcs->detect(analog_connector) ==
1396 connector_status_disconnected)
1397 return false;
1398
1399 return true;
1400}
1401
2b8d33f7 1402enum drm_connector_status
149c36a3 1403intel_sdvo_hdmi_sink_detect(struct drm_connector *connector)
9dff6af8 1404{
d2a82a6f 1405 struct drm_encoder *encoder = intel_attached_encoder(connector);
ea5b213a 1406 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
615fb93f 1407 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2b8d33f7 1408 enum drm_connector_status status = connector_status_connected;
9dff6af8
ML		 1409 struct edid *edid = NULL;
1410
ea5b213a 1411 edid = drm_get_edid(connector, intel_sdvo->base.ddc_bus);
57cdaf90 1412
7c3f0a27 1413 /* This is only applied to SDVO cards with multiple outputs */
ea5b213a 1414 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
7c3f0a27 1415 uint8_t saved_ddc, temp_ddc;
ea5b213a
CW		 1416 saved_ddc = intel_sdvo->ddc_bus;
1417 temp_ddc = intel_sdvo->ddc_bus >> 1;
7c3f0a27
ZY		 1418 /*
1419 * Don't use the 1 as the argument of DDC bus switch to get
1420 * the EDID. It is used for SDVO SPD ROM.
1421 */
1422 while(temp_ddc > 1) {
ea5b213a
CW		 1423 intel_sdvo->ddc_bus = temp_ddc;
1424 edid = drm_get_edid(connector, intel_sdvo->base.ddc_bus);
7c3f0a27
ZY		 1425 if (edid) {
1426 /*
1427 * When we can get the EDID, maybe it is the
1428 * correct DDC bus. Update it.
1429 */
ea5b213a 1430 intel_sdvo->ddc_bus = temp_ddc;
7c3f0a27
ZY		 1431 break;
1432 }
1433 temp_ddc >>= 1;
1434 }
1435 if (edid == NULL)
ea5b213a 1436 intel_sdvo->ddc_bus = saved_ddc;
7c3f0a27 1437 }
57cdaf90
KP		 1438 /* when there is no edid and no monitor is connected with VGA
1439 * port, try to use the CRT ddc to read the EDID for DVI-connector
1440 */
ea5b213a 1441 if (edid == NULL && intel_sdvo->analog_ddc_bus &&
d2a82a6f 1442 !intel_analog_is_connected(connector->dev))
ea5b213a 1443 edid = drm_get_edid(connector, intel_sdvo->analog_ddc_bus);
149c36a3 1444
9dff6af8 1445 if (edid != NULL) {
149c36a3 1446 bool is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
615fb93f 1447 bool need_digital = !!(intel_sdvo_connector->output_flag & SDVO_TMDS_MASK);
2b8d33f7 1448
149c36a3
AJ		 1449 /* DDC bus is shared, match EDID to connector type */
1450 if (is_digital && need_digital)
ea5b213a 1451 intel_sdvo->is_hdmi = drm_detect_hdmi_monitor(edid);
149c36a3
AJ		 1452 else if (is_digital != need_digital)
1453 status = connector_status_disconnected;
2b8d33f7 1454
149c36a3
AJ		 1455 connector->display_info.raw_edid = NULL;
1456 } else
2b8d33f7 1457 status = connector_status_disconnected;
149c36a3
AJ		 1458
1459 kfree(edid);
2b8d33f7 1460
1461 return status;
9dff6af8
ML		 1462}
1463
79e53945
JB		 1464static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector)
1465{
fb7a46f3 1466 uint16_t response;
d2a82a6f 1467 struct drm_encoder *encoder = intel_attached_encoder(connector);
ea5b213a 1468 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
615fb93f 1469 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
14571b4c 1470 enum drm_connector_status ret;
79e53945 1471
32aad86f
CW		 1472 if (!intel_sdvo_write_cmd(intel_sdvo,
1473 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0))
1474 return connector_status_unknown;
ea5b213a 1475 if (intel_sdvo->is_tv) {
d09c23de
ZY		 1476 /* add 30ms delay when the output type is SDVO-TV */
1477 mdelay(30);
1478 }
32aad86f
CW		 1479 if (!intel_sdvo_read_response(intel_sdvo, &response, 2))
1480 return connector_status_unknown;
79e53945 1481
51c8b407 1482 DRM_DEBUG_KMS("SDVO response %d %d\n", response & 0xff, response >> 8);
e2f0ba97 1483
fb7a46f3 1484 if (response == 0)
79e53945 1485 return connector_status_disconnected;
fb7a46f3 1486
ea5b213a 1487 intel_sdvo->attached_output = response;
14571b4c 1488
615fb93f 1489 if ((intel_sdvo_connector->output_flag & response) == 0)
14571b4c 1490 ret = connector_status_disconnected;
149c36a3
AJ		 1491 else if (response & SDVO_TMDS_MASK)
1492 ret = intel_sdvo_hdmi_sink_detect(connector);
14571b4c
ZW		 1493 else
1494 ret = connector_status_connected;
1495
1496 /* May update encoder flag for like clock for SDVO TV, etc.*/
1497 if (ret == connector_status_connected) {
ea5b213a
CW		 1498 intel_sdvo->is_tv = false;
1499 intel_sdvo->is_lvds = false;
1500 intel_sdvo->base.needs_tv_clock = false;
14571b4c
ZW		 1501
1502 if (response & SDVO_TV_MASK) {
ea5b213a
CW		 1503 intel_sdvo->is_tv = true;
1504 intel_sdvo->base.needs_tv_clock = true;
14571b4c
ZW		 1505 }
1506 if (response & SDVO_LVDS_MASK)
ea5b213a 1507 intel_sdvo->is_lvds = true;
fb7a46f3 1508 }
14571b4c
ZW		 1509
1510 return ret;
79e53945
JB		 1511}
1512
e2f0ba97 1513static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945 1514{
d2a82a6f 1515 struct drm_encoder *encoder = intel_attached_encoder(connector);
ea5b213a 1516 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
57cdaf90 1517 int num_modes;
79e53945
JB		 1518
1519 /* set the bus switch and get the modes */
ea5b213a 1520 num_modes = intel_ddc_get_modes(connector, intel_sdvo->base.ddc_bus);
79e53945 1521
57cdaf90
KP		 1522 /*
1523 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1524 * link between analog and digital outputs. So, if the regular SDVO
1525 * DDC fails, check to see if the analog output is disconnected, in
1526 * which case we'll look there for the digital DDC data.
e2f0ba97 1527 */
57cdaf90 1528 if (num_modes == 0 &&
ea5b213a 1529 intel_sdvo->analog_ddc_bus &&
d2a82a6f 1530 !intel_analog_is_connected(connector->dev)) {
57cdaf90
KP		 1531 /* Switch to the analog ddc bus and try that
1532 */
ea5b213a 1533 (void) intel_ddc_get_modes(connector, intel_sdvo->analog_ddc_bus);
e2f0ba97 1534 }
e2f0ba97
JB		 1535}
1536
1537/*
1538 * Set of SDVO TV modes.
1539 * Note! This is in reply order (see loop in get_tv_modes).
1540 * XXX: all 60Hz refresh?
1541 */
1542struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1543 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1544 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1545 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1546 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1547 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1548 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1549 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1550 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1551 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1552 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1553 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1554 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1555 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1556 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1557 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1558 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1559 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1560 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1561 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1562 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1563 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1564 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1565 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1566 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1567 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1568 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1569 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1570 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1571 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1572 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1573 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1574 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1575 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1576 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1577 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1578 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1579 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1580 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1581 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1582 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1583 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1584 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1585 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1586 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1587 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1588 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1589 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1590 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1591 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1592 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1593 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1594 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1595 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1596 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1597 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1598 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1599 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1600};
1601
1602static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1603{
d2a82a6f 1604 struct drm_encoder *encoder = intel_attached_encoder(connector);
ea5b213a 1605 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
7026d4ac 1606 struct intel_sdvo_sdtv_resolution_request tv_res;
ce6feabd
ZY		 1607 uint32_t reply = 0, format_map = 0;
1608 int i;
e2f0ba97
JB		 1609
1610 /* Read the list of supported input resolutions for the selected TV
1611 * format.
1612 */
40039750 1613 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1614 memcpy(&tv_res, &format_map,
32aad86f 1615 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
ce6feabd 1616
32aad86f
CW		 1617 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1618 return;
ce6feabd 1619
32aad86f
CW		 1620 BUILD_BUG_ON(sizeof(tv_res) != 3);
1621 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
1622 &tv_res, sizeof(tv_res)))
1623 return;
1624 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
e2f0ba97
JB		 1625 return;
1626
1627 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 1628 if (reply & (1 << i)) {
1629 struct drm_display_mode *nmode;
1630 nmode = drm_mode_duplicate(connector->dev,
32aad86f 1631 &sdvo_tv_modes[i]);
7026d4ac
ZW		 1632 if (nmode)
1633 drm_mode_probed_add(connector, nmode);
1634 }
e2f0ba97
JB		 1635}
1636
7086c87f
ML		 1637static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1638{
d2a82a6f 1639 struct drm_encoder *encoder = intel_attached_encoder(connector);
ea5b213a 1640 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
7086c87f 1641 struct drm_i915_private *dev_priv = connector->dev->dev_private;
12682a97 1642 struct drm_display_mode *newmode;
7086c87f
ML		 1643
1644 /*
1645 * Attempt to get the mode list from DDC.
1646 * Assume that the preferred modes are
1647 * arranged in priority order.
1648 */
ea5b213a 1649 intel_ddc_get_modes(connector, intel_sdvo->base.ddc_bus);
7086c87f 1650 if (list_empty(&connector->probed_modes) == false)
12682a97 1651 goto end;
7086c87f
ML		 1652
1653 /* Fetch modes from VBT */
1654 if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
7086c87f
ML		 1655 newmode = drm_mode_duplicate(connector->dev,
1656 dev_priv->sdvo_lvds_vbt_mode);
1657 if (newmode != NULL) {
1658 /* Guarantee the mode is preferred */
1659 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1660 DRM_MODE_TYPE_DRIVER);
1661 drm_mode_probed_add(connector, newmode);
1662 }
1663 }
12682a97 1664
1665end:
1666 list_for_each_entry(newmode, &connector->probed_modes, head) {
1667 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
ea5b213a 1668 intel_sdvo->sdvo_lvds_fixed_mode =
12682a97 1669 drm_mode_duplicate(connector->dev, newmode);
1670 break;
1671 }
1672 }
1673
7086c87f
ML		 1674}
1675
e2f0ba97
JB		 1676static int intel_sdvo_get_modes(struct drm_connector *connector)
1677{
615fb93f 1678 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e2f0ba97 1679
615fb93f 1680 if (IS_TV(intel_sdvo_connector))
e2f0ba97 1681 intel_sdvo_get_tv_modes(connector);
615fb93f 1682 else if (IS_LVDS(intel_sdvo_connector))
7086c87f 1683 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 1684 else
1685 intel_sdvo_get_ddc_modes(connector);
1686
32aad86f 1687 return !list_empty(&connector->probed_modes);
79e53945
JB		 1688}
1689
b9219c5e
ZY		 1690static
1691void intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
1692{
615fb93f 1693 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
b9219c5e
ZY		 1694 struct drm_device *dev = connector->dev;
1695
615fb93f
CW		 1696 if (IS_TV(intel_sdvo_connector)) {
1697 if (intel_sdvo_connector->left_property)
1698 drm_property_destroy(dev, intel_sdvo_connector->left_property);
1699 if (intel_sdvo_connector->right_property)
1700 drm_property_destroy(dev, intel_sdvo_connector->right_property);
1701 if (intel_sdvo_connector->top_property)
1702 drm_property_destroy(dev, intel_sdvo_connector->top_property);
1703 if (intel_sdvo_connector->bottom_property)
1704 drm_property_destroy(dev, intel_sdvo_connector->bottom_property);
1705 if (intel_sdvo_connector->hpos_property)
1706 drm_property_destroy(dev, intel_sdvo_connector->hpos_property);
1707 if (intel_sdvo_connector->vpos_property)
1708 drm_property_destroy(dev, intel_sdvo_connector->vpos_property);
1709 if (intel_sdvo_connector->saturation_property)
b9219c5e 1710 drm_property_destroy(dev,
615fb93f
CW		 1711 intel_sdvo_connector->saturation_property);
1712 if (intel_sdvo_connector->contrast_property)
b9219c5e 1713 drm_property_destroy(dev,
615fb93f
CW		 1714 intel_sdvo_connector->contrast_property);
1715 if (intel_sdvo_connector->hue_property)
1716 drm_property_destroy(dev, intel_sdvo_connector->hue_property);
b9219c5e 1717 }
32aad86f 1718 if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
615fb93f 1719 if (intel_sdvo_connector->brightness_property)
b9219c5e 1720 drm_property_destroy(dev,
615fb93f 1721 intel_sdvo_connector->brightness_property);
b9219c5e
ZY		 1722 }
1723 return;
1724}
1725
79e53945
JB		 1726static void intel_sdvo_destroy(struct drm_connector *connector)
1727{
615fb93f 1728 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
79e53945 1729
615fb93f 1730 if (intel_sdvo_connector->tv_format_property)
ce6feabd 1731 drm_property_destroy(connector->dev,
615fb93f 1732 intel_sdvo_connector->tv_format_property);
b9219c5e 1733
d2a82a6f 1734 intel_sdvo_destroy_enhance_property(connector);
79e53945
JB		 1735 drm_sysfs_connector_remove(connector);
1736 drm_connector_cleanup(connector);
d2a82a6f 1737 kfree(connector);
79e53945
JB		 1738}
1739
ce6feabd
ZY		 1740static int
1741intel_sdvo_set_property(struct drm_connector *connector,
1742 struct drm_property *property,
1743 uint64_t val)
1744{
d2a82a6f 1745 struct drm_encoder *encoder = intel_attached_encoder(connector);
ea5b213a 1746 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
615fb93f 1747 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
ce6feabd 1748 struct drm_crtc *crtc = encoder->crtc;
ce6feabd 1749 bool changed = false;
b9219c5e 1750 uint16_t temp_value;
32aad86f
CW		 1751 uint8_t cmd;
1752 int ret;
ce6feabd
ZY		 1753
1754 ret = drm_connector_property_set_value(connector, property, val);
32aad86f
CW		 1755 if (ret)
1756 return ret;
ce6feabd 1757
615fb93f 1758 if (property == intel_sdvo_connector->tv_format_property) {
32aad86f
CW		 1759 if (val >= TV_FORMAT_NUM)
1760 return -EINVAL;
1761
40039750 1762 if (intel_sdvo->tv_format_index ==
615fb93f 1763 intel_sdvo_connector->tv_format_supported[val])
32aad86f 1764 return 0;
ce6feabd 1765
40039750 1766 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
ce6feabd 1767 changed = true;
32aad86f 1768 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
b9219c5e
ZY		 1769 cmd = 0;
1770 temp_value = val;
615fb93f 1771 if (intel_sdvo_connector->left_property == property) {
b9219c5e 1772 drm_connector_property_set_value(connector,
615fb93f
CW		 1773 intel_sdvo_connector->right_property, val);
1774 if (intel_sdvo_connector->left_margin == temp_value)
32aad86f 1775 return 0;
b9219c5e 1776
615fb93f
CW		 1777 intel_sdvo_connector->left_margin = temp_value;
1778 intel_sdvo_connector->right_margin = temp_value;
1779 temp_value = intel_sdvo_connector->max_hscan -
1780 intel_sdvo_connector->left_margin;
b9219c5e 1781 cmd = SDVO_CMD_SET_OVERSCAN_H;
615fb93f 1782 } else if (intel_sdvo_connector->right_property == property) {
b9219c5e 1783 drm_connector_property_set_value(connector,
615fb93f
CW		 1784 intel_sdvo_connector->left_property, val);
1785 if (intel_sdvo_connector->right_margin == temp_value)
32aad86f 1786 return 0;
b9219c5e 1787
615fb93f
CW		 1788 intel_sdvo_connector->left_margin = temp_value;
1789 intel_sdvo_connector->right_margin = temp_value;
1790 temp_value = intel_sdvo_connector->max_hscan -
1791 intel_sdvo_connector->left_margin;
b9219c5e 1792 cmd = SDVO_CMD_SET_OVERSCAN_H;
615fb93f 1793 } else if (intel_sdvo_connector->top_property == property) {
b9219c5e 1794 drm_connector_property_set_value(connector,
615fb93f
CW		 1795 intel_sdvo_connector->bottom_property, val);
1796 if (intel_sdvo_connector->top_margin == temp_value)
32aad86f 1797 return 0;
b9219c5e 1798
615fb93f
CW		 1799 intel_sdvo_connector->top_margin = temp_value;
1800 intel_sdvo_connector->bottom_margin = temp_value;
1801 temp_value = intel_sdvo_connector->max_vscan -
1802 intel_sdvo_connector->top_margin;
b9219c5e 1803 cmd = SDVO_CMD_SET_OVERSCAN_V;
615fb93f 1804 } else if (intel_sdvo_connector->bottom_property == property) {
b9219c5e 1805 drm_connector_property_set_value(connector,
615fb93f
CW		 1806 intel_sdvo_connector->top_property, val);
1807 if (intel_sdvo_connector->bottom_margin == temp_value)
32aad86f
CW		 1808 return 0;
1809
615fb93f
CW		 1810 intel_sdvo_connector->top_margin = temp_value;
1811 intel_sdvo_connector->bottom_margin = temp_value;
1812 temp_value = intel_sdvo_connector->max_vscan -
1813 intel_sdvo_connector->top_margin;
b9219c5e 1814 cmd = SDVO_CMD_SET_OVERSCAN_V;
615fb93f
CW		 1815 } else if (intel_sdvo_connector->hpos_property == property) {
1816 if (intel_sdvo_connector->cur_hpos == temp_value)
32aad86f 1817 return 0;
b9219c5e
ZY		 1818
1819 cmd = SDVO_CMD_SET_POSITION_H;
615fb93f
CW		 1820 intel_sdvo_connector->cur_hpos = temp_value;
1821 } else if (intel_sdvo_connector->vpos_property == property) {
1822 if (intel_sdvo_connector->cur_vpos == temp_value)
32aad86f 1823 return 0;
b9219c5e
ZY		 1824
1825 cmd = SDVO_CMD_SET_POSITION_V;
615fb93f
CW		 1826 intel_sdvo_connector->cur_vpos = temp_value;
1827 } else if (intel_sdvo_connector->saturation_property == property) {
1828 if (intel_sdvo_connector->cur_saturation == temp_value)
32aad86f 1829 return 0;
b9219c5e
ZY		 1830
1831 cmd = SDVO_CMD_SET_SATURATION;
615fb93f
CW		 1832 intel_sdvo_connector->cur_saturation = temp_value;
1833 } else if (intel_sdvo_connector->contrast_property == property) {
1834 if (intel_sdvo_connector->cur_contrast == temp_value)
32aad86f 1835 return 0;
b9219c5e
ZY		 1836
1837 cmd = SDVO_CMD_SET_CONTRAST;
615fb93f
CW		 1838 intel_sdvo_connector->cur_contrast = temp_value;
1839 } else if (intel_sdvo_connector->hue_property == property) {
1840 if (intel_sdvo_connector->cur_hue == temp_value)
32aad86f 1841 return 0;
b9219c5e
ZY		 1842
1843 cmd = SDVO_CMD_SET_HUE;
615fb93f
CW		 1844 intel_sdvo_connector->cur_hue = temp_value;
1845 } else if (intel_sdvo_connector->brightness_property == property) {
1846 if (intel_sdvo_connector->cur_brightness == temp_value)
32aad86f 1847 return 0;
b9219c5e
ZY		 1848
1849 cmd = SDVO_CMD_SET_BRIGHTNESS;
615fb93f 1850 intel_sdvo_connector->cur_brightness = temp_value;
b9219c5e
ZY		 1851 }
1852 if (cmd) {
32aad86f 1853 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
b9219c5e 1854 return -EINVAL;
32aad86f 1855
b9219c5e
ZY		 1856 changed = true;
1857 }
1858 }
ce6feabd
ZY		 1859 if (changed && crtc)
1860 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
1861 crtc->y, crtc->fb);
32aad86f 1862 return 0;
ce6feabd
ZY		 1863}
1864
79e53945
JB		 1865static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
1866 .dpms = intel_sdvo_dpms,
1867 .mode_fixup = intel_sdvo_mode_fixup,
1868 .prepare = intel_encoder_prepare,
1869 .mode_set = intel_sdvo_mode_set,
1870 .commit = intel_encoder_commit,
1871};
1872
1873static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
c9fb15f6 1874 .dpms = drm_helper_connector_dpms,
79e53945
JB		 1875 .detect = intel_sdvo_detect,
1876 .fill_modes = drm_helper_probe_single_connector_modes,
ce6feabd 1877 .set_property = intel_sdvo_set_property,
79e53945
JB		 1878 .destroy = intel_sdvo_destroy,
1879};
1880
1881static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
1882 .get_modes = intel_sdvo_get_modes,
1883 .mode_valid = intel_sdvo_mode_valid,
d2a82a6f 1884 .best_encoder = intel_attached_encoder,
79e53945
JB		 1885};
1886
b358d0a6 1887static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945 1888{
ea5b213a 1889 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
d2a82a6f 1890
ea5b213a
CW		 1891 if (intel_sdvo->analog_ddc_bus)
1892 intel_i2c_destroy(intel_sdvo->analog_ddc_bus);
d2a82a6f 1893
ea5b213a 1894 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
d2a82a6f 1895 drm_mode_destroy(encoder->dev,
ea5b213a 1896 intel_sdvo->sdvo_lvds_fixed_mode);
d2a82a6f 1897
ea5b213a 1898 intel_encoder_destroy(encoder);
79e53945
JB		 1899}
1900
1901static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
1902 .destroy = intel_sdvo_enc_destroy,
1903};
1904
1905
e2f0ba97
JB		 1906/**
1907 * Choose the appropriate DDC bus for control bus switch command for this
1908 * SDVO output based on the controlled output.
1909 *
1910 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
1911 * outputs, then LVDS outputs.
1912 */
1913static void
b1083333 1914intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
ea5b213a 1915 struct intel_sdvo *sdvo, u32 reg)
e2f0ba97 1916{
b1083333 1917 struct sdvo_device_mapping *mapping;
e2f0ba97 1918
b1083333
AJ		 1919 if (IS_SDVOB(reg))
1920 mapping = &(dev_priv->sdvo_mappings[0]);
1921 else
1922 mapping = &(dev_priv->sdvo_mappings[1]);
e2f0ba97 1923
b1083333 1924 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
e2f0ba97
JB		 1925}
1926
1927static bool
ea5b213a 1928intel_sdvo_get_digital_encoding_mode(struct intel_sdvo *intel_sdvo, int device)
e2f0ba97 1929{
32aad86f
CW		 1930 return intel_sdvo_set_target_output(intel_sdvo,
1931 device == 0 ? SDVO_OUTPUT_TMDS0 : SDVO_OUTPUT_TMDS1) &&
1932 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE,
1933 &intel_sdvo->is_hdmi, 1);
e2f0ba97
JB		 1934}
1935
ea5b213a
CW		 1936static struct intel_sdvo *
1937intel_sdvo_chan_to_intel_sdvo(struct intel_i2c_chan *chan)
619ac3b7
ML		 1938{
1939 struct drm_device *dev = chan->drm_dev;
d2a82a6f 1940 struct drm_encoder *encoder;
619ac3b7 1941
d2a82a6f 1942 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
ea5b213a
CW		 1943 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
1944 if (intel_sdvo->base.ddc_bus == &chan->adapter)
1945 return intel_sdvo;
619ac3b7 1946 }
ea5b213a 1947
32aad86f 1948 return NULL;
619ac3b7
ML		 1949}
1950
1951static int intel_sdvo_master_xfer(struct i2c_adapter *i2c_adap,
1952 struct i2c_msg msgs[], int num)
1953{
ea5b213a 1954 struct intel_sdvo *intel_sdvo;
619ac3b7 1955 struct i2c_algo_bit_data *algo_data;
f9c10a9b 1956 const struct i2c_algorithm *algo;
619ac3b7
ML		 1957
1958 algo_data = (struct i2c_algo_bit_data *)i2c_adap->algo_data;
ea5b213a
CW		 1959 intel_sdvo =
1960 intel_sdvo_chan_to_intel_sdvo((struct intel_i2c_chan *)
1961 (algo_data->data));
1962 if (intel_sdvo == NULL)
619ac3b7
ML		 1963 return -EINVAL;
1964
ea5b213a 1965 algo = intel_sdvo->base.i2c_bus->algo;
619ac3b7 1966
ea5b213a 1967 intel_sdvo_set_control_bus_switch(intel_sdvo, intel_sdvo->ddc_bus);
619ac3b7
ML		 1968 return algo->master_xfer(i2c_adap, msgs, num);
1969}
1970
1971static struct i2c_algorithm intel_sdvo_i2c_bit_algo = {
1972 .master_xfer = intel_sdvo_master_xfer,
1973};
1974
714605e4 1975static u8
c751ce4f 1976intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg)
714605e4 1977{
1978 struct drm_i915_private *dev_priv = dev->dev_private;
1979 struct sdvo_device_mapping *my_mapping, *other_mapping;
1980
461ed3ca 1981 if (IS_SDVOB(sdvo_reg)) {
714605e4 1982 my_mapping = &dev_priv->sdvo_mappings[0];
1983 other_mapping = &dev_priv->sdvo_mappings[1];
1984 } else {
1985 my_mapping = &dev_priv->sdvo_mappings[1];
1986 other_mapping = &dev_priv->sdvo_mappings[0];
1987 }
1988
1989 /* If the BIOS described our SDVO device, take advantage of it. */
1990 if (my_mapping->slave_addr)
1991 return my_mapping->slave_addr;
1992
1993 /* If the BIOS only described a different SDVO device, use the
1994 * address that it isn't using.
1995 */
1996 if (other_mapping->slave_addr) {
1997 if (other_mapping->slave_addr == 0x70)
1998 return 0x72;
1999 else
2000 return 0x70;
2001 }
2002
2003 /* No SDVO device info is found for another DVO port,
2004 * so use mapping assumption we had before BIOS parsing.
2005 */
461ed3ca 2006 if (IS_SDVOB(sdvo_reg))
714605e4 2007 return 0x70;
2008 else
2009 return 0x72;
2010}
2011
14571b4c 2012static void
32aad86f
CW		 2013intel_sdvo_connector_init(struct drm_encoder *encoder,
2014 struct drm_connector *connector)
14571b4c
ZW		 2015{
2016 drm_connector_init(encoder->dev, connector, &intel_sdvo_connector_funcs,
2017 connector->connector_type);
6070a4a9 2018
14571b4c
ZW		 2019 drm_connector_helper_add(connector, &intel_sdvo_connector_helper_funcs);
2020
2021 connector->interlace_allowed = 0;
2022 connector->doublescan_allowed = 0;
2023 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
2024
2025 drm_mode_connector_attach_encoder(connector, encoder);
2026 drm_sysfs_connector_add(connector);
2027}
6070a4a9 2028
fb7a46f3 2029static bool
ea5b213a 2030intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
fb7a46f3 2031{
ea5b213a 2032 struct drm_encoder *encoder = &intel_sdvo->base.enc;
14571b4c
ZW		 2033 struct drm_connector *connector;
2034 struct intel_connector *intel_connector;
615fb93f 2035 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2036
615fb93f
CW		 2037 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2038 if (!intel_sdvo_connector)
14571b4c
ZW		 2039 return false;
2040
14571b4c 2041 if (device == 0) {
ea5b213a 2042 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
615fb93f 2043 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
14571b4c 2044 } else if (device == 1) {
ea5b213a 2045 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
615fb93f 2046 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
14571b4c
ZW		 2047 }
2048
615fb93f 2049 intel_connector = &intel_sdvo_connector->base;
14571b4c 2050 connector = &intel_connector->base;
eb1f8e4f 2051 connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
14571b4c
ZW		 2052 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2053 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2054
ea5b213a
CW		 2055 if (intel_sdvo_get_supp_encode(intel_sdvo, &intel_sdvo->encode)
2056 && intel_sdvo_get_digital_encoding_mode(intel_sdvo, device)
2057 && intel_sdvo->is_hdmi) {
14571b4c 2058 /* enable hdmi encoding mode if supported */
ea5b213a
CW		 2059 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
2060 intel_sdvo_set_colorimetry(intel_sdvo,
14571b4c
ZW		 2061 SDVO_COLORIMETRY_RGB256);
2062 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
2063 }
ea5b213a
CW		 2064 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2065 (1 << INTEL_ANALOG_CLONE_BIT));
14571b4c 2066
32aad86f 2067 intel_sdvo_connector_init(encoder, connector);
14571b4c
ZW		 2068
2069 return true;
2070}
2071
2072static bool
ea5b213a 2073intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
14571b4c 2074{
ea5b213a 2075 struct drm_encoder *encoder = &intel_sdvo->base.enc;
14571b4c
ZW		 2076 struct drm_connector *connector;
2077 struct intel_connector *intel_connector;
615fb93f 2078 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2079
615fb93f
CW		 2080 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2081 if (!intel_sdvo_connector)
2082 return false;
14571b4c 2083
615fb93f 2084 intel_connector = &intel_sdvo_connector->base;
14571b4c
ZW		 2085 connector = &intel_connector->base;
2086 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2087 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
14571b4c 2088
ea5b213a 2089 intel_sdvo->controlled_output |= type;
615fb93f 2090 intel_sdvo_connector->output_flag = type;
14571b4c 2091
ea5b213a
CW		 2092 intel_sdvo->is_tv = true;
2093 intel_sdvo->base.needs_tv_clock = true;
2094 intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
14571b4c 2095
32aad86f 2096 intel_sdvo_connector_init(encoder, connector);
14571b4c 2097
32aad86f
CW		 2098 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
2099 goto err;
14571b4c 2100
32aad86f
CW		 2101 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
2102 goto err;
14571b4c
ZW		 2103
2104 return true;
32aad86f
CW		 2105
2106err:
2107 kfree(intel_sdvo_connector);
2108 return false;
14571b4c
ZW		 2109}
2110
2111static bool
ea5b213a 2112intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2113{
ea5b213a 2114 struct drm_encoder *encoder = &intel_sdvo->base.enc;
14571b4c
ZW		 2115 struct drm_connector *connector;
2116 struct intel_connector *intel_connector;
615fb93f 2117 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2118
615fb93f
CW		 2119 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2120 if (!intel_sdvo_connector)
2121 return false;
14571b4c 2122
615fb93f 2123 intel_connector = &intel_sdvo_connector->base;
14571b4c 2124 connector = &intel_connector->base;
eb1f8e4f 2125 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
14571b4c
ZW		 2126 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2127 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
14571b4c
ZW		 2128
2129 if (device == 0) {
ea5b213a 2130 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
615fb93f 2131 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
14571b4c 2132 } else if (device == 1) {
ea5b213a 2133 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
615fb93f 2134 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
14571b4c
ZW		 2135 }
2136
ea5b213a
CW		 2137 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2138 (1 << INTEL_ANALOG_CLONE_BIT));
14571b4c 2139
32aad86f 2140 intel_sdvo_connector_init(encoder, connector);
14571b4c
ZW		 2141 return true;
2142}
2143
2144static bool
ea5b213a 2145intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2146{
ea5b213a 2147 struct drm_encoder *encoder = &intel_sdvo->base.enc;
14571b4c
ZW		 2148 struct drm_connector *connector;
2149 struct intel_connector *intel_connector;
615fb93f 2150 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2151
615fb93f
CW		 2152 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2153 if (!intel_sdvo_connector)
2154 return false;
14571b4c 2155
615fb93f
CW		 2156 intel_connector = &intel_sdvo_connector->base;
2157 connector = &intel_connector->base;
14571b4c
ZW		 2158 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2159 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
14571b4c 2160
ea5b213a 2161 intel_sdvo->is_lvds = true;
14571b4c
ZW		 2162
2163 if (device == 0) {
ea5b213a 2164 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
615fb93f 2165 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
14571b4c 2166 } else if (device == 1) {
ea5b213a 2167 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
615fb93f 2168 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
14571b4c
ZW		 2169 }
2170
ea5b213a
CW		 2171 intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) |
2172 (1 << INTEL_SDVO_LVDS_CLONE_BIT));
14571b4c 2173
32aad86f
CW		 2174 intel_sdvo_connector_init(encoder, connector);
2175 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
2176 goto err;
2177
2178 return true;
2179
2180err:
2181 kfree(intel_sdvo_connector);
2182 return false;
14571b4c
ZW		 2183}
2184
2185static bool
ea5b213a 2186intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
14571b4c 2187{
ea5b213a
CW		 2188 intel_sdvo->is_tv = false;
2189 intel_sdvo->base.needs_tv_clock = false;
2190 intel_sdvo->is_lvds = false;
fb7a46f3 2191
14571b4c 2192 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
fb7a46f3 2193
14571b4c 2194 if (flags & SDVO_OUTPUT_TMDS0)
ea5b213a 2195 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
14571b4c
ZW		 2196 return false;
2197
2198 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
ea5b213a 2199 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
14571b4c
ZW		 2200 return false;
2201
2202 /* TV has no XXX1 function block */
a1f4b7ff 2203 if (flags & SDVO_OUTPUT_SVID0)
ea5b213a 2204 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
14571b4c
ZW		 2205 return false;
2206
2207 if (flags & SDVO_OUTPUT_CVBS0)
ea5b213a 2208 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
14571b4c 2209 return false;
fb7a46f3 2210
14571b4c 2211 if (flags & SDVO_OUTPUT_RGB0)
ea5b213a 2212 if (!intel_sdvo_analog_init(intel_sdvo, 0))
14571b4c
ZW		 2213 return false;
2214
2215 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
ea5b213a 2216 if (!intel_sdvo_analog_init(intel_sdvo, 1))
14571b4c
ZW		 2217 return false;
2218
2219 if (flags & SDVO_OUTPUT_LVDS0)
ea5b213a 2220 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
14571b4c
ZW		 2221 return false;
2222
2223 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
ea5b213a 2224 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
14571b4c 2225 return false;
fb7a46f3 2226
14571b4c 2227 if ((flags & SDVO_OUTPUT_MASK) == 0) {
fb7a46f3 2228 unsigned char bytes[2];
2229
ea5b213a
CW		 2230 intel_sdvo->controlled_output = 0;
2231 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
51c8b407 2232 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
ea5b213a 2233 SDVO_NAME(intel_sdvo),
51c8b407 2234 bytes[0], bytes[1]);
14571b4c 2235 return false;
fb7a46f3 2236 }
ea5b213a 2237 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1);
fb7a46f3 2238
14571b4c 2239 return true;
fb7a46f3 2240}
2241
32aad86f
CW		 2242static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2243 struct intel_sdvo_connector *intel_sdvo_connector,
2244 int type)
ce6feabd 2245{
32aad86f 2246 struct drm_device *dev = intel_sdvo->base.enc.dev;
ce6feabd
ZY		 2247 struct intel_sdvo_tv_format format;
2248 uint32_t format_map, i;
ce6feabd 2249
32aad86f
CW		 2250 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2251 return false;
ce6feabd 2252
32aad86f
CW		 2253 if (!intel_sdvo_get_value(intel_sdvo,
2254 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2255 &format, sizeof(format)))
2256 return false;
ce6feabd 2257
32aad86f 2258 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
ce6feabd
ZY		 2259
2260 if (format_map == 0)
32aad86f 2261 return false;
ce6feabd 2262
615fb93f 2263 intel_sdvo_connector->format_supported_num = 0;
ce6feabd 2264 for (i = 0 ; i < TV_FORMAT_NUM; i++)
40039750
CW		 2265 if (format_map & (1 << i))
2266 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
ce6feabd
ZY		 2267
2268
615fb93f 2269 intel_sdvo_connector->tv_format_property =
32aad86f
CW		 2270 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2271 "mode", intel_sdvo_connector->format_supported_num);
ce6feabd 2272
615fb93f 2273 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
ce6feabd 2274 drm_property_add_enum(
615fb93f 2275 intel_sdvo_connector->tv_format_property, i,
40039750 2276 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
ce6feabd 2277
40039750 2278 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
32aad86f
CW		 2279 drm_connector_attach_property(&intel_sdvo_connector->base.base,
2280 intel_sdvo_connector->tv_format_property, 0);
2281 return true;
ce6feabd
ZY		 2282
2283}
2284
32aad86f
CW		 2285static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2286 struct intel_sdvo_connector *intel_sdvo_connector)
b9219c5e 2287{
32aad86f
CW		 2288 struct drm_device *dev = intel_sdvo->base.enc.dev;
2289 struct drm_connector *connector = &intel_sdvo_connector->base.base;
b9219c5e 2290 struct intel_sdvo_enhancements_reply sdvo_data;
b9219c5e
ZY		 2291 uint16_t response, data_value[2];
2292
32aad86f
CW		 2293 if (!intel_sdvo_get_value(intel_sdvo,
2294 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2295 &sdvo_data, sizeof(sdvo_data)))
2296 return false;
2297
b9219c5e
ZY		 2298 response = *((uint16_t *)&sdvo_data);
2299 if (!response) {
2300 DRM_DEBUG_KMS("No enhancement is supported\n");
32aad86f 2301 return true;
b9219c5e 2302 }
ea5b213a 2303 if (IS_TV(intel_sdvo_connector)) {
b9219c5e
ZY		 2304 /* when horizontal overscan is supported, Add the left/right
2305 * property
2306 */
2307 if (sdvo_data.overscan_h) {
32aad86f
CW		 2308 if (!intel_sdvo_get_value(intel_sdvo,
2309 SDVO_CMD_GET_MAX_OVERSCAN_H,
2310 &data_value, 4))
2311 return false;
2312
2313 if (!intel_sdvo_get_value(intel_sdvo,
2314 SDVO_CMD_GET_OVERSCAN_H,
2315 &response, 2))
2316 return false;
2317
ea5b213a
CW		 2318 intel_sdvo_connector->max_hscan = data_value[0];
2319 intel_sdvo_connector->left_margin = data_value[0] - response;
2320 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
2321 intel_sdvo_connector->left_property =
b9219c5e
ZY		 2322 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2323 "left_margin", 2);
ea5b213a
CW		 2324 intel_sdvo_connector->left_property->values[0] = 0;
2325 intel_sdvo_connector->left_property->values[1] = data_value[0];
b9219c5e 2326 drm_connector_attach_property(connector,
ea5b213a
CW		 2327 intel_sdvo_connector->left_property,
2328 intel_sdvo_connector->left_margin);
2329 intel_sdvo_connector->right_property =
b9219c5e
ZY		 2330 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2331 "right_margin", 2);
ea5b213a
CW		 2332 intel_sdvo_connector->right_property->values[0] = 0;
2333 intel_sdvo_connector->right_property->values[1] = data_value[0];
b9219c5e 2334 drm_connector_attach_property(connector,
ea5b213a
CW		 2335 intel_sdvo_connector->right_property,
2336 intel_sdvo_connector->right_margin);
b9219c5e
ZY		 2337 DRM_DEBUG_KMS("h_overscan: max %d, "
2338 "default %d, current %d\n",
2339 data_value[0], data_value[1], response);
2340 }
2341 if (sdvo_data.overscan_v) {
32aad86f
CW		 2342 if (!intel_sdvo_get_value(intel_sdvo,
2343 SDVO_CMD_GET_MAX_OVERSCAN_V,
2344 &data_value, 4))
2345 return false;
2346
2347 if (!intel_sdvo_get_value(intel_sdvo,
2348 SDVO_CMD_GET_OVERSCAN_V,
2349 &response, 2))
2350 return false;
2351
ea5b213a
CW		 2352 intel_sdvo_connector->max_vscan = data_value[0];
2353 intel_sdvo_connector->top_margin = data_value[0] - response;
2354 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
2355 intel_sdvo_connector->top_property =
b9219c5e
ZY		 2356 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2357 "top_margin", 2);
ea5b213a
CW		 2358 intel_sdvo_connector->top_property->values[0] = 0;
2359 intel_sdvo_connector->top_property->values[1] = data_value[0];
b9219c5e 2360 drm_connector_attach_property(connector,
ea5b213a
CW		 2361 intel_sdvo_connector->top_property,
2362 intel_sdvo_connector->top_margin);
2363 intel_sdvo_connector->bottom_property =
b9219c5e
ZY		 2364 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2365 "bottom_margin", 2);
ea5b213a
CW		 2366 intel_sdvo_connector->bottom_property->values[0] = 0;
2367 intel_sdvo_connector->bottom_property->values[1] = data_value[0];
b9219c5e 2368 drm_connector_attach_property(connector,
ea5b213a
CW		 2369 intel_sdvo_connector->bottom_property,
2370 intel_sdvo_connector->bottom_margin);
b9219c5e
ZY		 2371 DRM_DEBUG_KMS("v_overscan: max %d, "
2372 "default %d, current %d\n",
2373 data_value[0], data_value[1], response);
2374 }
2375 if (sdvo_data.position_h) {
32aad86f
CW		 2376 if (!intel_sdvo_get_value(intel_sdvo,
2377 SDVO_CMD_GET_MAX_POSITION_H,
2378 &data_value, 4))
2379 return false;
2380
2381 if (!intel_sdvo_get_value(intel_sdvo,
2382 SDVO_CMD_GET_POSITION_H,
2383 &response, 2))
2384 return false;
2385
ea5b213a
CW		 2386 intel_sdvo_connector->max_hpos = data_value[0];
2387 intel_sdvo_connector->cur_hpos = response;
2388 intel_sdvo_connector->hpos_property =
b9219c5e
ZY		 2389 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2390 "hpos", 2);
ea5b213a
CW		 2391 intel_sdvo_connector->hpos_property->values[0] = 0;
2392 intel_sdvo_connector->hpos_property->values[1] = data_value[0];
b9219c5e 2393 drm_connector_attach_property(connector,
ea5b213a
CW		 2394 intel_sdvo_connector->hpos_property,
2395 intel_sdvo_connector->cur_hpos);
b9219c5e
ZY		 2396 DRM_DEBUG_KMS("h_position: max %d, "
2397 "default %d, current %d\n",
2398 data_value[0], data_value[1], response);
2399 }
2400 if (sdvo_data.position_v) {
32aad86f
CW		 2401 if (!intel_sdvo_get_value(intel_sdvo,
2402 SDVO_CMD_GET_MAX_POSITION_V,
2403 &data_value, 4))
2404 return false;
2405
2406 if (!intel_sdvo_get_value(intel_sdvo,
2407 SDVO_CMD_GET_POSITION_V,
2408 &response, 2))
2409 return false;
2410
ea5b213a
CW		 2411 intel_sdvo_connector->max_vpos = data_value[0];
2412 intel_sdvo_connector->cur_vpos = response;
2413 intel_sdvo_connector->vpos_property =
b9219c5e
ZY		 2414 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2415 "vpos", 2);
ea5b213a
CW		 2416 intel_sdvo_connector->vpos_property->values[0] = 0;
2417 intel_sdvo_connector->vpos_property->values[1] = data_value[0];
b9219c5e 2418 drm_connector_attach_property(connector,
ea5b213a
CW		 2419 intel_sdvo_connector->vpos_property,
2420 intel_sdvo_connector->cur_vpos);
b9219c5e
ZY		 2421 DRM_DEBUG_KMS("v_position: max %d, "
2422 "default %d, current %d\n",
2423 data_value[0], data_value[1], response);
2424 }
b9219c5e 2425 if (sdvo_data.saturation) {
32aad86f
CW		 2426 if (!intel_sdvo_get_value(intel_sdvo,
2427 SDVO_CMD_GET_MAX_SATURATION,
2428 &data_value, 4))
2429 return false;
2430
2431 if (!intel_sdvo_get_value(intel_sdvo,
2432 SDVO_CMD_GET_SATURATION,
2433 &response, 2))
2434 return false;
2435
ea5b213a
CW		 2436 intel_sdvo_connector->max_saturation = data_value[0];
2437 intel_sdvo_connector->cur_saturation = response;
2438 intel_sdvo_connector->saturation_property =
b9219c5e
ZY		 2439 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2440 "saturation", 2);
ea5b213a
CW		 2441 intel_sdvo_connector->saturation_property->values[0] = 0;
2442 intel_sdvo_connector->saturation_property->values[1] =
b9219c5e
ZY		 2443 data_value[0];
2444 drm_connector_attach_property(connector,
ea5b213a
CW		 2445 intel_sdvo_connector->saturation_property,
2446 intel_sdvo_connector->cur_saturation);
b9219c5e
ZY		 2447 DRM_DEBUG_KMS("saturation: max %d, "
2448 "default %d, current %d\n",
2449 data_value[0], data_value[1], response);
2450 }
2451 if (sdvo_data.contrast) {
32aad86f
CW		 2452 if (!intel_sdvo_get_value(intel_sdvo,
2453 SDVO_CMD_GET_MAX_CONTRAST, &data_value, 4))
2454 return false;
2455
2456 if (!intel_sdvo_get_value(intel_sdvo,
2457 SDVO_CMD_GET_CONTRAST, &response, 2))
2458 return false;
2459
ea5b213a
CW		 2460 intel_sdvo_connector->max_contrast = data_value[0];
2461 intel_sdvo_connector->cur_contrast = response;
2462 intel_sdvo_connector->contrast_property =
b9219c5e
ZY		 2463 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2464 "contrast", 2);
ea5b213a
CW		 2465 intel_sdvo_connector->contrast_property->values[0] = 0;
2466 intel_sdvo_connector->contrast_property->values[1] = data_value[0];
b9219c5e 2467 drm_connector_attach_property(connector,
ea5b213a
CW		 2468 intel_sdvo_connector->contrast_property,
2469 intel_sdvo_connector->cur_contrast);
b9219c5e
ZY		 2470 DRM_DEBUG_KMS("contrast: max %d, "
2471 "default %d, current %d\n",
2472 data_value[0], data_value[1], response);
2473 }
2474 if (sdvo_data.hue) {
32aad86f
CW		 2475 if (!intel_sdvo_get_value(intel_sdvo,
2476 SDVO_CMD_GET_MAX_HUE, &data_value, 4))
2477 return false;
2478
2479 if (!intel_sdvo_get_value(intel_sdvo,
2480 SDVO_CMD_GET_HUE, &response, 2))
2481 return false;
2482
ea5b213a
CW		 2483 intel_sdvo_connector->max_hue = data_value[0];
2484 intel_sdvo_connector->cur_hue = response;
2485 intel_sdvo_connector->hue_property =
b9219c5e
ZY		 2486 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2487 "hue", 2);
ea5b213a
CW		 2488 intel_sdvo_connector->hue_property->values[0] = 0;
2489 intel_sdvo_connector->hue_property->values[1] =
b9219c5e
ZY		 2490 data_value[0];
2491 drm_connector_attach_property(connector,
ea5b213a
CW		 2492 intel_sdvo_connector->hue_property,
2493 intel_sdvo_connector->cur_hue);
b9219c5e
ZY		 2494 DRM_DEBUG_KMS("hue: max %d, default %d, current %d\n",
2495 data_value[0], data_value[1], response);
2496 }
2497 }
32aad86f 2498 if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
b9219c5e 2499 if (sdvo_data.brightness) {
32aad86f
CW		 2500 if (!intel_sdvo_get_value(intel_sdvo,
2501 SDVO_CMD_GET_MAX_BRIGHTNESS, &data_value, 4))
2502 return false;
2503
2504 if (!intel_sdvo_get_value(intel_sdvo,
2505 SDVO_CMD_GET_BRIGHTNESS, &response, 2))
2506 return false;
2507
ea5b213a
CW		 2508 intel_sdvo_connector->max_brightness = data_value[0];
2509 intel_sdvo_connector->cur_brightness = response;
2510 intel_sdvo_connector->brightness_property =
b9219c5e
ZY		 2511 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2512 "brightness", 2);
ea5b213a
CW		 2513 intel_sdvo_connector->brightness_property->values[0] = 0;
2514 intel_sdvo_connector->brightness_property->values[1] =
b9219c5e
ZY		 2515 data_value[0];
2516 drm_connector_attach_property(connector,
ea5b213a
CW		 2517 intel_sdvo_connector->brightness_property,
2518 intel_sdvo_connector->cur_brightness);
b9219c5e
ZY		 2519 DRM_DEBUG_KMS("brightness: max %d, "
2520 "default %d, current %d\n",
2521 data_value[0], data_value[1], response);
2522 }
2523 }
32aad86f 2524 return true;
b9219c5e
ZY		 2525}
2526
c751ce4f 2527bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg)
79e53945 2528{
b01f2c3a 2529 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 2530 struct intel_encoder *intel_encoder;
ea5b213a 2531 struct intel_sdvo *intel_sdvo;
79e53945
JB		 2532 u8 ch[0x40];
2533 int i;
461ed3ca 2534 u32 i2c_reg, ddc_reg, analog_ddc_reg;
79e53945 2535
ea5b213a
CW		 2536 intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
2537 if (!intel_sdvo)
7d57382e 2538 return false;
79e53945 2539
ea5b213a 2540 intel_sdvo->sdvo_reg = sdvo_reg;
308cd3a2 2541
ea5b213a 2542 intel_encoder = &intel_sdvo->base;
21d40d37 2543 intel_encoder->type = INTEL_OUTPUT_SDVO;
79e53945 2544
461ed3ca
ZY		 2545 if (HAS_PCH_SPLIT(dev)) {
2546 i2c_reg = PCH_GPIOE;
2547 ddc_reg = PCH_GPIOE;
2548 analog_ddc_reg = PCH_GPIOA;
2549 } else {
2550 i2c_reg = GPIOE;
2551 ddc_reg = GPIOE;
2552 analog_ddc_reg = GPIOA;
2553 }
2554
79e53945 2555 /* setup the DDC bus. */
461ed3ca
ZY		 2556 if (IS_SDVOB(sdvo_reg))
2557 intel_encoder->i2c_bus = intel_i2c_create(dev, i2c_reg, "SDVOCTRL_E for SDVOB");
308cd3a2 2558 else
461ed3ca 2559 intel_encoder->i2c_bus = intel_i2c_create(dev, i2c_reg, "SDVOCTRL_E for SDVOC");
308cd3a2 2560
21d40d37 2561 if (!intel_encoder->i2c_bus)
ad5b2a6d 2562 goto err_inteloutput;
79e53945 2563
ea5b213a 2564 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg);
79e53945 2565
308cd3a2 2566 /* Save the bit-banging i2c functionality for use by the DDC wrapper */
21d40d37 2567 intel_sdvo_i2c_bit_algo.functionality = intel_encoder->i2c_bus->algo->functionality;
79e53945 2568
79e53945
JB		 2569 /* Read the regs to test if we can talk to the device */
2570 for (i = 0; i < 0x40; i++) {
ea5b213a 2571 if (!intel_sdvo_read_byte(intel_sdvo, i, &ch[i])) {
8a4c47f3 2572 DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",
461ed3ca 2573 IS_SDVOB(sdvo_reg) ? 'B' : 'C');
79e53945
JB		 2574 goto err_i2c;
2575 }
2576 }
2577
619ac3b7 2578 /* setup the DDC bus. */
461ed3ca
ZY		 2579 if (IS_SDVOB(sdvo_reg)) {
2580 intel_encoder->ddc_bus = intel_i2c_create(dev, ddc_reg, "SDVOB DDC BUS");
ea5b213a 2581 intel_sdvo->analog_ddc_bus = intel_i2c_create(dev, analog_ddc_reg,
57cdaf90 2582 "SDVOB/VGA DDC BUS");
b01f2c3a 2583 dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
57cdaf90 2584 } else {
461ed3ca 2585 intel_encoder->ddc_bus = intel_i2c_create(dev, ddc_reg, "SDVOC DDC BUS");
ea5b213a 2586 intel_sdvo->analog_ddc_bus = intel_i2c_create(dev, analog_ddc_reg,
57cdaf90 2587 "SDVOC/VGA DDC BUS");
b01f2c3a 2588 dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
57cdaf90 2589 }
32aad86f 2590 if (intel_encoder->ddc_bus == NULL || intel_sdvo->analog_ddc_bus == NULL)
619ac3b7
ML		 2591 goto err_i2c;
2592
308cd3a2 2593 /* Wrap with our custom algo which switches to DDC mode */
21d40d37 2594 intel_encoder->ddc_bus->algo = &intel_sdvo_i2c_bit_algo;
619ac3b7 2595
14571b4c
ZW		 2596 /* encoder type will be decided later */
2597 drm_encoder_init(dev, &intel_encoder->enc, &intel_sdvo_enc_funcs, 0);
2598 drm_encoder_helper_add(&intel_encoder->enc, &intel_sdvo_helper_funcs);
2599
af901ca1 2600 /* In default case sdvo lvds is false */
32aad86f
CW		 2601 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
2602 goto err_enc;
79e53945 2603
ea5b213a
CW		 2604 if (intel_sdvo_output_setup(intel_sdvo,
2605 intel_sdvo->caps.output_flags) != true) {
51c8b407 2606 DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
461ed3ca 2607 IS_SDVOB(sdvo_reg) ? 'B' : 'C');
32aad86f 2608 goto err_enc;
79e53945
JB		 2609 }
2610
ea5b213a 2611 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
e2f0ba97 2612
79e53945 2613 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 2614 if (!intel_sdvo_set_target_input(intel_sdvo))
2615 goto err_enc;
79e53945 2616
32aad86f
CW		 2617 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
2618 &intel_sdvo->pixel_clock_min,
2619 &intel_sdvo->pixel_clock_max))
2620 goto err_enc;
79e53945 2621
8a4c47f3 2622 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
342dc382 2623 "clock range %dMHz - %dMHz, "
2624 "input 1: %c, input 2: %c, "
2625 "output 1: %c, output 2: %c\n",
ea5b213a
CW		 2626 SDVO_NAME(intel_sdvo),
2627 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
2628 intel_sdvo->caps.device_rev_id,
2629 intel_sdvo->pixel_clock_min / 1000,
2630 intel_sdvo->pixel_clock_max / 1000,
2631 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2632 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
342dc382 2633 /* check currently supported outputs */
ea5b213a 2634 intel_sdvo->caps.output_flags &
79e53945 2635 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
ea5b213a 2636 intel_sdvo->caps.output_flags &
79e53945 2637 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
7d57382e 2638 return true;
79e53945 2639
32aad86f
CW		 2640err_enc:
2641 drm_encoder_cleanup(&intel_encoder->enc);
79e53945 2642err_i2c:
ea5b213a
CW		 2643 if (intel_sdvo->analog_ddc_bus != NULL)
2644 intel_i2c_destroy(intel_sdvo->analog_ddc_bus);
21d40d37
EA		 2645 if (intel_encoder->ddc_bus != NULL)
2646 intel_i2c_destroy(intel_encoder->ddc_bus);
2647 if (intel_encoder->i2c_bus != NULL)
2648 intel_i2c_destroy(intel_encoder->i2c_bus);
ad5b2a6d 2649err_inteloutput:
ea5b213a 2650 kfree(intel_sdvo);
79e53945 2651
7d57382e 2652 return false;
79e53945 2653}
Linux 6.x block layer and io_uring tree(s)