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drm/i915: Fix RGB color range property for PCH platforms
[linux-block.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
79e53945 30#include <linux/delay.h>
2d1a8a48 31#include <linux/export.h>
760285e7
DH		 32#include <drm/drmP.h>
33#include <drm/drm_crtc.h>
34#include <drm/drm_edid.h>
ea5b213a 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
79e53945
JB		 37#include "i915_drv.h"
38#include "intel_sdvo_regs.h"
39
14571b4c
ZW		 40#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
41#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
42#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
a0b1c7a5 43#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
14571b4c
ZW		 44
45#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
0206e353 46 SDVO_TV_MASK)
14571b4c
ZW		 47
48#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
13946743 49#define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
14571b4c 50#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
32aad86f 51#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
52220085 52#define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
14571b4c 53
79e53945 54
2e88e40b 55static const char *tv_format_names[] = {
ce6feabd
ZY		 56 "NTSC_M" , "NTSC_J" , "NTSC_443",
57 "PAL_B" , "PAL_D" , "PAL_G" ,
58 "PAL_H" , "PAL_I" , "PAL_M" ,
59 "PAL_N" , "PAL_NC" , "PAL_60" ,
60 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
61 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
62 "SECAM_60"
63};
64
65#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
66
ea5b213a
CW		 67struct intel_sdvo {
68 struct intel_encoder base;
69
f899fc64 70 struct i2c_adapter *i2c;
f9c10a9b 71 u8 slave_addr;
e2f0ba97 72
e957d772
CW		 73 struct i2c_adapter ddc;
74
e2f0ba97 75 /* Register for the SDVO device: SDVOB or SDVOC */
eef4eacb 76 uint32_t sdvo_reg;
79e53945 77
e2f0ba97
JB		 78 /* Active outputs controlled by this SDVO output */
79 uint16_t controlled_output;
79e53945 80
e2f0ba97
JB		 81 /*
82 * Capabilities of the SDVO device returned by
83 * i830_sdvo_get_capabilities()
84 */
79e53945 85 struct intel_sdvo_caps caps;
e2f0ba97
JB		 86
87 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 88 int pixel_clock_min, pixel_clock_max;
89
fb7a46f3 90 /*
91 * For multiple function SDVO device,
92 * this is for current attached outputs.
93 */
94 uint16_t attached_output;
95
cc68c81a
SF		 96 /*
97 * Hotplug activation bits for this device
98 */
5fa7ac9c 99 uint16_t hotplug_active;
cc68c81a 100
e953fd7b
CW		 101 /**
102 * This is used to select the color range of RBG outputs in HDMI mode.
103 * It is only valid when using TMDS encoding and 8 bit per color mode.
104 */
105 uint32_t color_range;
106
e2f0ba97
JB		 107 /**
108 * This is set if we're going to treat the device as TV-out.
109 *
110 * While we have these nice friendly flags for output types that ought
111 * to decide this for us, the S-Video output on our HDMI+S-Video card
112 * shows up as RGB1 (VGA).
113 */
114 bool is_tv;
115
eef4eacb
DV		 116 /* On different gens SDVOB is at different places. */
117 bool is_sdvob;
118
ce6feabd 119 /* This is for current tv format name */
40039750 120 int tv_format_index;
ce6feabd 121
e2f0ba97
JB		 122 /**
123 * This is set if we treat the device as HDMI, instead of DVI.
124 */
125 bool is_hdmi;
da79de97
CW		 126 bool has_hdmi_monitor;
127 bool has_hdmi_audio;
12682a97 128
7086c87f 129 /**
6c9547ff
CW		 130 * This is set if we detect output of sdvo device as LVDS and
131 * have a valid fixed mode to use with the panel.
7086c87f
ML		 132 */
133 bool is_lvds;
e2f0ba97 134
12682a97 135 /**
136 * This is sdvo fixed pannel mode pointer
137 */
138 struct drm_display_mode *sdvo_lvds_fixed_mode;
139
c751ce4f 140 /* DDC bus used by this SDVO encoder */
e2f0ba97 141 uint8_t ddc_bus;
e751823d
EE		 142
143 /*
144 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd
145 */
146 uint8_t dtd_sdvo_flags;
14571b4c
ZW		 147};
148
149struct intel_sdvo_connector {
615fb93f
CW		 150 struct intel_connector base;
151
14571b4c
ZW		 152 /* Mark the type of connector */
153 uint16_t output_flag;
154
c3e5f67b 155 enum hdmi_force_audio force_audio;
7f36e7ed 156
14571b4c 157 /* This contains all current supported TV format */
40039750 158 u8 tv_format_supported[TV_FORMAT_NUM];
14571b4c 159 int format_supported_num;
c5521706 160 struct drm_property *tv_format;
14571b4c 161
b9219c5e 162 /* add the property for the SDVO-TV */
c5521706
CW		 163 struct drm_property *left;
164 struct drm_property *right;
165 struct drm_property *top;
166 struct drm_property *bottom;
167 struct drm_property *hpos;
168 struct drm_property *vpos;
169 struct drm_property *contrast;
170 struct drm_property *saturation;
171 struct drm_property *hue;
172 struct drm_property *sharpness;
173 struct drm_property *flicker_filter;
174 struct drm_property *flicker_filter_adaptive;
175 struct drm_property *flicker_filter_2d;
176 struct drm_property *tv_chroma_filter;
177 struct drm_property *tv_luma_filter;
e044218a 178 struct drm_property *dot_crawl;
b9219c5e
ZY		 179
180 /* add the property for the SDVO-TV/LVDS */
c5521706 181 struct drm_property *brightness;
b9219c5e
ZY		 182
183 /* Add variable to record current setting for the above property */
184 u32 left_margin, right_margin, top_margin, bottom_margin;
c5521706 185
b9219c5e
ZY		 186 /* this is to get the range of margin.*/
187 u32 max_hscan, max_vscan;
188 u32 max_hpos, cur_hpos;
189 u32 max_vpos, cur_vpos;
190 u32 cur_brightness, max_brightness;
191 u32 cur_contrast, max_contrast;
192 u32 cur_saturation, max_saturation;
193 u32 cur_hue, max_hue;
c5521706
CW		 194 u32 cur_sharpness, max_sharpness;
195 u32 cur_flicker_filter, max_flicker_filter;
196 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
197 u32 cur_flicker_filter_2d, max_flicker_filter_2d;
198 u32 cur_tv_chroma_filter, max_tv_chroma_filter;
199 u32 cur_tv_luma_filter, max_tv_luma_filter;
e044218a 200 u32 cur_dot_crawl, max_dot_crawl;
79e53945
JB		 201};
202
890f3359 203static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder)
ea5b213a 204{
4ef69c7a 205 return container_of(encoder, struct intel_sdvo, base.base);
ea5b213a
CW		 206}
207
df0e9248
CW		 208static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
209{
210 return container_of(intel_attached_encoder(connector),
211 struct intel_sdvo, base);
212}
213
615fb93f
CW		 214static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
215{
216 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
217}
218
fb7a46f3 219static bool
ea5b213a 220intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
32aad86f
CW		 221static bool
222intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
223 struct intel_sdvo_connector *intel_sdvo_connector,
224 int type);
225static bool
226intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
227 struct intel_sdvo_connector *intel_sdvo_connector);
fb7a46f3 228
79e53945
JB		 229/**
230 * Writes the SDVOB or SDVOC with the given value, but always writes both
231 * SDVOB and SDVOC to work around apparent hardware issues (according to
232 * comments in the BIOS).
233 */
ea5b213a 234static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
79e53945 235{
4ef69c7a 236 struct drm_device *dev = intel_sdvo->base.base.dev;
79e53945 237 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 238 u32 bval = val, cval = val;
239 int i;
240
ea5b213a
CW		 241 if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
242 I915_WRITE(intel_sdvo->sdvo_reg, val);
243 I915_READ(intel_sdvo->sdvo_reg);
461ed3ca
ZY		 244 return;
245 }
246
ea5b213a 247 if (intel_sdvo->sdvo_reg == SDVOB) {
79e53945
JB		 248 cval = I915_READ(SDVOC);
249 } else {
250 bval = I915_READ(SDVOB);
251 }
252 /*
253 * Write the registers twice for luck. Sometimes,
254 * writing them only once doesn't appear to 'stick'.
255 * The BIOS does this too. Yay, magic
256 */
257 for (i = 0; i < 2; i++)
258 {
259 I915_WRITE(SDVOB, bval);
260 I915_READ(SDVOB);
261 I915_WRITE(SDVOC, cval);
262 I915_READ(SDVOC);
263 }
264}
265
32aad86f 266static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
79e53945 267{
79e53945
JB		 268 struct i2c_msg msgs[] = {
269 {
e957d772 270 .addr = intel_sdvo->slave_addr,
79e53945
JB		 271 .flags = 0,
272 .len = 1,
e957d772 273 .buf = &addr,
79e53945
JB		 274 },
275 {
e957d772 276 .addr = intel_sdvo->slave_addr,
79e53945
JB		 277 .flags = I2C_M_RD,
278 .len = 1,
e957d772 279 .buf = ch,
79e53945
JB		 280 }
281 };
32aad86f 282 int ret;
79e53945 283
f899fc64 284 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
79e53945 285 return true;
79e53945 286
8a4c47f3 287 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 288 return false;
289}
290
79e53945
JB		 291#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
292/** Mapping of command numbers to names, for debug output */
005568be 293static const struct _sdvo_cmd_name {
e2f0ba97 294 u8 cmd;
2e88e40b 295 const char *name;
79e53945 296} sdvo_cmd_names[] = {
0206e353
AJ		 297 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
340
341 /* Add the op code for SDVO enhancements */
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
386
387 /* HDMI op code */
388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
404 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
405 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
406 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
407 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 408};
409
eef4eacb 410#define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC")
79e53945 411
ea5b213a 412static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
32aad86f 413 const void *args, int args_len)
79e53945 414{
79e53945
JB		 415 int i;
416
8a4c47f3 417 DRM_DEBUG_KMS("%s: W: %02X ",
ea5b213a 418 SDVO_NAME(intel_sdvo), cmd);
79e53945 419 for (i = 0; i < args_len; i++)
342dc382 420 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
79e53945 421 for (; i < 8; i++)
342dc382 422 DRM_LOG_KMS(" ");
04ad327f 423 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
79e53945 424 if (cmd == sdvo_cmd_names[i].cmd) {
342dc382 425 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 426 break;
427 }
428 }
04ad327f 429 if (i == ARRAY_SIZE(sdvo_cmd_names))
342dc382 430 DRM_LOG_KMS("(%02X)", cmd);
431 DRM_LOG_KMS("\n");
79e53945 432}
79e53945 433
e957d772
CW		 434static const char *cmd_status_names[] = {
435 "Power on",
436 "Success",
437 "Not supported",
438 "Invalid arg",
439 "Pending",
440 "Target not specified",
441 "Scaling not supported"
442};
443
32aad86f
CW		 444static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
445 const void *args, int args_len)
79e53945 446{
3bf3f452
BW		 447 u8 *buf, status;
448 struct i2c_msg *msgs;
449 int i, ret = true;
450
0274df3e 451 /* Would be simpler to allocate both in one go ? */
3bf3f452
BW		 452 buf = (u8 *)kzalloc(args_len * 2 + 2, GFP_KERNEL);
453 if (!buf)
454 return false;
455
456 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
0274df3e
AC		 457 if (!msgs) {
458 kfree(buf);
3bf3f452 459 return false;
0274df3e 460 }
79e53945 461
ea5b213a 462 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
79e53945
JB		 463
464 for (i = 0; i < args_len; i++) {
e957d772
CW		 465 msgs[i].addr = intel_sdvo->slave_addr;
466 msgs[i].flags = 0;
467 msgs[i].len = 2;
468 msgs[i].buf = buf + 2 *i;
469 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
470 buf[2*i + 1] = ((u8*)args)[i];
471 }
472 msgs[i].addr = intel_sdvo->slave_addr;
473 msgs[i].flags = 0;
474 msgs[i].len = 2;
475 msgs[i].buf = buf + 2*i;
476 buf[2*i + 0] = SDVO_I2C_OPCODE;
477 buf[2*i + 1] = cmd;
478
479 /* the following two are to read the response */
480 status = SDVO_I2C_CMD_STATUS;
481 msgs[i+1].addr = intel_sdvo->slave_addr;
482 msgs[i+1].flags = 0;
483 msgs[i+1].len = 1;
484 msgs[i+1].buf = &status;
485
486 msgs[i+2].addr = intel_sdvo->slave_addr;
487 msgs[i+2].flags = I2C_M_RD;
488 msgs[i+2].len = 1;
489 msgs[i+2].buf = &status;
490
491 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
492 if (ret < 0) {
493 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
3bf3f452
BW		 494 ret = false;
495 goto out;
e957d772
CW		 496 }
497 if (ret != i+3) {
498 /* failure in I2C transfer */
499 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
3bf3f452 500 ret = false;
e957d772
CW		 501 }
502
3bf3f452
BW		 503out:
504 kfree(msgs);
505 kfree(buf);
506 return ret;
79e53945
JB		 507}
508
b5c616a7
CW		 509static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
510 void *response, int response_len)
79e53945 511{
fc37381c 512 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
b5c616a7 513 u8 status;
33b52961 514 int i;
79e53945 515
d121a5d2
CW		 516 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
517
b5c616a7
CW		 518 /*
519 * The documentation states that all commands will be
520 * processed within 15µs, and that we need only poll
521 * the status byte a maximum of 3 times in order for the
522 * command to be complete.
523 *
524 * Check 5 times in case the hardware failed to read the docs.
fc37381c
CW		 525 *
526 * Also beware that the first response by many devices is to
527 * reply PENDING and stall for time. TVs are notorious for
528 * requiring longer than specified to complete their replies.
529 * Originally (in the DDX long ago), the delay was only ever 15ms
530 * with an additional delay of 30ms applied for TVs added later after
531 * many experiments. To accommodate both sets of delays, we do a
532 * sequence of slow checks if the device is falling behind and fails
533 * to reply within 5*15µs.
b5c616a7 534 */
d121a5d2
CW		 535 if (!intel_sdvo_read_byte(intel_sdvo,
536 SDVO_I2C_CMD_STATUS,
537 &status))
538 goto log_fail;
539
fc37381c
CW		 540 while (status == SDVO_CMD_STATUS_PENDING && --retry) {
541 if (retry < 10)
542 msleep(15);
543 else
544 udelay(15);
545
b5c616a7
CW		 546 if (!intel_sdvo_read_byte(intel_sdvo,
547 SDVO_I2C_CMD_STATUS,
548 &status))
d121a5d2
CW		 549 goto log_fail;
550 }
b5c616a7 551
79e53945 552 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
342dc382 553 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
79e53945 554 else
342dc382 555 DRM_LOG_KMS("(??? %d)", status);
79e53945 556
b5c616a7
CW		 557 if (status != SDVO_CMD_STATUS_SUCCESS)
558 goto log_fail;
79e53945 559
b5c616a7
CW		 560 /* Read the command response */
561 for (i = 0; i < response_len; i++) {
562 if (!intel_sdvo_read_byte(intel_sdvo,
563 SDVO_I2C_RETURN_0 + i,
564 &((u8 *)response)[i]))
565 goto log_fail;
e957d772 566 DRM_LOG_KMS(" %02X", ((u8 *)response)[i]);
b5c616a7 567 }
b5c616a7 568 DRM_LOG_KMS("\n");
b5c616a7 569 return true;
79e53945 570
b5c616a7 571log_fail:
d121a5d2 572 DRM_LOG_KMS("... failed\n");
b5c616a7 573 return false;
79e53945
JB		 574}
575
b358d0a6 576static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
79e53945
JB		 577{
578 if (mode->clock >= 100000)
579 return 1;
580 else if (mode->clock >= 50000)
581 return 2;
582 else
583 return 4;
584}
585
e957d772
CW		 586static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
587 u8 ddc_bus)
79e53945 588{
d121a5d2 589 /* This must be the immediately preceding write before the i2c xfer */
e957d772
CW		 590 return intel_sdvo_write_cmd(intel_sdvo,
591 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
592 &ddc_bus, 1);
79e53945
JB		 593}
594
32aad86f 595static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
79e53945 596{
d121a5d2
CW		 597 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
598 return false;
599
600 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
32aad86f 601}
79e53945 602
32aad86f
CW		 603static bool
604intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
605{
606 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
607 return false;
79e53945 608
32aad86f
CW		 609 return intel_sdvo_read_response(intel_sdvo, value, len);
610}
79e53945 611
32aad86f
CW		 612static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
613{
614 struct intel_sdvo_set_target_input_args targets = {0};
615 return intel_sdvo_set_value(intel_sdvo,
616 SDVO_CMD_SET_TARGET_INPUT,
617 &targets, sizeof(targets));
79e53945
JB		 618}
619
620/**
621 * Return whether each input is trained.
622 *
623 * This function is making an assumption about the layout of the response,
624 * which should be checked against the docs.
625 */
ea5b213a 626static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
79e53945
JB		 627{
628 struct intel_sdvo_get_trained_inputs_response response;
79e53945 629
1a3665c8 630 BUILD_BUG_ON(sizeof(response) != 1);
32aad86f
CW		 631 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
632 &response, sizeof(response)))
79e53945
JB		 633 return false;
634
635 *input_1 = response.input0_trained;
636 *input_2 = response.input1_trained;
637 return true;
638}
639
ea5b213a 640static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
79e53945
JB		 641 u16 outputs)
642{
32aad86f
CW		 643 return intel_sdvo_set_value(intel_sdvo,
644 SDVO_CMD_SET_ACTIVE_OUTPUTS,
645 &outputs, sizeof(outputs));
79e53945
JB		 646}
647
4ac41f47
DV		 648static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo,
649 u16 *outputs)
650{
651 return intel_sdvo_get_value(intel_sdvo,
652 SDVO_CMD_GET_ACTIVE_OUTPUTS,
653 outputs, sizeof(*outputs));
654}
655
ea5b213a 656static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
79e53945
JB		 657 int mode)
658{
32aad86f 659 u8 state = SDVO_ENCODER_STATE_ON;
79e53945
JB		 660
661 switch (mode) {
662 case DRM_MODE_DPMS_ON:
663 state = SDVO_ENCODER_STATE_ON;
664 break;
665 case DRM_MODE_DPMS_STANDBY:
666 state = SDVO_ENCODER_STATE_STANDBY;
667 break;
668 case DRM_MODE_DPMS_SUSPEND:
669 state = SDVO_ENCODER_STATE_SUSPEND;
670 break;
671 case DRM_MODE_DPMS_OFF:
672 state = SDVO_ENCODER_STATE_OFF;
673 break;
674 }
675
32aad86f
CW		 676 return intel_sdvo_set_value(intel_sdvo,
677 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
79e53945
JB		 678}
679
ea5b213a 680static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
79e53945
JB		 681 int *clock_min,
682 int *clock_max)
683{
684 struct intel_sdvo_pixel_clock_range clocks;
79e53945 685
1a3665c8 686 BUILD_BUG_ON(sizeof(clocks) != 4);
32aad86f
CW		 687 if (!intel_sdvo_get_value(intel_sdvo,
688 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
689 &clocks, sizeof(clocks)))
79e53945
JB		 690 return false;
691
692 /* Convert the values from units of 10 kHz to kHz. */
693 *clock_min = clocks.min * 10;
694 *clock_max = clocks.max * 10;
79e53945
JB		 695 return true;
696}
697
ea5b213a 698static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
79e53945
JB		 699 u16 outputs)
700{
32aad86f
CW		 701 return intel_sdvo_set_value(intel_sdvo,
702 SDVO_CMD_SET_TARGET_OUTPUT,
703 &outputs, sizeof(outputs));
79e53945
JB		 704}
705
ea5b213a 706static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
79e53945
JB		 707 struct intel_sdvo_dtd *dtd)
708{
32aad86f
CW		 709 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
710 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
79e53945
JB		 711}
712
ea5b213a 713static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 714 struct intel_sdvo_dtd *dtd)
715{
ea5b213a 716 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 717 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
718}
719
ea5b213a 720static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 721 struct intel_sdvo_dtd *dtd)
722{
ea5b213a 723 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 724 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
725}
726
e2f0ba97 727static bool
ea5b213a 728intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 729 uint16_t clock,
730 uint16_t width,
731 uint16_t height)
732{
733 struct intel_sdvo_preferred_input_timing_args args;
e2f0ba97 734
e642c6f1 735 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 736 args.clock = clock;
737 args.width = width;
738 args.height = height;
e642c6f1 739 args.interlace = 0;
12682a97 740
ea5b213a
CW		 741 if (intel_sdvo->is_lvds &&
742 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
743 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
12682a97 744 args.scaled = 1;
745
32aad86f
CW		 746 return intel_sdvo_set_value(intel_sdvo,
747 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
748 &args, sizeof(args));
e2f0ba97
JB		 749}
750
ea5b213a 751static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 752 struct intel_sdvo_dtd *dtd)
753{
1a3665c8
CW		 754 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
755 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
32aad86f
CW		 756 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
757 &dtd->part1, sizeof(dtd->part1)) &&
758 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
759 &dtd->part2, sizeof(dtd->part2));
e2f0ba97 760}
79e53945 761
ea5b213a 762static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
79e53945 763{
32aad86f 764 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
79e53945
JB		 765}
766
e2f0ba97 767static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
32aad86f 768 const struct drm_display_mode *mode)
79e53945 769{
e2f0ba97
JB		 770 uint16_t width, height;
771 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
772 uint16_t h_sync_offset, v_sync_offset;
6651819b 773 int mode_clock;
79e53945 774
c6ebd4c0
DV		 775 width = mode->hdisplay;
776 height = mode->vdisplay;
79e53945
JB		 777
778 /* do some mode translations */
c6ebd4c0
DV		 779 h_blank_len = mode->htotal - mode->hdisplay;
780 h_sync_len = mode->hsync_end - mode->hsync_start;
79e53945 781
c6ebd4c0
DV		 782 v_blank_len = mode->vtotal - mode->vdisplay;
783 v_sync_len = mode->vsync_end - mode->vsync_start;
79e53945 784
c6ebd4c0
DV		 785 h_sync_offset = mode->hsync_start - mode->hdisplay;
786 v_sync_offset = mode->vsync_start - mode->vdisplay;
79e53945 787
6651819b
DV		 788 mode_clock = mode->clock;
789 mode_clock /= intel_mode_get_pixel_multiplier(mode) ?: 1;
790 mode_clock /= 10;
791 dtd->part1.clock = mode_clock;
792
e2f0ba97
JB		 793 dtd->part1.h_active = width & 0xff;
794 dtd->part1.h_blank = h_blank_len & 0xff;
795 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 796 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 797 dtd->part1.v_active = height & 0xff;
798 dtd->part1.v_blank = v_blank_len & 0xff;
799 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 800 ((v_blank_len >> 8) & 0xf);
801
171a9e96 802 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 803 dtd->part2.h_sync_width = h_sync_len & 0xff;
804 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 805 (v_sync_len & 0xf);
e2f0ba97 806 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 807 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
808 ((v_sync_len & 0x30) >> 4);
809
e2f0ba97 810 dtd->part2.dtd_flags = 0x18;
59d92bfa
DV		 811 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
812 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
79e53945 813 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
59d92bfa 814 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
79e53945 815 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
59d92bfa 816 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
e2f0ba97
JB		 817
818 dtd->part2.sdvo_flags = 0;
819 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
820 dtd->part2.reserved = 0;
821}
822
823static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
32aad86f 824 const struct intel_sdvo_dtd *dtd)
e2f0ba97 825{
e2f0ba97
JB		 826 mode->hdisplay = dtd->part1.h_active;
827 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
828 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
171a9e96 829 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
e2f0ba97
JB		 830 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
831 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
832 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
833 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
834
835 mode->vdisplay = dtd->part1.v_active;
836 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
837 mode->vsync_start = mode->vdisplay;
838 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
171a9e96 839 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
e2f0ba97
JB		 840 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
841 mode->vsync_end = mode->vsync_start +
842 (dtd->part2.v_sync_off_width & 0xf);
843 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
844 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
845 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
846
847 mode->clock = dtd->part1.clock * 10;
848
171a9e96 849 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
59d92bfa
DV		 850 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
851 mode->flags |= DRM_MODE_FLAG_INTERLACE;
852 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
e2f0ba97 853 mode->flags |= DRM_MODE_FLAG_PHSYNC;
59d92bfa 854 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
e2f0ba97
JB		 855 mode->flags |= DRM_MODE_FLAG_PVSYNC;
856}
857
e27d8538 858static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
e2f0ba97 859{
e27d8538 860 struct intel_sdvo_encode encode;
e2f0ba97 861
1a3665c8 862 BUILD_BUG_ON(sizeof(encode) != 2);
e27d8538
CW		 863 return intel_sdvo_get_value(intel_sdvo,
864 SDVO_CMD_GET_SUPP_ENCODE,
865 &encode, sizeof(encode));
e2f0ba97
JB		 866}
867
ea5b213a 868static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
c751ce4f 869 uint8_t mode)
e2f0ba97 870{
32aad86f 871 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
e2f0ba97
JB		 872}
873
ea5b213a 874static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 875 uint8_t mode)
876{
32aad86f 877 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
e2f0ba97
JB		 878}
879
880#if 0
ea5b213a 881static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 882{
883 int i, j;
884 uint8_t set_buf_index[2];
885 uint8_t av_split;
886 uint8_t buf_size;
887 uint8_t buf[48];
888 uint8_t *pos;
889
32aad86f 890 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
e2f0ba97
JB		 891
892 for (i = 0; i <= av_split; i++) {
893 set_buf_index[0] = i; set_buf_index[1] = 0;
c751ce4f 894 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
e2f0ba97 895 set_buf_index, 2);
c751ce4f
EA		 896 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
897 intel_sdvo_read_response(encoder, &buf_size, 1);
e2f0ba97
JB		 898
899 pos = buf;
900 for (j = 0; j <= buf_size; j += 8) {
c751ce4f 901 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
e2f0ba97 902 NULL, 0);
c751ce4f 903 intel_sdvo_read_response(encoder, pos, 8);
e2f0ba97
JB		 904 pos += 8;
905 }
906 }
907}
908#endif
909
b6e0e543
DV		 910static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
911 unsigned if_index, uint8_t tx_rate,
912 uint8_t *data, unsigned length)
913{
914 uint8_t set_buf_index[2] = { if_index, 0 };
915 uint8_t hbuf_size, tmp[8];
916 int i;
917
918 if (!intel_sdvo_set_value(intel_sdvo,
919 SDVO_CMD_SET_HBUF_INDEX,
920 set_buf_index, 2))
921 return false;
922
923 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
924 &hbuf_size, 1))
925 return false;
926
927 /* Buffer size is 0 based, hooray! */
928 hbuf_size++;
929
930 DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
931 if_index, length, hbuf_size);
932
933 for (i = 0; i < hbuf_size; i += 8) {
934 memset(tmp, 0, 8);
935 if (i < length)
936 memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
937
938 if (!intel_sdvo_set_value(intel_sdvo,
939 SDVO_CMD_SET_HBUF_DATA,
940 tmp, 8))
941 return false;
942 }
943
944 return intel_sdvo_set_value(intel_sdvo,
945 SDVO_CMD_SET_HBUF_TXRATE,
946 &tx_rate, 1);
947}
948
3c17fe4b 949static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 950{
951 struct dip_infoframe avi_if = {
952 .type = DIP_TYPE_AVI,
3c17fe4b 953 .ver = DIP_VERSION_AVI,
e2f0ba97
JB		 954 .len = DIP_LEN_AVI,
955 };
81014b9d 956 uint8_t sdvo_data[4 + sizeof(avi_if.body.avi)];
3c17fe4b
DH		 957
958 intel_dip_infoframe_csum(&avi_if);
959
81014b9d
DV		 960 /* sdvo spec says that the ecc is handled by the hw, and it looks like
961 * we must not send the ecc field, either. */
962 memcpy(sdvo_data, &avi_if, 3);
963 sdvo_data[3] = avi_if.checksum;
964 memcpy(&sdvo_data[4], &avi_if.body, sizeof(avi_if.body.avi));
965
b6e0e543
DV		 966 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
967 SDVO_HBUF_TX_VSYNC,
968 sdvo_data, sizeof(sdvo_data));
e2f0ba97
JB		 969}
970
32aad86f 971static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
7026d4ac 972{
ce6feabd 973 struct intel_sdvo_tv_format format;
40039750 974 uint32_t format_map;
ce6feabd 975
40039750 976 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 977 memset(&format, 0, sizeof(format));
32aad86f 978 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
ce6feabd 979
32aad86f
CW		 980 BUILD_BUG_ON(sizeof(format) != 6);
981 return intel_sdvo_set_value(intel_sdvo,
982 SDVO_CMD_SET_TV_FORMAT,
983 &format, sizeof(format));
7026d4ac
ZW		 984}
985
32aad86f
CW		 986static bool
987intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
e811f5ae 988 const struct drm_display_mode *mode)
e2f0ba97 989{
32aad86f 990 struct intel_sdvo_dtd output_dtd;
79e53945 991
32aad86f
CW		 992 if (!intel_sdvo_set_target_output(intel_sdvo,
993 intel_sdvo->attached_output))
994 return false;
e2f0ba97 995
32aad86f
CW		 996 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
997 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
998 return false;
e2f0ba97 999
32aad86f
CW		 1000 return true;
1001}
1002
c9a29698
DV		 1003/* Asks the sdvo controller for the preferred input mode given the output mode.
1004 * Unfortunately we have to set up the full output mode to do that. */
32aad86f 1005static bool
c9a29698 1006intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
e811f5ae 1007 const struct drm_display_mode *mode,
c9a29698 1008 struct drm_display_mode *adjusted_mode)
32aad86f 1009{
c9a29698
DV		 1010 struct intel_sdvo_dtd input_dtd;
1011
32aad86f
CW		 1012 /* Reset the input timing to the screen. Assume always input 0. */
1013 if (!intel_sdvo_set_target_input(intel_sdvo))
1014 return false;
e2f0ba97 1015
32aad86f
CW		 1016 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
1017 mode->clock / 10,
1018 mode->hdisplay,
1019 mode->vdisplay))
1020 return false;
e2f0ba97 1021
32aad86f 1022 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
c9a29698 1023 &input_dtd))
32aad86f 1024 return false;
e2f0ba97 1025
c9a29698 1026 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
e751823d 1027 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags;
79e53945 1028
32aad86f
CW		 1029 return true;
1030}
12682a97 1031
32aad86f 1032static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
e811f5ae 1033 const struct drm_display_mode *mode,
32aad86f
CW		 1034 struct drm_display_mode *adjusted_mode)
1035{
890f3359 1036 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
6c9547ff 1037 int multiplier;
12682a97 1038
32aad86f
CW		 1039 /* We need to construct preferred input timings based on our
1040 * output timings. To do that, we have to set the output
1041 * timings, even though this isn't really the right place in
1042 * the sequence to do it. Oh well.
1043 */
1044 if (intel_sdvo->is_tv) {
1045 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
1046 return false;
12682a97 1047
c9a29698
DV		 1048 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1049 mode,
1050 adjusted_mode);
ea5b213a 1051 } else if (intel_sdvo->is_lvds) {
32aad86f 1052 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
6c9547ff 1053 intel_sdvo->sdvo_lvds_fixed_mode))
e2f0ba97 1054 return false;
12682a97 1055
c9a29698
DV		 1056 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1057 mode,
1058 adjusted_mode);
e2f0ba97 1059 }
32aad86f
CW		 1060
1061 /* Make the CRTC code factor in the SDVO pixel multiplier. The
6c9547ff 1062 * SDVO device will factor out the multiplier during mode_set.
32aad86f 1063 */
6c9547ff
CW		 1064 multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode);
1065 intel_mode_set_pixel_multiplier(adjusted_mode, multiplier);
32aad86f 1066
3685a8f3
VS		 1067 if (intel_sdvo->color_range)
1068 adjusted_mode->private_flags |= INTEL_MODE_LIMITED_COLOR_RANGE;
1069
e2f0ba97
JB		 1070 return true;
1071}
1072
1073static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1074 struct drm_display_mode *mode,
1075 struct drm_display_mode *adjusted_mode)
1076{
1077 struct drm_device *dev = encoder->dev;
1078 struct drm_i915_private *dev_priv = dev->dev_private;
1079 struct drm_crtc *crtc = encoder->crtc;
1080 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
890f3359 1081 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
6c9547ff 1082 u32 sdvox;
e2f0ba97 1083 struct intel_sdvo_in_out_map in_out;
6651819b 1084 struct intel_sdvo_dtd input_dtd, output_dtd;
6c9547ff
CW		 1085 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
1086 int rate;
e2f0ba97
JB		 1087
1088 if (!mode)
1089 return;
1090
1091 /* First, set the input mapping for the first input to our controlled
1092 * output. This is only correct if we're a single-input device, in
1093 * which case the first input is the output from the appropriate SDVO
1094 * channel on the motherboard. In a two-input device, the first input
1095 * will be SDVOB and the second SDVOC.
1096 */
ea5b213a 1097 in_out.in0 = intel_sdvo->attached_output;
e2f0ba97
JB		 1098 in_out.in1 = 0;
1099
c74696b9
PR		 1100 intel_sdvo_set_value(intel_sdvo,
1101 SDVO_CMD_SET_IN_OUT_MAP,
1102 &in_out, sizeof(in_out));
e2f0ba97 1103
6c9547ff
CW		 1104 /* Set the output timings to the screen */
1105 if (!intel_sdvo_set_target_output(intel_sdvo,
1106 intel_sdvo->attached_output))
1107 return;
e2f0ba97 1108
6651819b
DV		 1109 /* lvds has a special fixed output timing. */
1110 if (intel_sdvo->is_lvds)
1111 intel_sdvo_get_dtd_from_mode(&output_dtd,
1112 intel_sdvo->sdvo_lvds_fixed_mode);
1113 else
1114 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
c8d4bb54
DV		 1115 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1116 DRM_INFO("Setting output timings on %s failed\n",
1117 SDVO_NAME(intel_sdvo));
79e53945
JB		 1118
1119 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 1120 if (!intel_sdvo_set_target_input(intel_sdvo))
1121 return;
79e53945 1122
97aaf910
CW		 1123 if (intel_sdvo->has_hdmi_monitor) {
1124 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1125 intel_sdvo_set_colorimetry(intel_sdvo,
1126 SDVO_COLORIMETRY_RGB256);
1127 intel_sdvo_set_avi_infoframe(intel_sdvo);
1128 } else
1129 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
7026d4ac 1130
6c9547ff
CW		 1131 if (intel_sdvo->is_tv &&
1132 !intel_sdvo_set_tv_format(intel_sdvo))
1133 return;
e2f0ba97 1134
6651819b
DV		 1135 /* We have tried to get input timing in mode_fixup, and filled into
1136 * adjusted_mode.
1137 */
1138 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
e751823d
EE		 1139 if (intel_sdvo->is_tv || intel_sdvo->is_lvds)
1140 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
c8d4bb54
DV		 1141 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
1142 DRM_INFO("Setting input timings on %s failed\n",
1143 SDVO_NAME(intel_sdvo));
79e53945 1144
6c9547ff
CW		 1145 switch (pixel_multiplier) {
1146 default:
32aad86f
CW		 1147 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1148 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1149 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
79e53945 1150 }
32aad86f
CW		 1151 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1152 return;
79e53945
JB		 1153
1154 /* Set the SDVO control regs. */
a6c45cf0 1155 if (INTEL_INFO(dev)->gen >= 4) {
ba68e086
PZ		 1156 /* The real mode polarity is set by the SDVO commands, using
1157 * struct intel_sdvo_dtd. */
1158 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
3685a8f3 1159 if (!HAS_PCH_SPLIT(dev) && intel_sdvo->is_hdmi)
e953fd7b 1160 sdvox |= intel_sdvo->color_range;
6714afb1
CW		 1161 if (INTEL_INFO(dev)->gen < 5)
1162 sdvox |= SDVO_BORDER_ENABLE;
e2f0ba97 1163 } else {
6c9547ff 1164 sdvox = I915_READ(intel_sdvo->sdvo_reg);
ea5b213a 1165 switch (intel_sdvo->sdvo_reg) {
e2f0ba97
JB		 1166 case SDVOB:
1167 sdvox &= SDVOB_PRESERVE_MASK;
1168 break;
1169 case SDVOC:
1170 sdvox &= SDVOC_PRESERVE_MASK;
1171 break;
1172 }
1173 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1174 }
3573c410
PZ		 1175
1176 if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
1177 sdvox |= TRANSCODER_CPT(intel_crtc->pipe);
1178 else
1179 sdvox |= TRANSCODER(intel_crtc->pipe);
1180
da79de97 1181 if (intel_sdvo->has_hdmi_audio)
6c9547ff 1182 sdvox |= SDVO_AUDIO_ENABLE;
79e53945 1183
a6c45cf0 1184 if (INTEL_INFO(dev)->gen >= 4) {
e2f0ba97
JB		 1185 /* done in crtc_mode_set as the dpll_md reg must be written early */
1186 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1187 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945 1188 } else {
6c9547ff 1189 sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT;
79e53945
JB		 1190 }
1191
6714afb1
CW		 1192 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
1193 INTEL_INFO(dev)->gen < 5)
12682a97 1194 sdvox |= SDVO_STALL_SELECT;
ea5b213a 1195 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
79e53945
JB		 1196}
1197
4ac41f47 1198static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
79e53945 1199{
4ac41f47
DV		 1200 struct intel_sdvo_connector *intel_sdvo_connector =
1201 to_intel_sdvo_connector(&connector->base);
1202 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base);
1203 u16 active_outputs;
1204
1205 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1206
1207 if (active_outputs & intel_sdvo_connector->output_flag)
1208 return true;
1209 else
1210 return false;
1211}
1212
1213static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
1214 enum pipe *pipe)
1215{
1216 struct drm_device *dev = encoder->base.dev;
79e53945 1217 struct drm_i915_private *dev_priv = dev->dev_private;
4ac41f47
DV		 1218 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
1219 u32 tmp;
1220
1221 tmp = I915_READ(intel_sdvo->sdvo_reg);
1222
1223 if (!(tmp & SDVO_ENABLE))
1224 return false;
1225
1226 if (HAS_PCH_CPT(dev))
1227 *pipe = PORT_TO_PIPE_CPT(tmp);
1228 else
1229 *pipe = PORT_TO_PIPE(tmp);
1230
1231 return true;
1232}
1233
ce22c320
DV		 1234static void intel_disable_sdvo(struct intel_encoder *encoder)
1235{
1236 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1237 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
1238 u32 temp;
1239
1240 intel_sdvo_set_active_outputs(intel_sdvo, 0);
1241 if (0)
1242 intel_sdvo_set_encoder_power_state(intel_sdvo,
1243 DRM_MODE_DPMS_OFF);
1244
1245 temp = I915_READ(intel_sdvo->sdvo_reg);
1246 if ((temp & SDVO_ENABLE) != 0) {
776ca7cf
CW		 1247 /* HW workaround for IBX, we need to move the port to
1248 * transcoder A before disabling it. */
1249 if (HAS_PCH_IBX(encoder->base.dev)) {
1250 struct drm_crtc *crtc = encoder->base.crtc;
1251 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
1252
1253 if (temp & SDVO_PIPE_B_SELECT) {
1254 temp &= ~SDVO_PIPE_B_SELECT;
1255 I915_WRITE(intel_sdvo->sdvo_reg, temp);
1256 POSTING_READ(intel_sdvo->sdvo_reg);
1257
1258 /* Again we need to write this twice. */
1259 I915_WRITE(intel_sdvo->sdvo_reg, temp);
1260 POSTING_READ(intel_sdvo->sdvo_reg);
1261
1262 /* Transcoder selection bits only update
1263 * effectively on vblank. */
1264 if (crtc)
1265 intel_wait_for_vblank(encoder->base.dev, pipe);
1266 else
1267 msleep(50);
1268 }
1269 }
1270
ce22c320
DV		 1271 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
1272 }
1273}
1274
1275static void intel_enable_sdvo(struct intel_encoder *encoder)
1276{
1277 struct drm_device *dev = encoder->base.dev;
1278 struct drm_i915_private *dev_priv = dev->dev_private;
1279 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
1280 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
79e53945 1281 u32 temp;
ce22c320
DV		 1282 bool input1, input2;
1283 int i;
1284 u8 status;
1285
1286 temp = I915_READ(intel_sdvo->sdvo_reg);
776ca7cf
CW		 1287 if ((temp & SDVO_ENABLE) == 0) {
1288 /* HW workaround for IBX, we need to move the port
1289 * to transcoder A before disabling it. */
1290 if (HAS_PCH_IBX(dev)) {
1291 struct drm_crtc *crtc = encoder->base.crtc;
1292 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
1293
1294 /* Restore the transcoder select bit. */
1295 if (pipe == PIPE_B)
1296 temp |= SDVO_PIPE_B_SELECT;
1297 }
1298
ce22c320 1299 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
776ca7cf 1300 }
ce22c320
DV		 1301 for (i = 0; i < 2; i++)
1302 intel_wait_for_vblank(dev, intel_crtc->pipe);
1303
1304 status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
1305 /* Warn if the device reported failure to sync.
1306 * A lot of SDVO devices fail to notify of sync, but it's
1307 * a given it the status is a success, we succeeded.
1308 */
1309 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
1310 DRM_DEBUG_KMS("First %s output reported failure to "
1311 "sync\n", SDVO_NAME(intel_sdvo));
1312 }
1313
1314 if (0)
1315 intel_sdvo_set_encoder_power_state(intel_sdvo,
1316 DRM_MODE_DPMS_ON);
1317 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
1318}
1319
b2cabb0e 1320static void intel_sdvo_dpms(struct drm_connector *connector, int mode)
79e53945 1321{
b2cabb0e
DV		 1322 struct drm_crtc *crtc;
1323 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1324
1325 /* dvo supports only 2 dpms states. */
1326 if (mode != DRM_MODE_DPMS_ON)
1327 mode = DRM_MODE_DPMS_OFF;
1328
1329 if (mode == connector->dpms)
1330 return;
1331
1332 connector->dpms = mode;
1333
1334 /* Only need to change hw state when actually enabled */
1335 crtc = intel_sdvo->base.base.crtc;
1336 if (!crtc) {
1337 intel_sdvo->base.connectors_active = false;
1338 return;
1339 }
79e53945
JB		 1340
1341 if (mode != DRM_MODE_DPMS_ON) {
ea5b213a 1342 intel_sdvo_set_active_outputs(intel_sdvo, 0);
79e53945 1343 if (0)
ea5b213a 1344 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
79e53945 1345
b2cabb0e
DV		 1346 intel_sdvo->base.connectors_active = false;
1347
1348 intel_crtc_update_dpms(crtc);
79e53945 1349 } else {
b2cabb0e
DV		 1350 intel_sdvo->base.connectors_active = true;
1351
1352 intel_crtc_update_dpms(crtc);
79e53945
JB		 1353
1354 if (0)
ea5b213a
CW		 1355 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1356 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
79e53945 1357 }
0a91ca29 1358
b980514c 1359 intel_modeset_check_state(connector->dev);
79e53945
JB		 1360}
1361
79e53945
JB		 1362static int intel_sdvo_mode_valid(struct drm_connector *connector,
1363 struct drm_display_mode *mode)
1364{
df0e9248 1365 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
79e53945
JB		 1366
1367 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1368 return MODE_NO_DBLESCAN;
1369
ea5b213a 1370 if (intel_sdvo->pixel_clock_min > mode->clock)
79e53945
JB		 1371 return MODE_CLOCK_LOW;
1372
ea5b213a 1373 if (intel_sdvo->pixel_clock_max < mode->clock)
79e53945
JB		 1374 return MODE_CLOCK_HIGH;
1375
8545423a 1376 if (intel_sdvo->is_lvds) {
ea5b213a 1377 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
12682a97 1378 return MODE_PANEL;
1379
ea5b213a 1380 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
12682a97 1381 return MODE_PANEL;
1382 }
1383
79e53945
JB		 1384 return MODE_OK;
1385}
1386
ea5b213a 1387static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
79e53945 1388{
1a3665c8 1389 BUILD_BUG_ON(sizeof(*caps) != 8);
e957d772
CW		 1390 if (!intel_sdvo_get_value(intel_sdvo,
1391 SDVO_CMD_GET_DEVICE_CAPS,
1392 caps, sizeof(*caps)))
1393 return false;
1394
1395 DRM_DEBUG_KMS("SDVO capabilities:\n"
1396 " vendor_id: %d\n"
1397 " device_id: %d\n"
1398 " device_rev_id: %d\n"
1399 " sdvo_version_major: %d\n"
1400 " sdvo_version_minor: %d\n"
1401 " sdvo_inputs_mask: %d\n"
1402 " smooth_scaling: %d\n"
1403 " sharp_scaling: %d\n"
1404 " up_scaling: %d\n"
1405 " down_scaling: %d\n"
1406 " stall_support: %d\n"
1407 " output_flags: %d\n",
1408 caps->vendor_id,
1409 caps->device_id,
1410 caps->device_rev_id,
1411 caps->sdvo_version_major,
1412 caps->sdvo_version_minor,
1413 caps->sdvo_inputs_mask,
1414 caps->smooth_scaling,
1415 caps->sharp_scaling,
1416 caps->up_scaling,
1417 caps->down_scaling,
1418 caps->stall_support,
1419 caps->output_flags);
1420
1421 return true;
79e53945
JB		 1422}
1423
5fa7ac9c 1424static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
79e53945 1425{
768b107e 1426 struct drm_device *dev = intel_sdvo->base.base.dev;
5fa7ac9c 1427 uint16_t hotplug;
79e53945 1428
768b107e
DV		 1429 /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
1430 * on the line. */
1431 if (IS_I945G(dev) || IS_I945GM(dev))
5fa7ac9c 1432 return 0;
768b107e 1433
5fa7ac9c
JN		 1434 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1435 &hotplug, sizeof(hotplug)))
1436 return 0;
768b107e 1437
5fa7ac9c 1438 return hotplug;
79e53945
JB		 1439}
1440
cc68c81a 1441static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
79e53945 1442{
cc68c81a 1443 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
79e53945 1444
5fa7ac9c
JN		 1445 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG,
1446 &intel_sdvo->hotplug_active, 2);
79e53945
JB		 1447}
1448
fb7a46f3 1449static bool
ea5b213a 1450intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
fb7a46f3 1451{
bc65212c 1452 /* Is there more than one type of output? */
2294488d 1453 return hweight16(intel_sdvo->caps.output_flags) > 1;
fb7a46f3 1454}
1455
f899fc64 1456static struct edid *
e957d772 1457intel_sdvo_get_edid(struct drm_connector *connector)
f899fc64 1458{
e957d772
CW		 1459 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1460 return drm_get_edid(connector, &sdvo->ddc);
f899fc64
CW		 1461}
1462
ff482d83
CW		 1463/* Mac mini hack -- use the same DDC as the analog connector */
1464static struct edid *
1465intel_sdvo_get_analog_edid(struct drm_connector *connector)
1466{
f899fc64 1467 struct drm_i915_private *dev_priv = connector->dev->dev_private;
ff482d83 1468
0c1dab89 1469 return drm_get_edid(connector,
3bd7d909
DK		 1470 intel_gmbus_get_adapter(dev_priv,
1471 dev_priv->crt_ddc_pin));
ff482d83
CW		 1472}
1473
c43b5634 1474static enum drm_connector_status
8bf38485 1475intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
9dff6af8 1476{
df0e9248 1477 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
9d1a903d
CW		 1478 enum drm_connector_status status;
1479 struct edid *edid;
9dff6af8 1480
e957d772 1481 edid = intel_sdvo_get_edid(connector);
57cdaf90 1482
ea5b213a 1483 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
e957d772 1484 u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
9d1a903d 1485
7c3f0a27
ZY		 1486 /*
1487 * Don't use the 1 as the argument of DDC bus switch to get
1488 * the EDID. It is used for SDVO SPD ROM.
1489 */
9d1a903d 1490 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
e957d772
CW		 1491 intel_sdvo->ddc_bus = ddc;
1492 edid = intel_sdvo_get_edid(connector);
1493 if (edid)
7c3f0a27 1494 break;
7c3f0a27 1495 }
e957d772
CW		 1496 /*
1497 * If we found the EDID on the other bus,
1498 * assume that is the correct DDC bus.
1499 */
1500 if (edid == NULL)
1501 intel_sdvo->ddc_bus = saved_ddc;
7c3f0a27 1502 }
9d1a903d
CW		 1503
1504 /*
1505 * When there is no edid and no monitor is connected with VGA
1506 * port, try to use the CRT ddc to read the EDID for DVI-connector.
57cdaf90 1507 */
ff482d83
CW		 1508 if (edid == NULL)
1509 edid = intel_sdvo_get_analog_edid(connector);
149c36a3 1510
2f551c84 1511 status = connector_status_unknown;
9dff6af8 1512 if (edid != NULL) {
149c36a3 1513 /* DDC bus is shared, match EDID to connector type */
9d1a903d
CW		 1514 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1515 status = connector_status_connected;
da79de97
CW		 1516 if (intel_sdvo->is_hdmi) {
1517 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
1518 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
1519 }
13946743
CW		 1520 } else
1521 status = connector_status_disconnected;
9d1a903d
CW		 1522 kfree(edid);
1523 }
7f36e7ed
CW		 1524
1525 if (status == connector_status_connected) {
1526 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
c3e5f67b
DV		 1527 if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO)
1528 intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON);
7f36e7ed
CW		 1529 }
1530
2b8d33f7 1531 return status;
9dff6af8
ML		 1532}
1533
52220085
CW		 1534static bool
1535intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
1536 struct edid *edid)
1537{
1538 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1539 bool connector_is_digital = !!IS_DIGITAL(sdvo);
1540
1541 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
1542 connector_is_digital, monitor_is_digital);
1543 return connector_is_digital == monitor_is_digital;
1544}
1545
7b334fcb 1546static enum drm_connector_status
930a9e28 1547intel_sdvo_detect(struct drm_connector *connector, bool force)
79e53945 1548{
fb7a46f3 1549 uint16_t response;
df0e9248 1550 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1551 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
14571b4c 1552 enum drm_connector_status ret;
79e53945 1553
fc37381c
CW		 1554 if (!intel_sdvo_get_value(intel_sdvo,
1555 SDVO_CMD_GET_ATTACHED_DISPLAYS,
1556 &response, 2))
32aad86f 1557 return connector_status_unknown;
79e53945 1558
e957d772
CW		 1559 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
1560 response & 0xff, response >> 8,
1561 intel_sdvo_connector->output_flag);
e2f0ba97 1562
fb7a46f3 1563 if (response == 0)
79e53945 1564 return connector_status_disconnected;
fb7a46f3 1565
ea5b213a 1566 intel_sdvo->attached_output = response;
14571b4c 1567
97aaf910
CW		 1568 intel_sdvo->has_hdmi_monitor = false;
1569 intel_sdvo->has_hdmi_audio = false;
1570
615fb93f 1571 if ((intel_sdvo_connector->output_flag & response) == 0)
14571b4c 1572 ret = connector_status_disconnected;
13946743 1573 else if (IS_TMDS(intel_sdvo_connector))
8bf38485 1574 ret = intel_sdvo_tmds_sink_detect(connector);
13946743
CW		 1575 else {
1576 struct edid *edid;
1577
1578 /* if we have an edid check it matches the connection */
1579 edid = intel_sdvo_get_edid(connector);
1580 if (edid == NULL)
1581 edid = intel_sdvo_get_analog_edid(connector);
1582 if (edid != NULL) {
52220085
CW		 1583 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
1584 edid))
13946743 1585 ret = connector_status_connected;
52220085
CW		 1586 else
1587 ret = connector_status_disconnected;
1588
13946743
CW		 1589 kfree(edid);
1590 } else
1591 ret = connector_status_connected;
1592 }
14571b4c
ZW		 1593
1594 /* May update encoder flag for like clock for SDVO TV, etc.*/
1595 if (ret == connector_status_connected) {
ea5b213a
CW		 1596 intel_sdvo->is_tv = false;
1597 intel_sdvo->is_lvds = false;
1598 intel_sdvo->base.needs_tv_clock = false;
14571b4c
ZW		 1599
1600 if (response & SDVO_TV_MASK) {
ea5b213a
CW		 1601 intel_sdvo->is_tv = true;
1602 intel_sdvo->base.needs_tv_clock = true;
14571b4c
ZW		 1603 }
1604 if (response & SDVO_LVDS_MASK)
8545423a 1605 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
fb7a46f3 1606 }
14571b4c
ZW		 1607
1608 return ret;
79e53945
JB		 1609}
1610
e2f0ba97 1611static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945 1612{
ff482d83 1613 struct edid *edid;
79e53945
JB		 1614
1615 /* set the bus switch and get the modes */
e957d772 1616 edid = intel_sdvo_get_edid(connector);
79e53945 1617
57cdaf90
KP		 1618 /*
1619 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1620 * link between analog and digital outputs. So, if the regular SDVO
1621 * DDC fails, check to see if the analog output is disconnected, in
1622 * which case we'll look there for the digital DDC data.
e2f0ba97 1623 */
f899fc64
CW		 1624 if (edid == NULL)
1625 edid = intel_sdvo_get_analog_edid(connector);
1626
ff482d83 1627 if (edid != NULL) {
52220085
CW		 1628 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
1629 edid)) {
0c1dab89
CW		 1630 drm_mode_connector_update_edid_property(connector, edid);
1631 drm_add_edid_modes(connector, edid);
1632 }
13946743 1633
ff482d83 1634 kfree(edid);
e2f0ba97 1635 }
e2f0ba97
JB		 1636}
1637
1638/*
1639 * Set of SDVO TV modes.
1640 * Note! This is in reply order (see loop in get_tv_modes).
1641 * XXX: all 60Hz refresh?
1642 */
b1f559ec 1643static const struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1644 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1645 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1646 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1647 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1648 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1649 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1650 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1651 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1652 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1653 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1654 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1655 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1656 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1657 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1658 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1659 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1660 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1661 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1662 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1663 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1664 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1665 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1666 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1667 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1668 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1669 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1670 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1671 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1672 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1673 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1674 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1675 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1676 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1677 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1678 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1679 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1680 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1681 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1682 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1683 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1684 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1685 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1686 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1687 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1688 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1689 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1690 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1691 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1692 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1693 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1694 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1695 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1696 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1697 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1698 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1699 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1700 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1701};
1702
1703static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1704{
df0e9248 1705 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7026d4ac 1706 struct intel_sdvo_sdtv_resolution_request tv_res;
ce6feabd
ZY		 1707 uint32_t reply = 0, format_map = 0;
1708 int i;
e2f0ba97
JB		 1709
1710 /* Read the list of supported input resolutions for the selected TV
1711 * format.
1712 */
40039750 1713 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1714 memcpy(&tv_res, &format_map,
32aad86f 1715 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
ce6feabd 1716
32aad86f
CW		 1717 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1718 return;
ce6feabd 1719
32aad86f 1720 BUILD_BUG_ON(sizeof(tv_res) != 3);
e957d772
CW		 1721 if (!intel_sdvo_write_cmd(intel_sdvo,
1722 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
32aad86f
CW		 1723 &tv_res, sizeof(tv_res)))
1724 return;
1725 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
e2f0ba97
JB		 1726 return;
1727
1728 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 1729 if (reply & (1 << i)) {
1730 struct drm_display_mode *nmode;
1731 nmode = drm_mode_duplicate(connector->dev,
32aad86f 1732 &sdvo_tv_modes[i]);
7026d4ac
ZW		 1733 if (nmode)
1734 drm_mode_probed_add(connector, nmode);
1735 }
e2f0ba97
JB		 1736}
1737
7086c87f
ML		 1738static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1739{
df0e9248 1740 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7086c87f 1741 struct drm_i915_private *dev_priv = connector->dev->dev_private;
12682a97 1742 struct drm_display_mode *newmode;
7086c87f
ML		 1743
1744 /*
1745 * Attempt to get the mode list from DDC.
1746 * Assume that the preferred modes are
1747 * arranged in priority order.
1748 */
f899fc64 1749 intel_ddc_get_modes(connector, intel_sdvo->i2c);
7086c87f 1750 if (list_empty(&connector->probed_modes) == false)
12682a97 1751 goto end;
7086c87f
ML		 1752
1753 /* Fetch modes from VBT */
1754 if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
7086c87f
ML		 1755 newmode = drm_mode_duplicate(connector->dev,
1756 dev_priv->sdvo_lvds_vbt_mode);
1757 if (newmode != NULL) {
1758 /* Guarantee the mode is preferred */
1759 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1760 DRM_MODE_TYPE_DRIVER);
1761 drm_mode_probed_add(connector, newmode);
1762 }
1763 }
12682a97 1764
1765end:
1766 list_for_each_entry(newmode, &connector->probed_modes, head) {
1767 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
ea5b213a 1768 intel_sdvo->sdvo_lvds_fixed_mode =
12682a97 1769 drm_mode_duplicate(connector->dev, newmode);
6c9547ff 1770
8545423a 1771 intel_sdvo->is_lvds = true;
12682a97 1772 break;
1773 }
1774 }
1775
7086c87f
ML		 1776}
1777
e2f0ba97
JB		 1778static int intel_sdvo_get_modes(struct drm_connector *connector)
1779{
615fb93f 1780 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e2f0ba97 1781
615fb93f 1782 if (IS_TV(intel_sdvo_connector))
e2f0ba97 1783 intel_sdvo_get_tv_modes(connector);
615fb93f 1784 else if (IS_LVDS(intel_sdvo_connector))
7086c87f 1785 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 1786 else
1787 intel_sdvo_get_ddc_modes(connector);
1788
32aad86f 1789 return !list_empty(&connector->probed_modes);
79e53945
JB		 1790}
1791
fcc8d672
CW		 1792static void
1793intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
b9219c5e 1794{
615fb93f 1795 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
b9219c5e
ZY		 1796 struct drm_device *dev = connector->dev;
1797
c5521706
CW		 1798 if (intel_sdvo_connector->left)
1799 drm_property_destroy(dev, intel_sdvo_connector->left);
1800 if (intel_sdvo_connector->right)
1801 drm_property_destroy(dev, intel_sdvo_connector->right);
1802 if (intel_sdvo_connector->top)
1803 drm_property_destroy(dev, intel_sdvo_connector->top);
1804 if (intel_sdvo_connector->bottom)
1805 drm_property_destroy(dev, intel_sdvo_connector->bottom);
1806 if (intel_sdvo_connector->hpos)
1807 drm_property_destroy(dev, intel_sdvo_connector->hpos);
1808 if (intel_sdvo_connector->vpos)
1809 drm_property_destroy(dev, intel_sdvo_connector->vpos);
1810 if (intel_sdvo_connector->saturation)
1811 drm_property_destroy(dev, intel_sdvo_connector->saturation);
1812 if (intel_sdvo_connector->contrast)
1813 drm_property_destroy(dev, intel_sdvo_connector->contrast);
1814 if (intel_sdvo_connector->hue)
1815 drm_property_destroy(dev, intel_sdvo_connector->hue);
1816 if (intel_sdvo_connector->sharpness)
1817 drm_property_destroy(dev, intel_sdvo_connector->sharpness);
1818 if (intel_sdvo_connector->flicker_filter)
1819 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
1820 if (intel_sdvo_connector->flicker_filter_2d)
1821 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
1822 if (intel_sdvo_connector->flicker_filter_adaptive)
1823 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
1824 if (intel_sdvo_connector->tv_luma_filter)
1825 drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
1826 if (intel_sdvo_connector->tv_chroma_filter)
1827 drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
e044218a
CW		 1828 if (intel_sdvo_connector->dot_crawl)
1829 drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
c5521706
CW		 1830 if (intel_sdvo_connector->brightness)
1831 drm_property_destroy(dev, intel_sdvo_connector->brightness);
b9219c5e
ZY		 1832}
1833
79e53945
JB		 1834static void intel_sdvo_destroy(struct drm_connector *connector)
1835{
615fb93f 1836 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
79e53945 1837
c5521706 1838 if (intel_sdvo_connector->tv_format)
ce6feabd 1839 drm_property_destroy(connector->dev,
c5521706 1840 intel_sdvo_connector->tv_format);
b9219c5e 1841
d2a82a6f 1842 intel_sdvo_destroy_enhance_property(connector);
79e53945
JB		 1843 drm_sysfs_connector_remove(connector);
1844 drm_connector_cleanup(connector);
4b745b1e 1845 kfree(intel_sdvo_connector);
79e53945
JB		 1846}
1847
1aad7ac0
CW		 1848static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
1849{
1850 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1851 struct edid *edid;
1852 bool has_audio = false;
1853
1854 if (!intel_sdvo->is_hdmi)
1855 return false;
1856
1857 edid = intel_sdvo_get_edid(connector);
1858 if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
1859 has_audio = drm_detect_monitor_audio(edid);
38ab8a20 1860 kfree(edid);
1aad7ac0
CW		 1861
1862 return has_audio;
1863}
1864
ce6feabd
ZY		 1865static int
1866intel_sdvo_set_property(struct drm_connector *connector,
1867 struct drm_property *property,
1868 uint64_t val)
1869{
df0e9248 1870 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1871 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e953fd7b 1872 struct drm_i915_private *dev_priv = connector->dev->dev_private;
b9219c5e 1873 uint16_t temp_value;
32aad86f
CW		 1874 uint8_t cmd;
1875 int ret;
ce6feabd 1876
662595df 1877 ret = drm_object_property_set_value(&connector->base, property, val);
32aad86f
CW		 1878 if (ret)
1879 return ret;
ce6feabd 1880
3f43c48d 1881 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 1882 int i = val;
1883 bool has_audio;
1884
1885 if (i == intel_sdvo_connector->force_audio)
7f36e7ed
CW		 1886 return 0;
1887
1aad7ac0 1888 intel_sdvo_connector->force_audio = i;
7f36e7ed 1889
c3e5f67b 1890 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 1891 has_audio = intel_sdvo_detect_hdmi_audio(connector);
1892 else
c3e5f67b 1893 has_audio = (i == HDMI_AUDIO_ON);
7f36e7ed 1894
1aad7ac0 1895 if (has_audio == intel_sdvo->has_hdmi_audio)
7f36e7ed 1896 return 0;
7f36e7ed 1897
1aad7ac0 1898 intel_sdvo->has_hdmi_audio = has_audio;
7f36e7ed
CW		 1899 goto done;
1900 }
1901
e953fd7b
CW		 1902 if (property == dev_priv->broadcast_rgb_property) {
1903 if (val == !!intel_sdvo->color_range)
7f36e7ed
CW		 1904 return 0;
1905
e953fd7b 1906 intel_sdvo->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
7f36e7ed
CW		 1907 goto done;
1908 }
1909
c5521706
CW		 1910#define CHECK_PROPERTY(name, NAME) \
1911 if (intel_sdvo_connector->name == property) { \
1912 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
1913 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
1914 cmd = SDVO_CMD_SET_##NAME; \
1915 intel_sdvo_connector->cur_##name = temp_value; \
1916 goto set_value; \
1917 }
1918
1919 if (property == intel_sdvo_connector->tv_format) {
32aad86f
CW		 1920 if (val >= TV_FORMAT_NUM)
1921 return -EINVAL;
1922
40039750 1923 if (intel_sdvo->tv_format_index ==
615fb93f 1924 intel_sdvo_connector->tv_format_supported[val])
32aad86f 1925 return 0;
ce6feabd 1926
40039750 1927 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
c5521706 1928 goto done;
32aad86f 1929 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
b9219c5e 1930 temp_value = val;
c5521706 1931 if (intel_sdvo_connector->left == property) {
662595df 1932 drm_object_property_set_value(&connector->base,
c5521706 1933 intel_sdvo_connector->right, val);
615fb93f 1934 if (intel_sdvo_connector->left_margin == temp_value)
32aad86f 1935 return 0;
b9219c5e 1936
615fb93f
CW		 1937 intel_sdvo_connector->left_margin = temp_value;
1938 intel_sdvo_connector->right_margin = temp_value;
1939 temp_value = intel_sdvo_connector->max_hscan -
c5521706 1940 intel_sdvo_connector->left_margin;
b9219c5e 1941 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1942 goto set_value;
1943 } else if (intel_sdvo_connector->right == property) {
662595df 1944 drm_object_property_set_value(&connector->base,
c5521706 1945 intel_sdvo_connector->left, val);
615fb93f 1946 if (intel_sdvo_connector->right_margin == temp_value)
32aad86f 1947 return 0;
b9219c5e 1948
615fb93f
CW		 1949 intel_sdvo_connector->left_margin = temp_value;
1950 intel_sdvo_connector->right_margin = temp_value;
1951 temp_value = intel_sdvo_connector->max_hscan -
1952 intel_sdvo_connector->left_margin;
b9219c5e 1953 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1954 goto set_value;
1955 } else if (intel_sdvo_connector->top == property) {
662595df 1956 drm_object_property_set_value(&connector->base,
c5521706 1957 intel_sdvo_connector->bottom, val);
615fb93f 1958 if (intel_sdvo_connector->top_margin == temp_value)
32aad86f 1959 return 0;
b9219c5e 1960
615fb93f
CW		 1961 intel_sdvo_connector->top_margin = temp_value;
1962 intel_sdvo_connector->bottom_margin = temp_value;
1963 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1964 intel_sdvo_connector->top_margin;
b9219c5e 1965 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1966 goto set_value;
1967 } else if (intel_sdvo_connector->bottom == property) {
662595df 1968 drm_object_property_set_value(&connector->base,
c5521706 1969 intel_sdvo_connector->top, val);
615fb93f 1970 if (intel_sdvo_connector->bottom_margin == temp_value)
32aad86f
CW		 1971 return 0;
1972
615fb93f
CW		 1973 intel_sdvo_connector->top_margin = temp_value;
1974 intel_sdvo_connector->bottom_margin = temp_value;
1975 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1976 intel_sdvo_connector->top_margin;
b9219c5e 1977 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1978 goto set_value;
1979 }
1980 CHECK_PROPERTY(hpos, HPOS)
1981 CHECK_PROPERTY(vpos, VPOS)
1982 CHECK_PROPERTY(saturation, SATURATION)
1983 CHECK_PROPERTY(contrast, CONTRAST)
1984 CHECK_PROPERTY(hue, HUE)
1985 CHECK_PROPERTY(brightness, BRIGHTNESS)
1986 CHECK_PROPERTY(sharpness, SHARPNESS)
1987 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
1988 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
1989 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
1990 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
1991 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
e044218a 1992 CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
c5521706 1993 }
b9219c5e 1994
c5521706 1995 return -EINVAL; /* unknown property */
b9219c5e 1996
c5521706
CW		 1997set_value:
1998 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
1999 return -EIO;
b9219c5e 2000
b9219c5e 2001
c5521706 2002done:
c0c36b94
CW		 2003 if (intel_sdvo->base.base.crtc)
2004 intel_crtc_restore_mode(intel_sdvo->base.base.crtc);
c5521706 2005
32aad86f 2006 return 0;
c5521706 2007#undef CHECK_PROPERTY
ce6feabd
ZY		 2008}
2009
79e53945 2010static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
79e53945 2011 .mode_fixup = intel_sdvo_mode_fixup,
79e53945 2012 .mode_set = intel_sdvo_mode_set,
1f703855 2013 .disable = intel_encoder_noop,
79e53945
JB		 2014};
2015
2016static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
b2cabb0e 2017 .dpms = intel_sdvo_dpms,
79e53945
JB		 2018 .detect = intel_sdvo_detect,
2019 .fill_modes = drm_helper_probe_single_connector_modes,
ce6feabd 2020 .set_property = intel_sdvo_set_property,
79e53945
JB		 2021 .destroy = intel_sdvo_destroy,
2022};
2023
2024static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
2025 .get_modes = intel_sdvo_get_modes,
2026 .mode_valid = intel_sdvo_mode_valid,
df0e9248 2027 .best_encoder = intel_best_encoder,
79e53945
JB		 2028};
2029
b358d0a6 2030static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945 2031{
890f3359 2032 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
d2a82a6f 2033
ea5b213a 2034 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
d2a82a6f 2035 drm_mode_destroy(encoder->dev,
ea5b213a 2036 intel_sdvo->sdvo_lvds_fixed_mode);
d2a82a6f 2037
e957d772 2038 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 2039 intel_encoder_destroy(encoder);
79e53945
JB		 2040}
2041
2042static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
2043 .destroy = intel_sdvo_enc_destroy,
2044};
2045
b66d8424
CW		 2046static void
2047intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
2048{
2049 uint16_t mask = 0;
2050 unsigned int num_bits;
2051
2052 /* Make a mask of outputs less than or equal to our own priority in the
2053 * list.
2054 */
2055 switch (sdvo->controlled_output) {
2056 case SDVO_OUTPUT_LVDS1:
2057 mask |= SDVO_OUTPUT_LVDS1;
2058 case SDVO_OUTPUT_LVDS0:
2059 mask |= SDVO_OUTPUT_LVDS0;
2060 case SDVO_OUTPUT_TMDS1:
2061 mask |= SDVO_OUTPUT_TMDS1;
2062 case SDVO_OUTPUT_TMDS0:
2063 mask |= SDVO_OUTPUT_TMDS0;
2064 case SDVO_OUTPUT_RGB1:
2065 mask |= SDVO_OUTPUT_RGB1;
2066 case SDVO_OUTPUT_RGB0:
2067 mask |= SDVO_OUTPUT_RGB0;
2068 break;
2069 }
2070
2071 /* Count bits to find what number we are in the priority list. */
2072 mask &= sdvo->caps.output_flags;
2073 num_bits = hweight16(mask);
2074 /* If more than 3 outputs, default to DDC bus 3 for now. */
2075 if (num_bits > 3)
2076 num_bits = 3;
2077
2078 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
2079 sdvo->ddc_bus = 1 << num_bits;
2080}
79e53945 2081
e2f0ba97
JB		 2082/**
2083 * Choose the appropriate DDC bus for control bus switch command for this
2084 * SDVO output based on the controlled output.
2085 *
2086 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
2087 * outputs, then LVDS outputs.
2088 */
2089static void
b1083333 2090intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
ea5b213a 2091 struct intel_sdvo *sdvo, u32 reg)
e2f0ba97 2092{
b1083333 2093 struct sdvo_device_mapping *mapping;
e2f0ba97 2094
eef4eacb 2095 if (sdvo->is_sdvob)
b1083333
AJ		 2096 mapping = &(dev_priv->sdvo_mappings[0]);
2097 else
2098 mapping = &(dev_priv->sdvo_mappings[1]);
e2f0ba97 2099
b66d8424
CW		 2100 if (mapping->initialized)
2101 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
2102 else
2103 intel_sdvo_guess_ddc_bus(sdvo);
e2f0ba97
JB		 2104}
2105
e957d772
CW		 2106static void
2107intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
2108 struct intel_sdvo *sdvo, u32 reg)
2109{
2110 struct sdvo_device_mapping *mapping;
46eb3036 2111 u8 pin;
e957d772 2112
eef4eacb 2113 if (sdvo->is_sdvob)
e957d772
CW		 2114 mapping = &dev_priv->sdvo_mappings[0];
2115 else
2116 mapping = &dev_priv->sdvo_mappings[1];
2117
6cb1612a 2118 if (mapping->initialized && intel_gmbus_is_port_valid(mapping->i2c_pin))
e957d772 2119 pin = mapping->i2c_pin;
6cb1612a
JN		 2120 else
2121 pin = GMBUS_PORT_DPB;
e957d772 2122
6cb1612a
JN		 2123 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
2124
2125 /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow
2126 * our code totally fails once we start using gmbus. Hence fall back to
2127 * bit banging for now. */
2128 intel_gmbus_force_bit(sdvo->i2c, true);
e957d772
CW		 2129}
2130
fbfcc4f3
JN		 2131/* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */
2132static void
2133intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo)
2134{
2135 intel_gmbus_force_bit(sdvo->i2c, false);
e957d772
CW		 2136}
2137
e2f0ba97 2138static bool
e27d8538 2139intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
e2f0ba97 2140{
97aaf910 2141 return intel_sdvo_check_supp_encode(intel_sdvo);
e2f0ba97
JB		 2142}
2143
714605e4 2144static u8
eef4eacb 2145intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo)
714605e4 2146{
2147 struct drm_i915_private *dev_priv = dev->dev_private;
2148 struct sdvo_device_mapping *my_mapping, *other_mapping;
2149
eef4eacb 2150 if (sdvo->is_sdvob) {
714605e4 2151 my_mapping = &dev_priv->sdvo_mappings[0];
2152 other_mapping = &dev_priv->sdvo_mappings[1];
2153 } else {
2154 my_mapping = &dev_priv->sdvo_mappings[1];
2155 other_mapping = &dev_priv->sdvo_mappings[0];
2156 }
2157
2158 /* If the BIOS described our SDVO device, take advantage of it. */
2159 if (my_mapping->slave_addr)
2160 return my_mapping->slave_addr;
2161
2162 /* If the BIOS only described a different SDVO device, use the
2163 * address that it isn't using.
2164 */
2165 if (other_mapping->slave_addr) {
2166 if (other_mapping->slave_addr == 0x70)
2167 return 0x72;
2168 else
2169 return 0x70;
2170 }
2171
2172 /* No SDVO device info is found for another DVO port,
2173 * so use mapping assumption we had before BIOS parsing.
2174 */
eef4eacb 2175 if (sdvo->is_sdvob)
714605e4 2176 return 0x70;
2177 else
2178 return 0x72;
2179}
2180
14571b4c 2181static void
df0e9248
CW		 2182intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
2183 struct intel_sdvo *encoder)
14571b4c 2184{
df0e9248
CW		 2185 drm_connector_init(encoder->base.base.dev,
2186 &connector->base.base,
2187 &intel_sdvo_connector_funcs,
2188 connector->base.base.connector_type);
6070a4a9 2189
df0e9248
CW		 2190 drm_connector_helper_add(&connector->base.base,
2191 &intel_sdvo_connector_helper_funcs);
14571b4c 2192
8f4839e2 2193 connector->base.base.interlace_allowed = 1;
df0e9248
CW		 2194 connector->base.base.doublescan_allowed = 0;
2195 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
4ac41f47 2196 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
14571b4c 2197
df0e9248
CW		 2198 intel_connector_attach_encoder(&connector->base, &encoder->base);
2199 drm_sysfs_connector_add(&connector->base.base);
14571b4c 2200}
6070a4a9 2201
7f36e7ed
CW		 2202static void
2203intel_sdvo_add_hdmi_properties(struct intel_sdvo_connector *connector)
2204{
2205 struct drm_device *dev = connector->base.base.dev;
2206
3f43c48d 2207 intel_attach_force_audio_property(&connector->base.base);
e953fd7b
CW		 2208 if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev))
2209 intel_attach_broadcast_rgb_property(&connector->base.base);
7f36e7ed
CW		 2210}
2211
fb7a46f3 2212static bool
ea5b213a 2213intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
fb7a46f3 2214{
4ef69c7a 2215 struct drm_encoder *encoder = &intel_sdvo->base.base;
14571b4c 2216 struct drm_connector *connector;
cc68c81a 2217 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
14571b4c 2218 struct intel_connector *intel_connector;
615fb93f 2219 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2220
615fb93f
CW		 2221 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2222 if (!intel_sdvo_connector)
14571b4c
ZW		 2223 return false;
2224
14571b4c 2225 if (device == 0) {
ea5b213a 2226 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
615fb93f 2227 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
14571b4c 2228 } else if (device == 1) {
ea5b213a 2229 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
615fb93f 2230 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
14571b4c
ZW		 2231 }
2232
615fb93f 2233 intel_connector = &intel_sdvo_connector->base;
14571b4c 2234 connector = &intel_connector->base;
5fa7ac9c
JN		 2235 if (intel_sdvo_get_hotplug_support(intel_sdvo) &
2236 intel_sdvo_connector->output_flag) {
cc68c81a 2237 connector->polled = DRM_CONNECTOR_POLL_HPD;
5fa7ac9c 2238 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag;
cc68c81a
SF		 2239 /* Some SDVO devices have one-shot hotplug interrupts.
2240 * Ensure that they get re-enabled when an interrupt happens.
2241 */
2242 intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
2243 intel_sdvo_enable_hotplug(intel_encoder);
5fa7ac9c 2244 } else {
cc68c81a 2245 connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
5fa7ac9c 2246 }
14571b4c
ZW		 2247 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2248 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2249
e27d8538 2250 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
14571b4c 2251 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
e27d8538 2252 intel_sdvo->is_hdmi = true;
14571b4c 2253 }
14571b4c 2254
df0e9248 2255 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
f797d221
CW		 2256 if (intel_sdvo->is_hdmi)
2257 intel_sdvo_add_hdmi_properties(intel_sdvo_connector);
14571b4c
ZW		 2258
2259 return true;
2260}
2261
2262static bool
ea5b213a 2263intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
14571b4c 2264{
4ef69c7a
CW		 2265 struct drm_encoder *encoder = &intel_sdvo->base.base;
2266 struct drm_connector *connector;
2267 struct intel_connector *intel_connector;
2268 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2269
615fb93f
CW		 2270 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2271 if (!intel_sdvo_connector)
2272 return false;
14571b4c 2273
615fb93f 2274 intel_connector = &intel_sdvo_connector->base;
4ef69c7a
CW		 2275 connector = &intel_connector->base;
2276 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2277 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
14571b4c 2278
4ef69c7a
CW		 2279 intel_sdvo->controlled_output |= type;
2280 intel_sdvo_connector->output_flag = type;
14571b4c 2281
4ef69c7a
CW		 2282 intel_sdvo->is_tv = true;
2283 intel_sdvo->base.needs_tv_clock = true;
14571b4c 2284
df0e9248 2285 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
14571b4c 2286
4ef69c7a 2287 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
32aad86f 2288 goto err;
14571b4c 2289
4ef69c7a 2290 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f 2291 goto err;
14571b4c 2292
4ef69c7a 2293 return true;
32aad86f
CW		 2294
2295err:
123d5c01 2296 intel_sdvo_destroy(connector);
32aad86f 2297 return false;
14571b4c
ZW		 2298}
2299
2300static bool
ea5b213a 2301intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2302{
4ef69c7a
CW		 2303 struct drm_encoder *encoder = &intel_sdvo->base.base;
2304 struct drm_connector *connector;
2305 struct intel_connector *intel_connector;
2306 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2307
615fb93f
CW		 2308 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2309 if (!intel_sdvo_connector)
2310 return false;
14571b4c 2311
615fb93f 2312 intel_connector = &intel_sdvo_connector->base;
4ef69c7a 2313 connector = &intel_connector->base;
eb1f8e4f 2314 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
4ef69c7a
CW		 2315 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2316 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2317
2318 if (device == 0) {
2319 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2320 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2321 } else if (device == 1) {
2322 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2323 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2324 }
2325
df0e9248
CW		 2326 intel_sdvo_connector_init(intel_sdvo_connector,
2327 intel_sdvo);
4ef69c7a 2328 return true;
14571b4c
ZW		 2329}
2330
2331static bool
ea5b213a 2332intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2333{
4ef69c7a
CW		 2334 struct drm_encoder *encoder = &intel_sdvo->base.base;
2335 struct drm_connector *connector;
2336 struct intel_connector *intel_connector;
2337 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2338
615fb93f
CW		 2339 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2340 if (!intel_sdvo_connector)
2341 return false;
14571b4c 2342
615fb93f
CW		 2343 intel_connector = &intel_sdvo_connector->base;
2344 connector = &intel_connector->base;
4ef69c7a
CW		 2345 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2346 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2347
2348 if (device == 0) {
2349 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2350 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2351 } else if (device == 1) {
2352 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2353 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2354 }
2355
df0e9248 2356 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
4ef69c7a 2357 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f
CW		 2358 goto err;
2359
2360 return true;
2361
2362err:
123d5c01 2363 intel_sdvo_destroy(connector);
32aad86f 2364 return false;
14571b4c
ZW		 2365}
2366
2367static bool
ea5b213a 2368intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
14571b4c 2369{
ea5b213a
CW		 2370 intel_sdvo->is_tv = false;
2371 intel_sdvo->base.needs_tv_clock = false;
2372 intel_sdvo->is_lvds = false;
fb7a46f3 2373
14571b4c 2374 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
fb7a46f3 2375
14571b4c 2376 if (flags & SDVO_OUTPUT_TMDS0)
ea5b213a 2377 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
14571b4c
ZW		 2378 return false;
2379
2380 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
ea5b213a 2381 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
14571b4c
ZW		 2382 return false;
2383
2384 /* TV has no XXX1 function block */
a1f4b7ff 2385 if (flags & SDVO_OUTPUT_SVID0)
ea5b213a 2386 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
14571b4c
ZW		 2387 return false;
2388
2389 if (flags & SDVO_OUTPUT_CVBS0)
ea5b213a 2390 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
14571b4c 2391 return false;
fb7a46f3 2392
a0b1c7a5
CW		 2393 if (flags & SDVO_OUTPUT_YPRPB0)
2394 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
2395 return false;
2396
14571b4c 2397 if (flags & SDVO_OUTPUT_RGB0)
ea5b213a 2398 if (!intel_sdvo_analog_init(intel_sdvo, 0))
14571b4c
ZW		 2399 return false;
2400
2401 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
ea5b213a 2402 if (!intel_sdvo_analog_init(intel_sdvo, 1))
14571b4c
ZW		 2403 return false;
2404
2405 if (flags & SDVO_OUTPUT_LVDS0)
ea5b213a 2406 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
14571b4c
ZW		 2407 return false;
2408
2409 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
ea5b213a 2410 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
14571b4c 2411 return false;
fb7a46f3 2412
14571b4c 2413 if ((flags & SDVO_OUTPUT_MASK) == 0) {
fb7a46f3 2414 unsigned char bytes[2];
2415
ea5b213a
CW		 2416 intel_sdvo->controlled_output = 0;
2417 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
51c8b407 2418 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
ea5b213a 2419 SDVO_NAME(intel_sdvo),
51c8b407 2420 bytes[0], bytes[1]);
14571b4c 2421 return false;
fb7a46f3 2422 }
27f8227b 2423 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
fb7a46f3 2424
14571b4c 2425 return true;
fb7a46f3 2426}
2427
d0ddfbd3
JN		 2428static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)
2429{
2430 struct drm_device *dev = intel_sdvo->base.base.dev;
2431 struct drm_connector *connector, *tmp;
2432
2433 list_for_each_entry_safe(connector, tmp,
2434 &dev->mode_config.connector_list, head) {
2435 if (intel_attached_encoder(connector) == &intel_sdvo->base)
2436 intel_sdvo_destroy(connector);
2437 }
2438}
2439
32aad86f
CW		 2440static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2441 struct intel_sdvo_connector *intel_sdvo_connector,
2442 int type)
ce6feabd 2443{
4ef69c7a 2444 struct drm_device *dev = intel_sdvo->base.base.dev;
ce6feabd
ZY		 2445 struct intel_sdvo_tv_format format;
2446 uint32_t format_map, i;
ce6feabd 2447
32aad86f
CW		 2448 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2449 return false;
ce6feabd 2450
1a3665c8 2451 BUILD_BUG_ON(sizeof(format) != 6);
32aad86f
CW		 2452 if (!intel_sdvo_get_value(intel_sdvo,
2453 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2454 &format, sizeof(format)))
2455 return false;
ce6feabd 2456
32aad86f 2457 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
ce6feabd
ZY		 2458
2459 if (format_map == 0)
32aad86f 2460 return false;
ce6feabd 2461
615fb93f 2462 intel_sdvo_connector->format_supported_num = 0;
ce6feabd 2463 for (i = 0 ; i < TV_FORMAT_NUM; i++)
40039750
CW		 2464 if (format_map & (1 << i))
2465 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
ce6feabd
ZY		 2466
2467
c5521706 2468 intel_sdvo_connector->tv_format =
32aad86f
CW		 2469 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2470 "mode", intel_sdvo_connector->format_supported_num);
c5521706 2471 if (!intel_sdvo_connector->tv_format)
fcc8d672 2472 return false;
ce6feabd 2473
615fb93f 2474 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
ce6feabd 2475 drm_property_add_enum(
c5521706 2476 intel_sdvo_connector->tv_format, i,
40039750 2477 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
ce6feabd 2478
40039750 2479 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
662595df 2480 drm_object_attach_property(&intel_sdvo_connector->base.base.base,
c5521706 2481 intel_sdvo_connector->tv_format, 0);
32aad86f 2482 return true;
ce6feabd
ZY		 2483
2484}
2485
c5521706
CW		 2486#define ENHANCEMENT(name, NAME) do { \
2487 if (enhancements.name) { \
2488 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2489 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2490 return false; \
2491 intel_sdvo_connector->max_##name = data_value[0]; \
2492 intel_sdvo_connector->cur_##name = response; \
2493 intel_sdvo_connector->name = \
d9bc3c02 2494 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
c5521706 2495 if (!intel_sdvo_connector->name) return false; \
662595df 2496 drm_object_attach_property(&connector->base, \
c5521706
CW		 2497 intel_sdvo_connector->name, \
2498 intel_sdvo_connector->cur_##name); \
2499 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2500 data_value[0], data_value[1], response); \
2501 } \
0206e353 2502} while (0)
c5521706
CW		 2503
2504static bool
2505intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2506 struct intel_sdvo_connector *intel_sdvo_connector,
2507 struct intel_sdvo_enhancements_reply enhancements)
b9219c5e 2508{
4ef69c7a 2509 struct drm_device *dev = intel_sdvo->base.base.dev;
32aad86f 2510 struct drm_connector *connector = &intel_sdvo_connector->base.base;
b9219c5e
ZY		 2511 uint16_t response, data_value[2];
2512
c5521706
CW		 2513 /* when horizontal overscan is supported, Add the left/right property */
2514 if (enhancements.overscan_h) {
2515 if (!intel_sdvo_get_value(intel_sdvo,
2516 SDVO_CMD_GET_MAX_OVERSCAN_H,
2517 &data_value, 4))
2518 return false;
32aad86f 2519
c5521706
CW		 2520 if (!intel_sdvo_get_value(intel_sdvo,
2521 SDVO_CMD_GET_OVERSCAN_H,
2522 &response, 2))
2523 return false;
fcc8d672 2524
c5521706
CW		 2525 intel_sdvo_connector->max_hscan = data_value[0];
2526 intel_sdvo_connector->left_margin = data_value[0] - response;
2527 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
2528 intel_sdvo_connector->left =
d9bc3c02 2529 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
c5521706
CW		 2530 if (!intel_sdvo_connector->left)
2531 return false;
fcc8d672 2532
662595df 2533 drm_object_attach_property(&connector->base,
c5521706
CW		 2534 intel_sdvo_connector->left,
2535 intel_sdvo_connector->left_margin);
fcc8d672 2536
c5521706 2537 intel_sdvo_connector->right =
d9bc3c02 2538 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
c5521706
CW		 2539 if (!intel_sdvo_connector->right)
2540 return false;
32aad86f 2541
662595df 2542 drm_object_attach_property(&connector->base,
c5521706
CW		 2543 intel_sdvo_connector->right,
2544 intel_sdvo_connector->right_margin);
2545 DRM_DEBUG_KMS("h_overscan: max %d, "
2546 "default %d, current %d\n",
2547 data_value[0], data_value[1], response);
2548 }
32aad86f 2549
c5521706
CW		 2550 if (enhancements.overscan_v) {
2551 if (!intel_sdvo_get_value(intel_sdvo,
2552 SDVO_CMD_GET_MAX_OVERSCAN_V,
2553 &data_value, 4))
2554 return false;
fcc8d672 2555
c5521706
CW		 2556 if (!intel_sdvo_get_value(intel_sdvo,
2557 SDVO_CMD_GET_OVERSCAN_V,
2558 &response, 2))
2559 return false;
32aad86f 2560
c5521706
CW		 2561 intel_sdvo_connector->max_vscan = data_value[0];
2562 intel_sdvo_connector->top_margin = data_value[0] - response;
2563 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
2564 intel_sdvo_connector->top =
d9bc3c02
SH		 2565 drm_property_create_range(dev, 0,
2566 "top_margin", 0, data_value[0]);
c5521706
CW		 2567 if (!intel_sdvo_connector->top)
2568 return false;
32aad86f 2569
662595df 2570 drm_object_attach_property(&connector->base,
c5521706
CW		 2571 intel_sdvo_connector->top,
2572 intel_sdvo_connector->top_margin);
fcc8d672 2573
c5521706 2574 intel_sdvo_connector->bottom =
d9bc3c02
SH		 2575 drm_property_create_range(dev, 0,
2576 "bottom_margin", 0, data_value[0]);
c5521706
CW		 2577 if (!intel_sdvo_connector->bottom)
2578 return false;
32aad86f 2579
662595df 2580 drm_object_attach_property(&connector->base,
c5521706
CW		 2581 intel_sdvo_connector->bottom,
2582 intel_sdvo_connector->bottom_margin);
2583 DRM_DEBUG_KMS("v_overscan: max %d, "
2584 "default %d, current %d\n",
2585 data_value[0], data_value[1], response);
2586 }
32aad86f 2587
c5521706
CW		 2588 ENHANCEMENT(hpos, HPOS);
2589 ENHANCEMENT(vpos, VPOS);
2590 ENHANCEMENT(saturation, SATURATION);
2591 ENHANCEMENT(contrast, CONTRAST);
2592 ENHANCEMENT(hue, HUE);
2593 ENHANCEMENT(sharpness, SHARPNESS);
2594 ENHANCEMENT(brightness, BRIGHTNESS);
2595 ENHANCEMENT(flicker_filter, FLICKER_FILTER);
2596 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2597 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
2598 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
2599 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
fcc8d672 2600
e044218a
CW		 2601 if (enhancements.dot_crawl) {
2602 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2603 return false;
2604
2605 intel_sdvo_connector->max_dot_crawl = 1;
2606 intel_sdvo_connector->cur_dot_crawl = response & 0x1;
2607 intel_sdvo_connector->dot_crawl =
d9bc3c02 2608 drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
e044218a
CW		 2609 if (!intel_sdvo_connector->dot_crawl)
2610 return false;
2611
662595df 2612 drm_object_attach_property(&connector->base,
e044218a
CW		 2613 intel_sdvo_connector->dot_crawl,
2614 intel_sdvo_connector->cur_dot_crawl);
2615 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2616 }
2617
c5521706
CW		 2618 return true;
2619}
32aad86f 2620
c5521706
CW		 2621static bool
2622intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2623 struct intel_sdvo_connector *intel_sdvo_connector,
2624 struct intel_sdvo_enhancements_reply enhancements)
2625{
4ef69c7a 2626 struct drm_device *dev = intel_sdvo->base.base.dev;
c5521706
CW		 2627 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2628 uint16_t response, data_value[2];
32aad86f 2629
c5521706 2630 ENHANCEMENT(brightness, BRIGHTNESS);
fcc8d672 2631
c5521706
CW		 2632 return true;
2633}
2634#undef ENHANCEMENT
32aad86f 2635
c5521706
CW		 2636static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2637 struct intel_sdvo_connector *intel_sdvo_connector)
2638{
2639 union {
2640 struct intel_sdvo_enhancements_reply reply;
2641 uint16_t response;
2642 } enhancements;
32aad86f 2643
1a3665c8
CW		 2644 BUILD_BUG_ON(sizeof(enhancements) != 2);
2645
cf9a2f3a
CW		 2646 enhancements.response = 0;
2647 intel_sdvo_get_value(intel_sdvo,
2648 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2649 &enhancements, sizeof(enhancements));
c5521706
CW		 2650 if (enhancements.response == 0) {
2651 DRM_DEBUG_KMS("No enhancement is supported\n");
2652 return true;
b9219c5e 2653 }
32aad86f 2654
c5521706
CW		 2655 if (IS_TV(intel_sdvo_connector))
2656 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
0206e353 2657 else if (IS_LVDS(intel_sdvo_connector))
c5521706
CW		 2658 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2659 else
2660 return true;
e957d772
CW		 2661}
2662
2663static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
2664 struct i2c_msg *msgs,
2665 int num)
2666{
2667 struct intel_sdvo *sdvo = adapter->algo_data;
fcc8d672 2668
e957d772
CW		 2669 if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
2670 return -EIO;
2671
2672 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
2673}
2674
2675static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
2676{
2677 struct intel_sdvo *sdvo = adapter->algo_data;
2678 return sdvo->i2c->algo->functionality(sdvo->i2c);
2679}
2680
2681static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
2682 .master_xfer = intel_sdvo_ddc_proxy_xfer,
2683 .functionality = intel_sdvo_ddc_proxy_func
2684};
2685
2686static bool
2687intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
2688 struct drm_device *dev)
2689{
2690 sdvo->ddc.owner = THIS_MODULE;
2691 sdvo->ddc.class = I2C_CLASS_DDC;
2692 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
2693 sdvo->ddc.dev.parent = &dev->pdev->dev;
2694 sdvo->ddc.algo_data = sdvo;
2695 sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
2696
2697 return i2c_add_adapter(&sdvo->ddc) == 0;
b9219c5e
ZY		 2698}
2699
eef4eacb 2700bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
79e53945 2701{
b01f2c3a 2702 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 2703 struct intel_encoder *intel_encoder;
ea5b213a 2704 struct intel_sdvo *intel_sdvo;
084b612e 2705 u32 hotplug_mask;
79e53945 2706 int i;
79e53945 2707
ea5b213a
CW		 2708 intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
2709 if (!intel_sdvo)
7d57382e 2710 return false;
79e53945 2711
56184e3d 2712 intel_sdvo->sdvo_reg = sdvo_reg;
eef4eacb
DV		 2713 intel_sdvo->is_sdvob = is_sdvob;
2714 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1;
56184e3d 2715 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
fbfcc4f3
JN		 2716 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev))
2717 goto err_i2c_bus;
e957d772 2718
56184e3d 2719 /* encoder type will be decided later */
ea5b213a 2720 intel_encoder = &intel_sdvo->base;
21d40d37 2721 intel_encoder->type = INTEL_OUTPUT_SDVO;
373a3cf7 2722 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
79e53945 2723
79e53945
JB		 2724 /* Read the regs to test if we can talk to the device */
2725 for (i = 0; i < 0x40; i++) {
f899fc64
CW		 2726 u8 byte;
2727
2728 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
eef4eacb
DV		 2729 DRM_DEBUG_KMS("No SDVO device found on %s\n",
2730 SDVO_NAME(intel_sdvo));
f899fc64 2731 goto err;
79e53945
JB		 2732 }
2733 }
2734
084b612e
CW		 2735 hotplug_mask = 0;
2736 if (IS_G4X(dev)) {
2737 hotplug_mask = intel_sdvo->is_sdvob ?
2738 SDVOB_HOTPLUG_INT_STATUS_G4X : SDVOC_HOTPLUG_INT_STATUS_G4X;
2739 } else if (IS_GEN4(dev)) {
2740 hotplug_mask = intel_sdvo->is_sdvob ?
2741 SDVOB_HOTPLUG_INT_STATUS_I965 : SDVOC_HOTPLUG_INT_STATUS_I965;
2742 } else {
2743 hotplug_mask = intel_sdvo->is_sdvob ?
2744 SDVOB_HOTPLUG_INT_STATUS_I915 : SDVOC_HOTPLUG_INT_STATUS_I915;
2745 }
619ac3b7 2746
4ef69c7a 2747 drm_encoder_helper_add(&intel_encoder->base, &intel_sdvo_helper_funcs);
14571b4c 2748
ce22c320
DV		 2749 intel_encoder->disable = intel_disable_sdvo;
2750 intel_encoder->enable = intel_enable_sdvo;
4ac41f47 2751 intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
ce22c320 2752
af901ca1 2753 /* In default case sdvo lvds is false */
32aad86f 2754 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
f899fc64 2755 goto err;
79e53945 2756
ea5b213a
CW		 2757 if (intel_sdvo_output_setup(intel_sdvo,
2758 intel_sdvo->caps.output_flags) != true) {
eef4eacb
DV		 2759 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
2760 SDVO_NAME(intel_sdvo));
d0ddfbd3
JN		 2761 /* Output_setup can leave behind connectors! */
2762 goto err_output;
79e53945
JB		 2763 }
2764
e506d6fd
DV		 2765 /*
2766 * Cloning SDVO with anything is often impossible, since the SDVO
2767 * encoder can request a special input timing mode. And even if that's
2768 * not the case we have evidence that cloning a plain unscaled mode with
2769 * VGA doesn't really work. Furthermore the cloning flags are way too
2770 * simplistic anyway to express such constraints, so just give up on
2771 * cloning for SDVO encoders.
2772 */
2773 intel_sdvo->base.cloneable = false;
2774
fcbc50da
JN		 2775 /* Only enable the hotplug irq if we need it, to work around noisy
2776 * hotplug lines.
2777 */
5fa7ac9c 2778 if (intel_sdvo->hotplug_active)
fcbc50da
JN		 2779 dev_priv->hotplug_supported_mask |= hotplug_mask;
2780
ea5b213a 2781 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
e2f0ba97 2782
79e53945 2783 /* Set the input timing to the screen. Assume always input 0. */
32aad86f 2784 if (!intel_sdvo_set_target_input(intel_sdvo))
d0ddfbd3 2785 goto err_output;
79e53945 2786
32aad86f
CW		 2787 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
2788 &intel_sdvo->pixel_clock_min,
2789 &intel_sdvo->pixel_clock_max))
d0ddfbd3 2790 goto err_output;
79e53945 2791
8a4c47f3 2792 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
342dc382 2793 "clock range %dMHz - %dMHz, "
2794 "input 1: %c, input 2: %c, "
2795 "output 1: %c, output 2: %c\n",
ea5b213a
CW		 2796 SDVO_NAME(intel_sdvo),
2797 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
2798 intel_sdvo->caps.device_rev_id,
2799 intel_sdvo->pixel_clock_min / 1000,
2800 intel_sdvo->pixel_clock_max / 1000,
2801 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2802 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
342dc382 2803 /* check currently supported outputs */
ea5b213a 2804 intel_sdvo->caps.output_flags &
79e53945 2805 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
ea5b213a 2806 intel_sdvo->caps.output_flags &
79e53945 2807 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
7d57382e 2808 return true;
79e53945 2809
d0ddfbd3
JN		 2810err_output:
2811 intel_sdvo_output_cleanup(intel_sdvo);
2812
f899fc64 2813err:
373a3cf7 2814 drm_encoder_cleanup(&intel_encoder->base);
e957d772 2815 i2c_del_adapter(&intel_sdvo->ddc);
fbfcc4f3
JN		 2816err_i2c_bus:
2817 intel_sdvo_unselect_i2c_bus(intel_sdvo);
ea5b213a 2818 kfree(intel_sdvo);
79e53945 2819
7d57382e 2820 return false;
79e53945 2821}
Linux 6.x block layer and io_uring tree(s)