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drm/i915: Fix kerneldocs for intel_audio.c
[linux-block.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
79e53945 30#include <linux/delay.h>
2d1a8a48 31#include <linux/export.h>
760285e7 32#include <drm/drmP.h>
c6f95f27 33#include <drm/drm_atomic_helper.h>
760285e7
DH		 34#include <drm/drm_crtc.h>
35#include <drm/drm_edid.h>
ea5b213a 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945
JB		 38#include "i915_drv.h"
39#include "intel_sdvo_regs.h"
40
14571b4c
ZW		 41#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
42#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
43#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
a0b1c7a5 44#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
14571b4c
ZW		 45
46#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
0206e353 47 SDVO_TV_MASK)
14571b4c
ZW		 48
49#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
13946743 50#define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
14571b4c 51#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
32aad86f 52#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
52220085 53#define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
14571b4c 54
79e53945 55
4d9194de 56static const char * const tv_format_names[] = {
ce6feabd
ZY		 57 "NTSC_M" , "NTSC_J" , "NTSC_443",
58 "PAL_B" , "PAL_D" , "PAL_G" ,
59 "PAL_H" , "PAL_I" , "PAL_M" ,
60 "PAL_N" , "PAL_NC" , "PAL_60" ,
61 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
62 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
63 "SECAM_60"
64};
65
53abb679 66#define TV_FORMAT_NUM ARRAY_SIZE(tv_format_names)
ce6feabd 67
ea5b213a
CW		 68struct intel_sdvo {
69 struct intel_encoder base;
70
f899fc64 71 struct i2c_adapter *i2c;
f9c10a9b 72 u8 slave_addr;
e2f0ba97 73
e957d772
CW		 74 struct i2c_adapter ddc;
75
e2f0ba97 76 /* Register for the SDVO device: SDVOB or SDVOC */
f0f59a00 77 i915_reg_t sdvo_reg;
79e53945 78
e2f0ba97
JB		 79 /* Active outputs controlled by this SDVO output */
80 uint16_t controlled_output;
79e53945 81
e2f0ba97
JB		 82 /*
83 * Capabilities of the SDVO device returned by
19d415a2 84 * intel_sdvo_get_capabilities()
e2f0ba97 85 */
79e53945 86 struct intel_sdvo_caps caps;
e2f0ba97
JB		 87
88 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 89 int pixel_clock_min, pixel_clock_max;
90
fb7a46f3 91 /*
92 * For multiple function SDVO device,
93 * this is for current attached outputs.
94 */
95 uint16_t attached_output;
96
cc68c81a
SF		 97 /*
98 * Hotplug activation bits for this device
99 */
5fa7ac9c 100 uint16_t hotplug_active;
cc68c81a 101
e2f0ba97
JB		 102 /**
103 * This is set if we're going to treat the device as TV-out.
104 *
105 * While we have these nice friendly flags for output types that ought
106 * to decide this for us, the S-Video output on our HDMI+S-Video card
107 * shows up as RGB1 (VGA).
108 */
109 bool is_tv;
110
2a5c0832 111 enum port port;
eef4eacb 112
e2f0ba97
JB		 113 /**
114 * This is set if we treat the device as HDMI, instead of DVI.
115 */
116 bool is_hdmi;
da79de97
CW		 117 bool has_hdmi_monitor;
118 bool has_hdmi_audio;
abedc077 119 bool rgb_quant_range_selectable;
12682a97 120
7086c87f 121 /**
6c9547ff
CW		 122 * This is set if we detect output of sdvo device as LVDS and
123 * have a valid fixed mode to use with the panel.
7086c87f
ML		 124 */
125 bool is_lvds;
e2f0ba97 126
12682a97 127 /**
128 * This is sdvo fixed pannel mode pointer
129 */
130 struct drm_display_mode *sdvo_lvds_fixed_mode;
131
c751ce4f 132 /* DDC bus used by this SDVO encoder */
e2f0ba97 133 uint8_t ddc_bus;
e751823d
EE		 134
135 /*
136 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd
137 */
138 uint8_t dtd_sdvo_flags;
14571b4c
ZW		 139};
140
141struct intel_sdvo_connector {
615fb93f
CW		 142 struct intel_connector base;
143
14571b4c
ZW		 144 /* Mark the type of connector */
145 uint16_t output_flag;
146
147 /* This contains all current supported TV format */
40039750 148 u8 tv_format_supported[TV_FORMAT_NUM];
14571b4c 149 int format_supported_num;
c5521706 150 struct drm_property *tv_format;
14571b4c 151
b9219c5e 152 /* add the property for the SDVO-TV */
c5521706
CW		 153 struct drm_property *left;
154 struct drm_property *right;
155 struct drm_property *top;
156 struct drm_property *bottom;
157 struct drm_property *hpos;
158 struct drm_property *vpos;
159 struct drm_property *contrast;
160 struct drm_property *saturation;
161 struct drm_property *hue;
162 struct drm_property *sharpness;
163 struct drm_property *flicker_filter;
164 struct drm_property *flicker_filter_adaptive;
165 struct drm_property *flicker_filter_2d;
166 struct drm_property *tv_chroma_filter;
167 struct drm_property *tv_luma_filter;
e044218a 168 struct drm_property *dot_crawl;
b9219c5e
ZY		 169
170 /* add the property for the SDVO-TV/LVDS */
c5521706 171 struct drm_property *brightness;
b9219c5e 172
b9219c5e 173 /* this is to get the range of margin.*/
630d30a4
ML		 174 u32 max_hscan, max_vscan;
175};
176
177struct intel_sdvo_connector_state {
178 /* base.base: tv.saturation/contrast/hue/brightness */
179 struct intel_digital_connector_state base;
180
181 struct {
182 unsigned overscan_h, overscan_v, hpos, vpos, sharpness;
183 unsigned flicker_filter, flicker_filter_2d, flicker_filter_adaptive;
184 unsigned chroma_filter, luma_filter, dot_crawl;
185 } tv;
79e53945
JB		 186};
187
8aca63aa 188static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder)
ea5b213a 189{
8aca63aa 190 return container_of(encoder, struct intel_sdvo, base);
ea5b213a
CW		 191}
192
df0e9248
CW		 193static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
194{
8aca63aa 195 return to_sdvo(intel_attached_encoder(connector));
df0e9248
CW		 196}
197
630d30a4
ML		 198static struct intel_sdvo_connector *
199to_intel_sdvo_connector(struct drm_connector *connector)
200{
201 return container_of(connector, struct intel_sdvo_connector, base.base);
202}
203
5f88a9c6
VS		 204#define to_intel_sdvo_connector_state(conn_state) \
205 container_of((conn_state), struct intel_sdvo_connector_state, base.base)
615fb93f 206
fb7a46f3 207static bool
ea5b213a 208intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
32aad86f
CW		 209static bool
210intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
211 struct intel_sdvo_connector *intel_sdvo_connector,
212 int type);
213static bool
214intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
215 struct intel_sdvo_connector *intel_sdvo_connector);
fb7a46f3 216
79e53945
JB		 217/**
218 * Writes the SDVOB or SDVOC with the given value, but always writes both
219 * SDVOB and SDVOC to work around apparent hardware issues (according to
220 * comments in the BIOS).
221 */
ea5b213a 222static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
79e53945 223{
4ef69c7a 224 struct drm_device *dev = intel_sdvo->base.base.dev;
fac5e23e 225 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945
JB		 226 u32 bval = val, cval = val;
227 int i;
228
2a5c0832 229 if (HAS_PCH_SPLIT(dev_priv)) {
ea5b213a 230 I915_WRITE(intel_sdvo->sdvo_reg, val);
abab6311 231 POSTING_READ(intel_sdvo->sdvo_reg);
e8504ee2
VS		 232 /*
233 * HW workaround, need to write this twice for issue
234 * that may result in first write getting masked.
235 */
6e266956 236 if (HAS_PCH_IBX(dev_priv)) {
e8504ee2
VS		 237 I915_WRITE(intel_sdvo->sdvo_reg, val);
238 POSTING_READ(intel_sdvo->sdvo_reg);
239 }
461ed3ca
ZY		 240 return;
241 }
242
2a5c0832 243 if (intel_sdvo->port == PORT_B)
e2debe91
PZ		 244 cval = I915_READ(GEN3_SDVOC);
245 else
246 bval = I915_READ(GEN3_SDVOB);
247
79e53945
JB		 248 /*
249 * Write the registers twice for luck. Sometimes,
250 * writing them only once doesn't appear to 'stick'.
251 * The BIOS does this too. Yay, magic
252 */
253 for (i = 0; i < 2; i++)
254 {
e2debe91 255 I915_WRITE(GEN3_SDVOB, bval);
abab6311 256 POSTING_READ(GEN3_SDVOB);
e2debe91 257 I915_WRITE(GEN3_SDVOC, cval);
abab6311 258 POSTING_READ(GEN3_SDVOC);
79e53945
JB		 259 }
260}
261
32aad86f 262static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
79e53945 263{
79e53945
JB		 264 struct i2c_msg msgs[] = {
265 {
e957d772 266 .addr = intel_sdvo->slave_addr,
79e53945
JB		 267 .flags = 0,
268 .len = 1,
e957d772 269 .buf = &addr,
79e53945
JB		 270 },
271 {
e957d772 272 .addr = intel_sdvo->slave_addr,
79e53945
JB		 273 .flags = I2C_M_RD,
274 .len = 1,
e957d772 275 .buf = ch,
79e53945
JB		 276 }
277 };
32aad86f 278 int ret;
79e53945 279
f899fc64 280 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
79e53945 281 return true;
79e53945 282
8a4c47f3 283 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 284 return false;
285}
286
79e53945
JB		 287#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
288/** Mapping of command numbers to names, for debug output */
005568be 289static const struct _sdvo_cmd_name {
e2f0ba97 290 u8 cmd;
2e88e40b 291 const char *name;
579627ea 292} __attribute__ ((packed)) sdvo_cmd_names[] = {
0206e353
AJ		 293 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
294 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
295 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
296 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
297 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
336
337 /* Add the op code for SDVO enhancements */
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
382
383 /* HDMI op code */
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 404};
405
2a5c0832 406#define SDVO_NAME(svdo) ((svdo)->port == PORT_B ? "SDVOB" : "SDVOC")
79e53945 407
ea5b213a 408static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
32aad86f 409 const void *args, int args_len)
79e53945 410{
84fcb469
DV		 411 int i, pos = 0;
412#define BUF_LEN 256
413 char buffer[BUF_LEN];
414
415#define BUF_PRINT(args...) \
416 pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args)
417
79e53945 418
84fcb469
DV		 419 for (i = 0; i < args_len; i++) {
420 BUF_PRINT("%02X ", ((u8 *)args)[i]);
421 }
422 for (; i < 8; i++) {
423 BUF_PRINT(" ");
424 }
04ad327f 425 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
79e53945 426 if (cmd == sdvo_cmd_names[i].cmd) {
84fcb469 427 BUF_PRINT("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 428 break;
429 }
430 }
84fcb469
DV		 431 if (i == ARRAY_SIZE(sdvo_cmd_names)) {
432 BUF_PRINT("(%02X)", cmd);
433 }
434 BUG_ON(pos >= BUF_LEN - 1);
435#undef BUF_PRINT
436#undef BUF_LEN
437
438 DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer);
79e53945 439}
79e53945 440
4d9194de 441static const char * const cmd_status_names[] = {
e957d772
CW		 442 "Power on",
443 "Success",
444 "Not supported",
445 "Invalid arg",
446 "Pending",
447 "Target not specified",
448 "Scaling not supported"
449};
450
a8506684
DV		 451static bool __intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
452 const void *args, int args_len,
453 bool unlocked)
79e53945 454{
3bf3f452
BW		 455 u8 *buf, status;
456 struct i2c_msg *msgs;
457 int i, ret = true;
458
a8506684 459 /* Would be simpler to allocate both in one go ? */
5c67eeb6 460 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL);
3bf3f452
BW		 461 if (!buf)
462 return false;
463
464 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
0274df3e 465 if (!msgs) {
a8506684 466 kfree(buf);
3bf3f452 467 return false;
a8506684 468 }
79e53945 469
ea5b213a 470 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
79e53945
JB		 471
472 for (i = 0; i < args_len; i++) {
e957d772
CW		 473 msgs[i].addr = intel_sdvo->slave_addr;
474 msgs[i].flags = 0;
475 msgs[i].len = 2;
476 msgs[i].buf = buf + 2 *i;
477 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
478 buf[2*i + 1] = ((u8*)args)[i];
479 }
480 msgs[i].addr = intel_sdvo->slave_addr;
481 msgs[i].flags = 0;
482 msgs[i].len = 2;
483 msgs[i].buf = buf + 2*i;
484 buf[2*i + 0] = SDVO_I2C_OPCODE;
485 buf[2*i + 1] = cmd;
486
487 /* the following two are to read the response */
488 status = SDVO_I2C_CMD_STATUS;
489 msgs[i+1].addr = intel_sdvo->slave_addr;
490 msgs[i+1].flags = 0;
491 msgs[i+1].len = 1;
492 msgs[i+1].buf = &status;
493
494 msgs[i+2].addr = intel_sdvo->slave_addr;
495 msgs[i+2].flags = I2C_M_RD;
496 msgs[i+2].len = 1;
497 msgs[i+2].buf = &status;
498
a8506684
DV		 499 if (unlocked)
500 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
501 else
502 ret = __i2c_transfer(intel_sdvo->i2c, msgs, i+3);
e957d772
CW		 503 if (ret < 0) {
504 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
3bf3f452
BW		 505 ret = false;
506 goto out;
e957d772
CW		 507 }
508 if (ret != i+3) {
509 /* failure in I2C transfer */
510 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
3bf3f452 511 ret = false;
e957d772
CW		 512 }
513
3bf3f452
BW		 514out:
515 kfree(msgs);
516 kfree(buf);
517 return ret;
79e53945
JB		 518}
519
a8506684
DV		 520static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
521 const void *args, int args_len)
522{
523 return __intel_sdvo_write_cmd(intel_sdvo, cmd, args, args_len, true);
524}
525
b5c616a7
CW		 526static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
527 void *response, int response_len)
79e53945 528{
fc37381c 529 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
b5c616a7 530 u8 status;
84fcb469
DV		 531 int i, pos = 0;
532#define BUF_LEN 256
533 char buffer[BUF_LEN];
79e53945 534
d121a5d2 535
b5c616a7
CW		 536 /*
537 * The documentation states that all commands will be
538 * processed within 15µs, and that we need only poll
539 * the status byte a maximum of 3 times in order for the
540 * command to be complete.
541 *
542 * Check 5 times in case the hardware failed to read the docs.
fc37381c
CW		 543 *
544 * Also beware that the first response by many devices is to
545 * reply PENDING and stall for time. TVs are notorious for
546 * requiring longer than specified to complete their replies.
547 * Originally (in the DDX long ago), the delay was only ever 15ms
548 * with an additional delay of 30ms applied for TVs added later after
549 * many experiments. To accommodate both sets of delays, we do a
550 * sequence of slow checks if the device is falling behind and fails
551 * to reply within 5*15µs.
b5c616a7 552 */
d121a5d2
CW		 553 if (!intel_sdvo_read_byte(intel_sdvo,
554 SDVO_I2C_CMD_STATUS,
555 &status))
556 goto log_fail;
557
1ad87e72 558 while ((status == SDVO_CMD_STATUS_PENDING ||
46a3f4a3 559 status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) {
fc37381c
CW		 560 if (retry < 10)
561 msleep(15);
562 else
563 udelay(15);
564
b5c616a7
CW		 565 if (!intel_sdvo_read_byte(intel_sdvo,
566 SDVO_I2C_CMD_STATUS,
567 &status))
d121a5d2
CW		 568 goto log_fail;
569 }
b5c616a7 570
84fcb469
DV		 571#define BUF_PRINT(args...) \
572 pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args)
573
79e53945 574 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
84fcb469 575 BUF_PRINT("(%s)", cmd_status_names[status]);
79e53945 576 else
84fcb469 577 BUF_PRINT("(??? %d)", status);
79e53945 578
b5c616a7
CW		 579 if (status != SDVO_CMD_STATUS_SUCCESS)
580 goto log_fail;
79e53945 581
b5c616a7
CW		 582 /* Read the command response */
583 for (i = 0; i < response_len; i++) {
584 if (!intel_sdvo_read_byte(intel_sdvo,
585 SDVO_I2C_RETURN_0 + i,
586 &((u8 *)response)[i]))
587 goto log_fail;
84fcb469 588 BUF_PRINT(" %02X", ((u8 *)response)[i]);
b5c616a7 589 }
84fcb469
DV		 590 BUG_ON(pos >= BUF_LEN - 1);
591#undef BUF_PRINT
592#undef BUF_LEN
593
594 DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer);
b5c616a7 595 return true;
79e53945 596
b5c616a7 597log_fail:
84fcb469 598 DRM_DEBUG_KMS("%s: R: ... failed\n", SDVO_NAME(intel_sdvo));
b5c616a7 599 return false;
79e53945
JB		 600}
601
5e7234c9 602static int intel_sdvo_get_pixel_multiplier(const struct drm_display_mode *adjusted_mode)
79e53945 603{
aad941d5 604 if (adjusted_mode->crtc_clock >= 100000)
79e53945 605 return 1;
aad941d5 606 else if (adjusted_mode->crtc_clock >= 50000)
79e53945
JB		 607 return 2;
608 else
609 return 4;
610}
611
a8506684
DV		 612static bool __intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
613 u8 ddc_bus)
79e53945 614{
d121a5d2 615 /* This must be the immediately preceding write before the i2c xfer */
a8506684
DV		 616 return __intel_sdvo_write_cmd(intel_sdvo,
617 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
618 &ddc_bus, 1, false);
79e53945
JB		 619}
620
32aad86f 621static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
79e53945 622{
d121a5d2
CW		 623 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
624 return false;
625
626 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
32aad86f 627}
79e53945 628
32aad86f
CW		 629static bool
630intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
631{
632 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
633 return false;
79e53945 634
32aad86f
CW		 635 return intel_sdvo_read_response(intel_sdvo, value, len);
636}
79e53945 637
32aad86f
CW		 638static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
639{
640 struct intel_sdvo_set_target_input_args targets = {0};
641 return intel_sdvo_set_value(intel_sdvo,
642 SDVO_CMD_SET_TARGET_INPUT,
643 &targets, sizeof(targets));
79e53945
JB		 644}
645
646/**
647 * Return whether each input is trained.
648 *
649 * This function is making an assumption about the layout of the response,
650 * which should be checked against the docs.
651 */
ea5b213a 652static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
79e53945
JB		 653{
654 struct intel_sdvo_get_trained_inputs_response response;
79e53945 655
1a3665c8 656 BUILD_BUG_ON(sizeof(response) != 1);
32aad86f
CW		 657 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
658 &response, sizeof(response)))
79e53945
JB		 659 return false;
660
661 *input_1 = response.input0_trained;
662 *input_2 = response.input1_trained;
663 return true;
664}
665
ea5b213a 666static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
79e53945
JB		 667 u16 outputs)
668{
32aad86f
CW		 669 return intel_sdvo_set_value(intel_sdvo,
670 SDVO_CMD_SET_ACTIVE_OUTPUTS,
671 &outputs, sizeof(outputs));
79e53945
JB		 672}
673
4ac41f47
DV		 674static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo,
675 u16 *outputs)
676{
677 return intel_sdvo_get_value(intel_sdvo,
678 SDVO_CMD_GET_ACTIVE_OUTPUTS,
679 outputs, sizeof(*outputs));
680}
681
ea5b213a 682static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
79e53945
JB		 683 int mode)
684{
32aad86f 685 u8 state = SDVO_ENCODER_STATE_ON;
79e53945
JB		 686
687 switch (mode) {
688 case DRM_MODE_DPMS_ON:
689 state = SDVO_ENCODER_STATE_ON;
690 break;
691 case DRM_MODE_DPMS_STANDBY:
692 state = SDVO_ENCODER_STATE_STANDBY;
693 break;
694 case DRM_MODE_DPMS_SUSPEND:
695 state = SDVO_ENCODER_STATE_SUSPEND;
696 break;
697 case DRM_MODE_DPMS_OFF:
698 state = SDVO_ENCODER_STATE_OFF;
699 break;
700 }
701
32aad86f
CW		 702 return intel_sdvo_set_value(intel_sdvo,
703 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
79e53945
JB		 704}
705
ea5b213a 706static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
79e53945
JB		 707 int *clock_min,
708 int *clock_max)
709{
710 struct intel_sdvo_pixel_clock_range clocks;
79e53945 711
1a3665c8 712 BUILD_BUG_ON(sizeof(clocks) != 4);
32aad86f
CW		 713 if (!intel_sdvo_get_value(intel_sdvo,
714 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
715 &clocks, sizeof(clocks)))
79e53945
JB		 716 return false;
717
718 /* Convert the values from units of 10 kHz to kHz. */
719 *clock_min = clocks.min * 10;
720 *clock_max = clocks.max * 10;
79e53945
JB		 721 return true;
722}
723
ea5b213a 724static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
79e53945
JB		 725 u16 outputs)
726{
32aad86f
CW		 727 return intel_sdvo_set_value(intel_sdvo,
728 SDVO_CMD_SET_TARGET_OUTPUT,
729 &outputs, sizeof(outputs));
79e53945
JB		 730}
731
ea5b213a 732static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
79e53945
JB		 733 struct intel_sdvo_dtd *dtd)
734{
32aad86f
CW		 735 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
736 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
79e53945
JB		 737}
738
045ac3b5
JB		 739static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
740 struct intel_sdvo_dtd *dtd)
741{
742 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
743 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
744}
745
ea5b213a 746static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 747 struct intel_sdvo_dtd *dtd)
748{
ea5b213a 749 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 750 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
751}
752
ea5b213a 753static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 754 struct intel_sdvo_dtd *dtd)
755{
ea5b213a 756 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 757 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
758}
759
045ac3b5
JB		 760static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo,
761 struct intel_sdvo_dtd *dtd)
762{
763 return intel_sdvo_get_timing(intel_sdvo,
764 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
765}
766
e2f0ba97 767static bool
ea5b213a 768intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 769 uint16_t clock,
770 uint16_t width,
771 uint16_t height)
772{
773 struct intel_sdvo_preferred_input_timing_args args;
e2f0ba97 774
e642c6f1 775 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 776 args.clock = clock;
777 args.width = width;
778 args.height = height;
e642c6f1 779 args.interlace = 0;
12682a97 780
ea5b213a
CW		 781 if (intel_sdvo->is_lvds &&
782 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
783 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
12682a97 784 args.scaled = 1;
785
32aad86f
CW		 786 return intel_sdvo_set_value(intel_sdvo,
787 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
788 &args, sizeof(args));
e2f0ba97
JB		 789}
790
ea5b213a 791static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 792 struct intel_sdvo_dtd *dtd)
793{
1a3665c8
CW		 794 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
795 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
32aad86f
CW		 796 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
797 &dtd->part1, sizeof(dtd->part1)) &&
798 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
799 &dtd->part2, sizeof(dtd->part2));
e2f0ba97 800}
79e53945 801
ea5b213a 802static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
79e53945 803{
32aad86f 804 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
79e53945
JB		 805}
806
e2f0ba97 807static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
32aad86f 808 const struct drm_display_mode *mode)
79e53945 809{
e2f0ba97
JB		 810 uint16_t width, height;
811 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
812 uint16_t h_sync_offset, v_sync_offset;
6651819b 813 int mode_clock;
79e53945 814
1c4a814e
DV		 815 memset(dtd, 0, sizeof(*dtd));
816
c6ebd4c0
DV		 817 width = mode->hdisplay;
818 height = mode->vdisplay;
79e53945
JB		 819
820 /* do some mode translations */
c6ebd4c0
DV		 821 h_blank_len = mode->htotal - mode->hdisplay;
822 h_sync_len = mode->hsync_end - mode->hsync_start;
79e53945 823
c6ebd4c0
DV		 824 v_blank_len = mode->vtotal - mode->vdisplay;
825 v_sync_len = mode->vsync_end - mode->vsync_start;
79e53945 826
c6ebd4c0
DV		 827 h_sync_offset = mode->hsync_start - mode->hdisplay;
828 v_sync_offset = mode->vsync_start - mode->vdisplay;
79e53945 829
6651819b 830 mode_clock = mode->clock;
6651819b
DV		 831 mode_clock /= 10;
832 dtd->part1.clock = mode_clock;
833
e2f0ba97
JB		 834 dtd->part1.h_active = width & 0xff;
835 dtd->part1.h_blank = h_blank_len & 0xff;
836 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 837 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 838 dtd->part1.v_active = height & 0xff;
839 dtd->part1.v_blank = v_blank_len & 0xff;
840 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 841 ((v_blank_len >> 8) & 0xf);
842
171a9e96 843 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 844 dtd->part2.h_sync_width = h_sync_len & 0xff;
845 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 846 (v_sync_len & 0xf);
e2f0ba97 847 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 848 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
849 ((v_sync_len & 0x30) >> 4);
850
e2f0ba97 851 dtd->part2.dtd_flags = 0x18;
59d92bfa
DV		 852 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
853 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
79e53945 854 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
59d92bfa 855 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
79e53945 856 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
59d92bfa 857 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
e2f0ba97 858
e2f0ba97 859 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
e2f0ba97
JB		 860}
861
1c4a814e 862static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode,
32aad86f 863 const struct intel_sdvo_dtd *dtd)
e2f0ba97 864{
1c4a814e
DV		 865 struct drm_display_mode mode = {};
866
867 mode.hdisplay = dtd->part1.h_active;
868 mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
869 mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off;
870 mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
871 mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width;
872 mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
873 mode.htotal = mode.hdisplay + dtd->part1.h_blank;
874 mode.htotal += (dtd->part1.h_high & 0xf) << 8;
875
876 mode.vdisplay = dtd->part1.v_active;
877 mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
878 mode.vsync_start = mode.vdisplay;
879 mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
880 mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
881 mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0;
882 mode.vsync_end = mode.vsync_start +
e2f0ba97 883 (dtd->part2.v_sync_off_width & 0xf);
1c4a814e
DV		 884 mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
885 mode.vtotal = mode.vdisplay + dtd->part1.v_blank;
886 mode.vtotal += (dtd->part1.v_high & 0xf) << 8;
e2f0ba97 887
1c4a814e 888 mode.clock = dtd->part1.clock * 10;
e2f0ba97 889
59d92bfa 890 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
1c4a814e 891 mode.flags |= DRM_MODE_FLAG_INTERLACE;
59d92bfa 892 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
1c4a814e 893 mode.flags |= DRM_MODE_FLAG_PHSYNC;
3cea210f 894 else
1c4a814e 895 mode.flags |= DRM_MODE_FLAG_NHSYNC;
59d92bfa 896 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
1c4a814e 897 mode.flags |= DRM_MODE_FLAG_PVSYNC;
3cea210f 898 else
1c4a814e
DV		 899 mode.flags |= DRM_MODE_FLAG_NVSYNC;
900
901 drm_mode_set_crtcinfo(&mode, 0);
902
903 drm_mode_copy(pmode, &mode);
e2f0ba97
JB		 904}
905
e27d8538 906static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
e2f0ba97 907{
e27d8538 908 struct intel_sdvo_encode encode;
e2f0ba97 909
1a3665c8 910 BUILD_BUG_ON(sizeof(encode) != 2);
e27d8538
CW		 911 return intel_sdvo_get_value(intel_sdvo,
912 SDVO_CMD_GET_SUPP_ENCODE,
913 &encode, sizeof(encode));
e2f0ba97
JB		 914}
915
ea5b213a 916static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
c751ce4f 917 uint8_t mode)
e2f0ba97 918{
32aad86f 919 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
e2f0ba97
JB		 920}
921
ea5b213a 922static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 923 uint8_t mode)
924{
32aad86f 925 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
e2f0ba97
JB		 926}
927
928#if 0
ea5b213a 929static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 930{
931 int i, j;
932 uint8_t set_buf_index[2];
933 uint8_t av_split;
934 uint8_t buf_size;
935 uint8_t buf[48];
936 uint8_t *pos;
937
32aad86f 938 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
e2f0ba97
JB		 939
940 for (i = 0; i <= av_split; i++) {
941 set_buf_index[0] = i; set_buf_index[1] = 0;
c751ce4f 942 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
e2f0ba97 943 set_buf_index, 2);
c751ce4f
EA		 944 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
945 intel_sdvo_read_response(encoder, &buf_size, 1);
e2f0ba97
JB		 946
947 pos = buf;
948 for (j = 0; j <= buf_size; j += 8) {
c751ce4f 949 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
e2f0ba97 950 NULL, 0);
c751ce4f 951 intel_sdvo_read_response(encoder, pos, 8);
e2f0ba97
JB		 952 pos += 8;
953 }
954 }
955}
956#endif
957
b6e0e543
DV		 958static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
959 unsigned if_index, uint8_t tx_rate,
fff63867 960 const uint8_t *data, unsigned length)
b6e0e543
DV		 961{
962 uint8_t set_buf_index[2] = { if_index, 0 };
963 uint8_t hbuf_size, tmp[8];
964 int i;
965
966 if (!intel_sdvo_set_value(intel_sdvo,
967 SDVO_CMD_SET_HBUF_INDEX,
968 set_buf_index, 2))
969 return false;
970
971 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
972 &hbuf_size, 1))
973 return false;
974
975 /* Buffer size is 0 based, hooray! */
976 hbuf_size++;
977
978 DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
979 if_index, length, hbuf_size);
980
981 for (i = 0; i < hbuf_size; i += 8) {
982 memset(tmp, 0, 8);
983 if (i < length)
984 memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
985
986 if (!intel_sdvo_set_value(intel_sdvo,
987 SDVO_CMD_SET_HBUF_DATA,
988 tmp, 8))
989 return false;
990 }
991
992 return intel_sdvo_set_value(intel_sdvo,
993 SDVO_CMD_SET_HBUF_TXRATE,
994 &tx_rate, 1);
995}
996
abedc077 997static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
5f88a9c6 998 const struct intel_crtc_state *pipe_config)
e2f0ba97 999{
15dcd350 1000 uint8_t sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
15dcd350
DL		 1001 union hdmi_infoframe frame;
1002 int ret;
1003 ssize_t len;
1004
1005 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
0c1f528c
SS		 1006 &pipe_config->base.adjusted_mode,
1007 false);
15dcd350
DL		 1008 if (ret < 0) {
1009 DRM_ERROR("couldn't fill AVI infoframe\n");
1010 return false;
1011 }
3c17fe4b 1012
abedc077 1013 if (intel_sdvo->rgb_quant_range_selectable) {
f9fe0530 1014 if (pipe_config->limited_color_range)
15dcd350
DL		 1015 frame.avi.quantization_range =
1016 HDMI_QUANTIZATION_RANGE_LIMITED;
abedc077 1017 else
15dcd350
DL		 1018 frame.avi.quantization_range =
1019 HDMI_QUANTIZATION_RANGE_FULL;
abedc077
VS		 1020 }
1021
15dcd350
DL		 1022 len = hdmi_infoframe_pack(&frame, sdvo_data, sizeof(sdvo_data));
1023 if (len < 0)
1024 return false;
81014b9d 1025
b6e0e543
DV		 1026 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
1027 SDVO_HBUF_TX_VSYNC,
1028 sdvo_data, sizeof(sdvo_data));
e2f0ba97
JB		 1029}
1030
630d30a4 1031static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo,
5f88a9c6 1032 const struct drm_connector_state *conn_state)
7026d4ac 1033{
ce6feabd 1034 struct intel_sdvo_tv_format format;
40039750 1035 uint32_t format_map;
ce6feabd 1036
630d30a4 1037 format_map = 1 << conn_state->tv.mode;
ce6feabd 1038 memset(&format, 0, sizeof(format));
32aad86f 1039 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
ce6feabd 1040
32aad86f
CW		 1041 BUILD_BUG_ON(sizeof(format) != 6);
1042 return intel_sdvo_set_value(intel_sdvo,
1043 SDVO_CMD_SET_TV_FORMAT,
1044 &format, sizeof(format));
7026d4ac
ZW		 1045}
1046
32aad86f
CW		 1047static bool
1048intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
e811f5ae 1049 const struct drm_display_mode *mode)
e2f0ba97 1050{
32aad86f 1051 struct intel_sdvo_dtd output_dtd;
79e53945 1052
32aad86f
CW		 1053 if (!intel_sdvo_set_target_output(intel_sdvo,
1054 intel_sdvo->attached_output))
1055 return false;
e2f0ba97 1056
32aad86f
CW		 1057 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1058 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1059 return false;
e2f0ba97 1060
32aad86f
CW		 1061 return true;
1062}
1063
c9a29698
DV		 1064/* Asks the sdvo controller for the preferred input mode given the output mode.
1065 * Unfortunately we have to set up the full output mode to do that. */
32aad86f 1066static bool
c9a29698 1067intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
e811f5ae 1068 const struct drm_display_mode *mode,
c9a29698 1069 struct drm_display_mode *adjusted_mode)
32aad86f 1070{
c9a29698
DV		 1071 struct intel_sdvo_dtd input_dtd;
1072
32aad86f
CW		 1073 /* Reset the input timing to the screen. Assume always input 0. */
1074 if (!intel_sdvo_set_target_input(intel_sdvo))
1075 return false;
e2f0ba97 1076
32aad86f
CW		 1077 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
1078 mode->clock / 10,
1079 mode->hdisplay,
1080 mode->vdisplay))
1081 return false;
e2f0ba97 1082
32aad86f 1083 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
c9a29698 1084 &input_dtd))
32aad86f 1085 return false;
e2f0ba97 1086
c9a29698 1087 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
e751823d 1088 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags;
79e53945 1089
32aad86f
CW		 1090 return true;
1091}
12682a97 1092
5cec258b 1093static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config)
70484559 1094{
3c52f4eb 1095 unsigned dotclock = pipe_config->port_clock;
70484559
DV		 1096 struct dpll *clock = &pipe_config->dpll;
1097
1098 /* SDVO TV has fixed PLL values depend on its clock range,
1099 this mirrors vbios setting. */
1100 if (dotclock >= 100000 && dotclock < 140500) {
1101 clock->p1 = 2;
1102 clock->p2 = 10;
1103 clock->n = 3;
1104 clock->m1 = 16;
1105 clock->m2 = 8;
1106 } else if (dotclock >= 140500 && dotclock <= 200000) {
1107 clock->p1 = 1;
1108 clock->p2 = 10;
1109 clock->n = 6;
1110 clock->m1 = 12;
1111 clock->m2 = 8;
1112 } else {
1113 WARN(1, "SDVO TV clock out of range: %i\n", dotclock);
1114 }
1115
1116 pipe_config->clock_set = true;
1117}
1118
6cc5f341 1119static bool intel_sdvo_compute_config(struct intel_encoder *encoder,
0a478c27
ML		 1120 struct intel_crtc_state *pipe_config,
1121 struct drm_connector_state *conn_state)
32aad86f 1122{
8aca63aa 1123 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
630d30a4
ML		 1124 struct intel_sdvo_connector_state *intel_sdvo_state =
1125 to_intel_sdvo_connector_state(conn_state);
2d112de7
ACO		 1126 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1127 struct drm_display_mode *mode = &pipe_config->base.mode;
12682a97 1128
5d2d38dd
DV		 1129 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
1130 pipe_config->pipe_bpp = 8*3;
1131
6e266956 1132 if (HAS_PCH_SPLIT(to_i915(encoder->base.dev)))
5bfe2ac0
DV		 1133 pipe_config->has_pch_encoder = true;
1134
32aad86f
CW		 1135 /* We need to construct preferred input timings based on our
1136 * output timings. To do that, we have to set the output
1137 * timings, even though this isn't really the right place in
1138 * the sequence to do it. Oh well.
1139 */
1140 if (intel_sdvo->is_tv) {
1141 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
1142 return false;
12682a97 1143
c9a29698
DV		 1144 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1145 mode,
1146 adjusted_mode);
09ede541 1147 pipe_config->sdvo_tv_clock = true;
ea5b213a 1148 } else if (intel_sdvo->is_lvds) {
32aad86f 1149 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
6c9547ff 1150 intel_sdvo->sdvo_lvds_fixed_mode))
e2f0ba97 1151 return false;
12682a97 1152
c9a29698
DV		 1153 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1154 mode,
1155 adjusted_mode);
e2f0ba97 1156 }
32aad86f
CW		 1157
1158 /* Make the CRTC code factor in the SDVO pixel multiplier. The
6c9547ff 1159 * SDVO device will factor out the multiplier during mode_set.
32aad86f 1160 */
6cc5f341
DV		 1161 pipe_config->pixel_multiplier =
1162 intel_sdvo_get_pixel_multiplier(adjusted_mode);
32aad86f 1163
630d30a4 1164 if (intel_sdvo_state->base.force_audio != HDMI_AUDIO_OFF_DVI)
b32962f8
ML		 1165 pipe_config->has_hdmi_sink = intel_sdvo->has_hdmi_monitor;
1166
630d30a4
ML		 1167 if (intel_sdvo_state->base.force_audio == HDMI_AUDIO_ON ||
1168 (intel_sdvo_state->base.force_audio == HDMI_AUDIO_AUTO && intel_sdvo->has_hdmi_audio))
b32962f8 1169 pipe_config->has_audio = true;
9f04003e 1170
630d30a4 1171 if (intel_sdvo_state->base.broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
55bc60db 1172 /* See CEA-861-E - 5.1 Default Encoding Parameters */
4f3a8bc7
PZ		 1173 /* FIXME: This bit is only valid when using TMDS encoding and 8
1174 * bit per color mode. */
9f04003e 1175 if (pipe_config->has_hdmi_sink &&
18316c8c 1176 drm_match_cea_mode(adjusted_mode) > 1)
69f5acc8
DV		 1177 pipe_config->limited_color_range = true;
1178 } else {
9f04003e 1179 if (pipe_config->has_hdmi_sink &&
630d30a4 1180 intel_sdvo_state->base.broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED)
69f5acc8 1181 pipe_config->limited_color_range = true;
55bc60db
VS		 1182 }
1183
70484559
DV		 1184 /* Clock computation needs to happen after pixel multiplier. */
1185 if (intel_sdvo->is_tv)
1186 i9xx_adjust_sdvo_tv_clock(pipe_config);
1187
7949dd47
VS		 1188 /* Set user selected PAR to incoming mode's member */
1189 if (intel_sdvo->is_hdmi)
0e9f25d0 1190 adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio;
7949dd47 1191
e2f0ba97
JB		 1192 return true;
1193}
1194
630d30a4
ML		 1195#define UPDATE_PROPERTY(input, NAME) \
1196 do { \
1197 val = input; \
1198 intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_##NAME, &val, sizeof(val)); \
1199 } while (0)
1200
1201static void intel_sdvo_update_props(struct intel_sdvo *intel_sdvo,
5f88a9c6 1202 const struct intel_sdvo_connector_state *sdvo_state)
630d30a4 1203{
5f88a9c6 1204 const struct drm_connector_state *conn_state = &sdvo_state->base.base;
630d30a4
ML		 1205 struct intel_sdvo_connector *intel_sdvo_conn =
1206 to_intel_sdvo_connector(conn_state->connector);
1207 uint16_t val;
1208
1209 if (intel_sdvo_conn->left)
1210 UPDATE_PROPERTY(sdvo_state->tv.overscan_h, OVERSCAN_H);
1211
1212 if (intel_sdvo_conn->top)
1213 UPDATE_PROPERTY(sdvo_state->tv.overscan_v, OVERSCAN_V);
1214
1215 if (intel_sdvo_conn->hpos)
1216 UPDATE_PROPERTY(sdvo_state->tv.hpos, HPOS);
1217
1218 if (intel_sdvo_conn->vpos)
1219 UPDATE_PROPERTY(sdvo_state->tv.vpos, VPOS);
1220
1221 if (intel_sdvo_conn->saturation)
1222 UPDATE_PROPERTY(conn_state->tv.saturation, SATURATION);
1223
1224 if (intel_sdvo_conn->contrast)
1225 UPDATE_PROPERTY(conn_state->tv.contrast, CONTRAST);
1226
1227 if (intel_sdvo_conn->hue)
1228 UPDATE_PROPERTY(conn_state->tv.hue, HUE);
1229
1230 if (intel_sdvo_conn->brightness)
1231 UPDATE_PROPERTY(conn_state->tv.brightness, BRIGHTNESS);
1232
1233 if (intel_sdvo_conn->sharpness)
1234 UPDATE_PROPERTY(sdvo_state->tv.sharpness, SHARPNESS);
1235
1236 if (intel_sdvo_conn->flicker_filter)
1237 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter, FLICKER_FILTER);
1238
1239 if (intel_sdvo_conn->flicker_filter_2d)
1240 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_2d, FLICKER_FILTER_2D);
1241
1242 if (intel_sdvo_conn->flicker_filter_adaptive)
1243 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
1244
1245 if (intel_sdvo_conn->tv_chroma_filter)
1246 UPDATE_PROPERTY(sdvo_state->tv.chroma_filter, TV_CHROMA_FILTER);
1247
1248 if (intel_sdvo_conn->tv_luma_filter)
1249 UPDATE_PROPERTY(sdvo_state->tv.luma_filter, TV_LUMA_FILTER);
1250
1251 if (intel_sdvo_conn->dot_crawl)
1252 UPDATE_PROPERTY(sdvo_state->tv.dot_crawl, DOT_CRAWL);
1253
1254#undef UPDATE_PROPERTY
1255}
1256
fd6bbda9 1257static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
5f88a9c6
VS		 1258 const struct intel_crtc_state *crtc_state,
1259 const struct drm_connector_state *conn_state)
e2f0ba97 1260{
66478475 1261 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
f9fe0530
ML		 1262 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1263 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
5f88a9c6
VS		 1264 const struct intel_sdvo_connector_state *sdvo_state =
1265 to_intel_sdvo_connector_state(conn_state);
1266 const struct drm_display_mode *mode = &crtc_state->base.mode;
8aca63aa 1267 struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder);
6c9547ff 1268 u32 sdvox;
e2f0ba97 1269 struct intel_sdvo_in_out_map in_out;
6651819b 1270 struct intel_sdvo_dtd input_dtd, output_dtd;
6c9547ff 1271 int rate;
e2f0ba97 1272
630d30a4
ML		 1273 intel_sdvo_update_props(intel_sdvo, sdvo_state);
1274
e2f0ba97
JB		 1275 /* First, set the input mapping for the first input to our controlled
1276 * output. This is only correct if we're a single-input device, in
1277 * which case the first input is the output from the appropriate SDVO
1278 * channel on the motherboard. In a two-input device, the first input
1279 * will be SDVOB and the second SDVOC.
1280 */
ea5b213a 1281 in_out.in0 = intel_sdvo->attached_output;
e2f0ba97
JB		 1282 in_out.in1 = 0;
1283
c74696b9
PR		 1284 intel_sdvo_set_value(intel_sdvo,
1285 SDVO_CMD_SET_IN_OUT_MAP,
1286 &in_out, sizeof(in_out));
e2f0ba97 1287
6c9547ff
CW		 1288 /* Set the output timings to the screen */
1289 if (!intel_sdvo_set_target_output(intel_sdvo,
1290 intel_sdvo->attached_output))
1291 return;
e2f0ba97 1292
6651819b
DV		 1293 /* lvds has a special fixed output timing. */
1294 if (intel_sdvo->is_lvds)
1295 intel_sdvo_get_dtd_from_mode(&output_dtd,
1296 intel_sdvo->sdvo_lvds_fixed_mode);
1297 else
1298 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
c8d4bb54
DV		 1299 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1300 DRM_INFO("Setting output timings on %s failed\n",
1301 SDVO_NAME(intel_sdvo));
79e53945
JB		 1302
1303 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 1304 if (!intel_sdvo_set_target_input(intel_sdvo))
1305 return;
79e53945 1306
f9fe0530 1307 if (crtc_state->has_hdmi_sink) {
97aaf910
CW		 1308 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1309 intel_sdvo_set_colorimetry(intel_sdvo,
1310 SDVO_COLORIMETRY_RGB256);
f9fe0530 1311 intel_sdvo_set_avi_infoframe(intel_sdvo, crtc_state);
97aaf910
CW		 1312 } else
1313 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
7026d4ac 1314
6c9547ff 1315 if (intel_sdvo->is_tv &&
630d30a4 1316 !intel_sdvo_set_tv_format(intel_sdvo, conn_state))
6c9547ff 1317 return;
e2f0ba97 1318
6651819b 1319 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
eeb47937 1320
e751823d
EE		 1321 if (intel_sdvo->is_tv || intel_sdvo->is_lvds)
1322 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
c8d4bb54
DV		 1323 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
1324 DRM_INFO("Setting input timings on %s failed\n",
1325 SDVO_NAME(intel_sdvo));
79e53945 1326
f9fe0530 1327 switch (crtc_state->pixel_multiplier) {
6c9547ff 1328 default:
fd0753cf 1329 WARN(1, "unknown pixel multiplier specified\n");
32aad86f
CW		 1330 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1331 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1332 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
79e53945 1333 }
32aad86f
CW		 1334 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1335 return;
79e53945
JB		 1336
1337 /* Set the SDVO control regs. */
66478475 1338 if (INTEL_GEN(dev_priv) >= 4) {
ba68e086
PZ		 1339 /* The real mode polarity is set by the SDVO commands, using
1340 * struct intel_sdvo_dtd. */
1341 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
6e266956 1342 if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
69f5acc8 1343 sdvox |= HDMI_COLOR_RANGE_16_235;
66478475 1344 if (INTEL_GEN(dev_priv) < 5)
6714afb1 1345 sdvox |= SDVO_BORDER_ENABLE;
e2f0ba97 1346 } else {
6c9547ff 1347 sdvox = I915_READ(intel_sdvo->sdvo_reg);
2a5c0832 1348 if (intel_sdvo->port == PORT_B)
e2f0ba97 1349 sdvox &= SDVOB_PRESERVE_MASK;
2a5c0832 1350 else
e2f0ba97 1351 sdvox &= SDVOC_PRESERVE_MASK;
e2f0ba97
JB		 1352 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1353 }
3573c410 1354
b9eb89b2 1355 if (HAS_PCH_CPT(dev_priv))
eeb47937 1356 sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe);
3573c410 1357 else
eeb47937 1358 sdvox |= SDVO_PIPE_SEL(crtc->pipe);
3573c410 1359
de44e256
DV		 1360 if (crtc_state->has_audio) {
1361 WARN_ON_ONCE(INTEL_GEN(dev_priv) < 4);
6c9547ff 1362 sdvox |= SDVO_AUDIO_ENABLE;
de44e256 1363 }
79e53945 1364
66478475 1365 if (INTEL_GEN(dev_priv) >= 4) {
e2f0ba97 1366 /* done in crtc_mode_set as the dpll_md reg must be written early */
50a0bc90 1367 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
73f67aa8 1368 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
e2f0ba97 1369 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945 1370 } else {
f9fe0530 1371 sdvox |= (crtc_state->pixel_multiplier - 1)
6cc5f341 1372 << SDVO_PORT_MULTIPLY_SHIFT;
79e53945
JB		 1373 }
1374
6714afb1 1375 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
66478475 1376 INTEL_GEN(dev_priv) < 5)
12682a97 1377 sdvox |= SDVO_STALL_SELECT;
ea5b213a 1378 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
79e53945
JB		 1379}
1380
4ac41f47 1381static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
79e53945 1382{
4ac41f47
DV		 1383 struct intel_sdvo_connector *intel_sdvo_connector =
1384 to_intel_sdvo_connector(&connector->base);
1385 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base);
2f28c50b 1386 u16 active_outputs = 0;
4ac41f47
DV		 1387
1388 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1389
1390 if (active_outputs & intel_sdvo_connector->output_flag)
1391 return true;
1392 else
1393 return false;
1394}
1395
1396static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
1397 enum pipe *pipe)
1398{
1399 struct drm_device *dev = encoder->base.dev;
fac5e23e 1400 struct drm_i915_private *dev_priv = to_i915(dev);
8aca63aa 1401 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
2f28c50b 1402 u16 active_outputs = 0;
4ac41f47
DV		 1403 u32 tmp;
1404
1405 tmp = I915_READ(intel_sdvo->sdvo_reg);
7a7d1fb7 1406 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
4ac41f47 1407
7a7d1fb7 1408 if (!(tmp & SDVO_ENABLE) && (active_outputs == 0))
4ac41f47
DV		 1409 return false;
1410
6e266956 1411 if (HAS_PCH_CPT(dev_priv))
4ac41f47
DV		 1412 *pipe = PORT_TO_PIPE_CPT(tmp);
1413 else
1414 *pipe = PORT_TO_PIPE(tmp);
1415
1416 return true;
1417}
1418
045ac3b5 1419static void intel_sdvo_get_config(struct intel_encoder *encoder,
5cec258b 1420 struct intel_crtc_state *pipe_config)
045ac3b5 1421{
6c49f241 1422 struct drm_device *dev = encoder->base.dev;
fac5e23e 1423 struct drm_i915_private *dev_priv = to_i915(dev);
8aca63aa 1424 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
045ac3b5 1425 struct intel_sdvo_dtd dtd;
6c49f241 1426 int encoder_pixel_multiplier = 0;
18442d08 1427 int dotclock;
6c49f241
DV		 1428 u32 flags = 0, sdvox;
1429 u8 val;
045ac3b5
JB		 1430 bool ret;
1431
e1214b95
VS		 1432 pipe_config->output_types |= BIT(INTEL_OUTPUT_SDVO);
1433
b5a9fa09
DV		 1434 sdvox = I915_READ(intel_sdvo->sdvo_reg);
1435
045ac3b5
JB		 1436 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd);
1437 if (!ret) {
bb760063
DV		 1438 /* Some sdvo encoders are not spec compliant and don't
1439 * implement the mandatory get_timings function. */
045ac3b5 1440 DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n");
bb760063
DV		 1441 pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS;
1442 } else {
1443 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
1444 flags |= DRM_MODE_FLAG_PHSYNC;
1445 else
1446 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1447
bb760063
DV		 1448 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
1449 flags |= DRM_MODE_FLAG_PVSYNC;
1450 else
1451 flags |= DRM_MODE_FLAG_NVSYNC;
045ac3b5
JB		 1452 }
1453
2d112de7 1454 pipe_config->base.adjusted_mode.flags |= flags;
045ac3b5 1455
fdafa9e2
DV		 1456 /*
1457 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in
1458 * the sdvo port register, on all other platforms it is part of the dpll
1459 * state. Since the general pipe state readout happens before the
1460 * encoder->get_config we so already have a valid pixel multplier on all
1461 * other platfroms.
1462 */
50a0bc90 1463 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
6c49f241
DV		 1464 pipe_config->pixel_multiplier =
1465 ((sdvox & SDVO_PORT_MULTIPLY_MASK)
1466 >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
1467 }
045ac3b5 1468
2b85886a 1469 dotclock = pipe_config->port_clock;
e3b247da 1470
2b85886a
VS		 1471 if (pipe_config->pixel_multiplier)
1472 dotclock /= pipe_config->pixel_multiplier;
18442d08 1473
2d112de7 1474 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
18442d08 1475
6c49f241 1476 /* Cross check the port pixel multiplier with the sdvo encoder state. */
53b91408
DL		 1477 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT,
1478 &val, 1)) {
1479 switch (val) {
1480 case SDVO_CLOCK_RATE_MULT_1X:
1481 encoder_pixel_multiplier = 1;
1482 break;
1483 case SDVO_CLOCK_RATE_MULT_2X:
1484 encoder_pixel_multiplier = 2;
1485 break;
1486 case SDVO_CLOCK_RATE_MULT_4X:
1487 encoder_pixel_multiplier = 4;
1488 break;
1489 }
6c49f241 1490 }
fdafa9e2 1491
b5a9fa09
DV		 1492 if (sdvox & HDMI_COLOR_RANGE_16_235)
1493 pipe_config->limited_color_range = true;
1494
de44e256
DV		 1495 if (sdvox & SDVO_AUDIO_ENABLE)
1496 pipe_config->has_audio = true;
1497
9f04003e
DV		 1498 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE,
1499 &val, 1)) {
1500 if (val == SDVO_ENCODE_HDMI)
1501 pipe_config->has_hdmi_sink = true;
1502 }
1503
6c49f241
DV		 1504 WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier,
1505 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
1506 pipe_config->pixel_multiplier, encoder_pixel_multiplier);
045ac3b5
JB		 1507}
1508
fd6bbda9 1509static void intel_disable_sdvo(struct intel_encoder *encoder,
5f88a9c6
VS		 1510 const struct intel_crtc_state *old_crtc_state,
1511 const struct drm_connector_state *conn_state)
ce22c320 1512{
fac5e23e 1513 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
8aca63aa 1514 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
463320ae 1515 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
ce22c320
DV		 1516 u32 temp;
1517
1518 intel_sdvo_set_active_outputs(intel_sdvo, 0);
1519 if (0)
1520 intel_sdvo_set_encoder_power_state(intel_sdvo,
1521 DRM_MODE_DPMS_OFF);
1522
1523 temp = I915_READ(intel_sdvo->sdvo_reg);
776ca7cf 1524
1612c8bd
VS		 1525 temp &= ~SDVO_ENABLE;
1526 intel_sdvo_write_sdvox(intel_sdvo, temp);
1527
1528 /*
1529 * HW workaround for IBX, we need to move the port
1530 * to transcoder A after disabling it to allow the
1531 * matching DP port to be enabled on transcoder A.
1532 */
1533 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
0c241d5b
VS		 1534 /*
1535 * We get CPU/PCH FIFO underruns on the other pipe when
1536 * doing the workaround. Sweep them under the rug.
1537 */
1538 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1539 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1540
1612c8bd
VS		 1541 temp &= ~SDVO_PIPE_B_SELECT;
1542 temp |= SDVO_ENABLE;
1543 intel_sdvo_write_sdvox(intel_sdvo, temp);
1544
1545 temp &= ~SDVO_ENABLE;
1546 intel_sdvo_write_sdvox(intel_sdvo, temp);
0c241d5b 1547
0f0f74bc 1548 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
0c241d5b
VS		 1549 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1550 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
ce22c320
DV		 1551 }
1552}
1553
fd6bbda9 1554static void pch_disable_sdvo(struct intel_encoder *encoder,
5f88a9c6
VS		 1555 const struct intel_crtc_state *old_crtc_state,
1556 const struct drm_connector_state *old_conn_state)
3c65d1d1
VS		 1557{
1558}
1559
fd6bbda9 1560static void pch_post_disable_sdvo(struct intel_encoder *encoder,
5f88a9c6
VS		 1561 const struct intel_crtc_state *old_crtc_state,
1562 const struct drm_connector_state *old_conn_state)
3c65d1d1 1563{
fd6bbda9 1564 intel_disable_sdvo(encoder, old_crtc_state, old_conn_state);
3c65d1d1
VS		 1565}
1566
fd6bbda9 1567static void intel_enable_sdvo(struct intel_encoder *encoder,
5f88a9c6
VS		 1568 const struct intel_crtc_state *pipe_config,
1569 const struct drm_connector_state *conn_state)
ce22c320
DV		 1570{
1571 struct drm_device *dev = encoder->base.dev;
fac5e23e 1572 struct drm_i915_private *dev_priv = to_i915(dev);
8aca63aa 1573 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
463320ae 1574 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
79e53945 1575 u32 temp;
ce22c320
DV		 1576 bool input1, input2;
1577 int i;
d0a7b6de 1578 bool success;
ce22c320
DV		 1579
1580 temp = I915_READ(intel_sdvo->sdvo_reg);
3c65d1d1
VS		 1581 temp |= SDVO_ENABLE;
1582 intel_sdvo_write_sdvox(intel_sdvo, temp);
776ca7cf 1583
ce22c320 1584 for (i = 0; i < 2; i++)
0f0f74bc 1585 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
ce22c320 1586
d0a7b6de 1587 success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
ce22c320
DV		 1588 /* Warn if the device reported failure to sync.
1589 * A lot of SDVO devices fail to notify of sync, but it's
1590 * a given it the status is a success, we succeeded.
1591 */
d0a7b6de 1592 if (success && !input1) {
ce22c320
DV		 1593 DRM_DEBUG_KMS("First %s output reported failure to "
1594 "sync\n", SDVO_NAME(intel_sdvo));
1595 }
1596
1597 if (0)
1598 intel_sdvo_set_encoder_power_state(intel_sdvo,
1599 DRM_MODE_DPMS_ON);
1600 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
1601}
1602
c19de8eb
DL		 1603static enum drm_mode_status
1604intel_sdvo_mode_valid(struct drm_connector *connector,
1605 struct drm_display_mode *mode)
79e53945 1606{
df0e9248 1607 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
24b23882 1608 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
79e53945
JB		 1609
1610 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1611 return MODE_NO_DBLESCAN;
1612
ea5b213a 1613 if (intel_sdvo->pixel_clock_min > mode->clock)
79e53945
JB		 1614 return MODE_CLOCK_LOW;
1615
ea5b213a 1616 if (intel_sdvo->pixel_clock_max < mode->clock)
79e53945
JB		 1617 return MODE_CLOCK_HIGH;
1618
24b23882
MK		 1619 if (mode->clock > max_dotclk)
1620 return MODE_CLOCK_HIGH;
1621
8545423a 1622 if (intel_sdvo->is_lvds) {
ea5b213a 1623 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
12682a97 1624 return MODE_PANEL;
1625
ea5b213a 1626 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
12682a97 1627 return MODE_PANEL;
1628 }
1629
79e53945
JB		 1630 return MODE_OK;
1631}
1632
ea5b213a 1633static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
79e53945 1634{
1a3665c8 1635 BUILD_BUG_ON(sizeof(*caps) != 8);
e957d772
CW		 1636 if (!intel_sdvo_get_value(intel_sdvo,
1637 SDVO_CMD_GET_DEVICE_CAPS,
1638 caps, sizeof(*caps)))
1639 return false;
1640
1641 DRM_DEBUG_KMS("SDVO capabilities:\n"
1642 " vendor_id: %d\n"
1643 " device_id: %d\n"
1644 " device_rev_id: %d\n"
1645 " sdvo_version_major: %d\n"
1646 " sdvo_version_minor: %d\n"
1647 " sdvo_inputs_mask: %d\n"
1648 " smooth_scaling: %d\n"
1649 " sharp_scaling: %d\n"
1650 " up_scaling: %d\n"
1651 " down_scaling: %d\n"
1652 " stall_support: %d\n"
1653 " output_flags: %d\n",
1654 caps->vendor_id,
1655 caps->device_id,
1656 caps->device_rev_id,
1657 caps->sdvo_version_major,
1658 caps->sdvo_version_minor,
1659 caps->sdvo_inputs_mask,
1660 caps->smooth_scaling,
1661 caps->sharp_scaling,
1662 caps->up_scaling,
1663 caps->down_scaling,
1664 caps->stall_support,
1665 caps->output_flags);
1666
1667 return true;
79e53945
JB		 1668}
1669
5fa7ac9c 1670static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
79e53945 1671{
50a0bc90 1672 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
5fa7ac9c 1673 uint16_t hotplug;
79e53945 1674
50a0bc90 1675 if (!I915_HAS_HOTPLUG(dev_priv))
1d83d957
VS		 1676 return 0;
1677
768b107e
DV		 1678 /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
1679 * on the line. */
50a0bc90 1680 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
5fa7ac9c 1681 return 0;
768b107e 1682
5fa7ac9c
JN		 1683 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1684 &hotplug, sizeof(hotplug)))
1685 return 0;
768b107e 1686
5fa7ac9c 1687 return hotplug;
79e53945
JB		 1688}
1689
cc68c81a 1690static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
79e53945 1691{
8aca63aa 1692 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
79e53945 1693
5fa7ac9c
JN		 1694 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG,
1695 &intel_sdvo->hotplug_active, 2);
79e53945
JB		 1696}
1697
fb7a46f3 1698static bool
ea5b213a 1699intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
fb7a46f3 1700{
bc65212c 1701 /* Is there more than one type of output? */
2294488d 1702 return hweight16(intel_sdvo->caps.output_flags) > 1;
fb7a46f3 1703}
1704
f899fc64 1705static struct edid *
e957d772 1706intel_sdvo_get_edid(struct drm_connector *connector)
f899fc64 1707{
e957d772
CW		 1708 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1709 return drm_get_edid(connector, &sdvo->ddc);
f899fc64
CW		 1710}
1711
ff482d83
CW		 1712/* Mac mini hack -- use the same DDC as the analog connector */
1713static struct edid *
1714intel_sdvo_get_analog_edid(struct drm_connector *connector)
1715{
fac5e23e 1716 struct drm_i915_private *dev_priv = to_i915(connector->dev);
ff482d83 1717
0c1dab89 1718 return drm_get_edid(connector,
3bd7d909 1719 intel_gmbus_get_adapter(dev_priv,
41aa3448 1720 dev_priv->vbt.crt_ddc_pin));
ff482d83
CW		 1721}
1722
c43b5634 1723static enum drm_connector_status
8bf38485 1724intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
9dff6af8 1725{
df0e9248 1726 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
9d1a903d
CW		 1727 enum drm_connector_status status;
1728 struct edid *edid;
9dff6af8 1729
e957d772 1730 edid = intel_sdvo_get_edid(connector);
57cdaf90 1731
ea5b213a 1732 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
e957d772 1733 u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
9d1a903d 1734
7c3f0a27
ZY		 1735 /*
1736 * Don't use the 1 as the argument of DDC bus switch to get
1737 * the EDID. It is used for SDVO SPD ROM.
1738 */
9d1a903d 1739 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
e957d772
CW		 1740 intel_sdvo->ddc_bus = ddc;
1741 edid = intel_sdvo_get_edid(connector);
1742 if (edid)
7c3f0a27 1743 break;
7c3f0a27 1744 }
e957d772
CW		 1745 /*
1746 * If we found the EDID on the other bus,
1747 * assume that is the correct DDC bus.
1748 */
1749 if (edid == NULL)
1750 intel_sdvo->ddc_bus = saved_ddc;
7c3f0a27 1751 }
9d1a903d
CW		 1752
1753 /*
1754 * When there is no edid and no monitor is connected with VGA
1755 * port, try to use the CRT ddc to read the EDID for DVI-connector.
57cdaf90 1756 */
ff482d83
CW		 1757 if (edid == NULL)
1758 edid = intel_sdvo_get_analog_edid(connector);
149c36a3 1759
2f551c84 1760 status = connector_status_unknown;
9dff6af8 1761 if (edid != NULL) {
149c36a3 1762 /* DDC bus is shared, match EDID to connector type */
9d1a903d
CW		 1763 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1764 status = connector_status_connected;
da79de97
CW		 1765 if (intel_sdvo->is_hdmi) {
1766 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
1767 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
abedc077
VS		 1768 intel_sdvo->rgb_quant_range_selectable =
1769 drm_rgb_quant_range_selectable(edid);
da79de97 1770 }
13946743
CW		 1771 } else
1772 status = connector_status_disconnected;
9d1a903d
CW		 1773 kfree(edid);
1774 }
7f36e7ed 1775
2b8d33f7 1776 return status;
9dff6af8
ML		 1777}
1778
52220085
CW		 1779static bool
1780intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
1781 struct edid *edid)
1782{
1783 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1784 bool connector_is_digital = !!IS_DIGITAL(sdvo);
1785
1786 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
1787 connector_is_digital, monitor_is_digital);
1788 return connector_is_digital == monitor_is_digital;
1789}
1790
7b334fcb 1791static enum drm_connector_status
930a9e28 1792intel_sdvo_detect(struct drm_connector *connector, bool force)
79e53945 1793{
fb7a46f3 1794 uint16_t response;
df0e9248 1795 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1796 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
14571b4c 1797 enum drm_connector_status ret;
79e53945 1798
164c8598 1799 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 1800 connector->base.id, connector->name);
164c8598 1801
fc37381c
CW		 1802 if (!intel_sdvo_get_value(intel_sdvo,
1803 SDVO_CMD_GET_ATTACHED_DISPLAYS,
1804 &response, 2))
32aad86f 1805 return connector_status_unknown;
79e53945 1806
e957d772
CW		 1807 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
1808 response & 0xff, response >> 8,
1809 intel_sdvo_connector->output_flag);
e2f0ba97 1810
fb7a46f3 1811 if (response == 0)
79e53945 1812 return connector_status_disconnected;
fb7a46f3 1813
ea5b213a 1814 intel_sdvo->attached_output = response;
14571b4c 1815
97aaf910
CW		 1816 intel_sdvo->has_hdmi_monitor = false;
1817 intel_sdvo->has_hdmi_audio = false;
abedc077 1818 intel_sdvo->rgb_quant_range_selectable = false;
97aaf910 1819
615fb93f 1820 if ((intel_sdvo_connector->output_flag & response) == 0)
14571b4c 1821 ret = connector_status_disconnected;
13946743 1822 else if (IS_TMDS(intel_sdvo_connector))
8bf38485 1823 ret = intel_sdvo_tmds_sink_detect(connector);
13946743
CW		 1824 else {
1825 struct edid *edid;
1826
1827 /* if we have an edid check it matches the connection */
1828 edid = intel_sdvo_get_edid(connector);
1829 if (edid == NULL)
1830 edid = intel_sdvo_get_analog_edid(connector);
1831 if (edid != NULL) {
52220085
CW		 1832 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
1833 edid))
13946743 1834 ret = connector_status_connected;
52220085
CW		 1835 else
1836 ret = connector_status_disconnected;
1837
13946743
CW		 1838 kfree(edid);
1839 } else
1840 ret = connector_status_connected;
1841 }
14571b4c
ZW		 1842
1843 /* May update encoder flag for like clock for SDVO TV, etc.*/
1844 if (ret == connector_status_connected) {
ea5b213a
CW		 1845 intel_sdvo->is_tv = false;
1846 intel_sdvo->is_lvds = false;
14571b4c 1847
09ede541 1848 if (response & SDVO_TV_MASK)
ea5b213a 1849 intel_sdvo->is_tv = true;
14571b4c 1850 if (response & SDVO_LVDS_MASK)
8545423a 1851 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
fb7a46f3 1852 }
14571b4c
ZW		 1853
1854 return ret;
79e53945
JB		 1855}
1856
e2f0ba97 1857static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945 1858{
ff482d83 1859 struct edid *edid;
79e53945 1860
46a3f4a3 1861 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 1862 connector->base.id, connector->name);
46a3f4a3 1863
79e53945 1864 /* set the bus switch and get the modes */
e957d772 1865 edid = intel_sdvo_get_edid(connector);
79e53945 1866
57cdaf90
KP		 1867 /*
1868 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1869 * link between analog and digital outputs. So, if the regular SDVO
1870 * DDC fails, check to see if the analog output is disconnected, in
1871 * which case we'll look there for the digital DDC data.
e2f0ba97 1872 */
f899fc64
CW		 1873 if (edid == NULL)
1874 edid = intel_sdvo_get_analog_edid(connector);
1875
ff482d83 1876 if (edid != NULL) {
52220085
CW		 1877 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
1878 edid)) {
0c1dab89
CW		 1879 drm_mode_connector_update_edid_property(connector, edid);
1880 drm_add_edid_modes(connector, edid);
1881 }
13946743 1882
ff482d83 1883 kfree(edid);
e2f0ba97 1884 }
e2f0ba97
JB		 1885}
1886
1887/*
1888 * Set of SDVO TV modes.
1889 * Note! This is in reply order (see loop in get_tv_modes).
1890 * XXX: all 60Hz refresh?
1891 */
b1f559ec 1892static const struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1893 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1894 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1895 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1896 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1897 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1898 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1899 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1900 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1901 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1902 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1903 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1904 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1905 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1906 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1907 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1908 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1909 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1910 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1911 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1912 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1913 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1914 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1915 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1916 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1917 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1918 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1919 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1920 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1921 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1922 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1923 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1924 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1925 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1926 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1927 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1928 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1929 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1930 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1931 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1932 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1933 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1934 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1935 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1936 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1937 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1938 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1939 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1940 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1941 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1942 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1943 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1944 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1945 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1946 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1947 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1948 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1949 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1950};
1951
1952static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1953{
df0e9248 1954 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
630d30a4 1955 const struct drm_connector_state *conn_state = connector->state;
7026d4ac 1956 struct intel_sdvo_sdtv_resolution_request tv_res;
ce6feabd
ZY		 1957 uint32_t reply = 0, format_map = 0;
1958 int i;
e2f0ba97 1959
46a3f4a3 1960 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 1961 connector->base.id, connector->name);
46a3f4a3 1962
e2f0ba97
JB		 1963 /* Read the list of supported input resolutions for the selected TV
1964 * format.
1965 */
630d30a4 1966 format_map = 1 << conn_state->tv.mode;
ce6feabd 1967 memcpy(&tv_res, &format_map,
32aad86f 1968 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
ce6feabd 1969
32aad86f
CW		 1970 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1971 return;
ce6feabd 1972
32aad86f 1973 BUILD_BUG_ON(sizeof(tv_res) != 3);
e957d772
CW		 1974 if (!intel_sdvo_write_cmd(intel_sdvo,
1975 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
32aad86f
CW		 1976 &tv_res, sizeof(tv_res)))
1977 return;
1978 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
e2f0ba97
JB		 1979 return;
1980
1981 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 1982 if (reply & (1 << i)) {
1983 struct drm_display_mode *nmode;
1984 nmode = drm_mode_duplicate(connector->dev,
32aad86f 1985 &sdvo_tv_modes[i]);
7026d4ac
ZW		 1986 if (nmode)
1987 drm_mode_probed_add(connector, nmode);
1988 }
e2f0ba97
JB		 1989}
1990
7086c87f
ML		 1991static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1992{
df0e9248 1993 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
fac5e23e 1994 struct drm_i915_private *dev_priv = to_i915(connector->dev);
12682a97 1995 struct drm_display_mode *newmode;
7086c87f 1996
46a3f4a3 1997 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 1998 connector->base.id, connector->name);
46a3f4a3 1999
7086c87f 2000 /*
c3456fb3 2001 * Fetch modes from VBT. For SDVO prefer the VBT mode since some
4300a0f8 2002 * SDVO->LVDS transcoders can't cope with the EDID mode.
7086c87f 2003 */
41aa3448 2004 if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) {
7086c87f 2005 newmode = drm_mode_duplicate(connector->dev,
41aa3448 2006 dev_priv->vbt.sdvo_lvds_vbt_mode);
7086c87f
ML		 2007 if (newmode != NULL) {
2008 /* Guarantee the mode is preferred */
2009 newmode->type = (DRM_MODE_TYPE_PREFERRED |
2010 DRM_MODE_TYPE_DRIVER);
2011 drm_mode_probed_add(connector, newmode);
2012 }
2013 }
12682a97 2014
4300a0f8
DA		 2015 /*
2016 * Attempt to get the mode list from DDC.
2017 * Assume that the preferred modes are
2018 * arranged in priority order.
2019 */
2020 intel_ddc_get_modes(connector, &intel_sdvo->ddc);
2021
12682a97 2022 list_for_each_entry(newmode, &connector->probed_modes, head) {
2023 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
ea5b213a 2024 intel_sdvo->sdvo_lvds_fixed_mode =
12682a97 2025 drm_mode_duplicate(connector->dev, newmode);
6c9547ff 2026
8545423a 2027 intel_sdvo->is_lvds = true;
12682a97 2028 break;
2029 }
2030 }
7086c87f
ML		 2031}
2032
e2f0ba97
JB		 2033static int intel_sdvo_get_modes(struct drm_connector *connector)
2034{
615fb93f 2035 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e2f0ba97 2036
615fb93f 2037 if (IS_TV(intel_sdvo_connector))
e2f0ba97 2038 intel_sdvo_get_tv_modes(connector);
615fb93f 2039 else if (IS_LVDS(intel_sdvo_connector))
7086c87f 2040 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 2041 else
2042 intel_sdvo_get_ddc_modes(connector);
2043
32aad86f 2044 return !list_empty(&connector->probed_modes);
79e53945
JB		 2045}
2046
2047static void intel_sdvo_destroy(struct drm_connector *connector)
2048{
615fb93f 2049 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
79e53945 2050
79e53945 2051 drm_connector_cleanup(connector);
4b745b1e 2052 kfree(intel_sdvo_connector);
79e53945
JB		 2053}
2054
ce6feabd 2055static int
630d30a4
ML		 2056intel_sdvo_connector_atomic_get_property(struct drm_connector *connector,
2057 const struct drm_connector_state *state,
2058 struct drm_property *property,
2059 uint64_t *val)
ce6feabd 2060{
615fb93f 2061 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
630d30a4 2062 const struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state((void *)state);
c5521706
CW		 2063
2064 if (property == intel_sdvo_connector->tv_format) {
630d30a4 2065 int i;
b9219c5e 2066
630d30a4
ML		 2067 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
2068 if (state->tv.mode == intel_sdvo_connector->tv_format_supported[i]) {
2069 *val = i;
b9219c5e 2070
32aad86f 2071 return 0;
630d30a4 2072 }
b9219c5e 2073
630d30a4
ML		 2074 WARN_ON(1);
2075 *val = 0;
2076 } else if (property == intel_sdvo_connector->top ||
2077 property == intel_sdvo_connector->bottom)
2078 *val = intel_sdvo_connector->max_vscan - sdvo_state->tv.overscan_v;
2079 else if (property == intel_sdvo_connector->left ||
2080 property == intel_sdvo_connector->right)
2081 *val = intel_sdvo_connector->max_hscan - sdvo_state->tv.overscan_h;
2082 else if (property == intel_sdvo_connector->hpos)
2083 *val = sdvo_state->tv.hpos;
2084 else if (property == intel_sdvo_connector->vpos)
2085 *val = sdvo_state->tv.vpos;
2086 else if (property == intel_sdvo_connector->saturation)
2087 *val = state->tv.saturation;
2088 else if (property == intel_sdvo_connector->contrast)
2089 *val = state->tv.contrast;
2090 else if (property == intel_sdvo_connector->hue)
2091 *val = state->tv.hue;
2092 else if (property == intel_sdvo_connector->brightness)
2093 *val = state->tv.brightness;
2094 else if (property == intel_sdvo_connector->sharpness)
2095 *val = sdvo_state->tv.sharpness;
2096 else if (property == intel_sdvo_connector->flicker_filter)
2097 *val = sdvo_state->tv.flicker_filter;
2098 else if (property == intel_sdvo_connector->flicker_filter_2d)
2099 *val = sdvo_state->tv.flicker_filter_2d;
2100 else if (property == intel_sdvo_connector->flicker_filter_adaptive)
2101 *val = sdvo_state->tv.flicker_filter_adaptive;
2102 else if (property == intel_sdvo_connector->tv_chroma_filter)
2103 *val = sdvo_state->tv.chroma_filter;
2104 else if (property == intel_sdvo_connector->tv_luma_filter)
2105 *val = sdvo_state->tv.luma_filter;
2106 else if (property == intel_sdvo_connector->dot_crawl)
2107 *val = sdvo_state->tv.dot_crawl;
2108 else
2109 return intel_digital_connector_atomic_get_property(connector, state, property, val);
32aad86f 2110
630d30a4
ML		 2111 return 0;
2112}
b9219c5e 2113
630d30a4
ML		 2114static int
2115intel_sdvo_connector_atomic_set_property(struct drm_connector *connector,
2116 struct drm_connector_state *state,
2117 struct drm_property *property,
2118 uint64_t val)
2119{
2120 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2121 struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state(state);
b9219c5e 2122
630d30a4
ML		 2123 if (property == intel_sdvo_connector->tv_format) {
2124 state->tv.mode = intel_sdvo_connector->tv_format_supported[val];
b9219c5e 2125
630d30a4
ML		 2126 if (state->crtc) {
2127 struct drm_crtc_state *crtc_state =
2128 drm_atomic_get_new_crtc_state(state->state, state->crtc);
b9219c5e 2129
630d30a4
ML		 2130 crtc_state->connectors_changed = true;
2131 }
2132 } else if (property == intel_sdvo_connector->top ||
2133 property == intel_sdvo_connector->bottom)
2134 /* Cannot set these independent from each other */
2135 sdvo_state->tv.overscan_v = intel_sdvo_connector->max_vscan - val;
2136 else if (property == intel_sdvo_connector->left ||
2137 property == intel_sdvo_connector->right)
2138 /* Cannot set these independent from each other */
2139 sdvo_state->tv.overscan_h = intel_sdvo_connector->max_hscan - val;
2140 else if (property == intel_sdvo_connector->hpos)
2141 sdvo_state->tv.hpos = val;
2142 else if (property == intel_sdvo_connector->vpos)
2143 sdvo_state->tv.vpos = val;
2144 else if (property == intel_sdvo_connector->saturation)
2145 state->tv.saturation = val;
2146 else if (property == intel_sdvo_connector->contrast)
2147 state->tv.contrast = val;
2148 else if (property == intel_sdvo_connector->hue)
2149 state->tv.hue = val;
2150 else if (property == intel_sdvo_connector->brightness)
2151 state->tv.brightness = val;
2152 else if (property == intel_sdvo_connector->sharpness)
2153 sdvo_state->tv.sharpness = val;
2154 else if (property == intel_sdvo_connector->flicker_filter)
2155 sdvo_state->tv.flicker_filter = val;
2156 else if (property == intel_sdvo_connector->flicker_filter_2d)
2157 sdvo_state->tv.flicker_filter_2d = val;
2158 else if (property == intel_sdvo_connector->flicker_filter_adaptive)
2159 sdvo_state->tv.flicker_filter_adaptive = val;
2160 else if (property == intel_sdvo_connector->tv_chroma_filter)
2161 sdvo_state->tv.chroma_filter = val;
2162 else if (property == intel_sdvo_connector->tv_luma_filter)
2163 sdvo_state->tv.luma_filter = val;
2164 else if (property == intel_sdvo_connector->dot_crawl)
2165 sdvo_state->tv.dot_crawl = val;
2166 else
2167 return intel_digital_connector_atomic_set_property(connector, state, property, val);
c5521706 2168
32aad86f 2169 return 0;
ce6feabd
ZY		 2170}
2171
7a418e34
CW		 2172static int
2173intel_sdvo_connector_register(struct drm_connector *connector)
2174{
2175 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1ebaa0b9
CW		 2176 int ret;
2177
2178 ret = intel_connector_register(connector);
2179 if (ret)
2180 return ret;
7a418e34
CW		 2181
2182 return sysfs_create_link(&connector->kdev->kobj,
2183 &sdvo->ddc.dev.kobj,
2184 sdvo->ddc.dev.kobj.name);
2185}
2186
c191eca1
CW		 2187static void
2188intel_sdvo_connector_unregister(struct drm_connector *connector)
2189{
2190 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
2191
2192 sysfs_remove_link(&connector->kdev->kobj,
2193 sdvo->ddc.dev.kobj.name);
2194 intel_connector_unregister(connector);
2195}
2196
630d30a4
ML		 2197static struct drm_connector_state *
2198intel_sdvo_connector_duplicate_state(struct drm_connector *connector)
2199{
2200 struct intel_sdvo_connector_state *state;
2201
2202 state = kmemdup(connector->state, sizeof(*state), GFP_KERNEL);
2203 if (!state)
2204 return NULL;
2205
2206 __drm_atomic_helper_connector_duplicate_state(connector, &state->base.base);
2207 return &state->base.base;
2208}
2209
79e53945 2210static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
79e53945
JB		 2211 .detect = intel_sdvo_detect,
2212 .fill_modes = drm_helper_probe_single_connector_modes,
630d30a4
ML		 2213 .atomic_get_property = intel_sdvo_connector_atomic_get_property,
2214 .atomic_set_property = intel_sdvo_connector_atomic_set_property,
7a418e34 2215 .late_register = intel_sdvo_connector_register,
c191eca1 2216 .early_unregister = intel_sdvo_connector_unregister,
79e53945 2217 .destroy = intel_sdvo_destroy,
c6f95f27 2218 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
630d30a4 2219 .atomic_duplicate_state = intel_sdvo_connector_duplicate_state,
79e53945
JB		 2220};
2221
630d30a4
ML		 2222static int intel_sdvo_atomic_check(struct drm_connector *conn,
2223 struct drm_connector_state *new_conn_state)
2224{
2225 struct drm_atomic_state *state = new_conn_state->state;
2226 struct drm_connector_state *old_conn_state =
2227 drm_atomic_get_old_connector_state(state, conn);
2228 struct intel_sdvo_connector_state *old_state =
2229 to_intel_sdvo_connector_state(old_conn_state);
2230 struct intel_sdvo_connector_state *new_state =
2231 to_intel_sdvo_connector_state(new_conn_state);
2232
2233 if (new_conn_state->crtc &&
2234 (memcmp(&old_state->tv, &new_state->tv, sizeof(old_state->tv)) ||
2235 memcmp(&old_conn_state->tv, &new_conn_state->tv, sizeof(old_conn_state->tv)))) {
2236 struct drm_crtc_state *crtc_state =
2237 drm_atomic_get_new_crtc_state(new_conn_state->state,
2238 new_conn_state->crtc);
2239
2240 crtc_state->connectors_changed = true;
2241 }
2242
2243 return intel_digital_connector_atomic_check(conn, new_conn_state);
2244}
2245
79e53945
JB		 2246static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
2247 .get_modes = intel_sdvo_get_modes,
2248 .mode_valid = intel_sdvo_mode_valid,
630d30a4 2249 .atomic_check = intel_sdvo_atomic_check,
79e53945
JB		 2250};
2251
b358d0a6 2252static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945 2253{
8aca63aa 2254 struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder));
d2a82a6f 2255
ea5b213a 2256 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
d2a82a6f 2257 drm_mode_destroy(encoder->dev,
ea5b213a 2258 intel_sdvo->sdvo_lvds_fixed_mode);
d2a82a6f 2259
e957d772 2260 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 2261 intel_encoder_destroy(encoder);
79e53945
JB		 2262}
2263
2264static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
2265 .destroy = intel_sdvo_enc_destroy,
2266};
2267
b66d8424
CW		 2268static void
2269intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
2270{
2271 uint16_t mask = 0;
2272 unsigned int num_bits;
2273
2274 /* Make a mask of outputs less than or equal to our own priority in the
2275 * list.
2276 */
2277 switch (sdvo->controlled_output) {
2278 case SDVO_OUTPUT_LVDS1:
2279 mask |= SDVO_OUTPUT_LVDS1;
2280 case SDVO_OUTPUT_LVDS0:
2281 mask |= SDVO_OUTPUT_LVDS0;
2282 case SDVO_OUTPUT_TMDS1:
2283 mask |= SDVO_OUTPUT_TMDS1;
2284 case SDVO_OUTPUT_TMDS0:
2285 mask |= SDVO_OUTPUT_TMDS0;
2286 case SDVO_OUTPUT_RGB1:
2287 mask |= SDVO_OUTPUT_RGB1;
2288 case SDVO_OUTPUT_RGB0:
2289 mask |= SDVO_OUTPUT_RGB0;
2290 break;
2291 }
2292
2293 /* Count bits to find what number we are in the priority list. */
2294 mask &= sdvo->caps.output_flags;
2295 num_bits = hweight16(mask);
2296 /* If more than 3 outputs, default to DDC bus 3 for now. */
2297 if (num_bits > 3)
2298 num_bits = 3;
2299
2300 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
2301 sdvo->ddc_bus = 1 << num_bits;
2302}
79e53945 2303
e2f0ba97
JB		 2304/**
2305 * Choose the appropriate DDC bus for control bus switch command for this
2306 * SDVO output based on the controlled output.
2307 *
2308 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
2309 * outputs, then LVDS outputs.
2310 */
2311static void
b1083333 2312intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
8bd864b8 2313 struct intel_sdvo *sdvo)
e2f0ba97 2314{
b1083333 2315 struct sdvo_device_mapping *mapping;
e2f0ba97 2316
2a5c0832 2317 if (sdvo->port == PORT_B)
9d6c875d 2318 mapping = &dev_priv->vbt.sdvo_mappings[0];
b1083333 2319 else
9d6c875d 2320 mapping = &dev_priv->vbt.sdvo_mappings[1];
e2f0ba97 2321
b66d8424
CW		 2322 if (mapping->initialized)
2323 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
2324 else
2325 intel_sdvo_guess_ddc_bus(sdvo);
e2f0ba97
JB		 2326}
2327
e957d772
CW		 2328static void
2329intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
8bd864b8 2330 struct intel_sdvo *sdvo)
e957d772
CW		 2331{
2332 struct sdvo_device_mapping *mapping;
46eb3036 2333 u8 pin;
e957d772 2334
2a5c0832 2335 if (sdvo->port == PORT_B)
9d6c875d 2336 mapping = &dev_priv->vbt.sdvo_mappings[0];
e957d772 2337 else
9d6c875d 2338 mapping = &dev_priv->vbt.sdvo_mappings[1];
e957d772 2339
88ac7939
JN		 2340 if (mapping->initialized &&
2341 intel_gmbus_is_valid_pin(dev_priv, mapping->i2c_pin))
e957d772 2342 pin = mapping->i2c_pin;
6cb1612a 2343 else
988c7015 2344 pin = GMBUS_PIN_DPB;
e957d772 2345
6cb1612a
JN		 2346 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
2347
2348 /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow
2349 * our code totally fails once we start using gmbus. Hence fall back to
2350 * bit banging for now. */
2351 intel_gmbus_force_bit(sdvo->i2c, true);
e957d772
CW		 2352}
2353
fbfcc4f3
JN		 2354/* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */
2355static void
2356intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo)
2357{
2358 intel_gmbus_force_bit(sdvo->i2c, false);
e957d772
CW		 2359}
2360
e2f0ba97 2361static bool
e27d8538 2362intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
e2f0ba97 2363{
97aaf910 2364 return intel_sdvo_check_supp_encode(intel_sdvo);
e2f0ba97
JB		 2365}
2366
714605e4 2367static u8
c39055b0
ACO		 2368intel_sdvo_get_slave_addr(struct drm_i915_private *dev_priv,
2369 struct intel_sdvo *sdvo)
714605e4 2370{
714605e4 2371 struct sdvo_device_mapping *my_mapping, *other_mapping;
2372
2a5c0832 2373 if (sdvo->port == PORT_B) {
9d6c875d
JN		 2374 my_mapping = &dev_priv->vbt.sdvo_mappings[0];
2375 other_mapping = &dev_priv->vbt.sdvo_mappings[1];
714605e4 2376 } else {
9d6c875d
JN		 2377 my_mapping = &dev_priv->vbt.sdvo_mappings[1];
2378 other_mapping = &dev_priv->vbt.sdvo_mappings[0];
714605e4 2379 }
2380
2381 /* If the BIOS described our SDVO device, take advantage of it. */
2382 if (my_mapping->slave_addr)
2383 return my_mapping->slave_addr;
2384
2385 /* If the BIOS only described a different SDVO device, use the
2386 * address that it isn't using.
2387 */
2388 if (other_mapping->slave_addr) {
2389 if (other_mapping->slave_addr == 0x70)
2390 return 0x72;
2391 else
2392 return 0x70;
2393 }
2394
2395 /* No SDVO device info is found for another DVO port,
2396 * so use mapping assumption we had before BIOS parsing.
2397 */
2a5c0832 2398 if (sdvo->port == PORT_B)
714605e4 2399 return 0x70;
2400 else
2401 return 0x72;
2402}
2403
c393454d 2404static int
df0e9248
CW		 2405intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
2406 struct intel_sdvo *encoder)
14571b4c 2407{
c393454d
ID		 2408 struct drm_connector *drm_connector;
2409 int ret;
2410
2411 drm_connector = &connector->base.base;
2412 ret = drm_connector_init(encoder->base.base.dev,
2413 drm_connector,
df0e9248
CW		 2414 &intel_sdvo_connector_funcs,
2415 connector->base.base.connector_type);
c393454d
ID		 2416 if (ret < 0)
2417 return ret;
6070a4a9 2418
c393454d 2419 drm_connector_helper_add(drm_connector,
df0e9248 2420 &intel_sdvo_connector_helper_funcs);
14571b4c 2421
8f4839e2 2422 connector->base.base.interlace_allowed = 1;
df0e9248
CW		 2423 connector->base.base.doublescan_allowed = 0;
2424 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
4ac41f47 2425 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
14571b4c 2426
df0e9248 2427 intel_connector_attach_encoder(&connector->base, &encoder->base);
c393454d
ID		 2428
2429 return 0;
14571b4c 2430}
6070a4a9 2431
7f36e7ed 2432static void
55bc60db
VS		 2433intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
2434 struct intel_sdvo_connector *connector)
7f36e7ed 2435{
646d5772 2436 struct drm_i915_private *dev_priv = to_i915(connector->base.base.dev);
7f36e7ed 2437
3f43c48d 2438 intel_attach_force_audio_property(&connector->base.base);
646d5772 2439 if (INTEL_GEN(dev_priv) >= 4 && IS_MOBILE(dev_priv)) {
e953fd7b 2440 intel_attach_broadcast_rgb_property(&connector->base.base);
55bc60db 2441 }
7949dd47 2442 intel_attach_aspect_ratio_property(&connector->base.base);
0e9f25d0 2443 connector->base.base.state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
7f36e7ed
CW		 2444}
2445
08d9bc92
ACO		 2446static struct intel_sdvo_connector *intel_sdvo_connector_alloc(void)
2447{
2448 struct intel_sdvo_connector *sdvo_connector;
630d30a4 2449 struct intel_sdvo_connector_state *conn_state;
08d9bc92
ACO		 2450
2451 sdvo_connector = kzalloc(sizeof(*sdvo_connector), GFP_KERNEL);
2452 if (!sdvo_connector)
2453 return NULL;
2454
630d30a4
ML		 2455 conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL);
2456 if (!conn_state) {
08d9bc92
ACO		 2457 kfree(sdvo_connector);
2458 return NULL;
2459 }
2460
630d30a4
ML		 2461 __drm_atomic_helper_connector_reset(&sdvo_connector->base.base,
2462 &conn_state->base.base);
2463
08d9bc92
ACO		 2464 return sdvo_connector;
2465}
2466
fb7a46f3 2467static bool
ea5b213a 2468intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
fb7a46f3 2469{
4ef69c7a 2470 struct drm_encoder *encoder = &intel_sdvo->base.base;
de44e256 2471 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
14571b4c 2472 struct drm_connector *connector;
cc68c81a 2473 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
14571b4c 2474 struct intel_connector *intel_connector;
615fb93f 2475 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2476
46a3f4a3
CW		 2477 DRM_DEBUG_KMS("initialising DVI device %d\n", device);
2478
08d9bc92 2479 intel_sdvo_connector = intel_sdvo_connector_alloc();
615fb93f 2480 if (!intel_sdvo_connector)
14571b4c
ZW		 2481 return false;
2482
14571b4c 2483 if (device == 0) {
ea5b213a 2484 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
615fb93f 2485 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
14571b4c 2486 } else if (device == 1) {
ea5b213a 2487 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
615fb93f 2488 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
14571b4c
ZW		 2489 }
2490
615fb93f 2491 intel_connector = &intel_sdvo_connector->base;
14571b4c 2492 connector = &intel_connector->base;
5fa7ac9c
JN		 2493 if (intel_sdvo_get_hotplug_support(intel_sdvo) &
2494 intel_sdvo_connector->output_flag) {
5fa7ac9c 2495 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag;
cc68c81a
SF		 2496 /* Some SDVO devices have one-shot hotplug interrupts.
2497 * Ensure that they get re-enabled when an interrupt happens.
2498 */
2499 intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
3a2fb2c3 2500 intel_sdvo_enable_hotplug(intel_encoder);
5fa7ac9c 2501 } else {
821450c6 2502 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
5fa7ac9c 2503 }
14571b4c
ZW		 2504 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2505 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2506
de44e256
DV		 2507 /* gen3 doesn't do the hdmi bits in the SDVO register */
2508 if (INTEL_GEN(dev_priv) >= 4 &&
2509 intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
14571b4c 2510 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
e27d8538 2511 intel_sdvo->is_hdmi = true;
14571b4c 2512 }
14571b4c 2513
c393454d
ID		 2514 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2515 kfree(intel_sdvo_connector);
2516 return false;
2517 }
2518
f797d221 2519 if (intel_sdvo->is_hdmi)
55bc60db 2520 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector);
14571b4c
ZW		 2521
2522 return true;
2523}
2524
2525static bool
ea5b213a 2526intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
14571b4c 2527{
4ef69c7a
CW		 2528 struct drm_encoder *encoder = &intel_sdvo->base.base;
2529 struct drm_connector *connector;
2530 struct intel_connector *intel_connector;
2531 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2532
46a3f4a3
CW		 2533 DRM_DEBUG_KMS("initialising TV type %d\n", type);
2534
08d9bc92 2535 intel_sdvo_connector = intel_sdvo_connector_alloc();
615fb93f
CW		 2536 if (!intel_sdvo_connector)
2537 return false;
14571b4c 2538
615fb93f 2539 intel_connector = &intel_sdvo_connector->base;
4ef69c7a
CW		 2540 connector = &intel_connector->base;
2541 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2542 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
14571b4c 2543
4ef69c7a
CW		 2544 intel_sdvo->controlled_output |= type;
2545 intel_sdvo_connector->output_flag = type;
14571b4c 2546
4ef69c7a 2547 intel_sdvo->is_tv = true;
14571b4c 2548
c393454d
ID		 2549 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2550 kfree(intel_sdvo_connector);
2551 return false;
2552 }
14571b4c 2553
4ef69c7a 2554 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
32aad86f 2555 goto err;
14571b4c 2556
4ef69c7a 2557 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f 2558 goto err;
14571b4c 2559
4ef69c7a 2560 return true;
32aad86f
CW		 2561
2562err:
123d5c01 2563 intel_sdvo_destroy(connector);
32aad86f 2564 return false;
14571b4c
ZW		 2565}
2566
2567static bool
ea5b213a 2568intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2569{
4ef69c7a
CW		 2570 struct drm_encoder *encoder = &intel_sdvo->base.base;
2571 struct drm_connector *connector;
2572 struct intel_connector *intel_connector;
2573 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2574
46a3f4a3
CW		 2575 DRM_DEBUG_KMS("initialising analog device %d\n", device);
2576
8ce7da47 2577 intel_sdvo_connector = intel_sdvo_connector_alloc();
615fb93f
CW		 2578 if (!intel_sdvo_connector)
2579 return false;
14571b4c 2580
615fb93f 2581 intel_connector = &intel_sdvo_connector->base;
4ef69c7a 2582 connector = &intel_connector->base;
821450c6 2583 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
4ef69c7a
CW		 2584 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2585 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2586
2587 if (device == 0) {
2588 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2589 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2590 } else if (device == 1) {
2591 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2592 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2593 }
2594
c393454d
ID		 2595 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2596 kfree(intel_sdvo_connector);
2597 return false;
2598 }
2599
4ef69c7a 2600 return true;
14571b4c
ZW		 2601}
2602
2603static bool
ea5b213a 2604intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2605{
4ef69c7a
CW		 2606 struct drm_encoder *encoder = &intel_sdvo->base.base;
2607 struct drm_connector *connector;
2608 struct intel_connector *intel_connector;
2609 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2610
46a3f4a3
CW		 2611 DRM_DEBUG_KMS("initialising LVDS device %d\n", device);
2612
08d9bc92 2613 intel_sdvo_connector = intel_sdvo_connector_alloc();
615fb93f
CW		 2614 if (!intel_sdvo_connector)
2615 return false;
14571b4c 2616
615fb93f
CW		 2617 intel_connector = &intel_sdvo_connector->base;
2618 connector = &intel_connector->base;
4ef69c7a
CW		 2619 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2620 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2621
2622 if (device == 0) {
2623 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2624 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2625 } else if (device == 1) {
2626 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2627 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2628 }
2629
c393454d
ID		 2630 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2631 kfree(intel_sdvo_connector);
2632 return false;
2633 }
2634
4ef69c7a 2635 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f
CW		 2636 goto err;
2637
2638 return true;
2639
2640err:
123d5c01 2641 intel_sdvo_destroy(connector);
32aad86f 2642 return false;
14571b4c
ZW		 2643}
2644
2645static bool
ea5b213a 2646intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
14571b4c 2647{
ea5b213a 2648 intel_sdvo->is_tv = false;
ea5b213a 2649 intel_sdvo->is_lvds = false;
fb7a46f3 2650
14571b4c 2651 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
fb7a46f3 2652
14571b4c 2653 if (flags & SDVO_OUTPUT_TMDS0)
ea5b213a 2654 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
14571b4c
ZW		 2655 return false;
2656
2657 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
ea5b213a 2658 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
14571b4c
ZW		 2659 return false;
2660
2661 /* TV has no XXX1 function block */
a1f4b7ff 2662 if (flags & SDVO_OUTPUT_SVID0)
ea5b213a 2663 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
14571b4c
ZW		 2664 return false;
2665
2666 if (flags & SDVO_OUTPUT_CVBS0)
ea5b213a 2667 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
14571b4c 2668 return false;
fb7a46f3 2669
a0b1c7a5
CW		 2670 if (flags & SDVO_OUTPUT_YPRPB0)
2671 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
2672 return false;
2673
14571b4c 2674 if (flags & SDVO_OUTPUT_RGB0)
ea5b213a 2675 if (!intel_sdvo_analog_init(intel_sdvo, 0))
14571b4c
ZW		 2676 return false;
2677
2678 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
ea5b213a 2679 if (!intel_sdvo_analog_init(intel_sdvo, 1))
14571b4c
ZW		 2680 return false;
2681
2682 if (flags & SDVO_OUTPUT_LVDS0)
ea5b213a 2683 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
14571b4c
ZW		 2684 return false;
2685
2686 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
ea5b213a 2687 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
14571b4c 2688 return false;
fb7a46f3 2689
14571b4c 2690 if ((flags & SDVO_OUTPUT_MASK) == 0) {
fb7a46f3 2691 unsigned char bytes[2];
2692
ea5b213a
CW		 2693 intel_sdvo->controlled_output = 0;
2694 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
51c8b407 2695 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
ea5b213a 2696 SDVO_NAME(intel_sdvo),
51c8b407 2697 bytes[0], bytes[1]);
14571b4c 2698 return false;
fb7a46f3 2699 }
27f8227b 2700 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
fb7a46f3 2701
14571b4c 2702 return true;
fb7a46f3 2703}
2704
d0ddfbd3
JN		 2705static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)
2706{
2707 struct drm_device *dev = intel_sdvo->base.base.dev;
2708 struct drm_connector *connector, *tmp;
2709
2710 list_for_each_entry_safe(connector, tmp,
2711 &dev->mode_config.connector_list, head) {
d9255d57 2712 if (intel_attached_encoder(connector) == &intel_sdvo->base) {
34ea3d38 2713 drm_connector_unregister(connector);
d0ddfbd3 2714 intel_sdvo_destroy(connector);
d9255d57 2715 }
d0ddfbd3
JN		 2716 }
2717}
2718
32aad86f
CW		 2719static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2720 struct intel_sdvo_connector *intel_sdvo_connector,
2721 int type)
ce6feabd 2722{
4ef69c7a 2723 struct drm_device *dev = intel_sdvo->base.base.dev;
ce6feabd
ZY		 2724 struct intel_sdvo_tv_format format;
2725 uint32_t format_map, i;
ce6feabd 2726
32aad86f
CW		 2727 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2728 return false;
ce6feabd 2729
1a3665c8 2730 BUILD_BUG_ON(sizeof(format) != 6);
32aad86f
CW		 2731 if (!intel_sdvo_get_value(intel_sdvo,
2732 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2733 &format, sizeof(format)))
2734 return false;
ce6feabd 2735
32aad86f 2736 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
ce6feabd
ZY		 2737
2738 if (format_map == 0)
32aad86f 2739 return false;
ce6feabd 2740
615fb93f 2741 intel_sdvo_connector->format_supported_num = 0;
ce6feabd 2742 for (i = 0 ; i < TV_FORMAT_NUM; i++)
40039750
CW		 2743 if (format_map & (1 << i))
2744 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
ce6feabd
ZY		 2745
2746
c5521706 2747 intel_sdvo_connector->tv_format =
32aad86f
CW		 2748 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2749 "mode", intel_sdvo_connector->format_supported_num);
c5521706 2750 if (!intel_sdvo_connector->tv_format)
fcc8d672 2751 return false;
ce6feabd 2752
615fb93f 2753 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
ce6feabd 2754 drm_property_add_enum(
c5521706 2755 intel_sdvo_connector->tv_format, i,
40039750 2756 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
ce6feabd 2757
630d30a4 2758 intel_sdvo_connector->base.base.state->tv.mode = intel_sdvo_connector->tv_format_supported[0];
10223df2
VS		 2759 drm_object_attach_property(&intel_sdvo_connector->base.base.base,
2760 intel_sdvo_connector->tv_format, 0);
32aad86f 2761 return true;
ce6feabd
ZY		 2762
2763}
2764
630d30a4 2765#define _ENHANCEMENT(state_assignment, name, NAME) do { \
c5521706
CW		 2766 if (enhancements.name) { \
2767 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2768 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2769 return false; \
c5521706 2770 intel_sdvo_connector->name = \
d9bc3c02 2771 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
c5521706 2772 if (!intel_sdvo_connector->name) return false; \
630d30a4 2773 state_assignment = response; \
662595df 2774 drm_object_attach_property(&connector->base, \
630d30a4 2775 intel_sdvo_connector->name, 0); \
c5521706
CW		 2776 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2777 data_value[0], data_value[1], response); \
2778 } \
0206e353 2779} while (0)
c5521706 2780
630d30a4
ML		 2781#define ENHANCEMENT(state, name, NAME) _ENHANCEMENT((state)->name, name, NAME)
2782
c5521706
CW		 2783static bool
2784intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2785 struct intel_sdvo_connector *intel_sdvo_connector,
2786 struct intel_sdvo_enhancements_reply enhancements)
b9219c5e 2787{
4ef69c7a 2788 struct drm_device *dev = intel_sdvo->base.base.dev;
32aad86f 2789 struct drm_connector *connector = &intel_sdvo_connector->base.base;
630d30a4
ML		 2790 struct drm_connector_state *conn_state = connector->state;
2791 struct intel_sdvo_connector_state *sdvo_state =
2792 to_intel_sdvo_connector_state(conn_state);
b9219c5e
ZY		 2793 uint16_t response, data_value[2];
2794
c5521706
CW		 2795 /* when horizontal overscan is supported, Add the left/right property */
2796 if (enhancements.overscan_h) {
2797 if (!intel_sdvo_get_value(intel_sdvo,
2798 SDVO_CMD_GET_MAX_OVERSCAN_H,
2799 &data_value, 4))
2800 return false;
32aad86f 2801
c5521706
CW		 2802 if (!intel_sdvo_get_value(intel_sdvo,
2803 SDVO_CMD_GET_OVERSCAN_H,
2804 &response, 2))
2805 return false;
fcc8d672 2806
630d30a4
ML		 2807 sdvo_state->tv.overscan_h = response;
2808
c5521706 2809 intel_sdvo_connector->max_hscan = data_value[0];
c5521706 2810 intel_sdvo_connector->left =
d9bc3c02 2811 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
c5521706
CW		 2812 if (!intel_sdvo_connector->left)
2813 return false;
fcc8d672 2814
662595df 2815 drm_object_attach_property(&connector->base,
630d30a4 2816 intel_sdvo_connector->left, 0);
fcc8d672 2817
c5521706 2818 intel_sdvo_connector->right =
d9bc3c02 2819 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
c5521706
CW		 2820 if (!intel_sdvo_connector->right)
2821 return false;
32aad86f 2822
662595df 2823 drm_object_attach_property(&connector->base,
630d30a4 2824 intel_sdvo_connector->right, 0);
c5521706
CW		 2825 DRM_DEBUG_KMS("h_overscan: max %d, "
2826 "default %d, current %d\n",
2827 data_value[0], data_value[1], response);
2828 }
32aad86f 2829
c5521706
CW		 2830 if (enhancements.overscan_v) {
2831 if (!intel_sdvo_get_value(intel_sdvo,
2832 SDVO_CMD_GET_MAX_OVERSCAN_V,
2833 &data_value, 4))
2834 return false;
fcc8d672 2835
c5521706
CW		 2836 if (!intel_sdvo_get_value(intel_sdvo,
2837 SDVO_CMD_GET_OVERSCAN_V,
2838 &response, 2))
2839 return false;
32aad86f 2840
630d30a4
ML		 2841 sdvo_state->tv.overscan_v = response;
2842
c5521706 2843 intel_sdvo_connector->max_vscan = data_value[0];
c5521706 2844 intel_sdvo_connector->top =
d9bc3c02
SH		 2845 drm_property_create_range(dev, 0,
2846 "top_margin", 0, data_value[0]);
c5521706
CW		 2847 if (!intel_sdvo_connector->top)
2848 return false;
32aad86f 2849
662595df 2850 drm_object_attach_property(&connector->base,
630d30a4 2851 intel_sdvo_connector->top, 0);
fcc8d672 2852
c5521706 2853 intel_sdvo_connector->bottom =
d9bc3c02
SH		 2854 drm_property_create_range(dev, 0,
2855 "bottom_margin", 0, data_value[0]);
c5521706
CW		 2856 if (!intel_sdvo_connector->bottom)
2857 return false;
32aad86f 2858
662595df 2859 drm_object_attach_property(&connector->base,
630d30a4 2860 intel_sdvo_connector->bottom, 0);
c5521706
CW		 2861 DRM_DEBUG_KMS("v_overscan: max %d, "
2862 "default %d, current %d\n",
2863 data_value[0], data_value[1], response);
2864 }
32aad86f 2865
630d30a4
ML		 2866 ENHANCEMENT(&sdvo_state->tv, hpos, HPOS);
2867 ENHANCEMENT(&sdvo_state->tv, vpos, VPOS);
2868 ENHANCEMENT(&conn_state->tv, saturation, SATURATION);
2869 ENHANCEMENT(&conn_state->tv, contrast, CONTRAST);
2870 ENHANCEMENT(&conn_state->tv, hue, HUE);
2871 ENHANCEMENT(&conn_state->tv, brightness, BRIGHTNESS);
2872 ENHANCEMENT(&sdvo_state->tv, sharpness, SHARPNESS);
2873 ENHANCEMENT(&sdvo_state->tv, flicker_filter, FLICKER_FILTER);
2874 ENHANCEMENT(&sdvo_state->tv, flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2875 ENHANCEMENT(&sdvo_state->tv, flicker_filter_2d, FLICKER_FILTER_2D);
2876 _ENHANCEMENT(sdvo_state->tv.chroma_filter, tv_chroma_filter, TV_CHROMA_FILTER);
2877 _ENHANCEMENT(sdvo_state->tv.luma_filter, tv_luma_filter, TV_LUMA_FILTER);
fcc8d672 2878
e044218a
CW		 2879 if (enhancements.dot_crawl) {
2880 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2881 return false;
2882
630d30a4 2883 sdvo_state->tv.dot_crawl = response & 0x1;
e044218a 2884 intel_sdvo_connector->dot_crawl =
d9bc3c02 2885 drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
e044218a
CW		 2886 if (!intel_sdvo_connector->dot_crawl)
2887 return false;
2888
662595df 2889 drm_object_attach_property(&connector->base,
630d30a4 2890 intel_sdvo_connector->dot_crawl, 0);
e044218a
CW		 2891 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2892 }
2893
c5521706
CW		 2894 return true;
2895}
32aad86f 2896
c5521706
CW		 2897static bool
2898intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2899 struct intel_sdvo_connector *intel_sdvo_connector,
2900 struct intel_sdvo_enhancements_reply enhancements)
2901{
4ef69c7a 2902 struct drm_device *dev = intel_sdvo->base.base.dev;
c5521706
CW		 2903 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2904 uint16_t response, data_value[2];
32aad86f 2905
630d30a4 2906 ENHANCEMENT(&connector->state->tv, brightness, BRIGHTNESS);
fcc8d672 2907
c5521706
CW		 2908 return true;
2909}
2910#undef ENHANCEMENT
630d30a4 2911#undef _ENHANCEMENT
32aad86f 2912
c5521706
CW		 2913static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2914 struct intel_sdvo_connector *intel_sdvo_connector)
2915{
2916 union {
2917 struct intel_sdvo_enhancements_reply reply;
2918 uint16_t response;
2919 } enhancements;
32aad86f 2920
1a3665c8
CW		 2921 BUILD_BUG_ON(sizeof(enhancements) != 2);
2922
99016646
ID		 2923 if (!intel_sdvo_get_value(intel_sdvo,
2924 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2925 &enhancements, sizeof(enhancements)) ||
2926 enhancements.response == 0) {
c5521706
CW		 2927 DRM_DEBUG_KMS("No enhancement is supported\n");
2928 return true;
b9219c5e 2929 }
32aad86f 2930
c5521706
CW		 2931 if (IS_TV(intel_sdvo_connector))
2932 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
0206e353 2933 else if (IS_LVDS(intel_sdvo_connector))
c5521706
CW		 2934 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2935 else
2936 return true;
e957d772
CW		 2937}
2938
2939static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
2940 struct i2c_msg *msgs,
2941 int num)
2942{
2943 struct intel_sdvo *sdvo = adapter->algo_data;
fcc8d672 2944
a8506684 2945 if (!__intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
e957d772
CW		 2946 return -EIO;
2947
2948 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
2949}
2950
2951static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
2952{
2953 struct intel_sdvo *sdvo = adapter->algo_data;
2954 return sdvo->i2c->algo->functionality(sdvo->i2c);
2955}
2956
2957static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
2958 .master_xfer = intel_sdvo_ddc_proxy_xfer,
2959 .functionality = intel_sdvo_ddc_proxy_func
2960};
2961
a8506684
DV		 2962static void proxy_lock_bus(struct i2c_adapter *adapter,
2963 unsigned int flags)
2964{
2965 struct intel_sdvo *sdvo = adapter->algo_data;
2966 sdvo->i2c->lock_ops->lock_bus(sdvo->i2c, flags);
2967}
2968
2969static int proxy_trylock_bus(struct i2c_adapter *adapter,
2970 unsigned int flags)
2971{
2972 struct intel_sdvo *sdvo = adapter->algo_data;
2973 return sdvo->i2c->lock_ops->trylock_bus(sdvo->i2c, flags);
2974}
2975
2976static void proxy_unlock_bus(struct i2c_adapter *adapter,
2977 unsigned int flags)
2978{
2979 struct intel_sdvo *sdvo = adapter->algo_data;
2980 sdvo->i2c->lock_ops->unlock_bus(sdvo->i2c, flags);
2981}
2982
0db1aa42 2983static const struct i2c_lock_operations proxy_lock_ops = {
a8506684
DV		 2984 .lock_bus = proxy_lock_bus,
2985 .trylock_bus = proxy_trylock_bus,
2986 .unlock_bus = proxy_unlock_bus,
2987};
2988
e957d772
CW		 2989static bool
2990intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
c39055b0 2991 struct drm_i915_private *dev_priv)
e957d772 2992{
c39055b0 2993 struct pci_dev *pdev = dev_priv->drm.pdev;
52a05c30 2994
e957d772
CW		 2995 sdvo->ddc.owner = THIS_MODULE;
2996 sdvo->ddc.class = I2C_CLASS_DDC;
2997 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
52a05c30 2998 sdvo->ddc.dev.parent = &pdev->dev;
e957d772
CW		 2999 sdvo->ddc.algo_data = sdvo;
3000 sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
a8506684 3001 sdvo->ddc.lock_ops = &proxy_lock_ops;
e957d772
CW		 3002
3003 return i2c_add_adapter(&sdvo->ddc) == 0;
b9219c5e
ZY		 3004}
3005
2a5c0832
VS		 3006static void assert_sdvo_port_valid(const struct drm_i915_private *dev_priv,
3007 enum port port)
3008{
3009 if (HAS_PCH_SPLIT(dev_priv))
3010 WARN_ON(port != PORT_B);
3011 else
3012 WARN_ON(port != PORT_B && port != PORT_C);
3013}
3014
c39055b0 3015bool intel_sdvo_init(struct drm_i915_private *dev_priv,
f0f59a00 3016 i915_reg_t sdvo_reg, enum port port)
79e53945 3017{
21d40d37 3018 struct intel_encoder *intel_encoder;
ea5b213a 3019 struct intel_sdvo *intel_sdvo;
79e53945 3020 int i;
2a5c0832
VS		 3021
3022 assert_sdvo_port_valid(dev_priv, port);
3023
b14c5679 3024 intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL);
ea5b213a 3025 if (!intel_sdvo)
7d57382e 3026 return false;
79e53945 3027
56184e3d 3028 intel_sdvo->sdvo_reg = sdvo_reg;
2a5c0832 3029 intel_sdvo->port = port;
c39055b0
ACO		 3030 intel_sdvo->slave_addr =
3031 intel_sdvo_get_slave_addr(dev_priv, intel_sdvo) >> 1;
8bd864b8 3032 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo);
c39055b0 3033 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev_priv))
fbfcc4f3 3034 goto err_i2c_bus;
e957d772 3035
56184e3d 3036 /* encoder type will be decided later */
ea5b213a 3037 intel_encoder = &intel_sdvo->base;
21d40d37 3038 intel_encoder->type = INTEL_OUTPUT_SDVO;
79f255a0 3039 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
03cdc1d4 3040 intel_encoder->port = port;
c39055b0
ACO		 3041 drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
3042 &intel_sdvo_enc_funcs, 0,
580d8ed5 3043 "SDVO %c", port_name(port));
79e53945 3044
79e53945
JB		 3045 /* Read the regs to test if we can talk to the device */
3046 for (i = 0; i < 0x40; i++) {
f899fc64
CW		 3047 u8 byte;
3048
3049 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
eef4eacb
DV		 3050 DRM_DEBUG_KMS("No SDVO device found on %s\n",
3051 SDVO_NAME(intel_sdvo));
f899fc64 3052 goto err;
79e53945
JB		 3053 }
3054 }
3055
6cc5f341 3056 intel_encoder->compute_config = intel_sdvo_compute_config;
6e266956 3057 if (HAS_PCH_SPLIT(dev_priv)) {
3c65d1d1
VS		 3058 intel_encoder->disable = pch_disable_sdvo;
3059 intel_encoder->post_disable = pch_post_disable_sdvo;
3060 } else {
3061 intel_encoder->disable = intel_disable_sdvo;
3062 }
192d47a6 3063 intel_encoder->pre_enable = intel_sdvo_pre_enable;
ce22c320 3064 intel_encoder->enable = intel_enable_sdvo;
4ac41f47 3065 intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
045ac3b5 3066 intel_encoder->get_config = intel_sdvo_get_config;
ce22c320 3067
af901ca1 3068 /* In default case sdvo lvds is false */
32aad86f 3069 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
f899fc64 3070 goto err;
79e53945 3071
ea5b213a
CW		 3072 if (intel_sdvo_output_setup(intel_sdvo,
3073 intel_sdvo->caps.output_flags) != true) {
eef4eacb
DV		 3074 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
3075 SDVO_NAME(intel_sdvo));
d0ddfbd3
JN		 3076 /* Output_setup can leave behind connectors! */
3077 goto err_output;
79e53945
JB		 3078 }
3079
7ba220ce
CW		 3080 /* Only enable the hotplug irq if we need it, to work around noisy
3081 * hotplug lines.
3082 */
3083 if (intel_sdvo->hotplug_active) {
2a5c0832
VS		 3084 if (intel_sdvo->port == PORT_B)
3085 intel_encoder->hpd_pin = HPD_SDVO_B;
3086 else
3087 intel_encoder->hpd_pin = HPD_SDVO_C;
7ba220ce
CW		 3088 }
3089
e506d6fd
DV		 3090 /*
3091 * Cloning SDVO with anything is often impossible, since the SDVO
3092 * encoder can request a special input timing mode. And even if that's
3093 * not the case we have evidence that cloning a plain unscaled mode with
3094 * VGA doesn't really work. Furthermore the cloning flags are way too
3095 * simplistic anyway to express such constraints, so just give up on
3096 * cloning for SDVO encoders.
3097 */
bc079e8b 3098 intel_sdvo->base.cloneable = 0;
e506d6fd 3099
8bd864b8 3100 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo);
e2f0ba97 3101
79e53945 3102 /* Set the input timing to the screen. Assume always input 0. */
32aad86f 3103 if (!intel_sdvo_set_target_input(intel_sdvo))
d0ddfbd3 3104 goto err_output;
79e53945 3105
32aad86f
CW		 3106 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
3107 &intel_sdvo->pixel_clock_min,
3108 &intel_sdvo->pixel_clock_max))
d0ddfbd3 3109 goto err_output;
79e53945 3110
8a4c47f3 3111 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
342dc382 3112 "clock range %dMHz - %dMHz, "
3113 "input 1: %c, input 2: %c, "
3114 "output 1: %c, output 2: %c\n",
ea5b213a
CW		 3115 SDVO_NAME(intel_sdvo),
3116 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
3117 intel_sdvo->caps.device_rev_id,
3118 intel_sdvo->pixel_clock_min / 1000,
3119 intel_sdvo->pixel_clock_max / 1000,
3120 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
3121 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
342dc382 3122 /* check currently supported outputs */
ea5b213a 3123 intel_sdvo->caps.output_flags &
79e53945 3124 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
ea5b213a 3125 intel_sdvo->caps.output_flags &
79e53945 3126 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
7d57382e 3127 return true;
79e53945 3128
d0ddfbd3
JN		 3129err_output:
3130 intel_sdvo_output_cleanup(intel_sdvo);
3131
f899fc64 3132err:
373a3cf7 3133 drm_encoder_cleanup(&intel_encoder->base);
e957d772 3134 i2c_del_adapter(&intel_sdvo->ddc);
fbfcc4f3
JN		 3135err_i2c_bus:
3136 intel_sdvo_unselect_i2c_bus(intel_sdvo);
ea5b213a 3137 kfree(intel_sdvo);
79e53945 3138
7d57382e 3139 return false;
79e53945 3140}
Linux 6.x block layer and io_uring tree(s)